Circuit structure and control method thereof, and memory

Abstract

The present disclosure relates to the field of semiconductor technology, and relates to a circuit structure, a control method thereof, and a memory. The circuit structure includes a first control line, a second control line, a third control line, a fourth control line, a first circuit, and a second circuit, wherein: the first control line and the second control line are arranged at intervals; the third control line is located on a side of the second control line away from the first control line and includes a first connecting line and a second connecting line connected to each other; the fourth control line includes a third connecting line and a fourth connecting line connected to each other, the first connecting line is located between the second control line and the third connecting line, and the fourth connecting line is located between the second control line and the second connecting line; the first circuit connects the first control line, the third control line, and the fourth control line; and the second circuit connects the second control line, the third control line, and the fourth control line. The circuit structure disclosed herein can reduce the probability of control lines being incorrectly selected and improve product yield.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a circuit structure and a control method thereof, and a memory. Background Art

[0002] Memory is widely used in mobile devices such as mobile phones and tablets due to its advantages such as small size, high integration, and fast transmission speed. Memory typically includes multiple control lines, which can be easily affected by coupling with adjacent wiring and lead to misselection during use.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field. Summary of the Invention

[0004] In view of this, the present disclosure provides a circuit structure and a control method thereof, and a memory, which can reduce the probability of a control line being misselected and improve product yield.

[0005] According to one aspect of the present disclosure, there is provided a circuit structure, comprising:

[0006] a first control line and a second control line, wherein the first control line and the second control line both extend along a first direction and are arranged at intervals along a second direction, and the first direction intersects the second direction;

[0007] a third control line, located on a side of the second control line away from the first control line, and comprising a first connecting line and a second connecting line connected to each other, wherein the first connecting line and the second connecting line both extend along the first direction;

[0008] fourth control lines, comprising a third connection line and a fourth connection line connected to each other, wherein the first connection line is located between the second control line and the third connection line, the fourth connection line is located between the second control line and the second connection line, and the third connection line and the fourth connection line both extend along the first direction;

[0009] a first circuit connecting the first control line, the third control line, and the fourth control line;

[0010] The second circuit connects the second control line, the third control line, and the fourth control line.

[0011] In an exemplary embodiment of the present disclosure, the third control line further includes:

[0012] A first sub-line segment is connected between the first connecting line and the second connecting line.

[0013] In an exemplary embodiment of the present disclosure, the fourth control line further includes:

[0014] A second sub-line segment, the second sub-line segment is connected between the third connecting line and the fourth connecting line, the first sub-line segment and the second sub-line segment are insulated from each other, and the orthographic projection of the first sub-line segment in the wiring area corresponding to the circuit structure partially overlaps with the orthographic projection of the second sub-line segment in the wiring area.

[0015] In an exemplary embodiment of the present disclosure, the first circuit includes:

[0016] a first P-type transistor, wherein a source of the first P-type transistor is electrically connected to the third control line, a drain of the first P-type transistor is electrically connected to the control signal output terminal, and a control terminal of the first P-type transistor is electrically connected to the first control line;

[0017] a first N-type transistor, wherein a source of the first N-type transistor is grounded, a drain of the first N-type transistor is electrically connected to the control signal output terminal, and a control terminal of the first N-type transistor is electrically connected to the first control line;

[0018] a second N-type transistor, wherein a source of the second N-type transistor is grounded, a drain of the second N-type transistor is electrically connected to the control signal output terminal, and a control terminal of the second N-type transistor is electrically connected to the fourth control line.

[0019] In an exemplary embodiment of the present disclosure, the second circuit includes:

[0020] a second P-type transistor, wherein a source of the second P-type transistor is electrically connected to the third control line, a drain of the second P-type transistor is electrically connected to the control signal output terminal, and a control terminal of the second P-type transistor is electrically connected to the second control line;

[0021] a third N-type transistor, wherein a source of the third N-type transistor is grounded, a drain of the third N-type transistor is electrically connected to the control signal output terminal, and a control terminal of the third N-type transistor is electrically connected to the second control line;

[0022] a fourth N-type transistor, wherein a source of the fourth N-type transistor is grounded, a drain of the fourth N-type transistor is electrically connected to the control signal output terminal, and a control terminal of the fourth N-type transistor is electrically connected to the fourth control line.

[0023] In an exemplary embodiment of the present disclosure, the circuit structure further includes:

[0024] a fifth control line, located between the third control line and the fourth control line and adjacent to the third control line or the fourth control line, the fifth control line comprising a fifth connecting line and a sixth connecting line spliced ​​and distributed along the first direction, the fifth connecting line and the sixth connecting line being distributed on different layers; the fifth connecting line being distributed on the same layer as the first connecting line, the first sub-segment, and the third connecting line, the sixth connecting line being distributed on the same layer as the second connecting line, the second sub-segment, and the fourth connecting line, the first sub-segment being connected to the second connecting line via a first conductive post, and the second sub-segment being connected to the third connecting line via a second conductive post; or the fifth connecting line being distributed on the same layer as the first connecting line, the second sub-segment, and the third connecting line, the sixth connecting line being distributed on the same layer as the second connecting line, the first sub-segment, and the fourth connecting line, the first sub-segment being connected to the first connecting line via a first conductive post, the second sub-segment being connected to the fourth connecting line via a second conductive post, and the sixth connecting line being connected to the fifth connecting line via a third conductive post;

[0025] The third circuit connects the third control line, the fourth control line and the fifth control line.

[0026] In an exemplary embodiment of the present disclosure, the third circuit includes:

[0027] a third P-type transistor, wherein a source of the third P-type transistor is electrically connected to the third control line, a drain of the third P-type transistor is electrically connected to the control signal output terminal, and a control terminal of the third P-type transistor is electrically connected to the fifth control line;

[0028] a fifth N-type transistor, wherein a source of the fifth N-type transistor is grounded, a drain of the fifth N-type transistor is electrically connected to the control signal output terminal, and a control terminal of the fifth N-type transistor is electrically connected to the fifth control line;

[0029] a sixth N-type transistor, wherein the source of the sixth N-type transistor is grounded, the drain of the sixth N-type transistor is electrically connected to the control signal output terminal, and the control terminal of the sixth N-type transistor is electrically connected to the fourth control line.

[0030] According to one aspect of the present disclosure, a memory is provided, comprising any one of the circuit structures described above.

[0031] In an exemplary embodiment of the present disclosure, the first circuit of the circuit structure includes a first control signal output terminal, the second circuit of the circuit structure includes a second control signal output terminal, and the memory further includes:

[0032] a first word line electrically connected to the first control signal output terminal;

[0033] The second word line is electrically connected to the second control signal output terminal.

[0034] In an exemplary embodiment of the present disclosure, the memory further includes a decoding circuit, configured to provide a first signal to the first control line, a second signal to the third control line, and a third signal to the fourth control line.

[0035] In an exemplary embodiment of the present disclosure, the memory further includes a first storage area and a second storage area, and the first sub-line segment between the first connecting line and the second connecting line and the second sub-line segment between the third connecting line and the fourth connecting line are both located between the first storage area and the second storage area.

[0036] In an exemplary embodiment of the present disclosure, when the circuit structure includes a fifth control line and a third circuit, the third circuit includes a third control signal output terminal, and the memory further includes:

[0037] The third word line is electrically connected to the third control signal output terminal.

[0038] According to one aspect of the present disclosure, a circuit structure control method is provided, for controlling any one of the circuit structures described above, wherein a first circuit of the circuit structure includes a first control signal output terminal, the first control signal output terminal being electrically connected to a first word line, the control method comprising:

[0039] inputting a first signal to the first control line;

[0040] inputting a second signal to the third control line;

[0041] inputting a third signal to the fourth control line;

[0042] The first word line electrically connected to the first control signal output terminal is turned on according to the first signal, the second signal, and the third signal.

[0043] In the circuit structure, control method, and memory disclosed herein, since the third control line is located on the side of the second control line away from the first control line, the first connection line of the third control line is located between the second control line and the third connection line of the fourth control line, and the fourth connection line of the fourth control line is located between the second control line and the second connection line of the third control line, the fourth connection line can be used to separate the second control line from the second connection line, thereby preventing the second connection line from being adjacent to the second control line. This effectively increases the distance between the second control line and the second connection line, reduces the coupling capacitance between the third control line and the second control line, and thus reduces the probability of coupling between the third control line and the second control line. When signals are input to the first, third, and fourth control lines via the first circuit, the coupling between the second control line and the third control line can be reduced, reducing the probability of the second control line being erroneously selected, thereby helping to improve product yield.

[0044] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0046] Figure 1 Schematic diagram of the circuit structure in an embodiment of the present disclosure.

[0047] Figure 2 FIG. 1 is a partially enlarged schematic diagram of the third control line and the fourth control line in one embodiment of the present disclosure.

[0048] Figure 3 FIG. 1 is a partially enlarged schematic diagram of the third control line and the fourth control line in one embodiment of the present disclosure.

[0049] Figure 4 Schematic diagram of the first circuit in an embodiment of the present disclosure.

[0050] Figure 5 Schematic diagram of the second circuit in an embodiment of the present disclosure.

[0051] Figure 6 Schematic diagram of the third circuit in an embodiment of the present disclosure.

[0052] Figure 7 Schematic diagram of the circuit structure in the embodiment of the present disclosure.

[0053] Figure 8Schematic diagram of a memory in an embodiment of the present disclosure.

[0054] Figure 9 Flowchart of a control method of a circuit structure in an embodiment of the present disclosure.

[0055] Description of reference numerals:

[0056] 1. First control line; 2. Second control line; 3. Third control line; 31. First connecting line; 32. Second connecting line; 33. First sub-segment; 34. First conductive column; 4. Fourth control line; 41. Third connecting line; 42. Fourth connecting line; 43. Second sub-segment; 44. Second conductive column; 5. Fifth control line; 51. Fifth connecting line; 52. Sixth connecting line; 53. Third conductive column; 6. First contact structure; 7. Second contact structure; 8. Third contact structure; 9. Fourth contact structure; 100. First circuit; P1. First P-type transistor; N1. First N-type transistor ; N2, second N-type transistor; P2, second P-type transistor; N3, third N-type transistor; N4, fourth N-type transistor; P3, third P-type transistor; N5, fifth N-type transistor; N6, sixth N-type transistor; 101, control signal output terminal; 200, decoding circuit; 300, second circuit; 400, third circuit; 500, storage unit; 501, first storage unit; 502, second storage unit; 600, amplifier circuit; 700, bit line; A, first area; B, second area; C, array area; a, wiring area; x, first direction; y, second direction. DETAILED DESCRIPTION

[0057] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent identical or similar structures, and thus their detailed descriptions will be omitted. Furthermore, the figures are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0058] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to indicate open-ended inclusion and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc.; the terms "first", "second", "third" and "fourth" are used only as labels and do not limit the quantity of their objects. These terms distinguish a first element from another element. For example, without departing from the scope of this application, a first control line may be referred to as a second control line, and similarly, a second control line may be referred to as a first control line. Both the first control line and the second control line are control lines, but they are not the same control line.

[0059] The present disclosure provides a circuit structure, which may be a circuit in a memory, such as Figure 1 As shown, the circuit structure may include a first control line 1, a second control line 2, a third control line 3, a fourth control line 4, a first circuit 100 and a second circuit 300, wherein:

[0060] The first control line 1 and the second control line 2 both extend along the first direction x and are arranged at intervals along the second direction y, and the first direction x intersects the second direction y;

[0061] The third control line 3 is located on a side of the second control line 2 away from the first control line 1 and includes a first connecting line 31 and a second connecting line 32 connected to each other. The first connecting line 31 and the second connecting line 32 both extend along the first direction x.

[0062] The fourth control line 4 includes a third connection line 41 and a fourth connection line 42 connected to each other. The first connection line 31 is located between the second control line 2 and the third connection line 41. The fourth connection line 42 is located between the second control line 2 and the second connection line 32. The third connection line 41 and the fourth connection line 42 both extend along the first direction x.

[0063] The first circuit 100 connects the first control line 1, the third control line 3 and the fourth control line 4;

[0064] The second circuit 300 connects the second control line 2 , the third control line 3 , and the fourth control line 4 .

[0065] In the circuit structure disclosed herein, since the third control line 3 is located on the side of the second control line 2 away from the first control line 1, the first connection line 31 of the third control line 3 is located between the second control line 2 and the third connection line 41 of the fourth control line 4, and the fourth connection line 42 of the fourth control line 4 is located between the second control line 2 and the second connection line 32 of the third control line 3, the fourth connection line 42 can separate the second control line 2 from the second connection line 32, preventing the second connection line 32 from being adjacent to the second control line 2. This effectively increases the distance between the second control line 2 and the second connection line 32, reduces the coupling capacitance between the third control line 3 and the second control line 2, and thus reduces the probability of coupling between the third control line 3 and the second control line 2. When signals are input to the first control line 1, the third control line 3, and the fourth control line 4 through the first circuit 100, the coupling between the second control line 2 and the third control line 3 can be reduced, reducing the probability of the second control line 2 being erroneously selected, thereby helping to improve product yield and the spacing distribution in the first direction x. In some embodiments of the present disclosure, the spacing between the first connection line 31 and the second control line 2 is different from the spacing between the second connection line 32 and the second control line 2. For example, the spacing between the second connection line 32 and the second control line 2 is greater than the spacing between the first connection line 31 and the second control line 2. The first connection line 31 is adjacent to the second control line 2, and other wiring may be provided between the second connection line 32 and the second control line 2.

[0066] In an exemplary embodiment of the present disclosure, Figure 2 As shown, the third control line 3 may further include a first sub-segment 33, which may be connected between the first connection line 31 and the second connection line 32. In the first direction x, the first connection line 31, the first sub-segment 33 and the second connection line 32 may be connected in sequence.

[0067] The fourth control line 4 may also be located on a side of the second control line 2 away from the first control line 1. For example, the first control line 1, the second control line 2, and the fourth control line 4 may be sequentially spaced apart along the second direction y. The fourth control line 4 may be used to transmit control signals and may be made of a conductive material, such as aluminum or copper. Of course, other materials with good conductivity may also be used, which are not listed here.

[0068] In an exemplary embodiment of the present disclosure, the fourth control line 4 may include a third connection line 41 and a fourth connection line 42 connected to each other, the third connection line 41 and the fourth connection line 42 may both extend along the first direction x, the third connection line 41 and the fourth connection line 42 are not on the same horizontal line, the third connection line 41 and the fourth connection line 42 may be parallel to each other and spaced apart in the first direction x. In some embodiments of the present disclosure, the spacing between the third connection line 41 and the second control line 2 is different from the spacing between the fourth connection line 42 and the second control line 2. For example, the spacing between the third connection line 41 and the second control line 2 is greater than the spacing between the fourth connection line 42 and the second control line 2. The first connection line 31 may be located between the second control line 2 and the third connection line 41, and the fourth connection line 42 may be located between the second control line 2 and the second connection line 32.

[0069] In an exemplary embodiment of the present disclosure, the fourth control line 4 may further include a second sub-segment 43, which may be connected between the third connecting line 41 and the fourth connecting line 42. The second sub-segment 43 and the first sub-segment 33 may be insulated from each other. In the first direction x, the third connecting line 41, the second sub-segment 43, and the fourth connecting line 42 may be connected in sequence. The second sub-segment 43 and the first sub-segment 33 may intersect within the distribution space. For example, during the circuit structure manufacturing process, the first sub-segment 33 and the second sub-segment 43 may be arranged in different layers, and the orthographic projection of the first sub-segment 33 within the wiring area a of the circuit structure partially overlaps with the orthographic projection of the second sub-segment 43 within the wiring area a of the circuit structure.

[0070] For example, if Figure 2 As shown, the first connecting line 31, the second connecting line 32, the third connecting line 41, the fourth connecting line 42 and the second sub-segment 43 can all be located in the same layer, and the first sub-segment 33 and the first connecting line 31, the second connecting line 32, the second sub-segment 43, the third connecting line 41 and the fourth connecting line 42 are located in different layers. For example, a first contact structure 6 can be formed on the surface of the first connecting line 31, and a second contact structure 7 can be formed on the surface of the second connecting line 32. One end of the first sub-segment 33 can be connected to the end of the first contact structure 6 away from the first connecting line 31, and the other end of the first sub-segment 33 can be connected to the end of the second contact structure 7 away from the second connecting line 32, thereby making the first sub-segment 33 and the first connecting line 31, the second connecting line 32, the second sub-segment 43, the third connecting line 41 and the fourth connecting line 42 located in different layers. Optionally, as Figure 3As shown, the first connecting line 31, the second connecting line 32, the third connecting line 41 and the fourth connecting line 42 can all be located in the same layer, the first sub-segment 33 and the first connecting line 31, the second connecting line 32, the third connecting line 41 and the fourth connecting line 42 are located in different layers, and the second sub-segment 43 and the first connecting line 31, the second connecting line 32, the first sub-segment 33, the third connecting line 41 and the fourth connecting line 42 are all located in different layers. For example, a first contact structure 6 can be formed on the surface of the first connecting line 31, and a second contact structure 7 can be formed on the surface of the second connecting line 32. One end of the first sub-segment 33 can be connected to the end of the first contact structure 6 away from the first connecting line 31, and the other end of the first sub-segment 33 can be connected to the end of the second contact structure 7 away from the second connecting line 32, so that the first sub-segment 33 and the first connecting line 31, the second connecting line 32, the second sub-segment 43, the third connecting line 41 and the fourth connecting line 42 are located in different layers. At the same time, a third contact structure 8 can be formed on the surface of the third connecting line 41, and a fourth contact structure 9 can be formed on the surface of the fourth connecting line 42; the top ends of the third contact structure 8 and the fourth contact structure 9 are both higher than the top surface of the first sub-segment 33, or the top ends of the third contact structure 8 and the fourth contact structure 9 are both lower than the top ends of the first contact structure 6 and the second contact structure 7, one end of the second sub-segment 43 can be connected to the end of the third contact structure 8 away from the third connecting line 41, and the other end of the second sub-segment 43 can be connected to the end of the fourth contact structure 9 away from the fourth connecting line 42, and when the top ends of the third contact structure 8 and the fourth contact structure 9 are both lower than the top ends of the first contact structure 6 and the second contact structure 7, the top surface of the second sub-segment 43 is lower than the surface of the first sub-segment 33 close to the top ends of the first contact structure 6 and the second contact structure 7, thereby making the second sub-segment 43 and the first connecting line 31, the second connecting line 32, the first sub-segment 33, the third connecting line 41 and the fourth connecting line 42 all located in different layers.

[0071] like Figure 4 As shown, the first circuit 100 may include a plurality of control signal input terminals and at least one control signal output terminal 101. For example, it may include three control signal input terminals, which may be electrically connected to the first control line 1, the third control line 3, and the fourth control line 4, respectively. By applying control signals to the first control line 1, the third control line 3, and the fourth control line 4, respectively, the output signal of the control signal output terminal 101 of the first circuit 100 can be controlled.

[0072] In an exemplary embodiment of the present disclosure, the first circuit 100 may include a first P-type transistor (P1), a first N-type transistor (N1), and a second N-type transistor (N2), wherein:

[0073] The source of the first P-type transistor (P1) can serve as the first control signal input terminal of the first circuit 100, which can be electrically connected to the third control line 3, and then the control signal can be input to the first circuit 100 through the third control line 3. The drain of the first P-type transistor (P1) is electrically connected to the control signal output terminal 101, and the control terminal of the first P-type transistor (P1) can be electrically connected to the second control signal input terminal of the first circuit 100; the source of the first N-type transistor (N1) is grounded, the drain of the first N-type transistor (N1) is electrically connected to the control signal output terminal 101, and the control terminal of the first N-type transistor (N1) can also be electrically connected to the second control signal input terminal of the first circuit 100, and the second A control signal input terminal can be electrically connected to the first control line 1, and a control signal can be applied to the first circuit 100 through the first control line 1; the source of the second N-type transistor (N2) is grounded, and the drain of the second N-type transistor (N2) is electrically connected to the control signal output terminal 101. The control terminal of the second N-type transistor (N2) can serve as the third control signal input terminal of the first circuit 100, which can be electrically connected to the fourth control line 4, and a control signal can be applied to the first circuit 100 through the fourth control line 4; it should be noted that the types of signals applied to the first circuit 100 by the first control line 1, the third control line 3 and the fourth control line 4 can be the same or different, and no special limitation is made here.

[0074] For example, a low potential can be provided to the first control line 1, a low potential can be provided to the fourth control line 4, and a high potential can be provided to the third control line 3. In this case, the first P-type transistor (P1) is turned on, the first N-type transistor (N1) and the second N-type transistor (N2) are both turned off, and the control signal output terminal 101 outputs a high potential. In the standby state, a high potential can be provided to the first control line 1, a high potential can be provided to the fourth control line 4, and a low potential can be provided to the third control line 3. In this case, the first P-type transistor (P1) is turned off, the first N-type transistor (N1) and the second N-type transistor (N2) are both turned on, and the control signal output terminal 101 outputs a low potential. In the above process, since the distance between the second connection line 32 of the third control line 3 and the second control line 2 is relatively far, the coupling capacitance between the third control line 3 and the second control line 2 can be reduced to a certain extent, thereby reducing the probability of coupling between the third control line 3 and the second control line 2. When inputting signals to the first control line 1, the third control line 3 and the fourth control line 4, the probability of the second control line 2 being misselected is low due to the small coupling effect between the second control line 2 and the third control line 3, which can improve product yield.

[0075] like Figure 5As shown, the second circuit 300 may include multiple control signal input terminals and a control signal output terminal 301. For example, it may include three control signal input terminals, which may be electrically connected to the second control line 2, the third control line 3, and the fourth control line 4, respectively. By applying control signals to the second control line 2, the third control line 3, and the fourth control line 4, respectively, the output signal of the control signal output terminal 301 of the second circuit 300 can be controlled.

[0076] The structure of the second circuit 300 is substantially the same as that of the first circuit 100. Figure 5 For example, the second circuit 300 may also include a second P-type transistor (P2), a third N-type transistor (N3), and a fourth N-type transistor (N4), wherein:

[0077] The source of the second P-type transistor (P2) can serve as the first control signal input terminal of the second circuit 300, which can be electrically connected to the third control line 3, and then the control signal can be input to the second circuit 300 through the third control line 3. The drain of the second P-type transistor (P2) is electrically connected to the control signal output terminal 101, and the control terminal of the second P-type transistor (P2) can be electrically connected to the second control signal input terminal of the second circuit 300; the source of the third N-type transistor (N3) is grounded, the drain of the third N-type transistor (N3) is electrically connected to the control signal output terminal 101, and the control terminal of the third N-type transistor (N3) can also be electrically connected to the second control signal input terminal of the second circuit 300, and the second The control signal input terminal can be electrically connected to the second control line 2, and the control signal can be applied to the second circuit 300 through the second control line 2; the source of the fourth N-type transistor (N4) is grounded, and the drain of the fourth N-type transistor (N4) is electrically connected to the control signal output terminal 101. The control terminal of the fourth N-type transistor (N4) can serve as the third control signal input terminal of the second circuit 300, which can be electrically connected to the fourth control line 4, and the control signal can be applied to the second circuit 300 through the fourth control line 4; it should be noted that the types of signals applied to the second circuit 300 by the second control line 2, the third control line 3 and the fourth control line 4 can be the same or different, and no special limitation is made here.

[0078] In the process of applying a control signal to the third control line 3 when the first control line 1 needs to be selected (the second control line 2 does not need to be selected at this time), since the distance between the second connecting line 32 of the third control line 3 and the second control line 2 is large, the coupling effect between the second control line 2 and the third control line 3 is small. After the control signal is applied to the third control line 3, the probability of the second control line 2 being misselected is low, which can improve the product yield.

[0079] In an exemplary embodiment of the present disclosure, Figure 6As shown, the circuit structure of the present disclosure may further include a fifth control line 5 and a third circuit 400, wherein:

[0080] Continue to see Figure 1 As shown, the fifth control line 5 may be located between the third control line 3 and the fourth control line 4, and may be adjacent to at least a portion of the third control line 3 or the fourth control line 4. For example, the fifth control line 5 may be adjacent to the first connection line 31 of the third control line 3, and the spacing between the fifth control line 5 and the second connection line 32 of the third control line 3 is greater than the spacing between the fifth control line 5 and the first connection line 31 of the third control line 3. Alternatively, the fifth control line 5 may be adjacent to the third connection line 41 of the fourth control line 4, and the spacing between the fifth control line 5 and the fourth connection line 42 of the fourth control line 4 is greater than the spacing between the fifth control line 5 and the third connection line 41 of the fourth control line 4.

[0081] In an exemplary embodiment of the present disclosure, Figure 7 As shown, the fifth control line 5 may include a fifth connection line 51 and a sixth connection line 52 both extending along the first direction x. In the first direction x, the fifth connection line 51 and the sixth connection line 52 can be spliced, and the fifth connection line 51 and the sixth connection line 52 can be distributed in different layers. The fifth connection line 51 can be distributed in the same layer as the first connection line 31, the first sub-segment 33 and the third connection line 41; the sixth connection line 52 is distributed in the same layer as the second connection line 32, the second sub-segment 43 and the fourth connection line 42; the first sub-segment 33 can be connected to the second connection line 32 through the first conductive column 34; the second sub-segment 43 and the third connection line 41 can be connected through the second conductive column 44; the sixth connection line 52 can be connected to the fifth connection line 51 through the third conductive column 53. The fifth connecting line 51, the first connecting line 31, the first sub-segment 33 and the third connecting line 41 may be located in the lower layer of the sixth connecting line 52, the second connecting line 32, the second sub-segment 43 and the fourth connecting line 42, or the fifth connecting line 51, the first connecting line 31, the first sub-segment 33 and the third connecting line 41 may be located in the upper layer of the sixth connecting line 52, the second connecting line 32, the second sub-segment 43 and the fourth connecting line 42, without special limitation here.

[0082] In other embodiments of the present disclosure, the fifth connecting line 51 is distributed on the same layer as the first connecting line 31, the second sub-segment 43, and the third connecting line 41, and the sixth connecting line 52 is distributed on the same layer as the second connecting line 32, the first sub-segment 33, and the fourth connecting line 42. The first sub-segment 33 is connected to the first connecting line 31 via a first conductive post; the second sub-segment 43 is connected to the fourth connecting line 42 via a second conductive post; and the sixth connecting line 52 is connected to the fifth connecting line 51 via a third conductive post. The fifth connecting line 51, the first connecting line 31, the second sub-segment 43, and the third connecting line 41 may be located below the sixth connecting line 52, the second connecting line 32, the first sub-segment 33, and the fourth connecting line 42, or the fifth connecting line 51, the first connecting line 31, the second sub-segment 43, and the third connecting line 41 may be located above the sixth connecting line 52, the second connecting line 32, the first sub-segment 33, and the fourth connecting line 42, without any special limitation herein.

[0083] like Figure 6 As shown, the third circuit 400 may include multiple control signal input terminals and a control signal output terminal 401. For example, it may include three control signal input terminals, which may be electrically connected to the fifth control line 5, the third control line 3, and the fourth control line 4, respectively. By applying control signals to the fifth control line 5, the third control line 3, and the fourth control line 4, respectively, the output signal of the control signal output terminal 401 of the third circuit 400 can be controlled.

[0084] In an exemplary embodiment of the present disclosure, the structure of the third circuit 400 is the same as that of the first circuit 100 and / or the second circuit 300. For details, see Figure 6 For example, the third circuit 400 may also include a third P-type transistor (P3), a fifth N-type transistor (N5), and a sixth N-type transistor (N6), wherein:

[0085] The source of the third P-type transistor (P3) can serve as the first control signal input terminal of the third circuit 400, and can be electrically connected to the third control line 3, and can further input the control signal to the third circuit 400 through the third control line 3. The drain of the third P-type transistor (P3) is electrically connected to the control signal output terminal 101, and the control terminal of the third P-type transistor (P3) can be electrically connected to the second control signal input terminal of the third circuit 400; the source of the fifth N-type transistor (N5) is grounded, the drain of the fifth N-type transistor (N5) is electrically connected to the control signal output terminal 101, and the control terminal of the fifth N-type transistor (N5) can also be electrically connected to the second control signal input terminal of the third circuit 400, and the second The control signal input terminal can be electrically connected to the fifth control line 5, and the control signal can be applied to the third circuit 400 through the fifth control line 5; the source of the sixth N-type transistor (N6) is grounded, and the drain of the sixth N-type transistor (N6) is electrically connected to the control signal output terminal 101. The control terminal of the sixth N-type transistor (N6) can serve as the third control signal input terminal of the third circuit 400, which can be electrically connected to the fourth control line 4, and the control signal can be applied to the third circuit 400 through the fourth control line 4; it should be noted that the types of signals applied to the third circuit 400 by the fifth control line 5, the third control line 3 and the fourth control line 4 can be the same or different, and no special limitation is made here.

[0086] When the fifth control line 5 is adjacent to the first connection line 31 of the third control line 3, and the distance between the fifth control line 5 and the second connection line 32 of the third control line 3 is greater than the distance between the fifth control line 5 and the first connection line 31 of the third control line 3, in the process of applying a control signal to the third control line 3 when the first control line 1 needs to be selected (the fifth control line 5 does not need to be selected at this time), due to the larger distance between the second connection line 32 of the third control line 3 and the fifth control line 5, the coupling effect between the fifth control line 5 and the third control line 3 is smaller, and after the control signal is applied to the third control line 3, the probability of the fifth control line 5 being mistakenly selected is lower. Alternatively, when the fifth control line 5 is adjacent to the third connection line 41 of the fourth control line 4, and the spacing between the fifth control line 5 and the fourth connection line 42 of the fourth control line 4 is greater than the spacing between the fifth control line 5 and the third connection line 41 of the fourth control line 4, since the spacing between the fifth control line 5 and the fourth connection line 42 of the fourth control line 4 is larger, the coupling effect between the fifth control line 5 and the fourth control line 4 is smaller, and after applying the control signal to the fourth control line 4, the probability of the fifth control line 5 being misselected is lower.

[0087] In an exemplary embodiment of the present disclosure, there are multiple third control lines 3 and multiple fourth control lines 4. The third control line 3 connected to the first circuit 100, the third control line 3 connected to the second circuit 300, and the third control line 3 connected to the third circuit 400 are all different third control lines 3. At the same time, the fourth control line 4 connected to the first circuit 100, the fourth control line 4 connected to the second circuit 300, and the fourth control line 4 connected to the third circuit 400 are also different fourth control lines 4. That is, the first circuit 100, the second circuit 300, and the third circuit 400 are respectively connected to different third control lines 3, and at the same time, the first circuit 100, the second circuit 300, and the third circuit 400 are respectively connected to different fourth control lines 4.

[0088] It should be noted that the circuit structure of the present disclosure may also include other control lines, each of which may extend along the first direction X, and each of which may be spaced apart along the second direction y. The number of control lines in the circuit structure of the present disclosure is not particularly limited.

[0089] In an exemplary embodiment of the present disclosure, continue to refer to Figure 1 As shown, the circuit structure of the present disclosure may include a first area A and a second area B. The first area A and the second area B may be spaced apart. For example, the first area A and the second area B may be spaced apart side by side along the first direction x. Of course, the first area A and the second area B may also be spaced apart along other directions, which is not particularly limited here. In some embodiments of the present disclosure, the first control line 1, the second control line 2, the third control line 3, the fourth control line 4, and the fifth control line 5 may all pass through the first area A and the second area B. For example, the first connection line 31 of the third control line 3 may pass through the first area A, the second connection line 32 of the third control line 3 may pass through the second area B, and a control signal may be provided to the first area A through the first connection line 31; the third connection line 41 of the fourth control line 4 may pass through the first area A, the fourth connection line 42 of the fourth control line 4 may pass through the second area B, and a control signal may be provided to the second area B through the fourth connection line 42.

[0090] In an exemplary embodiment of the present disclosure, the first sub-segment 33 between the first connecting line 31 and the second connecting line 32 may be located between the first area A and the second area B, and at the same time, the second sub-segment 43 between the third connecting line 41 and the fourth connecting line 42 may also be located between the first area A and the second area B.

[0091] The embodiments of the present disclosure also provide a memory, which may include the circuit structure of any of the above embodiments. Some details and beneficial effects of the memory have been described in detail in the corresponding circuit structure, so they will not be repeated here.

[0092] In an exemplary embodiment of the present disclosure, Figure 8 As shown, the memory may further include an array region C and multiple word lines. The array region C may include multiple spaced memory cells 500, each memory cell 500 being connected to a corresponding word line. For example, the memory may include at least a first memory cell 501, a second memory cell 502, a first word line 6, and a second word line 7. The circuit structure of the present disclosure may be located within the array region C, and the first control line 1, the second control line 2, the third control line 3, the fourth control line 4, and the fifth control line 5 may all pass through the multiple memory cells 500. The first circuit 100 may be located within the first memory cell 501, and the control signal output terminal 101 of the first circuit 100 may be electrically connected to the first word line 6. The second circuit 300 may be located within the second memory cell 502, and the control signal output terminal 301 of the second circuit 300 may be electrically connected to the second word line 7. The control signal output terminal 101 of the first circuit 100 may be defined as the first control signal output terminal 101, and the control signal output terminal 301 of the second circuit 300 may be defined as the second control signal output terminal 301. The first word line 6 can be opened or closed by controlling the potential output by the first control signal output terminal 101. For example, when the potential output by the first control signal output terminal 101 is a high potential, the first word line 6 is opened, and when the potential output by the first control signal output terminal is a low potential, the first word line 6 is disconnected. Correspondingly, the second word line 7 can be opened or closed by controlling the potential output by the second control signal output terminal 301. For example, when the potential output by the second control signal output terminal 301 is a high potential, the second word line 7 is opened, and when the potential output by the second control signal output terminal 301 is a low potential, the second word line 7 is disconnected.

[0093] In an exemplary embodiment of the present disclosure, continue to refer to Figure 1 As shown, the memory disclosed in the present invention may also include a decoding circuit 200, which may be electrically connected to the first control line 1, the third control line 3 and the fourth control line 4. The decoding circuit 200 may provide a first signal to the first control line 1, a second signal to the third control line 3, and a third signal to the fourth control line 4.

[0094] When it is necessary to open the first word line 6, the first signal may be a low-potential signal, the second signal may be a high-potential signal, and the third signal may be a low-potential signal; that is, the decoding circuit 200 may provide a low potential to the first control line 1, a high potential to the third control line 3, and a low potential to the fourth control line 4. At this time, the first P-type transistor (P1) in the first circuit 100 is turned on, the first N-type transistor (N1) and the second N-type transistor (N2) are both turned off, the control signal output terminal 101 of the first circuit 100 outputs a high potential, and the first word line 6 is turned on. In the standby state, the first signal may be a high-voltage signal, the second signal may be a low-voltage signal, and the third signal may be a high-voltage signal; that is, the decoding circuit 200 may provide a high voltage to the first control line 1, a low voltage to the third control line 3, and a high voltage to the fourth control line 4. At this time, the first P-type transistor (P1) in the first circuit 100 is disconnected, the first N-type transistor (N1) and the second N-type transistor (N2) are both turned on, the control signal output terminal 101 of the first circuit 100 outputs a low voltage, and the first word line 6 is turned off.

[0095] In the embodiment of the present disclosure, the principle of opening or closing the second word line 7 is similar to the principle of opening or closing the first word line 6 , and therefore, it will not be described in detail here.

[0096] In some embodiments of the present disclosure, when the circuit structure includes the fifth control line 5 and the third circuit 400, the control signal output terminal 401 of the third circuit 400 can be defined as the third control signal output terminal 401. The memory of the present disclosure may further include a third word line 8, which is electrically connected to the third control signal output terminal 401. The third word line 8 can be controlled to be turned on or off by the potential output by the third control signal output terminal 401. For example, when the potential output by the third control signal output terminal 401 is a high potential, the third word line 8 is turned on, and when the potential output by the third control signal output terminal 401 is a low potential, the third word line 8 is turned off.

[0097] In some embodiments of the present disclosure, the memory of the present disclosure may also include an amplifier circuit 600 and multiple bit lines 700. Each storage unit 500 can be electrically connected to a bit line 700 accordingly, and the amplifier circuit 600 can also be electrically connected to the bit line 700. The external signal can be amplified by the amplifier circuit 600, and the amplified signal can be input into the bit line 700.

[0098] In an exemplary embodiment of the present disclosure, the memory of the present disclosure may be a dynamic random access memory (DRAM), a static random access memory (SRAM), etc. Of course, other storage devices may also be used, which are not listed here one by one.

[0099] The present disclosure also provides a circuit structure control method for controlling the circuit structure in any of the above embodiments. Figure 9 A flow chart showing a control method of the circuit structure of the present disclosure is shown. Figure 9 As shown, the control method of the present disclosure includes steps S110 to S140, wherein:

[0100] Step S110, inputting a first signal to the first control line;

[0101] Step S120, inputting a second signal to the third control line;

[0102] Step S130, inputting a third signal to the fourth control line;

[0103] Step S140 , turning on the first word line electrically connected to the first control signal output terminal according to the first signal, the second signal, and the third signal.

[0104] When the first word line 6 needs to be turned on, the first signal can be a low-voltage signal, the second signal can be a high-voltage signal, and the third signal can be a low-voltage signal; that is, a low voltage can be provided to the first control line 1, a high voltage can be provided to the third control line 3, and a low voltage can be provided to the fourth control line 4. At this time, the first P-type transistor (P1) in the first circuit 100 is turned on, the first N-type transistor (N1) and the second N-type transistor (N2) are turned off, the first control signal output terminal 101 outputs a high voltage, and the first word line 6 is turned on. In the standby state, the first signal can be a high-voltage signal, the second signal can be a low-voltage signal, and the third signal can be a high-voltage signal; that is, a high voltage can be provided to the first control line 1, a low voltage can be provided to the third control line 3, and a high voltage can be provided to the fourth control line 4. At this time, the first P-type transistor (P1) in the first circuit 100 is turned off, the first N-type transistor (N1) and the second N-type transistor (N2) are turned on, the first control signal output terminal 101 outputs a low voltage, and the first word line 6 is turned off.

[0105] In the embodiment of the present disclosure, after providing a low potential to the first control line 1, a high potential to the third control line 3, and a low potential to the fourth control line 4, the potential within the second word line 7 connected to the second circuit 300 can be simultaneously detected to determine the risk of second word line 7 being turned on, thereby determining whether the circuit structure of the present disclosure can reduce the probability of erroneous turning on of the second word line 7. Actual measurements have shown that after providing a low potential to the first control line 1, a high potential to the third control line 3, and a low potential to the fourth control line 4, the potential within the second word line 7 is significantly lower than the potential within the first word line 6, and the potential within the second word line 7 is insufficient to turn on the second word line 7. Therefore, the circuit structure of the present disclosure can reduce the probability of erroneous turning on of the second word line 7 to a certain extent, thereby improving product yield.

[0106] It should be noted that although the steps of the control method of the circuit structure in the present disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in this specific order, or that all steps must be performed to achieve the desired results. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps.

[0107] The present disclosure also provides an electronic device, which may include the memory in any of the above embodiments. The specific details and beneficial effects have been described in detail in the corresponding circuit structure and memory embodiments, so they will not be repeated here.

[0108] For example, the electronic device may be a battery-powered mobile device such as a mobile phone, a tablet computer, or a wearable device.

[0109] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the appended claims.

Claims

1. A circuit structure, characterized in that: include: a first control line and a second control line, wherein the first control line and the second control line both extend along a first direction and are arranged at intervals along a second direction, and the first direction intersects the second direction; a third control line, located on a side of the second control line away from the first control line, and comprising a first connecting line and a second connecting line connected to each other, wherein the first connecting line and the second connecting line both extend along the first direction; fourth control lines, comprising a third connection line and a fourth connection line connected to each other, wherein the first connection line is located between the second control line and the third connection line, the fourth connection line is located between the second control line and the second connection line, and the third connection line and the fourth connection line both extend along the first direction; a first circuit connecting the first control line, the third control line, and the fourth control line; a second circuit connecting the second control line, the third control line, and the fourth control line; The first circuit includes: a first P-type transistor, wherein a source of the first P-type transistor is electrically connected to the third control line, a drain of the first P-type transistor is electrically connected to the control signal output terminal, and a control terminal of the first P-type transistor is electrically connected to the first control line; a first N-type transistor, wherein a source of the first N-type transistor is grounded, a drain of the first N-type transistor is electrically connected to the control signal output terminal, and a control terminal of the first N-type transistor is electrically connected to the first control line; a second N-type transistor, wherein a source of the second N-type transistor is grounded, a drain of the second N-type transistor is electrically connected to the control signal output terminal, and a control terminal of the second N-type transistor is electrically connected to the fourth control line; The second circuit includes: a second P-type transistor, wherein a source of the second P-type transistor is electrically connected to the third control line, a drain of the second P-type transistor is electrically connected to the control signal output terminal, and a control terminal of the second P-type transistor is electrically connected to the second control line; a third N-type transistor, wherein a source of the third N-type transistor is grounded, a drain of the third N-type transistor is electrically connected to the control signal output terminal, and a control terminal of the third N-type transistor is electrically connected to the second control line; a fourth N-type transistor, wherein a source of the fourth N-type transistor is grounded, a drain of the fourth N-type transistor is electrically connected to the control signal output terminal, and a control terminal of the fourth N-type transistor is electrically connected to the fourth control line.

2. The circuit structure according to claim 1, wherein: The third control line further includes a first sub-line segment, and the first sub-line segment is connected between the first connecting line and the second connecting line; The fourth control line also includes a second sub-line segment, which is connected between the third connecting line and the fourth connecting line. The first sub-line segment and the second sub-line segment are insulated from each other, and the orthographic projection of the first sub-line segment in the wiring area corresponding to the circuit structure partially overlaps with the orthographic projection of the second sub-line segment in the wiring area.

3. The circuit structure according to claim 2, wherein: The circuit structure further includes: a fifth control line, located between the third control line and the fourth control line and adjacent to the third control line or the fourth control line, the fifth control line comprising a fifth connecting line and a sixth connecting line spliced ​​and distributed along the first direction, the fifth connecting line and the sixth connecting line being distributed on different layers; the fifth connecting line being distributed on the same layer as the first connecting line, the first sub-segment, and the third connecting line, the sixth connecting line being distributed on the same layer as the second connecting line, the second sub-segment, and the fourth connecting line, the first sub-segment being connected to the second connecting line via a first conductive post, and the second sub-segment being connected to the third connecting line via a second conductive post; or the fifth connecting line being distributed on the same layer as the first connecting line, the second sub-segment, and the third connecting line, the sixth connecting line being distributed on the same layer as the second connecting line, the first sub-segment, and the fourth connecting line, the first sub-segment being connected to the first connecting line via a first conductive post, the second sub-segment being connected to the fourth connecting line via a second conductive post, and the sixth connecting line being connected to the fifth connecting line via a third conductive post; The third circuit connects the third control line, the fourth control line and the fifth control line.

4. The circuit structure according to claim 3, wherein: The third circuit includes: a third P-type transistor, wherein a source of the third P-type transistor is electrically connected to the third control line, a drain of the third P-type transistor is electrically connected to the control signal output terminal, and a control terminal of the third P-type transistor is electrically connected to the fifth control line; a fifth N-type transistor, wherein a source of the fifth N-type transistor is grounded, a drain of the fifth N-type transistor is electrically connected to the control signal output terminal, and a control terminal of the fifth N-type transistor is electrically connected to the fifth control line; a sixth N-type transistor, wherein the source of the sixth N-type transistor is grounded, the drain of the sixth N-type transistor is electrically connected to the control signal output terminal, and the control terminal of the sixth N-type transistor is electrically connected to the fourth control line.

5. A memory, characterized in that: The invention comprises the circuit structure according to any one of claims 1 to 4.

6. The memory according to claim 5, wherein: The first circuit of the circuit structure includes a first control signal output terminal, the second circuit of the circuit structure includes a second control signal output terminal, and the memory further includes: a first word line electrically connected to the first control signal output terminal; The second word line is electrically connected to the second control signal output terminal.

7. The memory according to claim 6, wherein: The memory further includes a decoding circuit configured to provide a first signal to the first control line, a second signal to the third control line, and a third signal to the fourth control line.

8. The memory according to claim 6, wherein: When the circuit structure includes a fifth control line and a third circuit, the third circuit includes a third control signal output terminal, and the memory further includes: The third word line is electrically connected to the third control signal output terminal.

9. A method for controlling a circuit structure, for controlling the circuit structure according to any one of claims 1 to 4, characterized in that: The first circuit of the circuit structure includes a first control signal output terminal, the first control signal output terminal is electrically connected to the first word line, and the control method includes: inputting a first signal to the first control line; inputting a second signal to the third control line; inputting a third signal to the fourth control line; The first word line electrically connected to the first control signal output terminal is turned on according to the first signal, the second signal, and the third signal.

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