A zq calibration circuit, operation method, memory and storage system

Abstract

Embodiments of the present application disclose a ZQ calibration circuit, an operation method, a memory and a storage system. The ZQ calibration circuit comprises a logic control circuit and a calibration circuit. The logic control circuit comprises a calibration code generation circuit and a mapping conversion circuit. The calibration code generation circuit is configured to generate an initial calibration code in response to a calibration command. The mapping conversion circuit is configured to control the calibration code generation circuit to convert the initial calibration code into a target calibration code of a target adjustment step in response to a code adjustment signal. The calibration circuit is configured to calibrate an interface impedance of a target semiconductor device based on the target calibration code.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to a ZQ calibration circuit, operating method, memory, and storage system. Background Technology

[0002] Semiconductor memories, which include integrated circuits such as microprocessors, memory circuits, and gate array circuits, are currently used in various electronic devices, such as personal computers, server computers, and workstations. As the operating speed of electronic devices increases, impedance mismatch at the memory interface makes high-speed data transmission difficult. Therefore, ZQ calibration is introduced into the memory to calibrate the impedance at the memory interface, thereby ensuring high-speed data transmission. However, the ZQ calibration circuits currently used have relatively fixed calibration methods and cannot flexibly adapt to different calibration scenarios. Summary of the Invention

[0003] In view of this, embodiments of this application provide a ZQ calibration circuit, operating method, memory, and storage system, which can adjust the calibration step size under different calibration scenarios to shorten calibration time or increase calibration accuracy.

[0004] To achieve the above objectives, the technical solution of the present invention is implemented as follows:

[0005] In a first aspect, embodiments of this application provide a ZQ calibration circuit, comprising: a logic control circuit and a calibration circuit; wherein...

[0006] The logic control circuit includes: a calibration code generation circuit and a mapping conversion circuit, wherein: the calibration code generation circuit is configured to generate an initial calibration code in response to a calibration command; and the mapping conversion circuit is configured to control the calibration code generation circuit to convert the initial calibration code into a target calibration code with a target adjustment step size in response to a code adjustment signal.

[0007] The calibration circuit is configured to calibrate the interface impedance of the target semiconductor device based on the target calibration code.

[0008] In the above scheme, the code adjustment signal includes a first sub-adjustment signal and / or a second sub-adjustment signal; the mapping conversion circuit includes a first conversion sub-circuit and / or a second conversion sub-circuit; wherein,

[0009] The first conversion sub-circuit is configured to: in response to the first sub-adjustment signal, control the calibration code generation circuit to convert the initial calibration code into a first target calibration code; the adjustment step size of the first target calibration code is greater than or equal to the adjustment step size of the initial calibration code;

[0010] The second conversion sub-circuit is configured to: in response to the second sub-adjustment signal, control the calibration code generation circuit to convert the initial calibration code into a second target calibration code, wherein the adjustment step size of the second target calibration code is less than or equal to the adjustment step size of the initial calibration code.

[0011] In the above scheme, the mapping conversion circuit includes: a multiplexer MUX; wherein,

[0012] The MUX is configured to: in response to a code adjustment signal, control the calibration code generation circuit to convert the initial calibration code into the target calibration code; the target calibration code includes a first target calibration code or a second target calibration code; the code adjustment signal is generated based on the most significant bit of the initial calibration code.

[0013] In the above scheme, the calibration code generation circuit includes: a comparator and a counter; wherein,

[0014] The comparator is configured to: in response to the calibration command, compare the current voltage across the interface impedance of the target semiconductor device with a reference voltage, generate a comparison result, and output the comparison result;

[0015] The counter, connected to the comparator, is configured to receive the comparison result and generate the initial calibration code based on the comparison result.

[0016] In the above scheme, the calibration code generation circuit further includes: a first flip-flop connected between the comparator and the counter, configured to: receive the comparison result and a first clock signal; sample the comparison result based on the first clock signal and output a control signal;

[0017] The counter is also configured to receive the control signal and the second clock signal, and generate the initial calibration code based on the control signal and the second clock signal.

[0018] In the above scheme, the initial calibration code includes pull-up calibration code and pull-down calibration code; the target calibration code includes pull-up target calibration code and pull-down target calibration code; the code adjustment signal includes pull-up code adjustment signal and pull-down code adjustment signal; the calibration code generation circuit includes pull-up code generation sub-circuit and pull-down code generation sub-circuit; the mapping conversion circuit includes pull-up conversion sub-circuit and pull-down conversion sub-circuit; wherein;

[0019] The pull-up code generation sub-circuit is configured to generate the pull-up calibration code in response to the calibration command;

[0020] The pull-up conversion sub-circuit is configured to: control the pull-up code generation sub-circuit to convert the pull-up calibration code into the pull-up target calibration code in response to the pull-up code adjustment signal;

[0021] The drop-down code generation sub-circuit is configured to generate the drop-down calibration code in response to the calibration command;

[0022] The pull-down conversion sub-circuit is configured to: control the pull-down code generation sub-circuit to convert the pull-down calibration code into the pull-down target calibration code in response to the pull-down code adjustment signal.

[0023] In the above scheme, the calibration circuit includes: a pull-up calibration sub-circuit and a pull-down calibration sub-circuit, wherein,

[0024] The pull-up calibration sub-circuit is configured to perform pull-up calibration on the interface impedance of the target semiconductor device based on the pull-up target calibration code.

[0025] The pull-down calibration sub-circuit is configured to perform pull-down calibration on the interface impedance of the target semiconductor device based on the pull-down target calibration code.

[0026] In the above scheme, the pull-up calibration sub-circuit includes: a pull-up resistor network and a first pull-down resistor network connected in series; the pull-down calibration sub-circuit includes a second pull-down resistor network;

[0027] The pull-up resistor network, the first pull-down resistor network, and the second pull-down resistor network include multiple parallel metal-oxide-semiconductor (MOS) transistors.

[0028] In the above scheme, the ZQ calibration circuit further includes a code output circuit, configured to: receive a latch command; output the target calibration code corresponding to the completion of this calibration based on the latch command; wherein the latch command is generated when the target calibration code corresponding to the completion of this calibration is different from the target calibration code corresponding to the completion of the previous calibration.

[0029] In the above scheme, the code output circuit includes: a pull-up code sub-output circuit; the latch command includes a first sub-latch command; the target calibration code includes a pull-up target calibration code; wherein;

[0030] The pull-up code sub-output circuit includes: a second flip-flop and a third flip-flop connected in series. The second flip-flop is configured to: temporarily store the pull-up target calibration code corresponding to the completion of this calibration. The third flip-flop is configured to: receive a first sub-latch command and output the pull-up target calibration code corresponding to the completion of this calibration based on the first sub-latch command. The first sub-latch command is generated when the pull-up target calibration code corresponding to the completion of this calibration is different from the pull-up target calibration code corresponding to the completion of the previous calibration.

[0031] In the above scheme, the code output circuit includes: a pull-down code sub-output circuit; the latch command includes a second sub-latch command; the target calibration code includes a pull-down target calibration code; wherein;

[0032] The pull-down code sub-output circuit includes a fourth flip-flop and a fifth flip-flop. The fourth flip-flop is configured to temporarily store the pull-down target calibration code corresponding to the completion of the current calibration. The fifth flip-flop is configured to receive a second sub-latch command and output the pull-down target calibration code corresponding to the completion of the current calibration based on the second sub-latch command. The second sub-latch command is generated when the pull-down target calibration code corresponding to the completion of the current calibration is different from the pull-down target calibration code corresponding to the completion of the previous calibration.

[0033] Secondly, embodiments of this application provide a method for operating a memory, the method comprising:

[0034] Generate an initial calibration code based on the received calibration command;

[0035] The initial calibration code is converted into a target calibration code with a target adjustment step size;

[0036] The interface impedance of the target semiconductor device is calibrated based on the target calibration code.

[0037] In the above scheme, the target calibration code includes: a first target calibration code and / or a second target calibration code; wherein, the adjustment step size of the first target calibration code is greater than or equal to the adjustment step size of the initial calibration code; and the adjustment step size of the second target calibration code is less than or equal to the adjustment step size of the initial calibration code.

[0038] In the above scheme, converting the initial calibration code into a target calibration code with a target adjustment step size includes:

[0039] A code adjustment signal is generated based on the most significant bit of the initial calibration code; the initial calibration code is converted into the target calibration code based on the code adjustment signal; the target calibration code includes a first target calibration code or a second target calibration code.

[0040] In the above scheme, generating the initial calibration code based on the received calibration command includes:

[0041] In response to the calibration command, the current voltage is compared with the reference voltage, and a comparison result is generated;

[0042] The initial calibration code is generated based on the comparison results;

[0043] Wherein, the current voltage is the current voltage across the interface impedance of the target semiconductor device.

[0044] In the above scheme, generating the initial calibration code based on the comparison result includes:

[0045] The control signal is obtained by sampling the comparison result based on the first clock signal;

[0046] The initial calibration code is generated based on the control signal and the second clock signal.

[0047] In the above scheme, the method further includes:

[0048] Receive latch command;

[0049] Based on the latch command, output the target calibration code corresponding to the completion of this calibration;

[0050] The latch command is generated when the target calibration code corresponding to the completion of this calibration is different from the target calibration code corresponding to the completion of the previous calibration.

[0051] In the above scheme, the target calibration code includes a pull-up target calibration code; the step of outputting the target calibration code corresponding to the completion of this calibration based on the latch command includes:

[0052] Temporarily store the target calibration code corresponding to the completion of this calibration;

[0053] Receive the first sub-latch command included in the latch command, and output the pull-up target calibration code corresponding to the completion of this calibration based on the first sub-latch command;

[0054] The first sub-latch command is generated when the target calibration code corresponding to the completion of this calibration is different from the target calibration code corresponding to the completion of the previous calibration.

[0055] In the above scheme, the target calibration code includes a drop-down calibration code; the step of outputting the target calibration code corresponding to the completion of this calibration based on the latch command further includes:

[0056] Temporarily store the drop-down target calibration code corresponding to the completion of this calibration;

[0057] The system receives the second sub-latch command included in the latch command, and outputs the drop-down target calibration code corresponding to the completion of this calibration based on the second sub-latch command; wherein, the second sub-latch command is generated when the drop-down target calibration code corresponding to the completion of this calibration is different from the drop-down target calibration code corresponding to the completion of the previous calibration.

[0058] Thirdly, embodiments of this application provide a memory, including:

[0059] The storage array is configured to store data.

[0060] And, peripheral circuitry coupled to the memory array and including: a ZQ calibration circuit, wherein: the ZQ calibration circuitry includes: a logic control circuit and a calibration circuit; wherein,

[0061] The control logic circuit includes: a calibration code generation circuit and a mapping conversion circuit, wherein the calibration code generation circuit is configured to generate an initial calibration code in response to a calibration command; and the mapping conversion circuit is configured to control the calibration code generation circuit to convert the initial calibration code into a target calibration code with a target adjustment step size in response to a code adjustment signal.

[0062] The calibration circuit is configured to calibrate the interface impedance of the target semiconductor device based on the target calibration code.

[0063] In the above scheme, the storage array is a three-dimensional NAND storage array.

[0064] Fourthly, embodiments of this application also provide a storage system, including: one or more memories; the memories including: a storage array configured to: store data; and peripheral circuitry coupled to the storage array and including: a ZQ calibration circuitry, wherein: the ZQ calibration circuitry includes: a logic control circuitry and a calibration circuitry; wherein the control logic circuitry includes: a calibration code generation circuitry and a mapping conversion circuitry, wherein the calibration code generation circuitry is configured to generate an initial calibration code in response to a calibration command; the mapping conversion circuitry is configured to control the calibration code generation circuitry to convert the initial calibration code into a target calibration code with a target adjustment step size in response to a code adjustment signal; the calibration circuitry is configured to: calibrate the interface impedance of a target semiconductor based on the target calibration codery;

[0065] A memory controller, which is coupled to the one or more memories and configured to control the memories.

[0066] In the above scheme, the storage system includes a solid-state drive (SSD) or a memory card.

[0067] This application provides a ZQ calibration circuit, an operating method, a memory, and a storage system. The ZQ calibration circuit includes a logic control circuit and a calibration circuit. The logic control circuit includes a calibration code generation circuit and a mapping conversion circuit. The calibration code generation circuit is configured to generate an initial calibration code in response to a calibration command. The mapping conversion circuit is configured to control the calibration code generation circuit to convert the initial calibration code into a target calibration code with a target adjustment step size in response to a code adjustment signal. The calibration circuit is configured to calibrate the interface impedance of a target semiconductor device based on the target calibration code. The ZQ calibration circuit provided in this application uses a mapping conversion circuit to control the calibration code generation circuit to convert the initial calibration code into a target calibration code. The adjustment step size of the target calibration code meets the target adjustment step size, enabling the ZQ calibration circuit to be applicable to calibration in different scenarios. Furthermore, if the target adjustment step size is longer, the calibration time is shortened; if the target adjustment step size is smaller, the calibration accuracy is increased. Attached Figure Description

[0068] In accompanying drawings that are not necessarily drawn to scale, the same reference numerals can describe similar components in different views. The same numbers with different letter suffixes can represent different instances of similar components. The accompanying drawings generally illustrate the various embodiments discussed in this document by way of example, not limitation.

[0069] Figure 1 This diagram illustrates the structure of a ZQ calibration circuit in the related art.

[0070] Figure 2 This application provides a schematic diagram of the structure of the ZQ calibration circuit according to an embodiment. Figure 1 ;

[0071] Figure 3 This diagram shows a schematic of the structure of the mapping conversion circuit 2013 provided in an embodiment of this application;

[0072] Figure 4 This application provides a schematic diagram of the structure of a ZQ calibration circuit according to an embodiment. Figure 2 ;

[0073] Figure 5 This application illustrates the ZQ method for converting initial calibration codes into target calibration codes, as provided in an embodiment of this application.

[0074] A schematic diagram showing the relationship between the MUX, calibration code generation circuit, and ZQ calibration control circuit in the calibration circuit.

[0075] Figure 6 This diagram shows a schematic of the calibration code generation circuit 2011 provided in an embodiment of this application.

[0076] Figure 7 This application provides a schematic diagram of the structure of a ZQ calibration circuit according to an embodiment. Figure 3 ;

[0077] Figure 8 This document shows a schematic diagram of the structure of the pull-up calibration sub-circuit and the pull-down calibration sub-circuit provided in an embodiment of this application;

[0078] Figure 9 This illustration shows a schematic diagram of the pull-up resistor network provided in an embodiment of this application;

[0079] Figure 10 This illustration shows a schematic diagram of the structure of the first pull-down resistor network and the second pull-down resistor network provided in an embodiment of this application;

[0080] Figure 11 This application provides a schematic diagram of the structure of a ZQ calibration circuit according to an embodiment. Figure 4 ;

[0081] Figure 12 This paper presents a complete structural schematic diagram of the ZQ calibration circuit provided in an embodiment of this application;

[0082] Figure 13 The embodiments shown in this application provide Figure 12 The timing diagram of the ZQ calibration circuit shown is shown below.

[0083] Figure 14 This application illustrates the embodiments provided with [the following] and [the following]: Figure 2 A schematic diagram of the structure of a pull-up resistor grid or a pull-down resistor grid in a parallel ZQ calibration circuit;

[0084] Figure 15 A flowchart illustrating the operation method of the memory provided in an embodiment of this application is shown;

[0085] Figure 16 This illustration shows a schematic diagram of a memory structure provided in an embodiment of this application;

[0086] Figure 17 This illustration shows a schematic diagram of a memory including peripheral circuitry provided in an embodiment of this application;

[0087] Figure 18 This illustration shows a schematic diagram of a storage system provided in an embodiment of this application;

[0088] Figure 19 This illustration shows a schematic diagram of the structure of a memory card including a storage system provided in an embodiment of this application;

[0089] Figure 20This diagram illustrates the structure of a solid-state drive (SSD) containing a storage system, as provided in an embodiment of this application. Detailed Implementation

[0090] Various embodiments of the invention are described in more detail below with reference to the accompanying drawings. Other embodiments, variations of any disclosed embodiment, can be formed by different configurations or arrangements of the elements and features in the embodiments of the invention. Therefore, the embodiments of the invention are not limited to those set forth herein. Rather, the described embodiments are provided so that the embodiments of the invention are thorough and complete, and fully convey the scope of the embodiments of the invention to those skilled in the art. It should be noted that references to "embodiment," "another embodiment," etc., do not necessarily indicate only one embodiment, and different references to any such phrases do not necessarily refer to the same embodiment. It should be understood that although the terms "first," "second," "third," etc., may be used herein to identify various elements, these elements are not limited by these terms. These terms are used to distinguish one element from another element having the same or similar name. Therefore, a first element in one embodiment may also be referred to as a second or third element in another embodiment without departing from the spirit and scope of the embodiments of the invention.

[0091] The accompanying drawings are not necessarily drawn to scale, and in some cases, the scale may be enlarged to clearly show the features of the embodiments. When an element is referred to as a connection or coupling to another element, it should be understood that the former may be directly connected to or coupled to the latter, or may be electrically connected to or coupled to the latter via one or more intermediate elements between the two. Furthermore, it should be understood that when an element is referred to as being "between" two elements, the element may be the only element between the two elements, or there may be one or more intermediate elements.

[0092] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, singular forms are intended to include plural forms unless the context clearly indicates otherwise. Unless otherwise stated or clearly understood from the context, the articles “a” and / or “an” used in embodiments of the invention and the appended claims should be interpreted as meaning “one or more”. It should be further understood that the terms “comprising,” “including,” “containing,” and “comprising” as used in embodiments of the invention specify the presence of the stated element and do not exclude the presence or addition of one or more other elements. The term “and / or” as used in embodiments of the invention includes any and all combinations of one or more of the associated listed items. Unless otherwise defined, all terms used in embodiments of the invention, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains in light of embodiments of the invention. It should be further understood that unless explicitly defined in embodiments of the invention, terms such as “belong to” as defined in common dictionaries should be interpreted as having a meaning consistent with their meaning in the context of embodiments of the invention and related technologies, and should not be interpreted in an idealized or overly formal manner.

[0093] In the following description, numerous specific details are set forth to provide a thorough understanding of the invention, which can be practiced without some or all of these specific details. In other instances, well-known processing structures and / or processes have not been described in detail so as not to unnecessarily obscure the invention. It should also be understood that, in some cases, unless otherwise specifically apparent to those skilled in the art, a feature or element described with respect to one embodiment may be used alone or in combination with other features or elements of another embodiment. Various embodiments of the invention are described in detail below with reference to the accompanying drawings. The following description focuses on detail to facilitate understanding of embodiments of the invention. Well-known technical details may have been omitted so as not to obscure the features and aspects of the embodiments of the invention.

[0094] Flash memory is a low-cost, high-density, non-volatile firmware storage medium that can be electrically erased and reprogrammed. Flash memory includes NOR flash memory and NAND flash memory, named after NOR and NAND logic gates, respectively. NAND flash memory allows its data bus to operate at Double Data Rate (DDR). To ensure correct data transmission, the NAND flash memory input / output interface impedance is calibrated using the ZQ calibration command to ensure that the interface impedance meets requirements. Specifically, as... Figure 1 As shown in Figure 1, a block diagram of a ZQ calibration circuit in the related art is illustrated. Figure 1The ZQ calibration circuit 100 includes: a ZQ calibration control unit 101, a pull-up resistor network 102, a pull-down resistor network 103, a reference voltage generator 104, a pull-up comparator 105, a pull-down comparator 106, a P-code counter 107, and an N-code counter 108. That is, the ZQ calibration circuit includes a pull-up calibration branch (including components such as the pull-up resistor network 102, pull-up comparator 105, and P-code counter) and a pull-down calibration branch (including components such as the pull-down resistor network 103, pull-down comparator 106, and N-code counter 108). For the calibration of a specific pull-up resistor, the supply voltage VDDQ is divided by the pull-up resistor network and the reference resistor, thereby providing a voltage to node ZQ. The reference resistor coupled to node ZQ typically has 240 ohms (Ω). The pull-up comparator compares the voltage at node ZQ with the reference voltage VREF output from the reference voltage generator, thereby generating a pull-up adjustment signal. The reference voltage VREF is typically set to half the supply voltage, i.e., VDDQ / 2. A P-code counter receives the pull-up adjustment signal, generating a binary code PCODE<0:N>. This binary code PCODE<0:N> turns the parallel-coupled MOS transistors in the pull-up resistors of the pull-up resistor network on / off, thereby calibrating the pull-up resistors. Since the calibrated pull-up resistor value affects the voltage at node ZQ, this process is repeated until the resistance value of the pull-up resistors is equal to that of the reference resistor 109. During this pull-up resistor calibration, the generated binary code PCODE<0:N> is also input to other pull-up resistors in the pull-up resistor network to determine their resistance values.

[0095] For pull-down calibration, similar to pull-up calibration, a binary code NCODE<0:N> is generated by a pull-down comparator and an N-code counter. At node ZQ', the voltage becomes equal to the reference voltage VREF, so that the pull-down resistors in the pull-down resistor network are equal to the pull-up resistors in the pull-up resistor network.

[0096] The ZQ calibration control unit in the ZQ calibration circuit receives short ZQ calibration commands (ZQCS, corresponding to short ZQ calibration) or long ZQ calibration commands (ZQCL, corresponding to long ZQ calibration) from the memory controller coupled to the NAND flash memory to compensate for changes in input / output interface impedance caused by variations in process, voltage, and temperature (PVT). Long ZQ calibration commands are typically used during DRAM power-on initialization and reset conditions; short ZQ calibration commands tend to be used to track minute changes in voltage and temperature during normal operation and periodically calibrate the interface impedance during idle periods to maintain linear output driver and interface impedance across the entire voltage and temperature range. However, currently used ZQ calibration circuits are not suitable for various application scenarios, such as those requiring shorter calibration times or improved calibration accuracy.

[0097] To address the aforementioned technical problems, this application provides a ZQ calibration circuit. This circuit uses a mapping conversion circuit to control a calibration code generation circuit, converting an initial calibration code into a target calibration code. The adjustment step size of this target calibration code satisfies the target adjustment step size, enabling the ZQ calibration circuit to be applicable to calibration in different scenarios. Furthermore, if the target adjustment step size increases, the calibration time is shortened; if the target adjustment step size decreases, the calibration accuracy is increased.

[0098] The embodiments of the present invention will be further described in detail below with reference to the accompanying drawings and specific examples.

[0099] Figure 2 This diagram illustrates the structure of a ZQ calibration circuit provided in an embodiment of this application.

[0100] Specifically, such as Figure 2 As shown, the ZQ calibration circuit 200 includes a logic control circuit 201 and a calibration circuit 202; wherein, the logic control circuit 201 includes a calibration code generation circuit 2011 and a mapping conversion circuit 2012, wherein; the calibration code generation circuit 2011 is configured to generate an initial calibration code in response to a calibration command; the mapping conversion circuit is configured to control the calibration code generation circuit to convert the initial calibration code into a target calibration code with a target adjustment step size in response to a code adjustment signal;

[0101] The calibration circuit is configured to calibrate the interface impedance of the target semiconductor device 300 based on the target calibration code.

[0102] It should be noted that in ZQ calibration, the desired goal is to achieve sufficient resolution while using as few adjustment steps as possible (one adjustment step is considered one step). To achieve this goal, the idea behind this application is to use different adjustment step sizes for different usage scenarios. For example, if the goal is to shorten calibration time, the initial adjustment step size is increased, resulting in larger adjustments each time, thus shortening the adjustment time. Conversely, if the goal is to improve calibration accuracy, the initial adjustment step size is decreased, resulting in smaller adjustments each time, thus improving calibration accuracy. The ZQ calibration circuit provided in this application uses a mapping conversion circuit to control the calibration code generation circuit to convert the initial adjustment step size into a target calibration code with a target adjustment step size, thereby achieving the goal of shortening adjustment time or improving calibration accuracy. The target semiconductor device may be, but is not limited to, a memory. The scheme for increasing calibration accuracy or shortening calibration time implemented in the ZQ calibration circuit provided in this application can be applied to long ZQ calibration and / or short ZQ calibration.

[0103] In some embodiments, such as Figure 3 As shown, the code adjustment signal includes a first sub-adjustment signal and / or a second sub-adjustment signal; the mapping conversion circuit 2012 includes: a first conversion sub-circuit 301 and / or a second conversion sub-circuit 302; wherein,

[0104] The first conversion sub-circuit 301 is configured to: in response to the first sub-adjustment signal, control the calibration code generation circuit 2011 to convert the initial calibration code into a first target calibration code; the adjustment step size of the first target calibration code is greater than or equal to the adjustment step size of the initial calibration code;

[0105] The second conversion sub-circuit 302 is configured to, in response to the second sub-adjustment signal, control the calibration code generation circuit 2011 to convert the initial calibration code into a second target calibration code, wherein the adjustment step size of the second target calibration code is less than or equal to the adjustment step size of the initial calibration code.

[0106] It should be noted that the first conversion sub-circuit 301 is adapted to a calibration scenario where adjustment time is shortened. The second conversion sub-circuit 302 is adapted to a calibration scenario where calibration accuracy is improved. In the calibration scenario where adjustment time is shortened, the adjustment step size of the first target calibration code is greater than or equal to the adjustment step size of the initial calibration code. In the calibration scenario where calibration accuracy is improved, the adjustment step size of the second target calibration code is less than or equal to the adjustment step size of the initial calibration code.

[0107] Since the calibration of the interface impedance of the target semiconductor device 300 requires multiple steps in both calibration scenarios aimed at shortening adjustment time and improving calibration accuracy, increasing the adjustment step size can speed up calibration in the latter scenario. However, calibration accuracy must also be considered. In other words, in this scenario, the first target calibration code used in one or more calibration steps is equal to the initial calibration code. Similarly, in the scenario aimed at improving calibration accuracy, since multiple calibration steps are also required, calibration time must be considered while ensuring accuracy. Therefore, in this scenario, the second target calibration code used in one or more calibration steps is equal to the initial calibration code.

[0108] The above Figure 3 This example only illustrates one logical structure of the mapping conversion circuit 2012. In practical applications, the mapping conversion circuit 2012 may include only the first conversion sub-circuit 301, or only the second conversion circuit 202, or may include the components described above. Figure 3The first conversion sub-circuit 301 and the second conversion sub-circuit 302 are shown. It should be noted that the above description is functional only. The mapping conversion circuit 2012 includes both the first conversion sub-circuit 301 and / or the second conversion sub-circuit 302 to achieve the conversion of calibration codes for the two different calibration scenarios described above. In reality, the first conversion sub-circuit 301 and the second conversion sub-circuit 302 may only be a single hardware structure capable of converting calibration codes under the two calibration scenarios described above.

[0109] In some embodiments, such as Figure 4 As shown, the mapping conversion circuit includes: a multiplexer MUX 401; wherein,

[0110] The MUX is configured to: in response to a code adjustment signal, control the calibration code generation circuit to convert the initial calibration code into the target calibration code; the target calibration code includes a first target calibration code or a second target calibration code; the code adjustment signal is generated based on the most significant bit of the initial calibration code.

[0111] Here, a specific implementation method for converting the initial calibration code into the target calibration code is described.

[0112] In this code conversion method, the MUX receives the code adjustment signal and, in response to the code adjustment signal, controls the calibration code generation circuit 2011 to convert the initial calibration code into the target calibration code. The code adjustment signal is generated based on the highest value of the initial calibration code.

[0113] Specifically, generating the code adjustment signal based on the most significant bit of the initial calibration code can include: outputting a code adjustment signal based on whether the most significant bit is 1 or 0. In an optional embodiment, in a calibration scenario aimed at shortening adjustment time, when the most significant bit is 1, a first sub-adjustment signal is generated; under this first sub-adjustment signal, the adjustment step size of the first target calibration code output by the calibration code generation circuit controlled by the MUX is greater than the initial calibration code; when the most significant bit is 0, a first sub-adjustment signal is generated, and under this first sub-adjustment signal, the adjustment step size of the first target calibration code output by the calibration code generation circuit controlled by the MUX is equal to the initial calibration code. In a calibration scenario aimed at improving calibration accuracy, when the most significant bit is 1, a second sub-adjustment signal is generated, and under this second sub-adjustment signal, the adjustment step size of the second target calibration code output by the calibration code generation circuit controlled by the MUX is less than the initial calibration code; when the most significant bit is 0, a second sub-adjustment signal is generated, and under this second sub-adjustment signal, the adjustment step size of the second target calibration code output by the calibration code generation circuit controlled by the MUX is equal to the initial calibration code.

[0114] To understand the above code conversion process, as follows: Figure 5 As shown, this diagram illustrates the relationship between the MUX, calibration code generation circuit, and ZQ calibration control circuit in the ZQ calibration circuit when converting the initial calibration code into the target calibration code. Figure 5 In this circuit, the counter and comparator are included in the aforementioned calibration code generation circuit 2011; the MUX is included in the mapping conversion circuit 2012; the code adjustment signal controlling the MUX can be directly generated based on the most significant bit of the initial calibration code, that is, as shown in the example. Figure 5 As shown, the most significant bit CNT4 of the initial calibration code is directly connected to the MUX, meaning the most significant bit of the initial calibration code directly controls the MUX. In one of the aforementioned embodiments, in a calibration scenario requiring shorter adjustment time, when the most significant bit is 1, under the first sub-adjustment signal generated by the ZQ calibration control circuit, the MUX controls the adjustment step size of the first target calibration code output by the calibration code generation circuit to be greater than that of the initial calibration code. At this time, the MUX selects to connect CNT1 according to the first sub-adjustment signal to merge the two adjustment steps in the initial calibration code, effectively reducing the original two-step calibration to a single-step calibration, thus speeding up the calibration process. When the most significant bit is 0, under the first sub-adjustment signal generated by the ZQ calibration control circuit, the MUX controls the adjustment step size of the first target calibration code output by the calibration code generation circuit to be equal to that of the initial calibration code. At this time, the MUX selects to connect CNT0 according to the second sub-adjustment signal, making the adjustment step size of the first target calibration code equal to that of the initial calibration code.

[0115] based on Figure 5 The diagram illustrates the relationship. Assuming the initial calibration code contains 6 bits, in a calibration scenario where adjustment time is shortened, the initial calibration code is converted into a first target calibration code based on the first sub-adjustment signal generated from the most significant bit. The correspondence between the initial calibration code and the first target calibration code is shown in Table 1 below.

[0116] Table 1. Correspondence between initial calibration codes and first target calibration codes.

[0117]

[0118]

[0119] For calibration scenarios that improve calibration accuracy, assuming the initial calibration code contains 5 bits, the initial calibration code is converted into a second target calibration code based on the second sub-adjustment signal generated by the highest bit. The correspondence between the initial calibration code and the second target calibration code is shown in Table 2 below.

[0120] Table 2. Correspondence between initial calibration codes and second target calibration codes.

[0121]

[0122] It should be noted that the conversion methods in Tables 1 and 2 above are merely illustrative. In practical applications, the correspondence between the initial calibration code and the target calibration code should be selected according to actual needs and the actual circuit structure. Furthermore, as shown in Table 2, the correspondence between the initial calibration code and the target calibration code indicates that to achieve code expansion and improve calibration resolution (or accuracy), additional MOS transistors are needed for low-order calibration of the interface impedance of the semiconductor device.

[0123] In some other embodiments, such as Figure 4 As shown, the logic control circuit 201 further includes a ZQ calibration control circuit 2013; the mapping conversion circuit 2012 includes a multiplexer MUX 401; wherein,

[0124] The ZQ calibration control circuit 2013 is configured to: generate the code adjustment signal based on the most significant bit of the initial calibration code; and send the code adjustment signal to the MUX.

[0125] The MUX 401 is configured to: in response to a code adjustment signal, control the calibration code generation circuit to convert the initial calibration code into the target calibration code; the target calibration code includes a first target calibration code or a second target calibration code.

[0126] In this embodiment, the ZQ calibration control circuit 2013 in the logic control circuit 101 generates a code adjustment signal based on the most significant bit of the initial calibration code and provides the code adjustment signal to the MUX. Then, the MUX controls the calibration code generation circuit to convert the initial calibration code into the target calibration code based on the code adjustment signal. When the code adjustment signal includes a first sub-adjustment signal, the target calibration code includes a first target calibration code (calibration scenario to shorten adjustment time); when the code adjustment signal includes a second sub-adjustment signal, the target calibration code includes a second target calibration code (calibration scenario to improve calibration accuracy).

[0127] Specifically, generating the code adjustment signal based on the most significant bit of the initial calibration code can include: outputting a code adjustment signal based on whether the most significant bit is 1 or 0. In an optional embodiment, in a calibration scenario aimed at shortening adjustment time, when the most significant bit is 1, under the first sub-adjustment signal generated by the ZQ calibration control circuit, the adjustment step size of the first target calibration code output by the calibration code generation circuit controlled by the MUX is greater than the initial calibration code; when the most significant bit is 0, under the first sub-adjustment signal generated by the ZQ calibration control circuit, the adjustment step size of the first target calibration code output by the calibration code generation circuit controlled by the MUX is equal to the initial calibration code. In a calibration scenario aimed at improving calibration accuracy, when the most significant bit is 1, under the second sub-adjustment signal generated by the ZQ calibration control circuit, the adjustment step size of the second target calibration code output by the calibration code generation circuit controlled by the MUX is less than the initial calibration code; when the most significant bit is 0, under the second sub-adjustment signal generated by the ZQ calibration control circuit, the adjustment step size of the second target calibration code output by the calibration code generation circuit controlled by the MUX is equal to the initial calibration code.

[0128] It should be noted that, Figure 5 The ZQ calibration control circuit is not shown, meaning the process by which the ZQ calibration control circuit generates a code adjustment signal based on the most significant bit of the initial calibration code is not illustrated. The control of the MUX is the same in this case and will not be described further.

[0129] In some embodiments, such as Figure 6 As shown, the calibration code generation circuit 2011 includes: a comparator 601 and a counter 602; wherein,

[0130] The comparator 601 is configured to: in response to the calibration command, compare the current voltage across the interface impedance of the target semiconductor device with a reference voltage, generate a comparison result, and output the comparison result;

[0131] The counter 602 is configured to receive the comparison result and generate the initial calibration code based on the comparison result.

[0132] It should be noted that the current voltage is the voltage across the interface impedance of the target semiconductor device. That is, comparator 601 compares the reference voltage with the voltage value across the interface impedance of the target semiconductor device in the current calibration cycle (or the current calibration step), and outputs the comparison result to counter 602; counter 602 generates the initial calibration code based on the comparison result.

[0133] In some embodiments, such as Figure 6 As shown, the calibration code generation circuit 2011 may further include: a first flip-flop 603 connected between the comparator 601 and the counter 602, configured to: receive the comparison result and a first clock signal; sample the comparison result based on the first clock signal and output a control signal;

[0134] The counter 602 is also configured to receive the control signal and the second clock signal, and generate the initial calibration code based on the control signal and the second clock signal.

[0135] It should be noted that the function of the first flip-flop 603 here is to obtain a relatively stable comparison result. As an optional embodiment, the first flip-flop 603 can be a D flip-flop (DFF). A DFF is an information storage device with memory function and two stable states. Its triggering methods include level triggering and edge triggering. The former can be triggered when CP (clock pulse) = 1, while the latter is mostly triggered at the leading edge of CP (positive transition 0→1). The triggering method of the first flip-flop 603 provided in this embodiment can be edge triggering. That is, the comparison result is sampled when the first clock signal edge arrives. Since the output of a DFF only changes when the clock signal changes, sampling the comparison result using this first flip-flop yields a relatively stable control signal.

[0136] Subsequently, counter 602 generates an initial calibration code (such as the aforementioned PCODE<0:N> and / or NCODE<0:N>) based on the second clock signal and the control signal. Here, the use of "first" and "second" for the first clock signal and the second clock signal is merely for the convenience of describing two clock signals in two different processes; the two are not directly related and should not be interpreted as limitations on either.

[0137] It should be noted that the aforementioned Figures 1 to 6 The structure of the ZQ calibration circuit shown is only a detailed description of the technical solution provided in this application embodiment from a principle perspective. In practical applications, the ZQ calibration circuit should be divided into pull-up calibration and pull-down calibration.

[0138] Specifically, in some embodiments, such as Figure 7 As shown, the initial calibration code includes an upward calibration code and a downward calibration code; the target calibration code includes an upward target calibration code and a downward target calibration code; the calibration code generation circuit 2011 includes an upward code generation sub-circuit 701 and a downward code generation sub-circuit 702; the mapping conversion circuit includes an upward conversion sub-circuit 703 and a downward conversion sub-circuit 704; wherein;

[0139] The pull-up code generation sub-circuit 701 is configured to generate the pull-up calibration code in response to the calibration command;

[0140] The pull-up conversion sub-circuit 703 is configured to: control the pull-up code generation sub-circuit to convert the pull-up calibration code into the pull-up target calibration code in response to the pull-up code adjustment signal;

[0141] The drop-down code generation sub-circuit 702 is configured to generate the drop-down calibration code in response to the calibration command;

[0142] The pull-down conversion sub-circuit 704 is configured to: control the pull-down code generation sub-circuit to convert the pull-down calibration code into the pull-down target calibration code in response to the pull-down code adjustment signal.

[0143] It should be noted that ZQ calibration includes pull-up calibration and pull-down calibration. Correspondingly, the initial calibration code includes pull-up calibration code and pull-down calibration code; the target calibration code includes pull-up target calibration code and pull-down target calibration code; the calibration code generation circuit 2011 includes pull-up code generation sub-circuit 701 and pull-down code generation sub-circuit 702; and the mapping conversion circuit includes pull-up conversion sub-circuit 703 and pull-down conversion sub-circuit 704. The pull-up code generation sub-circuit 701 and pull-down code generation sub-circuit 702 in the pull-up calibration branch and the pull-down calibration branch operate on similar principles, and both can be implemented as described above. Figure 6The two circuits achieve their functions through their respective structures, differing only in that: the pull-up code generation subcircuit 701 generates pull-up calibration codes; while the pull-down code generation subcircuit 702 generates pull-down calibration codes. The working principles of the pull-up conversion subcircuit and pull-down conversion subcircuit in the mapping conversion circuit are also similar, and both can be implemented using the aforementioned... Figure 3 and Figure 4 The structures shown achieve their functions, with the difference being that: the pull-up conversion sub-circuit 703, in response to the pull-up code adjustment signal, controls the pull-up code generation sub-circuit to convert the pull-up calibration code into the pull-up target calibration code; and the pull-down conversion sub-circuit 704, in response to the pull-down code adjustment signal, controls the pull-down code generation sub-circuit to convert the pull-down calibration code into the pull-down target calibration code.

[0144] Correspondingly, in some embodiments, such as Figure 7 As shown, the calibration circuit 202 includes: a pull-up calibration sub-circuit 705 and a pull-down calibration sub-circuit 706, wherein,

[0145] The pull-up calibration sub-circuit 705 is configured to perform pull-up calibration on the interface impedance of the target semiconductor device based on the pull-up target calibration code.

[0146] The pull-down calibration sub-circuit 706 is configured to perform pull-down calibration on the interface impedance of the target semiconductor device based on the pull-down target calibration code.

[0147] Among them, such as Figure 8 As shown, the pull-up calibration sub-circuit 705 includes: a pull-up resistor network 801 and a first pull-down resistor network 802 connected in series; the pull-down calibration sub-circuit 706 includes a second pull-down resistor network 803.

[0148] The pull-up resistor network, the first pull-down resistor network, and the second pull-down resistor network include multiple parallel metal-oxide-semiconductor (MOS) transistors.

[0149] Specifically, the pull-up resistor network 801, such as Figure 9 As shown, it contains multiple MOS transistors connected in parallel. The first pull-down resistor network 802 and the second pull-down resistor network 803 are as follows... Figure 10As shown, it includes multiple parallel MOS transistors. The pull-up resistor network 801 and the first pull-down resistor network 802 contain the same number of parallel MOS transistors, and corresponding two MOS transistors are connected in series. One end of the comparator 601 (pull-up comparator) in the pull-up code generation sub-circuit of the calibration code generation circuit 2011 is connected at its series connection point. This pull-up comparator receives the voltage across the interface impedance of the target semiconductor device during pull-up calibration (the current voltage of pull-up calibration), and the other end of the pull-up comparator is connected to a reference voltage. The second pull-down resistor network 803 contains the same number of parallel MOS transistors as the pull-up resistor network 801 and the first pull-down resistor network 802. One end of the MOS transistor in the second pull-down resistor network 803 is connected to the power supply voltage VDDQ (or Vddq) through a voltage divider resistor 804, and the other end is grounded to VSS. The pull-down generator circuit includes a comparator 601 (pull-down comparator). One end of the comparator is connected to the connection line between the voltage divider resistor 804 and the second pull-down resistor network 803. This pull-down comparator receives the voltage across the interface impedance of the target semiconductor device during pull-down calibration (the current voltage for pull-down calibration). The other end of the comparator is connected to a reference voltage. The reference voltages for pull-up and pull-down calibrations can be the same or different. It should be noted that one end of the first pull-down resistor network 802 is connected through a pull-up resistor in the pull-up resistor network, and the other end is grounded; its structure is also as described above. Figure 10 As shown.

[0150] In some embodiments, such as Figure 11 As shown, the ZQ calibration circuit 200 further includes a code output circuit 203, configured to: receive a latch command; output the target calibration code corresponding to the completion of this calibration based on the latch command; wherein the latch command is generated when the target calibration code corresponding to the completion of this calibration is different from the target calibration code corresponding to the completion of the previous calibration.

[0151] It should be noted that the ZQ calibration circuit provided in this application embodiment also includes a code output circuit, which, upon receiving a latch command, outputs the target calibration code corresponding to the completion of this calibration based on the latch command. Here, "completion of this calibration" can refer to the completion of both pull-up and pull-down calibrations. The completion of pull-up and pull-down calibrations can refer to the interface impedance of the target semiconductor device meeting requirements. The resistance value of the pull-up resistor network under the action of the target calibration code is similar to that described above. Figure 1 The reference resistance value 109 is equal to the second pull-down resistor network; the resistance value of the second pull-down resistor network under the action of the pull-down target calibration code is equal to the reference resistance value 109, which means that the pull-up calibration and pull-down calibration are completed, that is, the interface impedance of a target semiconductor device meets the requirements.

[0152] Here, the latch command may be generated by the ZQ calibration control circuit when it determines that the target calibration code corresponding to the completion of this calibration is different from the target calibration code corresponding to the completion of the previous calibration, and transmitted to the code output circuit for updating and saving the latest target calibration code for later use. In other words, if the target calibration code corresponding to the completion of this calibration is the same as the target calibration code corresponding to the completion of the previous calibration, there is no need to waste an output, thus saving some calibration time.

[0153] Based on the aforementioned ZQ calibration, which includes pull-up calibration and pull-down calibration, correspondingly, as follows: Figure 11 As shown, the code output circuit 203 includes: a pull-up code sub-output circuit 1101; the latch command includes a first sub-latch command, wherein;

[0154] The pull-up code sub-output circuit 1101 includes: a second flip-flop and a third flip-flop connected in series. The second flip-flop is configured to: temporarily store the pull-up target calibration code corresponding to the completion of the current calibration. The third flip-flop is configured to: receive a first sub-latch command and output the pull-up target calibration code corresponding to the completion of the current calibration based on the first sub-latch command. The first sub-latch command is generated when the pull-up target calibration code corresponding to the completion of the current calibration is different from the pull-up target calibration code corresponding to the completion of the previous calibration.

[0155] It should be noted that the timing for re-storing the pull-up target calibration code can be when the pull-up target calibration code corresponding to the completion of this calibration is different from the pull-up target calibration code corresponding to the completion of the previous calibration, in which case the pull-up target calibration code corresponding to the completion of this calibration can be transmitted and stored.

[0156] In some embodiments, the code output circuit 203 includes: a pull-down code sub-output circuit 1102; the latch command includes a second sub-latch command, wherein;

[0157] The pull-down code sub-output circuit includes a fourth flip-flop and a fifth flip-flop. The fourth flip-flop is configured to temporarily store the pull-down target calibration code corresponding to the completion of the current calibration. The fifth flip-flop is configured to receive a second sub-latch command and output the pull-down target calibration code corresponding to the completion of the current calibration based on the second sub-latch command. The second sub-latch command is generated when the pull-down target calibration code corresponding to the completion of the current calibration is different from the pull-down target calibration code corresponding to the completion of the previous calibration.

[0158] It should be noted that the timing for re-storing the drop-down target calibration code can be: when the drop-down target calibration code corresponding to the completion of this calibration is different, the drop-down target calibration code corresponding to the completion of this calibration is transmitted and stored.

[0159] To understand the embodiments of this application, such as Figures 12 to 13 As shown. Among them, Figure 12 This diagram shows a relatively complete circuit structure of a ZQ calibration circuit 200 provided in an embodiment of this application. Figure 13 Showing based on Figure 12 The timing diagram of the ZQ calibration circuit.

[0160] exist Figure 12 In this context, the ZQ calibration controller is an example of the ZQ calibration control circuit 2013 within the aforementioned logic control circuit 201. This ZQ calibration controller receives calibration commands and generates a calibration enable (signal) Cal EN based on the calibration commands. It can also receive latch commands and generate a latch enable (signal) ZQ Latch based on the latch commands. Furthermore, it receives reset commands and generates a reset enable (signal) Rst based on the reset commands. The various commands received by the ZQ calibration controller are sent by the memory controller included in the storage system to which the ZQ calibration circuit belongs.

[0161] In this circuit, comparator 1, counter 1, and mapping conversion circuit 1 correspond to the pull-up comparator, pull-up counter, and pull-up conversion sub-circuit in the aforementioned pull-up calibration; comparator 2, counter 2, and mapping conversion circuit 2 correspond to the pull-down pull-up comparator, pull-down pull-up counter, and pull-down conversion sub-circuit in the aforementioned pull-down calibration. D1 and D2 correspond to the aforementioned first flip-flop; D3 and D4 correspond to the second and third flip-flops, respectively; D5 and D6 correspond to the third and fourth flip-flops, respectively. Pu_rslt is the pull-up comparison result; Pu_rslt_s is the pull-up control signal; Pd_rslt is the pull-down comparison result; Pd_rslt_s is the pull-down control signal.

[0162] based on Figure 12 , combined Figure 13 The timing diagram shows that the ZQ calibration circuit provided in this application embodiment works as follows: For pull-up calibration, the memory controller sends a calibration command, the ZQ calibration controller receives the calibration command, and generates a calibration enable (signal) Cal EN based on the calibration command; the ZQ calibration circuit provided in this application embodiment starts calibration based on the calibration enable (signal) Cal EN, and its specific workflow is the same as described above. Figure 1 The description is similar to that in the previous section, but the difference is that the pull-up calibration code is converted into the pull-up target calibration code (PU Code) by the mapping and conversion circuit 1. <n:0>Then, the pull-up target calibration code is applied to the pull-up resistor network PU, which calibrates the interface impedance of the target semiconductor device, until the pull-up resistors in the pull-up resistor network are aligned with, for example, the interface impedance of the target semiconductor device. Figure 1 The reference resistor values ​​are equal, completing the pull-up calibration of the interface impedance of the target semiconductor device. Similarly, the pull-down calibration follows the same process, with the pull-down calibration code being converted into the pull-down target calibration code (PD Code) by the mapping and conversion circuit 2. <n:0>Using this drop-down target calibration code PD Code <n:0>The pull-down calibration is completed; the specific process will not be detailed here. After completing the pull-up and pull-down calibrations, if the target calibration code obtained in this calibration (pull-up target calibration code and pull-down target calibration code) is different from the aforementioned target calibration code, the ZQ update flag ZQUF will also be set. When the memory controller is in the set state according to this ZQ update flag, it sends a latch command to the ZQ calibration controller. The ZQ calibration controller generates a latch enable (signal) ZQ Latch based on the latch command. D3 and D4 work together to output the pull-up target calibration code obtained in this calibration; D5 and D6 work together to output the pull-down target calibration code obtained in this calibration, for later use. After the ZQ calibration is completed and the target calibration code is stored, the ZQ calibration controller can also receive a reset command and generate a reset enable (signal) Rst based on the reset command to reset the ZQ calibration circuit.

[0163] This application provides a ZQ calibration circuit that uses a mapping conversion circuit to control a calibration code generation circuit to convert an initial calibration code into a target calibration code. The adjustment step size of the target calibration code satisfies the target adjustment step size, so that the ZQ calibration circuit can be used for calibration in different scenarios. Furthermore, if the target adjustment step size is longer, the calibration time is shortened; if the target adjustment step size is smaller, the calibration accuracy is increased.

[0164] In practical applications, with Figure 2 The proposed solution also employs a technique that achieves sufficient resolution while using only the fewest possible adjustment steps (one adjustment step is one step). Specifically, such as... Figure 14 As shown, the calibration code is not converted through a mapping conversion circuit, only when... Figure 5 The existing pull-up and pull-down resistor networks are modified with default transistors to adjust the step size of the calibration code, enabling step size adjustment for different scenarios. It should be noted that in actual implementation, this method requires adding a default transistor to each die in the memory array within the memory.

[0165] This application also provides a method for operating a memory, such as... Figure 15 As shown, the method may specifically include:

[0166] S1501: Generate initial calibration code based on the received calibration command;

[0167] S1502: Convert the initial calibration code into a target calibration code with a target adjustment step size;

[0168] S1503: Calibrate the interface impedance of the target semiconductor device based on the target calibration code.

[0169] It should be noted that S1501 may include:

[0170] In response to the calibration command, the current voltage is compared with the reference voltage, and a comparison result is generated;

[0171] The initial calibration code is generated based on the comparison results;

[0172] Wherein, the current voltage is the current voltage across the interface impedance of the target semiconductor device.

[0173] The step of generating the initial calibration code based on the comparison result may include:

[0174] The control signal is obtained by sampling the comparison result based on the first clock signal;

[0175] The initial calibration code is generated based on the control signal and the second clock signal.

[0176] In some embodiments, the target calibration code includes: a first target calibration code and / or a second target calibration code; wherein the adjustment step size of the first target calibration code is greater than or equal to the adjustment step size of the initial calibration code; and the adjustment step size of the second target calibration code is less than or equal to the adjustment step size of the initial calibration code.

[0177] In some embodiments, converting the initial calibration code into a target calibration code with a target adjustment step size includes:

[0178] A code adjustment signal is generated based on the most significant bit of the initial calibration code; the initial calibration code is converted into the target calibration code based on the code adjustment signal; the target calibration code includes a first target calibration code or a second target calibration code.

[0179] In some embodiments, the method further includes:

[0180] Receive latch command;

[0181] Based on the latch command, output the target calibration code corresponding to the completion of this calibration;

[0182] The latch command is generated when the target calibration code corresponding to the completion of this calibration is different from the target calibration code corresponding to the completion of the previous calibration.

[0183] In some embodiments, the target calibration code includes an upward target calibration code; outputting the target calibration code corresponding to the completion of this calibration includes:

[0184] Temporarily store the target calibration code corresponding to the completion of this calibration;

[0185] Receive the first sub-latch command included in the latch command, and output the pull-up target calibration code corresponding to the completion of this calibration based on the first sub-latch command;

[0186] The first sub-latch command is generated when the target calibration code corresponding to the completion of this calibration is different from the target calibration code corresponding to the completion of the previous calibration.

[0187] In some embodiments, the target calibration code includes a drop-down calibration code; the step of outputting the target calibration code corresponding to the completion of this calibration further includes:

[0188] Temporarily store the drop-down target calibration code corresponding to the completion of this calibration;

[0189] The system receives the second sub-latch command included in the latch command, and outputs the drop-down target calibration code corresponding to the completion of this calibration based on the second sub-latch command; wherein, the second sub-latch command is generated when the drop-down target calibration code corresponding to the completion of this calibration is different from the drop-down target calibration code corresponding to the completion of the previous calibration.

[0190] It should be noted that the memory operation method provided in this application embodiment is based on the ZQ calibration circuit provided in the aforementioned application embodiment. The terms appearing in the operation method have also been described in detail in the aforementioned description of the ZQ calibration circuit, and can be referred to the aforementioned description, and will not be repeated here.

[0191] The memory operation method provided in this application converts the initial calibration code into a target calibration code with a target adjustment step size, and uses the target calibration code to calibrate the interface impedance of the target semiconductor device, so as to shorten the calibration time or improve the calibration accuracy and meet the ZQ calibration requirements in different scenarios.

[0192] This application also provides a memory, such as... Figure 16 As shown, the memory 160 includes a memory array 1601 configured to store data;

[0193] And, peripheral circuitry 1602, coupled to the storage array 1601 and including: ZQ calibration circuitry 200, wherein: ZQ calibration circuitry 200 includes: logic control circuitry and calibration circuitry; wherein,

[0194] The control logic circuit includes: a calibration code generation circuit and a mapping conversion circuit, wherein the calibration code generation circuit is configured to generate an initial calibration code in response to a calibration command; and the mapping conversion circuit is configured to control the calibration code generation circuit to convert the initial calibration code into a target calibration code with a target adjustment step size in response to a code adjustment signal.

[0195] The calibration circuit is configured to calibrate the interface impedance of the target semiconductor device based on the target calibration code.

[0196] In some embodiments, the storage array is a three-dimensional NAND storage array.

[0197] It should be noted that the memory 160 provided in this application embodiment includes a memory array 1601 and peripheral circuitry 1602, wherein the peripheral circuitry 1602 may include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 17 Some exemplary peripheral circuitry is shown. Peripheral circuitry 1602 includes a page buffer / sensor amplifier 1704, a column decoder / bit line driver 1706, a row decoder / word line driver 1708, a voltage generator 1710, a control logic unit 1712, a register 1714, an interface 1716, and a data bus 1718. It should be understood that in some examples, additional peripheral circuitry may be included. Figure 17 Additional peripheral circuitry not shown.

[0198] Page buffer / sensor amplifier 1704 can be configured to read data from memory array 1601 and program (write) data to memory array 1601 according to control signals from control logic unit 1712. In one example, page buffer / sensor amplifier 1704 can store a page of programming data (write data) to be programmed into a page of memory array 1601. In another example, page buffer / sensor amplifier 1704 can perform a programming verification operation to ensure that data has been correctly programmed into the memory cell coupled to the selected word line. In yet another example, page buffer / sensor amplifier 1704 can also sense a low-power signal from the bit line representing the data bits stored in the memory cell and amplify a small voltage swing to a recognizable logic level during a read operation. Column decoder / bit line driver 1706 can be configured to be controlled by control logic unit 1712 and select one or more NAND memory strings by applying a bit line voltage generated from voltage generator 1710.

[0199] The row decoder / word line driver 1708 can be configured to be controlled by the control logic unit 1712 and to select / deselect memory blocks of the memory array 1601 and select / deselect word lines of the memory blocks. The row decoder / word line driver 1708 can also be configured to drive word lines using word line voltages generated from the voltage generator 1710. In some embodiments, the row decoder / word line driver 1708 is configured to perform erase operations on memory cells coupled to one or more selected word lines. The voltage generator 1710 can be configured to be controlled by the control logic unit 1712 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory array 1601.

[0200] Control logic unit 1712 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. Register 1714 can be coupled to control logic unit 1712 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Interface 1716 can be coupled to control logic unit 1712 and acts as a control buffer to buffer control commands received from the host (not shown) and relay them to control logic unit 1712, as well as to buffer status information received from control logic unit 1712 and relay it to the host. Interface 1716 can also be coupled to column decoder / bitline driver 1706 via data bus 1718 and acts as a data I / O interface and data buffer to buffer data and relay it to or from memory array 1601.

[0201] It should be noted that the ZQ calibration circuit 200 described above is also included in the peripheral circuit 1602, wherein the logic control circuit 201 in the ZQ calibration circuit 200 is connected to... Figure 17 The control logic unit 1712 in the peripheral circuit 1602 corresponds to the aforementioned circuit; the calibration circuit 202 and other circuits in the ZQ calibration circuit 200 can correspond to the aforementioned description. Figure 17 Additional peripheral circuitry is not shown. The function and structure of the ZQ calibration circuit 200 have been described in detail above and will not be repeated here.

[0202] This application also provides a storage system, such as... Figure 18 As shown, the storage system 180 includes: one or more memories 160; the memories 160 include: a storage array configured to: store data; and peripheral circuitry coupled to the storage array and including: a ZQ calibration circuitry, wherein: the ZQ calibration circuitry includes: a logic control circuitry and a calibration circuitry; wherein the control logic circuitry includes: a calibration code generation circuitry and a mapping conversion circuitry, wherein the calibration code generation circuitry is configured to generate an initial calibration code in response to a calibration command; the mapping conversion circuitry is configured to control the calibration code generation circuitry to convert the initial calibration code into a target calibration code with a target adjustment step size in response to a code adjustment signal; the calibration circuitry is configured to: perform calibration based on the target calibration codery;

[0203] A memory controller 1801 is coupled to the one or more memories and configured to control the memories.

[0204] In some embodiments, the storage system includes a solid-state drive (SSD) or a memory card.

[0205] It should be noted that the storage system provided in this application embodiment includes the aforementioned memory 160. The memory 160 contains the ZQ calibration circuit 200 described above. The principle and structure of the ZQ calibration circuit 200 have been described in detail above and will not be repeated here.

[0206] In practical applications, storage system 180 can include various storage devices, specifically, such as... Figure 19 and Figure 20 ,in, Figure 19 A schematic diagram of the structure of a memory card provided in an embodiment of this disclosure is shown; Figure 20 This diagram illustrates the structure of an SSD provided by an embodiment of the present disclosure.

[0207] exist Figure 19 In this configuration, the memory controller 1801 and a single memory 160 can be integrated into the memory card 1902. The memory card can include PC cards (PCMCIA, Personal Computer Memory Card International Association), CF cards, Smart Media (SM) cards, memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), UFS, etc. The memory card may also include a memory card connector 1904 that couples the memory card to the host computer.

[0208] exist Figure 20 In this configuration, the memory controller 1801 and multiple memories 160 can be integrated into the SSD 2002. The SSD may also include an SSD connector 2004 that couples the SSD to the host. In some implementations, the storage capacity and / or operating speed of the SSD is greater than that of the memory card.

[0209] This application also provides an electronic device, including: a storage system; the storage system includes one or more memories; the memories include a storage array and peripheral circuitry including a ZQ calibration circuit with any of the aforementioned structures;

[0210] And a host computer coupled to the memory system and configured to control the memory system.

[0211] This disclosure also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the steps of any of the methods described above. The aforementioned storage medium includes various media capable of storing program code, such as mobile storage devices, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0212] It should be noted that, in the several embodiments provided in this disclosure, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components can be combined, or integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed can be through some interfaces, and the indirect coupling or communication connection between devices or units can be electrical, mechanical, or other forms.

[0213] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.

[0214] In addition, each functional unit in the various embodiments of this disclosure can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit; the integrated unit can be implemented in hardware or in the form of hardware plus software functional units.

[0215] Those skilled in the art will understand that all or part of the steps of the above method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it performs the steps of the above method embodiments. The aforementioned storage medium includes various media capable of storing program code, such as mobile storage devices, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0216] Alternatively, if the integrated units described above are implemented as software functional modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of the embodiments of this disclosure, or the parts that contribute to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the methods described in the various embodiments of this disclosure. The aforementioned storage medium includes various media capable of storing program code, such as mobile storage devices, ROM, RAM, magnetic disks, or optical disks.

[0217] The above description is intended to be illustrative and not restrictive. For example, the above examples (or one or more aspects thereof) may be used in combination with each other. Other embodiments may be used, such as those that may be used by one of ordinary skill in the art upon reading the above description. It should be understood that it is not intended to interpret or limit the scope or meaning of the claims. Furthermore, in the above detailed description, various features may be combined together to simplify the invention. This should not be construed as meaning that any unclaimed disclosed feature is essential to any claim. Rather, the subject matter of the disclosure may lie in fewer than all features of a particular disclosed embodiment. Therefore, the appended claims are thus incorporated into the detailed description, wherein each claim is an independent, separate embodiment, and these embodiments are contemplated to be combined with each other in various combinations or substitutions. The scope of the invention should be determined by reference to the appended claims and the full scope of their equivalents.

Claims

1. A ZQ calibration circuit, characterized in that, include: Logic control circuit and calibration circuit; among which, The logic control circuit includes: a calibration code generation circuit and a mapping conversion circuit, wherein: the calibration code generation circuit is configured to: generate an initial calibration code in response to a calibration command, the adjustment step size of the initial calibration code being an initial adjustment step size; the mapping conversion circuit is configured to: control the calibration code generation circuit to convert the initial calibration code having the initial adjustment step size into a target calibration code with a target adjustment step size in response to a code adjustment signal. The calibration circuit is configured to calibrate the interface impedance of the target semiconductor device based on the target calibration code.

2. The ZQ calibration circuit according to claim 1, characterized in that, The code adjustment signal includes a first sub-adjustment signal and / or a second sub-adjustment signal; the mapping conversion circuit includes a first conversion sub-circuit and / or a second conversion sub-circuit; wherein... The first conversion sub-circuit is configured to: in response to the first sub-adjustment signal, control the calibration code generation circuit to convert the initial calibration code into a first target calibration code; the adjustment step size of the first target calibration code is greater than or equal to the adjustment step size of the initial calibration code; The second conversion sub-circuit is configured to: in response to the second sub-adjustment signal, control the calibration code generation circuit to convert the initial calibration code into a second target calibration code, wherein the adjustment step size of the second target calibration code is less than or equal to the adjustment step size of the initial calibration code.

3. The ZQ calibration circuit according to claim 1, characterized in that, The mapping conversion circuit includes: a multiplexer (MUX); wherein... The MUX is configured to: in response to a code adjustment signal, control the calibration code generation circuit to convert the initial calibration code into the target calibration code; the target calibration code includes a first target calibration code or a second target calibration code; the code adjustment signal is generated based on the most significant bit of the initial calibration code.

4. The ZQ calibration circuit according to any one of claims 1 to 3, characterized in that, The calibration code generation circuit includes a comparator and a counter; wherein... The comparator is configured to: in response to the calibration command, compare the current voltage across the interface impedance of the target semiconductor device with a reference voltage, generate a comparison result, and output the comparison result; The counter, connected to the comparator, is configured to receive the comparison result and generate the initial calibration code based on the comparison result.

5. The ZQ calibration circuit according to claim 4, characterized in that, The calibration code generation circuit further includes: a first flip-flop connected between the comparator and the counter, configured to: receive the comparison result and a first clock signal; sample the comparison result based on the first clock signal and output a control signal; The counter is also configured to receive the control signal and the second clock signal, and generate the initial calibration code based on the control signal and the second clock signal.

6. The ZQ calibration circuit according to claim 1, characterized in that, The initial calibration code includes an upward calibration code and a downward calibration code; the target calibration code includes an upward target calibration code and a downward target calibration code; the code adjustment signal includes an upward code adjustment signal and a downward code adjustment signal; the calibration code generation circuit includes an upward code generation sub-circuit and a downward code generation sub-circuit; the mapping conversion circuit includes an upward conversion sub-circuit and a downward conversion sub-circuit. in; The pull-up code generation sub-circuit is configured to generate the pull-up calibration code in response to the calibration command; The pull-up conversion sub-circuit is configured to: control the pull-up code generation sub-circuit to convert the pull-up calibration code into the pull-up target calibration code in response to the pull-up code adjustment signal; The drop-down code generation sub-circuit is configured to generate the drop-down calibration code in response to the calibration command; The pull-down conversion sub-circuit is configured to: control the pull-down code generation sub-circuit to convert the pull-down calibration code into the pull-down target calibration code in response to the pull-down code adjustment signal.

7. The ZQ calibration circuit according to claim 6, characterized in that, The calibration circuit includes: a pull-up calibration sub-circuit and a pull-down calibration sub-circuit, wherein... The pull-up calibration sub-circuit is configured to perform pull-up calibration on the interface impedance of the target semiconductor device based on the pull-up target calibration code. The pull-down calibration sub-circuit is configured to perform pull-down calibration on the interface impedance of the target semiconductor device based on the pull-down target calibration code.

8. The ZQ calibration circuit according to claim 7, characterized in that, The pull-up calibration sub-circuit includes: a pull-up resistor network and a first pull-down resistor network connected in series; the pull-down calibration sub-circuit includes a second pull-down resistor network; The pull-up resistor network, the first pull-down resistor network, and the second pull-down resistor network include multiple parallel metal-oxide-semiconductor (MOS) transistors.

9. The ZQ calibration circuit according to claim 1, characterized in that, The ZQ calibration circuit further includes a code output circuit, configured to: receive a latch command; and output the target calibration code corresponding to the completion of the current calibration based on the latch command; wherein the latch command is generated when the target calibration code corresponding to the completion of the current calibration is different from the target calibration code corresponding to the completion of the previous calibration.

10. The ZQ calibration circuit according to claim 9, characterized in that, The code output circuit includes: a pull-up code sub-output circuit; the latch command includes a first sub-latch command; the target calibration code includes a pull-up target calibration code; wherein; The pull-up code sub-output circuit includes: a second flip-flop and a third flip-flop connected in series. The second flip-flop is configured to: temporarily store the pull-up target calibration code corresponding to the completion of this calibration. The third flip-flop is configured to: receive a first sub-latch command and output the pull-up target calibration code corresponding to the completion of this calibration based on the first sub-latch command. The first sub-latch command is generated when the pull-up target calibration code corresponding to the completion of this calibration is different from the pull-up target calibration code corresponding to the completion of the previous calibration.

11. The ZQ calibration circuit according to claim 9, characterized in that, The code output circuit includes: a pull-down code sub-output circuit; the latch command includes a second sub-latch command; the target calibration code includes a pull-down target calibration code; wherein; The pull-down code sub-output circuit includes a fourth flip-flop and a fifth flip-flop. The fourth flip-flop is configured to temporarily store the pull-down target calibration code corresponding to the completion of the current calibration. The fifth flip-flop is configured to receive a second sub-latch command and output the pull-down target calibration code corresponding to the completion of the current calibration based on the second sub-latch command. The second sub-latch command is generated when the pull-down target calibration code corresponding to the completion of the current calibration is different from the pull-down target calibration code corresponding to the completion of the previous calibration.

12. A method for operating a memory, characterized in that, The method includes: An initial calibration code is generated based on the received calibration command, and the adjustment step size of the initial calibration code is the initial adjustment step size; The initial calibration code with the initial adjustment step size is converted into a target calibration code with the target adjustment step size; The interface impedance of the target semiconductor device is calibrated based on the target calibration code.

13. The operating method according to claim 12, characterized in that, The target calibration code includes: a first target calibration code and / or a second target calibration code; wherein the adjustment step size of the first target calibration code is greater than or equal to the adjustment step size of the initial calibration code; and the adjustment step size of the second target calibration code is less than or equal to the adjustment step size of the initial calibration code.

14. The operating method according to claim 12, characterized in that, The step of converting the initial calibration code into a target calibration code with a target adjustment step size includes: A code adjustment signal is generated based on the most significant bit of the initial calibration code; the initial calibration code is converted into the target calibration code based on the code adjustment signal; the target calibration code includes a first target calibration code or a second target calibration code.

15. The operating method according to claim 12, characterized in that, The generation of the initial calibration code based on the received calibration command includes: In response to the calibration command, the current voltage is compared with the reference voltage, and a comparison result is generated; The initial calibration code is generated based on the comparison results; Wherein, the current voltage is the current voltage across the interface impedance of the target semiconductor device.

16. The operating method according to claim 15, characterized in that, The step of generating the initial calibration code based on the comparison result includes: The control signal is obtained by sampling the comparison result based on the first clock signal; The initial calibration code is generated based on the control signal and the second clock signal.

17. The operating method according to claim 12, characterized in that, The method further includes: Receive latch command; Based on the latch command, output the target calibration code corresponding to the completion of this calibration; The latch command is generated when the target calibration code corresponding to the completion of this calibration is different from the target calibration code corresponding to the completion of the previous calibration.

18. The operating method according to claim 17, characterized in that, The target calibration code includes a pull-up target calibration code; the step of outputting the target calibration code corresponding to the completion of this calibration based on the latch command includes: Temporarily store the target calibration code corresponding to the completion of this calibration; Receive the first sub-latch command included in the latch command, and output the pull-up target calibration code corresponding to the completion of this calibration based on the first sub-latch command; The first sub-latch command is generated when the target calibration code corresponding to the completion of this calibration is different from the target calibration code corresponding to the completion of the previous calibration.

19. The operating method according to claim 17, characterized in that, The target calibration code includes a drop-down calibration code; the step of outputting the target calibration code corresponding to the completion of this calibration based on the latch command further includes: Temporarily store the drop-down target calibration code corresponding to the completion of this calibration; The system receives the second sub-latch command included in the latch command, and outputs the drop-down target calibration code corresponding to the completion of this calibration based on the second sub-latch command; wherein, the second sub-latch command is generated when the drop-down target calibration code corresponding to the completion of this calibration is different from the drop-down target calibration code corresponding to the completion of the previous calibration.

20. A memory, characterized in that, include: The storage array is configured to store data. And, peripheral circuitry coupled to the memory array and including: a ZQ calibration circuit, wherein: the ZQ calibration circuitry includes: a logic control circuit and a calibration circuit; wherein, The control logic circuit includes: a calibration code generation circuit and a mapping conversion circuit, wherein the calibration code generation circuit is configured to generate an initial calibration code in response to a calibration command, the adjustment step size of the initial calibration code being an initial adjustment step size; the mapping conversion circuit is configured to control the calibration code generation circuit to convert the initial calibration code having the initial adjustment step size into a target calibration code with a target adjustment step size in response to a code adjustment signal. The calibration circuit is configured to calibrate the interface impedance of the target semiconductor device based on the target calibration code.

21. The memory according to claim 20, characterized in that, The storage array is a three-dimensional NAND storage array.

22. A storage system, characterized in that, include: One or more memory units; The memory includes: a memory array configured to store data; and peripheral circuitry coupled to the memory array and including: a ZQ calibration circuitry, wherein: the ZQ calibration circuitry includes: a logic control circuitry and a calibration circuitry; wherein the control logic circuitry includes: a calibration code generation circuitry and a mapping conversion circuitry, wherein the calibration code generation circuitry is configured to generate an initial calibration code in response to a calibration command, the initial calibration code having an adjustment step size of an initial adjustment step size; the mapping conversion circuitry is configured to control the calibration code generation circuitry to convert the initial calibration code having the initial adjustment step size into a target calibration code with a target adjustment step size in response to a code adjustment signal; the calibration circuitry is configured to calibrate the interface impedance of a target semiconductor based on the target calibration codery; A memory controller, which is coupled to the one or more memories and configured to control the memories.

23. The storage system according to claim 22, characterized in that, The storage system is contained in solid-state drives (SSDs) or memory cards.

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