A tbc solar cell and a method of manufacturing the same

Abstract

The application discloses a TBC solar cell and a preparation method thereof. The preparation method comprises two boron diffusion steps and two phosphorus diffusion steps, and a first dense tunneling oxide layer, a first non-dense tunneling oxide layer, a second dense tunneling oxide layer and a second non-dense tunneling oxide layer are deposited. While ensuring that the first and second polycrystalline silicon layers have high doping concentrations, the first and second dense tunneling oxide layers effectively prevent the diffusion depth of doping ions in the silicon substrate, thereby improving the collection efficiency of carriers and maintaining good passivation effects. In addition, the first electrode grid is embedded in the first non-dense tunneling oxide layer, and the second electrode grid is embedded in the second non-dense tunneling oxide layer, so that the contact effect is good, the absorption efficiency of the first and second electrode grids for the carriers transported in the transverse direction is enhanced, and compared with the prior art, the process difficulty is low and the error rate is low.

Description

Technical Field

[0001] This invention relates to the field of photovoltaic cell manufacturing technology, specifically to a TBC solar cell and its preparation method. Background Technology

[0002] Solar cells, also known as photovoltaic cells, have become the choice for the new era due to their unique advantages. They can directly convert solar energy into electrical energy, based on the photovoltaic effect of semiconductor PN junctions. In the industrialization of solar cells, low cost and high efficiency have always been the continuous pursuit.

[0003] Existing TBC (Transient Charge Cycle) cells face a design challenge: how to improve the carrier collection efficiency of the back grid while maintaining good passivation. Typically, to enhance carrier collection efficiency, the polycrystalline silicon layer requires a high doping concentration to increase its conductivity. However, a high doping concentration also increases the diffusion depth of dopant ions in the silicon substrate. If this diffusion depth exceeds the thickness of the tunneling layer, it may compromise the integrity of the tunneling layer, affecting passivation and consequently impacting cell performance and stability.

[0004] On the other hand, if the doping concentration of the polycrystalline silicon layer is reduced in order to achieve better passivation effect and reduce the diffusion depth of dopant ions in the silicon substrate, it will increase the difficulty of carrier collection by the back gate line, thereby affecting the overall photoelectric conversion efficiency of the battery.

[0005] Furthermore, an appropriate distance is typically required between the back gate lines and the tunneling layer to avoid hindering the lateral transport of charge carriers in the polysilicon layer, thereby maximizing the cell's efficiency. However, if the distance between the back gate lines and the tunneling layer is not set properly, it will directly affect the cell's photoelectric conversion efficiency, thus placing higher demands on the manufacturing process and increasing manufacturing costs. Summary of the Invention

[0006] The purpose of this invention is to provide a TBC solar cell and its fabrication method, in order to solve the problem in the prior art that it is difficult to maintain a good passivation effect while improving the carrier collection efficiency of the back grid lines, and the problem that the manufacturing cost is increased in order to ensure that the distance between the back grid lines and the tunneling layer is set properly.

[0007] To solve the technical problems in the prior art, the technical solution adopted by the present invention is as follows:

[0008] A method for preparing a TBC solar cell includes the following steps:

[0009] S1: Double-sided polishing of the N-type silicon substrate, first boron diffusion to form the front PN junction and the back PN junction;

[0010] S2: A first dense tunneling oxide layer, a first non-dense tunneling oxide layer, and a first polycrystalline silicon layer are sequentially deposited on the back side of an N-type silicon substrate; a second boron diffusion layer is formed to create a P-type polycrystalline silicon layer on the back side, and a back side BSG layer is also formed.

[0011] S3: Laser removal of the backside BSG layer between the N-region and the Gap region on the backside of the N-type silicon substrate;

[0012] The first acid pickling removes the front and side surfaces of the N-type silicon substrate to form a wrapped BSG layer;

[0013] The first alkaline wash removes the back P-type polycrystalline silicon layer from the N-region and Gap region on the back of the N-type silicon substrate, and forms an expanded P-type polycrystalline silicon layer on the front and side of the N-type silicon substrate.

[0014] The second acid pickling removes the first non-dense tunneling oxide layer and the first dense tunneling oxide layer formed on the front and side surfaces of the N-type silicon substrate, as well as the first non-dense tunneling oxide layer and the first dense tunneling oxide layer in the N region and the Gap region on the back surface of the N-type silicon substrate.

[0015] The second alkaline wash removes the front PN junction of the N-type silicon substrate and the back PN junction of the N-region and Gap region on the back of the N-type silicon substrate;

[0016] S4: The first phosphorus diffusion forms a front N+ layer on the front side of the N-type silicon substrate and a back N+ layer on the back side of the N-type silicon substrate in the N region and Gap region.

[0017] S5: A second dense tunneling oxide layer, a second non-dense tunneling oxide layer, and a second polycrystalline silicon layer are sequentially deposited on the back side of the N-type silicon substrate; a second phosphorus diffusion is performed to form the back-side N-type polycrystalline silicon layer and the back-side PSG layer.

[0018] S6: Laser removal of the back PSG layer between the P-region and the Gap region on the back of the N-type silicon substrate;

[0019] The third acid pickling process removes the PSG layer formed on the front and side surfaces of the N-type silicon substrate.

[0020] The third alkaline wash removes the back N-type polycrystalline silicon layer on the P-region and Gap region of the N-type silicon substrate, and forms an expanded N-type polycrystalline silicon layer on the front and side of the N-type silicon substrate.

[0021] The fourth acid pickling removes the second non-dense tunneling oxide layer and the second dense tunneling oxide layer formed on the front and side surfaces of the N-type silicon substrate, as well as the second non-dense tunneling oxide layer and the second dense tunneling oxide layer in the P-region and Gap region on the back surface of the N-type silicon substrate.

[0022] The fourth alkaline wash removes the N+ layer on the front side of the N-type silicon substrate and the N+ layer on the back side of the Gap region of the N-type silicon substrate;

[0023] S7: Texturing the gap areas on the front and back sides of the N-type silicon substrate; the fifth acid pickling removes the back BSG layer of the P-region and the back PSG layer of the N-region on the back side of the N-type silicon substrate.

[0024] S8: Alumina layer is deposited on an N-type silicon substrate by ALD;

[0025] S9: Deposit a front passivation film and a back passivation film on an N-type silicon substrate;

[0026] S10: Print a first electrode gate line in the P region and a second electrode gate line in the N region on the back side of the N-type silicon substrate, respectively. The first electrode gate line passes through the back passivation film, the back alumina layer, and the back P-type polysilicon layer in sequence and is embedded in the first non-dense tunneling oxide layer. The second electrode gate line passes through the back passivation film, the back alumina layer, and the back N-type polysilicon layer in sequence and is embedded in the second non-dense tunneling oxide layer.

[0027] Preferably, in step S1, the double-sided polishing of the N-type silicon substrate includes:

[0028] S11: The N-type silicon substrate is subjected to the first double-sided polishing in a wet alkaline polishing tank. The alkaline solution used for the first double-sided polishing is composed of H2O, NaOH and polishing additives in a volume ratio of 290-310:10-20:2-8, wherein the NaOH concentration is 1%-5%, the process time is 80s-120s, and the tank temperature of the wet alkaline polishing tank is 50℃-75℃.

[0029] S12: The N-type silicon substrate is subjected to a second double-sided polishing in a wet alkaline polishing tank. The alkaline solution used for the second double-sided polishing is composed of H2O, NaOH and polishing additives in a volume ratio of 290-310:10-20:2-8, wherein the NaOH concentration is 1%-5%, the process time is 350s-450s, and the temperature of the wet alkaline polishing tank is 50℃-75℃.

[0030] Preferably, in step S1, the diffusion temperature of the first boron diffusion is 800℃~900℃, and the diffusion time is 40s~60s.

[0031] Preferably, in step S2, the deposition time of the first dense tunneling oxide layer is 300s to 500s, the deposition temperature is 600℃ to 700℃, and the thickness of the first dense tunneling oxide layer is 2±0.2nm.

[0032] The deposition time of the first non-dense tunneling oxide layer is 500s to 700s, the deposition temperature is 500℃ to 600℃, and the thickness of the first non-dense tunneling oxide layer is 2.5±0.3nm.

[0033] The deposition time of the first polycrystalline silicon layer is 11000s to 13000s, the deposition temperature is 500℃ to 600℃, and the thickness of the first polycrystalline silicon layer is 300±10nm.

[0034] The diffusion temperature of the second boron diffusion is 700℃~900℃, the diffusion time is 200s~400s, the oxidation temperature is 850℃~950℃, the oxidation time is 3000s~3500s, the annealing temperature is 700℃~900℃, and the annealing time is 1300s~1700s. The thickness of the back side BSG layer is 90±5nm.

[0035] Preferably, in step S3, the laser power is 45% and the overlap rate is 55%;

[0036] The first pickling is carried out by a wet acid tank chain machine. The tank temperature of the wet acid tank chain machine is 30℃~50℃, and the process time is 70s~90s. The acid solution used for the first pickling is composed of H2O and HF in a volume ratio of 1~5:2.

[0037] The first alkaline wash is carried out using a wet alkaline polishing tank machine. The tank temperature of the wet alkaline polishing tank machine is 50℃~75℃, and the process time is 100s~200s. The alkaline solution used for the first alkaline wash is composed of H2O, NaOH and polishing additives in a volume ratio of 290~310:10~20:2~8, wherein the NaOH concentration is 1%~5%.

[0038] The second pickling is carried out using a wet acid polishing tank machine. The tank temperature of the wet acid polishing tank machine is 30℃~50℃, and the process time is 10s~30s. The acid solution used for the second pickling is composed of H2O and HF in a volume ratio of 7~11:1.

[0039] The second alkaline wash is performed using a wet alkaline polishing tank machine. The tank temperature of the wet alkaline polishing tank machine is 50℃~75℃, and the process time is 200s~400s. The alkaline solution used for the second alkaline wash is composed of H2O, NaOH and polishing additives in a volume ratio of 290~310:15~22:2~8, wherein the NaOH concentration is 1%~5%.

[0040] Preferably, in step S4, the diffusion temperature of the first phosphorus diffusion is 700℃~800℃, and the diffusion time is 100s~150s.

[0041] Preferably, in step S5, the deposition time of the second dense tunneling oxide layer is 300s to 500s, the deposition temperature is 600℃ to 700℃, and the thickness of the second dense tunneling oxide layer is 2±0.2nm.

[0042] The deposition time of the second non-dense tunneling oxide layer is 500s to 700s, the deposition temperature is 500℃ to 600℃, and the thickness of the second non-dense tunneling oxide layer is 2.5±0.3nm.

[0043] The deposition time of the second polysilicon layer is 11000s to 13000s, the deposition temperature is 500℃ to 600℃, and the thickness of the second polysilicon layer is 300±10nm.

[0044] The diffusion temperature of the second phosphorus diffusion is 850℃~950℃, the diffusion time is 1000s~1500s, the oxidation temperature is 850℃~950℃, the oxidation time is 500s~700s, and the thickness of the back PSG layer is 50±5nm.

[0045] Preferably, in step S6, the laser power is 40% and the overlap rate is 60%;

[0046] The third pickling is carried out by a wet acid tank chain machine. The tank temperature of the wet acid tank chain machine is 30℃~50℃, the process time is 40s~60s, and the acid solution used for the third pickling is composed of H2O and HF in a volume ratio of 1~5:2.

[0047] The third alkaline wash is carried out using a wet alkaline polishing tank machine. The tank temperature of the wet alkaline polishing tank machine is 50℃~75℃, and the process time is 100s~200s. The alkaline solution used for the third alkaline wash is composed of H2O, NaOH and polishing additives in a volume ratio of 290~310:10~20:2~8, wherein the NaOH concentration is 1%~5%.

[0048] The fourth pickling is carried out using a wet acid polishing tank machine. The tank temperature of the wet acid polishing tank machine is 30℃~50℃, and the process time is 10s~30s. The acid solution used for the fourth pickling is composed of H2O and HF in a volume ratio of 7~11:1.

[0049] The fourth alkaline wash is performed using a wet alkaline polishing tank machine. The tank temperature of the wet alkaline polishing tank machine is 50℃~75℃, and the process time is 200s~400s. The alkaline solution used in the fourth alkaline wash is composed of H2O, NaOH and polishing additives in a volume ratio of 290~310:15~22:2~8, of which the NaOH concentration is 1%~5%.

[0050] Preferably, in step S7, the texturing process uses a texturing alkaline solution, which is composed of H2O, NaOH, and texturing additives in a volume ratio of 290-310:8-15:1-6, wherein the NaOH concentration is 1%-3%; the temperature of the texturing alkaline solution is 60-70°C, and the texturing process time is 350-450 seconds.

[0051] The fifth pickling process uses an acid solution composed of H2O and HF in a volume ratio of 1 to 5:2, with a process time of 150 to 250 seconds and a solution temperature of 40 to 50 degrees Celsius.

[0052] Preferably, in step S8, the deposition temperature of the alumina layer is 180±20℃, the deposition time is 300±40s, and the thickness of the alumina layer is 5±1nm.

[0053] Preferably, in step S9, the coating process temperature is 500°C and the process time per nanometer is 5–15 seconds;

[0054] The front passivation film has a 6-layer structure, including silicon nitride a: 8±3nm; silicon nitride b: 14±4nm; silicon nitride c: 20±4nm; silicon oxynitride a: 12±4nm; silicon oxynitride b: 10±3nm; and silicon dioxide: 6±2nm.

[0055] The back passivation film has a three-layer structure, including silicon nitride d: 20±2nm; silicon nitride e: 20±2nm; silicon nitride f: 50±5nm.

[0056] This application also claims a TBC solar cell prepared using the TBC solar cell preparation method described above.

[0057] Due to the application of the above technical solution, the beneficial effects of this application compared with the prior art are as follows:

[0058] The process route designed in this application includes two boron expansion steps and two phosphorus expansion steps, and involves depositing a first dense tunneling oxide layer, a first non-dense tunneling oxide layer, a second dense tunneling oxide layer, and a second non-dense tunneling oxide layer. While ensuring high doping concentrations in the first and second polycrystalline silicon layers, the first and second dense tunneling oxide layers effectively prevent the diffusion depth of dopant ions in the silicon substrate, thereby improving carrier collection efficiency and maintaining good passivation effect.

[0059] Furthermore, the first electrode gate line is embedded in the first non-dense tunneling oxide layer, and the second electrode gate line is embedded in the second non-dense tunneling oxide layer, resulting in good contact and enhancing the absorption efficiency of the first and second electrode gate lines for laterally transported charge carriers. Compared with the prior art, which requires setting an appropriate distance between the back gate line and the tunneling layer, the process is less difficult and has a lower error rate. Attached Figure Description

[0060] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0061] Figure 1 This is a schematic diagram of the TBC solar cell structure in Embodiment 2 of the present invention.

[0062] Explanation of reference numerals in the attached figures:

[0063] 1-N-type silicon substrate; 2-Front-side textured structure; 3-Front-side alumina layer; 4-Front-side passivation film; 5-Back-side PN junction; 6-First dense tunneling oxide layer; 7-First non-dense tunneling oxide layer; 8-Back-side P-type polysilicon layer; 9-Back-side alumina layer; 10-Back-side passivation film; 20-Back-side textured structure; 30-Back-side N+ layer; 40-Second dense tunneling oxide layer; 50-Second non-dense tunneling oxide layer; 60-Back-side N-type polysilicon layer; 100-First electrode gate line; 200-Second electrode gate line. Detailed Implementation

[0064] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0065] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0066] In this application, the terms "upper," "lower," "left," "right," "front," "rear," "top," "bottom," "inner," "outer," "middle," "vertical," "horizontal," "lateral," and "longitudinal" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are primarily for the purpose of better describing the invention and its embodiments, and are not intended to limit the indicated device, element, or component to having a specific orientation, or to be constructed and operated in a specific orientation.

[0067] Furthermore, in addition to indicating direction or positional relationship, some of the aforementioned terms may also have other meanings. For example, the term "above" may also be used in certain situations to indicate a dependency or connection. Those skilled in the art can understand the specific meaning of these terms in this invention based on the specific circumstances.

[0068] Furthermore, the terms "installation," "setup," "equipped with," "connection," "linking," and "socketing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral structure; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium, or an internal connection between two devices, components, or parts. Those skilled in the art can understand the specific meaning of these terms in this invention based on the specific circumstances.

[0069] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0070] Example 1

[0071] This embodiment relates to a method for preparing a TBC solar cell, including the following steps:

[0072] S1: Double-sided polishing of the N-type silicon substrate, first boron diffusion to form the front PN junction and the back PN junction;

[0073] S2: A first dense tunneling oxide layer, a first non-dense tunneling oxide layer, and a first polycrystalline silicon layer are sequentially deposited on the back side of an N-type silicon substrate; a second boron diffusion layer is formed to create a P-type polycrystalline silicon layer on the back side, and a back side BSG layer is also formed.

[0074] S3: Laser removal of the backside BSG layer between the N-region and the Gap region on the backside of the N-type silicon substrate;

[0075] The first acid pickling removes the front and side surfaces of the N-type silicon substrate to form a wrapped BSG layer;

[0076] The first alkaline wash removes the back P-type polycrystalline silicon layer on the back of the N-type silicon substrate from the N-region and Gap region, and forms an expanded P-type polycrystalline silicon layer on the front and side of the N-type silicon substrate.

[0077] The second acid pickling removes the first non-dense tunneling oxide layer and the first dense tunneling oxide layer formed on the front and side surfaces of the N-type silicon substrate, as well as the first non-dense tunneling oxide layer and the first dense tunneling oxide layer in the N region and the Gap region on the back surface of the N-type silicon substrate.

[0078] The second alkaline wash removes the front PN junction of the N-type silicon substrate and the back PN junction of the N-region and Gap region on the back of the N-type silicon substrate;

[0079] S4: The first phosphorus diffusion forms a front N+ layer on the front side of the N-type silicon substrate and a back N+ layer on the back side of the N-type silicon substrate in the N region and Gap region.

[0080] S5: A second dense tunneling oxide layer, a second non-dense tunneling oxide layer, and a second polycrystalline silicon layer are sequentially deposited on the back side of the N-type silicon substrate; a second phosphorus diffusion is performed to form the back-side N-type polycrystalline silicon layer and the back-side PSG layer.

[0081] S6: Laser removal of the back PSG layer between the P-region and the Gap region on the back of the N-type silicon substrate;

[0082] The third acid pickling process removes the PSG layer formed on the front and side surfaces of the N-type silicon substrate.

[0083] The third alkaline wash removes the back N-type polysilicon layer from the P-region and Gap region on the back of the N-type silicon substrate, and forms an expanded N-type polysilicon layer on the front and side of the N-type silicon substrate.

[0084] The fourth acid pickling removes the second non-dense tunneling oxide layer and the second dense tunneling oxide layer formed on the front and side surfaces of the N-type silicon substrate, as well as the second non-dense tunneling oxide layer and the second dense tunneling oxide layer in the P-region and Gap region on the back surface of the N-type silicon substrate.

[0085] The fourth alkaline wash removes the N+ layer on the front side of the N-type silicon substrate and the N+ layer on the back side of the Gap region of the N-type silicon substrate;

[0086] S7: Texturing the gap areas on the front and back sides of the N-type silicon substrate; the fifth acid pickling removes the back BSG layer of the P-region and the back PSG layer of the N-region on the back side of the N-type silicon substrate.

[0087] S8: Alumina layer is deposited on an N-type silicon substrate by ALD;

[0088] S9: Deposit a front passivation film and a back passivation film on an N-type silicon substrate;

[0089] S10: Print a first electrode gate line in the P region and a second electrode gate line in the N region on the back side of the N-type silicon substrate, respectively. The first electrode gate line passes through the back passivation film, the back alumina layer, and the back P-type polysilicon layer in sequence and is embedded in the first non-dense tunneling oxide layer. The second electrode gate line passes through the back passivation film, the back alumina layer, and the back N-type polysilicon layer in sequence and is embedded in the second non-dense tunneling oxide layer.

[0090] Preferably, in step S1, the N-type silicon substrate is polished on both sides, including:

[0091] S11: The N-type silicon substrate is subjected to the first double-sided polishing in a wet alkaline polishing tank. The alkaline solution used for the first double-sided polishing is composed of H2O, NaOH and polishing additives in a volume ratio of 290-310:10-20:2-8, wherein the NaOH concentration is 1%-5%, the process time is 80s-120s, and the tank temperature of the wet alkaline polishing tank is 50℃-75℃.

[0092] S12: The N-type silicon substrate is subjected to a second double-sided polishing in a wet alkaline polishing tank. The alkaline solution used for the second double-sided polishing is composed of H2O, NaOH and polishing additives in a volume ratio of 290-310:10-20:2-8, wherein the NaOH concentration is 1%-5%, the process time is 350s-450s, and the temperature of the wet alkaline polishing tank is 50℃-75℃.

[0093] Preferably, in step S1, the diffusion temperature of the first boron diffusion is 800℃~900℃, and the diffusion time is 40s~60s.

[0094] Preferably, in step S2, the deposition time of the first dense tunneling oxide layer is 300s to 500s, the deposition temperature is 600℃ to 700℃, and the thickness of the first dense tunneling oxide layer is 2±0.2nm.

[0095] The deposition time of the first non-dense tunneling oxide layer is 500s to 700s, the deposition temperature is 500℃ to 600℃, and the thickness of the first non-dense tunneling oxide layer is 2.5±0.3nm.

[0096] The deposition time of the first polycrystalline silicon layer is 11000s~13000s, the deposition temperature is 500℃~600℃, and the thickness of the first polycrystalline silicon layer is 300±10nm;

[0097] The diffusion temperature of the second boron diffusion is 700℃~900℃, the diffusion time is 200s~400s, the oxidation temperature is 850℃~950℃, the oxidation time is 3000s~3500s, the annealing temperature is 700℃~900℃, the annealing time is 1300s~1700s, and the thickness of the BSG layer on the back side is 90±5nm.

[0098] Preferably, in step S3, the laser power is 45% and the overlap rate is 55%;

[0099] The first pickling is carried out by a wet acid tank chain machine. The tank temperature of the wet acid tank chain machine is 30℃~50℃, and the process time is 70s~90s. The acid solution used for the first pickling is composed of H2O and HF in a volume ratio of 1~5:2.

[0100] The first alkaline wash is carried out using a wet alkaline polishing tank machine. The tank temperature of the wet alkaline polishing tank machine is 50℃~75℃, and the process time is 100s~200s. The alkaline solution used for the first alkaline wash is composed of H2O, NaOH and polishing additives in a volume ratio of 290~310:10~20:2~8, wherein the NaOH concentration is 1%~5%.

[0101] The second pickling is carried out using a wet acid polishing tank machine. The tank temperature of the wet acid polishing tank machine is 30℃~50℃, and the process time is 10s~30s. The acid solution used for the second pickling is composed of H2O and HF in a volume ratio of 7~11:1.

[0102] The second alkaline wash is performed using a wet alkaline polishing tank machine. The tank temperature of the wet alkaline polishing tank machine is 50℃~75℃, and the process time is 200s~400s. The alkaline solution used for the second alkaline wash is composed of H2O, NaOH and polishing additives in a volume ratio of 290~310:15~22:2~8, wherein the NaOH concentration is 1%~5%.

[0103] Preferably, in step S4, the diffusion temperature of the first phosphorus diffusion is 700℃~800℃, and the diffusion time is 100s~150s.

[0104] Preferably, in step S5, the deposition time of the second dense tunneling oxide layer is 300s to 500s, the deposition temperature is 600℃ to 700℃, and the thickness of the second dense tunneling oxide layer is 2±0.2nm.

[0105] The deposition time of the second non-dense tunneling oxide layer is 500s to 700s, the deposition temperature is 500℃ to 600℃, and the thickness of the second non-dense tunneling oxide layer is 2.5±0.3nm.

[0106] The deposition time of the second polysilicon layer is 11000s to 13000s, the deposition temperature is 500℃ to 600℃, and the thickness of the second polysilicon layer is 300±10nm.

[0107] The diffusion temperature of the second phosphorus diffusion was 850℃~950℃, the diffusion time was 1000s~1500s, the oxidation temperature was 850℃~950℃, the oxidation time was 500s~700s, and the thickness of the PSG layer on the back side was 50±5nm.

[0108] Preferably, in step S6, the laser power is 40% and the overlap rate is 60%;

[0109] The third pickling is carried out by a wet acid tank chain machine. The tank temperature of the wet acid tank chain machine is 30℃~50℃, the process time is 40s~60s, and the acid solution used for the third pickling is composed of H2O and HF in a volume ratio of 1~5:2.

[0110] The third alkaline wash is carried out using a wet alkaline polishing tank machine. The tank temperature of the wet alkaline polishing tank machine is 50℃~75℃, and the process time is 100s~200s. The alkaline solution used for the third alkaline wash is composed of H2O, NaOH and polishing additives in a volume ratio of 290~310:10~20:2~8, wherein the NaOH concentration is 1%~5%.

[0111] The fourth pickling is carried out using a wet acid polishing tank machine. The tank temperature of the wet acid polishing tank machine is 30℃~50℃, and the process time is 10s~30s. The acid solution used for the fourth pickling is composed of H2O and HF in a volume ratio of 7~11:1.

[0112] The fourth alkaline wash is performed using a wet alkaline polishing tank machine. The tank temperature of the wet alkaline polishing tank machine is 50℃~75℃, and the process time is 200s~400s. The alkaline solution used in the fourth alkaline wash is composed of H2O, NaOH and polishing additives in a volume ratio of 290~310:15~22:2~8, of which the NaOH concentration is 1%~5%.

[0113] Preferably, in step S7, the texturing process uses an alkaline solution for texturing, which is composed of H2O, NaOH, and texturing additives in a volume ratio of 290-310:8-15:1-6, wherein the NaOH concentration is 1%-3%; the temperature of the alkaline solution for texturing is 60-70°C, and the texturing process time is 350-450 seconds.

[0114] The fifth pickling process uses an acid solution composed of H2O and HF in a volume ratio of 1 to 5:2, with a process time of 150 to 250 seconds and a solution temperature of 40 to 50 degrees Celsius.

[0115] Preferably, in step S8, the deposition temperature of the alumina layer is 180±20℃, the deposition time is 300±40s, and the thickness of the alumina layer is 5±1nm.

[0116] Preferably, in step S9, the coating process temperature is 500°C and the process time per nanometer is 5–15 seconds;

[0117] The passivation film on the front side has a 6-layer structure, including silicon nitride a: 8±3nm; silicon nitride b: 14±4nm; silicon nitride c: 20±4nm; silicon oxynitride a: 12±4nm; silicon oxynitride b: 10±3nm; and silicon dioxide: 6±2nm.

[0118] The back passivation film has a three-layer structure, including silicon nitride d: 20±2nm; silicon nitride e: 20±2nm; silicon nitride f: 50±5nm.

[0119] Example 2

[0120] like Figure 1 As shown, this embodiment relates to a TBC solar cell, which is prepared using the TBC solar cell preparation method described in Example 1.

[0121] In this embodiment, the TBC solar cell includes an N-type silicon substrate 1, and the front side of the N-type silicon substrate 1 consists of a front textured structure 2, a front alumina layer 3, and a front passivation film 4, arranged from the inside out.

[0122] The back side of the N-type silicon substrate 1 has N-regions, gap regions, and P-regions arranged sequentially. For example... Figure 1 As shown, the N region, Gap region, and P region are arranged from left to right.

[0123] At the P region, the back side of the N-type silicon substrate 1, from the inside out, consists of a back PN junction 5, a first dense tunneling oxide layer 6, a first non-dense tunneling oxide layer 7, a back P-type polycrystalline silicon layer 8, a back aluminum oxide layer 9, and a back passivation film 10.

[0124] At the gap region, the back side of the N-type silicon substrate 1 consists of a back textured structure 20, a back aluminum oxide layer 9, and a back passivation film 10, arranged from the inside out.

[0125] At the N region, the back side of the N-type silicon substrate 1 consists of, from the inside out, a back N+ layer 30, a second dense tunneling oxide layer 40, a second non-dense tunneling oxide layer 50, a back N-type polycrystalline silicon layer 60, a back aluminum oxide layer 9, and a back passivation film 10.

[0126] The back side of the N-type silicon substrate 1 is also provided with a first electrode gate line 100 and a second electrode gate line 200. The first electrode gate line 100 passes through the back passivation film 10, the back alumina layer 9, and the back P-type polysilicon layer 8 in sequence and is embedded in the first non-dense tunneling oxide layer 7. The second electrode gate line 200 passes through the back passivation film 10, the back alumina layer 9, and the back N-type polysilicon layer 60 in sequence and is embedded in the second non-dense tunneling oxide layer 50.

[0127] Due to the application of the above technical solution, the beneficial effects of this application compared with the prior art are as follows:

[0128] The process route designed in this application includes two boron expansion steps and two phosphorus expansion steps, and involves depositing a first dense tunneling oxide layer, a first non-dense tunneling oxide layer, a second dense tunneling oxide layer, and a second non-dense tunneling oxide layer. While ensuring high doping concentrations in the first and second polycrystalline silicon layers, the first and second dense tunneling oxide layers effectively prevent the diffusion depth of dopant ions in the silicon substrate, thereby improving carrier collection efficiency and maintaining good passivation effect.

[0129] Furthermore, the first electrode gate line is embedded in the first non-dense tunneling oxide layer, and the second electrode gate line is embedded in the second non-dense tunneling oxide layer, resulting in good contact and enhancing the absorption efficiency of the first and second electrode gate lines for laterally transported charge carriers. Compared with the prior art, which requires setting an appropriate distance between the back gate line and the tunneling layer, the process is less difficult and has a lower error rate.

[0130] Finally, it should be noted that the above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for preparing a TBC solar cell, characterized in that, Includes the following steps: S1: Double-sided polishing of the N-type silicon substrate, first boron diffusion to form the front PN junction and the back PN junction; S2: A first dense tunneling oxide layer, a first non-dense tunneling oxide layer, and a first polycrystalline silicon layer are sequentially deposited on the back side of an N-type silicon substrate; a second boron diffusion layer is formed to create a P-type polycrystalline silicon layer on the back side, and a back side BSG layer is also formed. S3: Laser removal of the backside BSG layer between the N-region and the Gap region on the backside of the N-type silicon substrate; The first acid pickling removes the front and side surfaces of the N-type silicon substrate to form a wrapped BSG layer; The first alkaline wash removes the back P-type polycrystalline silicon layer on the back of the N-type silicon substrate from the N-region and Gap region, and forms an expanded P-type polycrystalline silicon layer on the front and side of the N-type silicon substrate. The second acid pickling removes the first non-dense tunneling oxide layer and the first dense tunneling oxide layer formed on the front and side surfaces of the N-type silicon substrate, as well as the first non-dense tunneling oxide layer and the first dense tunneling oxide layer in the N region and the Gap region on the back surface of the N-type silicon substrate. The second alkaline wash removes the front PN junction of the N-type silicon substrate and the back PN junction of the N-region and Gap region on the back of the N-type silicon substrate; S4: The first phosphorus diffusion forms a front N+ layer on the front side of the N-type silicon substrate and a back N+ layer on the back side of the N-type silicon substrate in the N region and Gap region. S5: A second dense tunneling oxide layer, a second non-dense tunneling oxide layer, and a second polycrystalline silicon layer are sequentially deposited on the back side of the N-type silicon substrate; a second phosphorus diffusion is performed to form the back-side N-type polycrystalline silicon layer and the back-side PSG layer. S6: Laser removal of the back PSG layer between the P-region and the Gap region on the back of the N-type silicon substrate; The third acid pickling process removes the PSG layer formed on the front and side surfaces of the N-type silicon substrate. The third alkaline wash removes the back N-type polysilicon layer from the P-region and Gap region on the back of the N-type silicon substrate, and forms an expanded N-type polysilicon layer on the front and side of the N-type silicon substrate. The fourth acid pickling removes the second non-dense tunneling oxide layer and the second dense tunneling oxide layer formed on the front and side surfaces of the N-type silicon substrate, as well as the second non-dense tunneling oxide layer and the second dense tunneling oxide layer in the P-region and Gap region on the back surface of the N-type silicon substrate. The fourth alkaline wash removes the N+ layer on the front side of the N-type silicon substrate and the N+ layer on the back side of the Gap region of the N-type silicon substrate; S7: Texturing the gap areas on the front and back sides of the N-type silicon substrate; the fifth acid pickling removes the back BSG layer of the P-region and the back PSG layer of the N-region on the back side of the N-type silicon substrate. S8: Alumina layer is deposited on an N-type silicon substrate by ALD; S9: Deposit a front passivation film and a back passivation film on an N-type silicon substrate; S10: Print a first electrode gate line in the P region and a second electrode gate line in the N region on the back side of the N-type silicon substrate, respectively. The first electrode gate line passes through the back passivation film, the back alumina layer, and the back P-type polysilicon layer in sequence and is embedded in the first non-dense tunneling oxide layer. The second electrode gate line passes through the back passivation film, the back alumina layer, and the back N-type polysilicon layer in sequence and is embedded in the second non-dense tunneling oxide layer.

2. The method for preparing a TBC solar cell as described in claim 1, characterized in that, In step S1, the double-sided polishing of the N-type silicon substrate includes: S11: The N-type silicon substrate is subjected to the first double-sided polishing in a wet alkaline polishing tank. The alkaline solution used for the first double-sided polishing is composed of H2O, NaOH and polishing additives in a volume ratio of 290-310:10-20:2-8, wherein the NaOH concentration is 1%-5%, the process time is 80s-120s, and the tank temperature of the wet alkaline polishing tank is 50℃-75℃. S12: The N-type silicon substrate is subjected to a second double-sided polishing in a wet alkaline polishing tank. The alkaline solution used for the second double-sided polishing is composed of H2O, NaOH and polishing additives in a volume ratio of 290-310:10-20:2-8, wherein the NaOH concentration is 1%-5%, the process time is 350s-450s, and the temperature of the wet alkaline polishing tank is 50℃-75℃.

3. The method for preparing a TBC solar cell as described in claim 1, characterized in that, In step S1, the diffusion temperature of the first boron diffusion is 800℃~900℃, and the diffusion time is 40s~60s.

4. The method for preparing a TBC solar cell as described in claim 1, characterized in that, In step S2, the deposition time of the first dense tunneling oxide layer is 300s to 500s, the deposition temperature is 600℃ to 700℃, and the thickness of the first dense tunneling oxide layer is 2±0.2nm. The deposition time of the first non-dense tunneling oxide layer is 500s to 700s, the deposition temperature is 500℃ to 600℃, and the thickness of the first non-dense tunneling oxide layer is 2.5±0.3nm. The deposition time of the first polycrystalline silicon layer is 11000s to 13000s, the deposition temperature is 500℃ to 600℃, and the thickness of the first polycrystalline silicon layer is 300±10nm. The diffusion temperature of the second boron diffusion is 700℃~900℃, the diffusion time is 200s~400s, the oxidation temperature is 850℃~950℃, the oxidation time is 3000s~3500s, the annealing temperature is 700℃~900℃, and the annealing time is 1300s~1700s. The thickness of the back side BSG layer is 90±5nm.

5. The method for preparing a TBC solar cell as described in claim 1, characterized in that, In step S3, the laser power is 45% and the overlap rate is 55%. The first pickling is carried out by a wet acid tank chain machine. The tank temperature of the wet acid tank chain machine is 30℃~50℃, and the process time is 70s~90s. The acid solution used for the first pickling is composed of H2O and HF in a volume ratio of 1~5:

2. The first alkaline wash is carried out using a wet alkaline polishing tank machine. The tank temperature of the wet alkaline polishing tank machine is 50℃~75℃, and the process time is 100s~200s. The alkaline solution used for the first alkaline wash is composed of H2O, NaOH and polishing additives in a volume ratio of 290~310:10~20:2~8, wherein the NaOH concentration is 1%~5%. The second pickling is carried out using a wet acid polishing tank machine. The tank temperature of the wet acid polishing tank machine is 30℃~50℃, and the process time is 10s~30s. The acid solution used for the second pickling is composed of H2O and HF in a volume ratio of 7~11:

1. The second alkaline wash is performed using a wet alkaline polishing tank machine. The tank temperature of the wet alkaline polishing tank machine is 50℃~75℃, and the process time is 200s~400s. The alkaline solution used for the second alkaline wash is composed of H2O, NaOH and polishing additives in a volume ratio of 290~310:15~22:2~8, wherein the NaOH concentration is 1%~5%.

6. The method for preparing a TBC solar cell as described in claim 1, characterized in that, In step S4, the diffusion temperature of the first phosphorus diffusion is 700℃~800℃, and the diffusion time is 100s~150s.

7. The method for preparing a TBC solar cell as described in claim 1, characterized in that, In step S5, the deposition time of the second dense tunneling oxide layer is 300s to 500s, the deposition temperature is 600℃ to 700℃, and the thickness of the second dense tunneling oxide layer is 2±0.2nm. The deposition time of the second non-dense tunneling oxide layer is 500s to 700s, the deposition temperature is 500℃ to 600℃, and the thickness of the second non-dense tunneling oxide layer is 2.5±0.3nm. The deposition time of the second polysilicon layer is 11000s to 13000s, the deposition temperature is 500℃ to 600℃, and the thickness of the second polysilicon layer is 300±10nm. The diffusion temperature of the second phosphorus diffusion is 850℃~950℃, the diffusion time is 1000s~1500s, the oxidation temperature is 850℃~950℃, the oxidation time is 500s~700s, and the thickness of the back PSG layer is 50±5nm.

8. The method for preparing a TBC solar cell as described in claim 1, characterized in that, In step S6, the laser power is 40% and the overlap rate is 60%. The third pickling is carried out by a wet acid tank chain machine. The tank temperature of the wet acid tank chain machine is 30℃~50℃, the process time is 40s~60s, and the acid solution used for the third pickling is composed of H2O and HF in a volume ratio of 1~5:

2. The third alkaline wash is carried out using a wet alkaline polishing tank machine. The tank temperature of the wet alkaline polishing tank machine is 50℃~75℃, and the process time is 100s~200s. The alkaline solution used for the third alkaline wash is composed of H2O, NaOH and polishing additives in a volume ratio of 290~310:10~20:2~8, wherein the NaOH concentration is 1%~5%. The fourth pickling is carried out using a wet acid polishing tank machine. The tank temperature of the wet acid polishing tank machine is 30℃~50℃, and the process time is 10s~30s. The acid solution used for the fourth pickling is composed of H2O and HF in a volume ratio of 7~11:

1. The fourth alkaline wash is performed using a wet alkaline polishing tank machine. The tank temperature of the wet alkaline polishing tank machine is 50℃~75℃, and the process time is 200s~400s. The alkaline solution used in the fourth alkaline wash is composed of H2O, NaOH and polishing additives in a volume ratio of 290~310:15~22:2~8, of which the NaOH concentration is 1%~5%.

9. The method for preparing a TBC solar cell as described in claim 1, characterized in that, In step S7, the texturing process uses an alkaline solution for texturing, which is composed of H2O, NaOH, and texturing additives in a volume ratio of 290-310:8-15:1-6, wherein the NaOH concentration is 1%-3%; the temperature of the alkaline solution for texturing is 60-70℃, and the texturing process time is 350s-450s. The fifth pickling process uses an acid solution composed of H2O and HF in a volume ratio of 1 to 5:2, with a process time of 150 to 250 seconds and a solution temperature of 40 to 50 degrees Celsius.

10. The method for preparing a TBC solar cell as described in claim 1, characterized in that, In step S8, the deposition temperature of the alumina layer is 180±20℃, the deposition time is 300±40s, and the thickness of the alumina layer is 5±1nm.

11. The method for preparing a TBC solar cell as described in claim 1, characterized in that, In step S9, the coating process temperature is 500℃, and the process time per nanometer is 5 to 15 seconds. The front passivation film has a 6-layer structure, including silicon nitride a: 8±3nm; silicon nitride b: 14±4nm; silicon nitride c: 20±4nm; silicon oxynitride a: 12±4nm; silicon oxynitride b: 10±3nm; and silicon dioxide: 6±2nm. The back passivation film has a three-layer structure, including silicon nitride d: 20±2nm; silicon nitride e: 20±2nm; silicon nitride f: 50±5nm.

12. A TBC solar cell, characterized in that, It is prepared using the method for preparing TBC solar cells as described in any one of claims 1 to 11.

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