Under-voltage protection circuit, power supply system and under-voltage protection method of switching power supply

Abstract

The present application discloses an undervoltage protection circuit for a switching power supply, a power supply system, and an undervoltage protection method. The undervoltage protection circuit of the switching power supply includes: a current processing module, a comparison module, a timing module, a falling edge acquisition module, and an operation module. The current processing module is configured to obtain the input voltage value of the chip; the comparison module is configured to compare the input voltage value with a reference voltage value and generate a first signal according to the comparison result; the timing module is configured to respond to the first signal, determine whether to perform a timing operation according to the first signal, generate a second signal and send it to the operation module; the falling edge acquisition module is configured to detect the falling edge in the switch-on signal of the switch tube to obtain a falling edge sampling signal; the operation module is configured to perform a logical operation on the second signal and the falling edge sampling signal to generate an undervoltage protection signal. This solution can obtain an accurate undervoltage protection signal, ensure that the system can normally enter the standby mode when jumping from the load state to the no-load state, and avoid the occurrence of error signals.

Description

Technical Field

[0001] The present invention generally relates to the technical field of switching power supplies, and particularly relates to an undervoltage protection circuit, a power supply system and an undervoltage protection method for a switching power supply. Background Art

[0002] With the rapid development of electronic information technology, the flyback switching power supply, as a switching power supply that uses a flyback high-frequency transformer to isolate the input and output circuits, has been increasingly applied in daily devices. In order to ensure that the system will not be damaged when the AC input voltage is lower than the normal voltage, an undervoltage protection scheme needs to be set. The related undervoltage protection scheme samples the input voltage through an auxiliary winding and converts it into a current, then converts the current into a voltage, and compares the voltage with a reference voltage. When the voltage is less than the reference voltage, the timer starts timing and when the timing reaches the detection time, an undervoltage protection signal with a high level is output; when the voltage is not less than the reference voltage, the timer does not work and an undervoltage protection signal with a low level is output. This undervoltage protection signal is used to determine whether the AC input voltage is too low. When the undervoltage protection signal is at a high level, the system is turned off; when the undervoltage protection signal is at a low level, it does not affect the system operation.

[0003] In the above scheme, when the system works under normal AC input voltage and rapidly switches from a stable load state to an idle state, the output feedback signal of the system will quickly become an extremely low value, and then it needs to wait for the circuit loop to be established and return to normal. Among them, the loop response of the circuit requires a certain time, which is the standby time. During the standby time, the switching signal of the switch tube in the circuit remains low. If the standby time exceeds the detection time of the undervoltage protection, since the auxiliary winding cannot sample the input voltage when the switch tube is turned off, the output undervoltage protection signal is at a high level, resulting in a misjudgment operation on the AC input voltage.

[0004] Currently, in the related art, the above situation is avoided by extending the detection time of the undervoltage protection. However, this scheme cannot quickly respond when the system is under a stable load, and once the circuit loop response time becomes longer due to changes in the system peripheral parameters, it will still result in an incorrect judgment signal, causing the system to shut down. Summary of the Invention

[0005] In view of the above defects or deficiencies in the prior art, it is desirable to provide an undervoltage protection circuit, a power supply system and an undervoltage protection method for a switching power supply.

[0006] In a first aspect, the present application provides an undervoltage protection circuit for a switching power supply. The undervoltage protection of the switching power supply includes: a current processing module, a comparison module, a timing module, a falling edge acquisition module and an operation module;

[0007] The input end of the current processing module is connected to the detection pin of the chip, the output end of the current processing module is connected to the first input end of the comparison module, the output end of the comparison module is connected to the input end of the timing module, the output end of the timing module is connected to the first end of the operation module, and the input end of the falling edge acquisition module is connected to the main switch tube of the chip; the output end of the falling edge acquisition module is connected to the second end of the operation module;

[0008] The current processing module is used to obtain the input voltage value of the chip and send it to the comparison module;

[0009] The comparison module is used to compare the input voltage value with a reference voltage value, generate a first signal according to the comparison result and send it to the timing module; the reference voltage value is stored at the second input end of the comparison module;

[0010] The timing module is used to respond to the first signal, judge whether to perform a timing operation according to the first signal, generate a second signal and send it to the operation module;

[0011] The falling edge acquisition module is used to detect the falling edge in the switch-on signal of the main switch tube, obtain a falling edge sampling signal and send it to the operation module;

[0012] The operation module is used to perform a logical operation on the second signal and the falling edge sampling signal to generate an undervoltage protection signal.

[0013] In one embodiment, the operation module includes: a first inverter, a second inverter, a first NAND gate and a second NAND gate; the output end of the falling edge acquisition module is connected to the input end of the first inverter, the output end of the first inverter is connected to the first input end of the first NAND gate, the second input end of the first NAND gate is connected to the output end of the second NAND gate, the output end of the first NAND gate is connected to the first input end of the second NAND gate, the second input end of the second NAND gate is connected to the output end of the timing module, the output end of the second NAND gate is further connected to the input end of the second inverter, and the output end of the second inverter outputs the undervoltage protection signal.

[0014] In one embodiment, the falling edge acquisition module is further used for:

[0015] When it detects that the switch-on signal is at a high level, generate a falling edge sampling signal with a low level; or, when it detects the arrival of the falling edge of the switch-on signal, generate a falling edge sampling signal with a high level.

[0016] In one embodiment, the operation module is further used for:

[0017] When the input voltage value is not less than the reference voltage value, a second signal with a low level is obtained, and when the system exits the standby mode, a falling-edge sampling signal of the low level is obtained; according to the second signal with the low level and the falling-edge sampling signal of the low level, an undervoltage protection signal with the low level is obtained; or,

[0018] When the input voltage value is less than the reference voltage value, a second signal with a high level is obtained, and when the system exits the standby mode, a falling-edge sampling signal of the high level is obtained; according to the second signal with the high level and the falling-edge sampling signal of the high level, an undervoltage protection signal with the high level is obtained.

[0019] In one embodiment, the timing module is further configured to:

[0020] When the first signal is at a high level, generate the second signal with the low level; the first signal is at a high level when the comparison module determines that the input voltage value is not less than the reference voltage value; or,

[0021] When the first signal is at a low level, perform a timing operation and when the time reaches a preset detection time, generate the second signal with the high level; the first signal is at a low level when the comparison module determines that the input voltage value is less than the reference voltage value.

[0022] In one embodiment, the falling-edge acquisition module includes: a first switching transistor, a second switching transistor, a resistor, a capacitor, a Schmitt trigger, and a first NOR gate;

[0023] The drain of the first switching transistor is connected to the power supply terminal of the chip, the source of the first switching transistor is connected to one end of the resistor, the other end of the resistor is respectively connected to the drain of the second switching transistor and the input terminal of the Schmitt trigger, the input terminal of the Schmitt trigger is further connected to one end of the capacitor, the output terminal of the Schmitt trigger is connected to the first input terminal of the first NOR gate, the main switching transistor is respectively connected to the gate of the first switching transistor, the gate of the second switching transistor, and the second input terminal of the first NOR gate, the other end of the capacitor and the source of the second switching transistor are both grounded, and the output terminal of the first NOR gate is connected to the input terminal of the first inverter.

[0024] In one embodiment, the falling-edge acquisition module includes: a current mirror, a third inverter, a first NOR gate, a second NOR gate, a first switching transistor, a second switching transistor, a capacitor, and a Schmitt trigger;

[0025] The main switching transistor is connected to the input terminal of the third inverter. The output terminal of the third inverter is connected to the first input terminal of the first NOR gate. The second input terminal of the first NOR gate is connected to the output terminal of the second NOR gate. The output terminal of the first NOR gate is connected to the first input terminal of the second NOR gate. The second input terminal of the second NOR gate is connected to the output terminal of the Schmitt trigger. The output terminal of the first NOR gate is respectively connected to the gates of the first switching transistor and the second switching transistor. The input terminal of the current mirror is connected to the power supply terminal. The output terminal of the current mirror is connected to the drain of the first switching transistor. The source of the first switching transistor is respectively connected to the drain of the second switching transistor, one end of the capacitor, and the input terminal of the Schmitt trigger. The source of the second switching transistor and the other end of the capacitor are both grounded. The output terminal of the second NOR gate is connected to the input terminal of the first inverter.

[0026] In one embodiment, the current mirror includes: a third switching transistor and a fourth switching transistor. The drain of the third switching transistor is respectively connected to the power supply terminal and the drain of the fourth switching transistor. The gate of the third switching transistor is connected to the gate of the fourth switching transistor. The source of the third switching transistor, the gate of the third switching transistor, and the gate of the fourth switching transistor are respectively connected to the second input terminal of the comparison module. The source of the fourth switching transistor is connected to the drain of the first switching transistor.

[0027] In a second aspect, the present application provides a power supply system, including the undervoltage protection circuit of the switching power supply as described in the first aspect above.

[0028] In a third aspect, the present application provides an undervoltage protection method, which includes:

[0029] The current processing module acquires the input voltage value of the chip and sends it to the comparison module;

[0030] The comparison module compares the input voltage value with the reference voltage value, generates a first signal according to the comparison result and sends it to the timing module;

[0031] The timing module responds to the first signal, determines whether to perform a timing operation according to the first signal, generates a second signal and sends it to the operation module;

[0032] The falling edge acquisition module detects the falling edge in the switching transistor turn-on signal of the main switching transistor in the chip, obtains the corresponding falling edge sampling signal and sends it to the operation module;

[0033] The operation module performs a logical operation on the second signal and the falling edge sampling signal to generate an undervoltage protection signal.

[0034] The undervoltage protection circuit, power supply system and undervoltage protection method of the switching power supply provided by the embodiment of the present application. The undervoltage protection circuit of the switching power supply includes: a current processing module, a comparison module, a timing module, a falling edge acquisition module and an operation module. The input end of the current processing module is connected to the detection pin of the chip, the output end of the current processing module is connected to the first input end of the comparison module, the output end of the comparison module is connected to the input end of the timing module, the output end of the timing module is connected to the first end of the operation module, the input end of the falling edge acquisition module is connected to the main switching tube of the chip, and the output end of the falling edge acquisition module is connected to the second end of the operation module; the current processing module is used to obtain the input voltage value of the chip and send it to the comparison module, the comparison module is used to compare the input voltage value with the reference voltage value, generate a first signal according to the comparison result and send it to the timing module; the timing module is used to respond to the first signal, judge whether to perform a timing operation according to the first signal, generate a second signal and send it to the operation module; the falling edge acquisition module is used to detect the falling edge in the switching tube turn-on signal of the main switching tube, obtain a falling edge sampling signal and send it to the operation module; the operation module is used to perform a logical operation on the second signal and the falling edge sampling signal to generate an undervoltage protection signal. Compared with the prior art, after obtaining the input voltage value of the chip, the undervoltage protection circuit can compare the input voltage value with the reference voltage value, so that the timing module generates a second signal according to the comparison result, providing data guiding information for subsequent judgment of whether undervoltage protection occurs, and detecting the falling edge in the switching tube turn-on signal of the main switching tube through the falling edge acquisition module to obtain a falling edge sampling signal. Therefore, while considering the second signal, the falling edge sampling signal in the switching tube turn-on signal of the main switching tube is also fully considered, generating an undervoltage protection signal more comprehensively, and then accurately determining whether the input voltage value of the chip is in an undervoltage state or a normal state. It can ensure that when the system jumps from the load state to the no-load state, it can normally enter the standby mode without generating an incorrect undervoltage protection signal, resulting in system shutdown. Description of the Drawings

[0035] By reading the detailed description of the non-limiting embodiments with reference to the following drawings, other features, objects and advantages of the present application will become more apparent:

[0036] Figure 1 It is a schematic flowchart of the undervoltage protection method in the related art provided by the embodiment of the present application;

[0037] Figure 2 It is a schematic structural diagram of the undervoltage protection circuit of the switching power supply provided by the embodiment of the present application;

[0038] Figure 3 It is a schematic structural diagram of the overall circuit of the switching power supply provided by the embodiment of the present application;

[0039] Figure 4 Schematic diagram of the undervoltage protection circuit of the switching power supply provided by the embodiment of the present application;

[0040] Figure 5 Schematic diagram of the falling edge acquisition module provided by the embodiment of the present application;

[0041] Figure 6 Schematic diagram of the falling edge acquisition module provided by another embodiment of the present application;

[0042] Figure 7 Schematic diagram of the process of the undervoltage protection method provided by the embodiment of the present application;

[0043] Figure 8 Schematic diagram of the process of the undervoltage protection method provided by another embodiment of the present application;

[0044] Figure 9 Schematic diagram of the corresponding waveform when the load jumps when the input voltage value is in the normal state provided by the embodiment of the present application;

[0045] Figure 10 Schematic diagram of the corresponding waveform when the load jumps when the input voltage value is in the undervoltage state provided by the embodiment of the present application.

[0046] Explanation of reference numerals:

[0047] Current processing module - 10; comparison module - 20; timing module - 30; falling edge acquisition module - 40; operation module - 50; detection pin - 51; primary part - 60; secondary part - 70; auxiliary part - 80. Detailed implementation manners

[0048] The present application will be further described in detail below with reference to the drawings and embodiments. It can be understood that the specific embodiments described herein are only used to explain the related invention, rather than limiting the invention. Additionally, it should be noted that for the convenience of description, only the parts related to the invention are shown in the drawings.

[0049] It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments can be combined with each other. The present application will be described in detail below with reference to the drawings and embodiments.

[0050] It can be understood, please refer to Figure 1As shown in the figure, the undervoltage protection scheme of the related technology is to first obtain the AC voltage, sample the input voltage through the auxiliary winding, convert the input voltage into current, then input the current into the current-to-voltage module inside the system to convert the current into a voltage with a certain ratio, and then input the voltage into the voltage comparator to compare it with the reference voltage to obtain the comparison result. Then, send the comparison result to the timing module. If the comparison result shows that the voltage is less than the reference voltage, the timer starts timing, and when the timing reaches the detection time, an undervoltage protection signal with a high level is output to control the shutdown of the system, that is, the system stops working; if the comparison result shows that the voltage is not less than the reference voltage, an undervoltage protection signal with a low level is output to control the normal operation of the system.

[0051] The defect of the above scheme is that when the system works under normal AC input voltage and quickly switches from a stable load state to an unloaded state, the output feedback signal of the system will quickly become an extremely low value, and then it needs to wait for the circuit loop to be established before returning to normal. Among them, the loop response of the circuit requires a certain amount of time, which is the standby time. During the standby time, the switching signal of the switching transistor in the circuit remains low. If the standby time exceeds the detection time of undervoltage protection, since the auxiliary winding cannot sample the input voltage when the switching transistor is turned off, the output undervoltage protection signal is at a high level, resulting in misjudgment of the AC input voltage.

[0052] Currently, in the related technology, the above situation is avoided by extending the detection time of undervoltage protection. However, this scheme cannot quickly respond when the system is under a stable load, and once the circuit loop response time becomes longer due to changes in the system peripheral parameters, it will still result in an incorrect judgment signal, causing the system to shut down.

[0053] Based on the above defects, the present application provides an undervoltage protection circuit for a switching power supply. Compared with the prior art, after obtaining the input voltage value of the chip, the undervoltage protection circuit can compare the input voltage value with the reference voltage value, so that the timing module generates a second signal according to the comparison result to provide data guidance information for subsequent judgment of whether undervoltage protection occurs, and detects the falling edge in the switching transistor turn-on signal of the main switching transistor through the falling edge acquisition module to obtain the falling edge sampling signal. Therefore, while considering the second signal, the falling edge sampling signal in the switching transistor turn-on signal of the main switching transistor is also fully considered to generate the undervoltage protection signal more comprehensively, and then accurately determine whether the input voltage value of the chip is in an undervoltage state or a normal state, which can ensure that when the system jumps from the load state to the unloaded state, it can normally enter the standby mode without generating an incorrect undervoltage protection signal that causes the system to shut down.

[0054] Please refer to Figure 2 as shown in the figure Figure 2Schematic diagram of the undervoltage protection circuit of the switching power supply provided by the embodiment of the present application. The undervoltage protection circuit of the switching power supply includes: a current processing module 10, a comparison module 20, a timing module 30, a falling-edge acquisition module 40, and an operation module 50. The input end of the current processing module 10 is connected to the detection pin 51 of the chip, the output end of the current processing module 10 is connected to the first input end of the comparison module 20, the output end of the comparison module 20 is connected to the input end of the timing module 30, the output end of the timing module 30 is connected to the first end of the operation module 50, and the input end of the falling-edge acquisition module 40 is connected to the main switching tube of the chip; the output end of the falling-edge acquisition module 40 is connected to the second end of the operation module 50. Among them, the main switching tube of the above chip is in Figure 2 not shown.

[0055] The current processing module 10 is used to obtain the input voltage value of the chip and send it to the comparison module 20; the comparison module 20 is used to compare the input voltage value with the reference voltage value, generate a first signal according to the comparison result and send it to the timing module 30; the reference voltage value is stored at the second input end of the comparison module; the timing module 30 is used to respond to the first signal, judge whether to perform a timing operation according to the first signal, generate a second signal and send it to the operation module 50; the falling-edge acquisition module 40 is used to detect the falling edge in the switching tube on signal of the main switching tube, obtain a falling-edge sampling signal and send it to the operation module 50; the operation module 50 is used to perform a logical operation on the second signal and the falling-edge sampling signal to generate an undervoltage protection signal.

[0056] It should be noted that the undervoltage protection circuit provided by the embodiment of the present application can be applied to a switching power supply system. For example, it can be applied to a flyback converter, or can also be applied to a forward converter. The flyback converter is widely used in AC / DC and DC / DC conversions and provides isolation between the input stage and the output stage. Among them, the above chip can be a processor chip, a sensor chip, a storage chip, a communication chip, or a control chip.

[0057] Please refer to Figure 3 as shown Figure 3 Schematic diagram of the overall circuit of the switching power supply provided by the embodiment of the present application. The overall circuit includes a primary part 60, a secondary part 70, and an auxiliary part 80. The primary part 60 includes a primary winding Np, a primary switching tube Q1, and a primary control circuit. The primary control circuit includes a chip, a photo-sensitive triode I1B, a capacitor C5, and a sampling resistor R CS, sampling resistor R5 and capacitor C6. The non - corresponding end of the primary winding Np is connected to the input voltage terminal, the corresponding end of the primary winding Np is connected to the drain of the main switch Q1, and both ends of the primary winding Np are connected to the RCD spike absorption circuit. This RCD spike absorption circuit includes R1, C1 and D1. The source of the main switch Q1 is grounded through the primary sampling resistor R CS and then grounded. The gate of the main switch Q1 is connected to the DRV pin of the chip in the primary control circuit. The input voltage terminal Vbulk is connected to the VDD pin of the chip through the current - limiting resistor R0. This input voltage terminal Vbulk is used to provide a startup voltage for the chip.

[0058] The secondary part 70 includes a secondary winding Ns, an output rectifier diode D2, a sampling resistor R2 and a light - emitting diode I1A. The non - corresponding end of the secondary winding Ns is grounded, the corresponding end of the secondary winding Ns is connected to the anode of the output rectifier diode D2. The cathode of the output rectifier diode D2 is respectively connected to the sampling resistor R2, the output capacitor C2, the sampling resistor R3 and the output voltage terminal Vout. The output capacitor C2 is used to stabilize the voltage of the output voltage terminal Vout. The output voltage terminal Vout is connected to the input terminal of TL431 through the sampling resistor R3 and the sampling resistor R4, and the output terminal of TL431 is connected to the light - emitting diode I1A. The output current of TL431 is feedback to the FB pin of the primary chip through the optocoupler composed of the light - emitting diode I1A and the primary photosensitive triode I1B.

[0059] The auxiliary part 80 includes an auxiliary winding Na, a diode D3, a capacitor C4, a sampling resistor R H and a sampling resistor R L , the non - corresponding end of the auxiliary winding Na is grounded, the corresponding end of the auxiliary winding Na is connected to one end of the sampling resistor R H . The other end of the sampling resistor R H is respectively connected to one end of the sampling resistor R L and the ZCD pin of the primary chip. The other end of the sampling resistor R L is grounded and connected to one end of the capacitor C4. The corresponding end of the auxiliary winding Na is also connected to the anode of the diode D3, and the cathode of the diode D3 is connected to the VDD pin of the chip.

[0060] It is understandable that the above chip is a primary-side chip. The ZCD pin of the primary-side chip is a detection pin used to detect the input voltage value. The VDD pin of the primary-side chip is the input pin of the power supply, and the FB pin is the feedback pin used to adjust the stability of the output voltage. By controlling the FB pin, the adjustment and stabilization of the output voltage can be achieved, ensuring the normal operation of the system. The CS pin is used to connect the chip to an external circuit or component to transmit signals and power to complete the functions of the chip. The GND pin is the grounding pin of the chip, used to connect to the ground wire of the device, connecting the circuit of the chip to the ground wire of the device to ensure the stability and safety of the circuit. For example, when the CS pin is at a high level, the chip is in an idle state and does not communicate with external devices. When the CS pin is at a low level, the chip establishes a connection with an external device and conducts data transmission.

[0061] Specifically, when the main switch Q1 in the circuit is turned on, the Vbulk terminal is used to provide a startup voltage for the chip. The voltage value corresponding to the same-name terminal of the auxiliary winding Na can be determined based on the provided startup voltage value and can be expressed by the following formula. Among them, the same-name terminal of the auxiliary winding Na can be referred to as Figure 3 point A shown on

[0062] V A =-Vbulk*Na / Np;

[0063] where Vbulk is the startup voltage value, Na is the number of turns of the auxiliary winding, and Np is the number of turns of the primary winding.

[0064] Taking the detection pin ZCD pin of the chip as an example, after obtaining the voltage value corresponding to the same-name terminal of the auxiliary winding Na, the current value input to the detection pin ZCD is obtained based on the voltage value corresponding to the same-name terminal of the auxiliary winding Na and the sampling resistance value, and it is expressed by the following formula:

[0065]

[0066] where Vbulk is the startup voltage value, Na is the number of turns of the auxiliary winding, Np is the number of turns of the primary winding, R H is the sampling resistance value, and I ZCD is the current value input to the detection pin ZCD.

[0067] The above current processing module can internally include a resistance value R ZCD , after obtaining the current value input to the detection pin ZCD, the current value input to the detection pin ZCD is reduced by a ratio K through the current processing module to obtain a reduced current value, and based on the reduced current value and the resistance value R ZCD calculation, the input voltage value Vsense of the chip is obtained, and it can be expressed by the following formula:

[0068]

[0069] Among them, R ZCD is the resistance value inside the current processing module, K is the proportionality coefficient, 0 < k < 1, R H is the sampling resistance value, and Vbulk is the startup voltage value.

[0070] It should be noted that by reducing the current value input to the detection pin ZCD according to the ratio K, the reduced current value can be obtained, which can reduce the power consumption of the internal circuit. In the above formula of the input voltage value Vsense, k, R ZCD , Na, and Np are all fixed values, and the startup voltage value Vbulk is a variable value. Therefore, there is a linear relationship between the input voltage value Vsense and the startup voltage value Vbulk, so that the current processing module can obtain the input voltage value of the chip and send it to the comparison module 20.

[0071] Optionally, please refer to Figure 4 , the first input terminal of the above comparison module 20 can be the positive terminal, and the second input terminal can be the negative terminal. The positive terminal of the comparison module 20 is used to receive the input voltage value Vsense sent by the current processing module 10. After obtaining the input voltage value Vsense of the chip, the input voltage value Vsense can be compared with the reference voltage value Vref stored at the negative terminal to obtain a comparison result, which is used to represent whether the input voltage value Vsense is less than the reference voltage value Vref. Among them, the magnitude of the above reference voltage value Vref can be custom-set according to actual requirements.

[0072] When the comparison result represents that the input voltage value Vsense is less than the reference voltage value Vref, a first signal Vcomp with a low level is generated, indicating that the input voltage value Vsense is too low; when the comparison result represents that the input voltage value Vsense is not less than the reference voltage value Vref, a first signal Vcomp with a high level is generated, indicating that the input voltage value Vsense is normal. Among them, the low level and high level of the first signal Vcomp represent the working state of the first signal Vcomp. When the first signal Vcomp is at a low level, it represents that the working state of the first signal Vcomp is "0", and at this time it is in an invalid state; when the first signal Vcomp is at a high level, it represents that the working state of the first signal Vcomp is "1", and at this time it is in an effective state.

[0073] It should be noted that since there are fluctuations in the power grid during operation, the power supply system may be unstable during operation. If the first signal Vcomp output by the comparison module is used as the final undervoltage protection signal, the system will shut down directly due to an accidental fluctuation in the power grid. Therefore, it is necessary to set up a timing module 30 to further determine whether the input voltage value Vsense is in the undervoltage state, and the first signal Vcomp needs to be sent to the timing module 30.

[0074] In this embodiment, the input voltage value is compared with the reference voltage value by the comparison module, and the first signal can be generated coarsely, providing good data guiding information for subsequent determination of whether the input voltage value is in the undervoltage state.

[0075] Optionally, the timing module 30 may include a timer. The timing module 30 is configured to: receive and respond to the first signal, determine whether to perform a timing operation according to the first signal, and generate a second signal. The second signal may include two working states: high level and low level, with high level being "1" and low level being "0". When the first signal Vcomp is at a high level, the timer is turned off, generating a second signal Timeout at a low level; when the first signal Vcomp is at a low level, the timer is started and begins to count. When the time reaches the preset detection time, a second signal Timeout at a high level is generated. Among them, the detection time can be custom-set according to actual needs, for example, it can be 40ms - 80ms.

[0076] It can be understood that when the system jumps from a stable load state to an idle state, the system will enter the standby mode. After entering the standby mode, the main switch Q1 has no switching action, and its switch drive terminal does not output a waveform. When the main switch Q1 is not conducting, the input voltage value cannot be sampled, that is, the input voltage value Vsense is constantly zero, and the corresponding first signal Vcomp is at a low level. If the second signal Timeout is used as the judgment criterion for whether the input voltage value is too low, when the timing is started and the time reaches the preset detection time, the corresponding second signal Timeout is output at a high level, and the system will shut down directly. Thus, when the system jumps from a stable load state to an idle state, the system misjudges the input voltage value, generating an incorrect judgment signal and causing the system to shut down.

[0077] In this embodiment, to avoid the above situation, a falling-edge acquisition module is provided to detect the falling edge in the switch-on signal of the main switch tube, so as to obtain a falling-edge sampling signal delay and send it to the operation module, enabling the operation module to perform a logical operation based on the second signal Timeout and the falling-edge sampling signal delay to obtain the final undervoltage protection signal Vbrown. This final undervoltage protection signal Vbrown is used to determine whether the input voltage value Vsense is in an undervoltage state. When the undervoltage protection signal Vbrown is at a high level, indicating that the input voltage value Vsense is in an undervoltage state, in order to prevent the system from being damaged, it is necessary to control the system to shut down; when the undervoltage protection signal Vbrown is at a low level, indicating that it is determined that the input voltage value Vsense is in a normal state, the control system operates normally.

[0078] Among them, the above-mentioned falling-edge acquisition module is further used for: when detecting that the switch-on signal of the switch tube is at a high level, generating a falling-edge sampling signal with a low level; when detecting the arrival of the falling edge of the switch-on signal of the switch tube, generating a falling-edge sampling signal with a high level.

[0079] It should be noted that the above-mentioned falling-edge sampling signal delay is a delay signal of the falling edge of the switch-on signal (Gate_on) of the main switch tube. When the main switch tube Q1 in the above circuit conducts, the corresponding switch-on signal Gate_on is at a high level, and the corresponding falling-edge sampling signal delay is at a low level; when the falling edge of the main switch tube Q1 arrives, indicating that the main switch tube Q1 will turn off, the corresponding falling-edge sampling signal delay is at a high level. When the system is in a stable load state, the main switch tube Q1 conducts, the corresponding switch-on signal Gate_on is at a high level, and the corresponding falling-edge sampling signal delay is at a low level; when the system is in an idle state, the system will enter the standby mode. After entering the standby mode, the main switch tube Q1 has no switching action and is not conducting, and the input voltage value cannot be sampled, that is, the input voltage value Vsense is constantly zero. When the system exits the standby mode, the system will detect and provide a switching signal for the main switch tube, and the input voltage value Vsense is sampled when the main switch tube is turned on. Therefore, the switch-on signal Gate_on can be waited for once again in the standby mode, and the system can normally determine whether Vsense is in an undervoltage state. In this embodiment, due to the introduction of the falling-edge sampling signal delay signal, the falling edge in the switch-on signal of the main switch tube can be accurately detected, and the problem of misjudging whether Vsense is in an undervoltage state in the standby mode of the system can be solved.

[0080] In this embodiment, the operation module may be provided with at least one logic operation unit. After obtaining the second signal Timeout and the falling-edge sampling signal delay, the logic operation unit in the operation module can perform a logic operation on the second signal Timeout and the falling-edge sampling signal delay to obtain an undervoltage protection signal Vbrown. Since the undervoltage protection signal Vbrown incorporates the second signal Timeout and the falling-edge sampling signal delay in the switching tube turn-on signal of the main switching tube, it can solve the problem of the system misjudging and shutting down when the system jumps from a stable load to no load and the loop response time is long.

[0081] The undervoltage protection circuit of the switching power supply provided by the embodiment of the present application includes: a current processing module, a comparison module, a timing module, a falling-edge acquisition module, and an operation module. The input end of the current processing module is connected to the detection pin of the chip, the output end of the current processing module is connected to the first input end of the comparison module, the output end of the comparison module is connected to the input end of the timing module, the output end of the timing module is connected to the first end of the operation module, the input end of the falling-edge acquisition module is connected to the main switching tube of the chip, and the output end of the falling-edge acquisition module is connected to the second end of the operation module; the current processing module is configured to obtain the input voltage value of the chip and send it to the comparison module, the comparison module is configured to compare the input voltage value with a reference voltage value, generate a first signal according to the comparison result and send it to the timing module; the timing module is configured to respond to the first signal, determine whether to perform a timing operation according to the first signal, generate a second signal and send it to the operation module; the falling-edge acquisition module is configured to detect the falling edge in the switching tube turn-on signal of the main switching tube, obtain a falling-edge sampling signal and send it to the operation module; the operation module is configured to perform a logic operation on the second signal and the falling-edge sampling signal to generate an undervoltage protection signal. Compared with the prior art, after obtaining the input voltage value of the chip, the undervoltage protection circuit can compare the input voltage value with the reference voltage value, so that the timing module generates a second signal according to the comparison result, providing data guiding information for subsequent determination of whether undervoltage protection occurs, and detecting the falling edge in the switching tube turn-on signal of the main switching tube through the falling-edge acquisition module to obtain a falling-edge sampling signal, so that while considering the second signal, it also fully considers the falling-edge sampling signal in the switching tube turn-on signal of the main switching tube, generating an undervoltage protection signal more comprehensively, and then accurately determining whether the input voltage value of the chip is in an undervoltage state or a normal state, which can ensure that when the system jumps from a load state to a no-load state, it can normally enter the standby mode without generating an incorrect undervoltage protection signal, resulting in system shutdown.

[0082] In one embodiment, please continue to refer to Figure 4As shown in the figure, the above-mentioned operation module includes: a first inverter INV1, a second inverter INV2, a first NAND gate NAD1, and a second NAND gate NAD2; the output end of the falling-edge acquisition module is connected to the input end of the first inverter INV1, the output end of the first inverter INV1 is connected to the first input end of the first NAND gate NAD1, the second input end of the first NAND gate NAD1 is connected to the output end of the second NAND gate NAD2, the output end of the first NAND gate NAD1 is connected to the first input end of the second NAND gate NAD2, the second input end of the second NAND gate NAD2 is connected to the output end of the timing module, the output end of the second NAND gate NAD2 is further connected to the input end of the second inverter INV2, and the output end of the second inverter INV2 outputs an undervoltage protection signal.

[0083] It should be noted that the above-mentioned operation module can be an inverting latch structure composed of two NAND gates and two inverters, also known as an RS latch structure. The RS latch structure is composed of two cross-connected gate circuits, where the output of each gate circuit is connected to the input of the other gate circuit. The two inverters are the first inverter INV1 and the second inverter INV2 respectively, and the two NAND gates are the first NAND gate NAD1 and the second NAND gate NAD2 respectively. The inverter is used to invert the input signal so that the output signal has a phase opposite to that of the input signal. The NAND gate is used for the combination of an AND gate and a NOT gate. First, an AND operation is performed, and then a NOT operation is performed. The NAND gate outputs a high level when one or more of the input terminals are at a low level; only when all inputs are at a high level, the output is at a low level.

[0084] The above-mentioned RS latch structure includes two input terminals (S and R), an output terminal (Q), and a complementary output terminal (Q’). Its core principle is to lock the output terminal into two states by controlling the input terminals. One state is "0", and the other state is "1". When the R (reset) input is 1, Q (output) is 0, and Q’ (complementary output) is 1; when the S (set) input is 1, Q is 1, and Q’ (complementary output) is 0. When both the inputs R and S are 0, the inverting latch will retain the previous output state, that is, the outputs Q and Q’ remain unchanged as the previous output states respectively. When both the inputs R and S are 1, the latch will be in an unstable state, and its output state will be uncertain.

[0085] In this embodiment, by performing a logical operation on the second signal Timeout and the falling-edge sampling signal delay through the operation module, the undervoltage protection signal Vbrown can be accurately obtained, solving the problem that the system misjudges and shuts down when the system jumps from a stable load to no load and the loop response time is long.

[0086] In one of the embodiments, please refer to Figure 5As shown in the figure, the above-mentioned falling-edge acquisition module includes: a first switching transistor PM1, a second switching transistor NM1, a resistor R0, a capacitor C0, a Schmitt trigger schmitt, and a first NOR gate NOR1.

[0087] The drain of the first switching transistor PM1 is connected to the power supply terminal VCC of the chip. The source of the first switching transistor PM1 is connected to one end of the resistor R0. The other end of the resistor R0 is respectively connected to the drain of the second switching transistor NM1 and the input terminal of the Schmitt trigger schmitt. The input terminal of the Schmitt trigger schmitt is also connected to one end of the capacitor C0. The output terminal of the Schmitt trigger schmitt is connected to the first input terminal of the first NOR gate NOR1. The main switching transistor is respectively connected to the gate of the first switching transistor PM1, the gate of the second switching transistor NM1, and the second input terminal of the first NOR gate NOR1. The other end of the capacitor C0 and the source of the second switching transistor NM1 are both grounded. The output terminal of the first NOR gate NOR1 is connected to the input terminal of the first inverter.

[0088] It should be noted that the above-mentioned Schmitt trigger generally has two stable states. However, different from the general trigger, the Schmitt trigger adopts a potential triggering method, and its state is maintained by the input signal potential. For input signals with two different change directions of negative decreasing and positive increasing, the Schmitt trigger has different threshold voltages. When the input voltage is higher than the positive threshold voltage, the output is high level; when the input voltage is lower than the negative threshold voltage, the output is low level; when the input is between the positive and negative threshold voltages, the output does not change. That is to say, the threshold voltages corresponding to the output flipping from high level to low level or from low level to high level are different. The NOR gate is a logic operation gate. When all inputs are 0, the output is 1; when any one input is 1, the output is 0. The above-mentioned capacitor C0 is an energy storage element used to store charge and has an impedance effect on alternating current. The resistor R0 is used for current limiting.

[0089] Specifically, when the switching transistor turn-on signal Gate_on of the main switching transistor is at high level, the output falling-edge sampling signal delay is at low level. When the falling edge of the switching transistor turn-on signal Gate_on of the main switching transistor arrives, the output falling-edge sampling signal delay is at high level.

[0090] When the above-mentioned first switching transistor PM1 is turned on, the voltage VCC charges the capacitor C0 after passing through the current-limiting resistor R0 to achieve the purpose of voltage stabilization. After a period of time, when the voltage on the capacitor C0 is greater than the upper threshold voltage of the Schmitt trigger schmitt, it flips to a high level, that is, the output is a high level. Then, it and the high-level switching transistor enable signal Gate_on jointly pass through the first NOR gate NOR1 for logical operation to obtain a low-level falling-edge sampling signal delay. Therefore, when the switching transistor enable signal Gate_on is at a high level, the corresponding output falling-edge sampling signal delay is at a low level. Similarly, when the falling edge of the switching transistor enable signal Gate_on arrives, the corresponding output falling-edge sampling signal delay is at a high level. Among them, the high-level pulse time of the falling-edge sampling signal delay can be determined by the capacitance value of the jump capacitor C0 or the resistance value of the current-limiting resistor R0.

[0091] In one of the embodiments, please refer to Figure 6 As shown, the above-mentioned falling-edge acquisition module includes: a current mirror, a third inverter INV3, a first NOR gate NOR1, a second NOR gate NOR2, a first switching transistor PM1, a second switching transistor NM1, a capacitor C0, and a Schmitt trigger schmitt;

[0092] The main switching transistor is connected to the input end of the third inverter INV3. The output end of the third inverter INV3 is connected to the first input end of the first NOR gate NOR1. The second input end of the first NOR gate NOR1 is connected to the output end of the second NOR gate NOR2. The output end of the first NOR gate NOR1 is connected to the first input end of the second NOR gate NOR2. The second input end of the second NOR gate NOR2 is connected to the output end of the Schmitt trigger schmitt. The output end of the first NOR gate NOR1 is respectively connected to the gates of the first switching transistor PM1 and the second switching transistor NM1. The input end of the current mirror is connected to the power supply terminal VCC, and the output end of the current mirror is connected to the drain of the first switching transistor PM1. The source of the first switching transistor PM1 is respectively connected to the drain of the second switching transistor NM1, one end of the capacitor C0, and the input end of the Schmitt trigger schmitt. The source of the second switching transistor schmittNM1 and the other end of the capacitor C0 are both grounded. The output end of the second NOR gate NOR2 is connected to the input end of the first inverter.

[0093] It should be noted that the above-mentioned current mirror can be composed of an NPN transistor and a PNP transistor. The emitter of the NPN transistor is connected to the base of the PNP transistor. In this way, the base currents of the two transistors can be equal, thereby realizing current ratio amplification.

[0094] Among them, the above current mirror includes: a third switching transistor PM3 and a fourth switching transistor PM4. The drain of the third switching transistor PM3 is respectively connected to the power supply terminal VCC and the drain of the fourth switching transistor PM4. The gate of the third switching transistor PM3 is connected to the gate of the fourth switching transistor PM4. The source of the third switching transistor PM3, the gate of the third switching transistor PM3, and the gate of the fourth switching transistor PM4 are respectively connected to the second input terminal of the comparison module. The source of the fourth switching transistor PM4 is connected to the drain of the first switching transistor PM1.

[0095] Specifically, a reference voltage is stored in the second input terminal of the comparison module, and a reference current IREF can be obtained according to the reference voltage VREF. When the system changes from a stable load state to an unloaded state, the switching transistor turn-on signal Gate_on changes from a high level to a low level. The output of the third inverter INV3 is at a high level, and the output of the first NOR gate NOR1 is at a low level. At this time, the falling-edge sampling signal delay output is at a high level. The reference current IREF passes through the current mirror composed of the third switching transistor PM3 and the fourth switching transistor PM4. The third switching transistor PM3 copies the reference current to the fourth switching transistor PM4 according to a certain ratio. When the first switching transistor PM1 is turned on, the current copied to the fourth switching transistor PM4 charges the capacitor C0. After a period of time, when the voltage on the capacitor C0 is greater than the upper threshold voltage of the Schmitt trigger schmitt, it flips to a high level, that is, the output is at a high level. Then, it and the output result of the first NOR gate NOR1 are jointly subjected to a logical operation through the second NOR gate NOR2, and the falling-edge sampling signal delay output is at a low level. Therefore, when the switching transistor turn-on signal Gate_on is at a high level, the corresponding falling-edge sampling signal delay output is at a low level. Similarly, when the falling edge of the switching transistor turn-on signal Gate_on arrives, the corresponding falling-edge sampling signal delay output is at a high level. Among them, the high-level pulse time of the falling-edge sampling signal delay can be determined by adjusting the capacitance value of the capacitor C0, the reference current value IREF, or the proportionality coefficient of the current mirror.

[0096] In this embodiment, by setting the falling-edge acquisition module, the falling edge in the switching transistor turn-on signal of the main switching transistor can be accurately detected, so as to determine the pulse state of the falling-edge sampling signal, so as to generate a corresponding undervoltage protection signal based on the falling-edge sampling signal and the second signal, solving the problem that the system misjudges and shuts down when the system jumps from a stable load to an unloaded state and the loop response time is long.

[0097] In one of the embodiments, the above operation module is further configured to:

[0098] When the input voltage value is not less than the reference voltage value, a second signal with a low level is obtained, and when the system exits the standby mode, a falling-edge sampling signal with a low level is obtained; according to the second signal with a low level and the falling-edge sampling signal with a low level, an undervoltage protection signal with a low level is obtained; or,

[0099] When the input voltage value is less than the reference voltage value, a second signal with a high level is obtained, and when the system exits the standby mode, a falling-edge sampling signal with a high level is obtained; according to the second signal with a high level and the falling-edge sampling signal with a high level, an undervoltage protection signal with a high level is obtained.

[0100] As an implementable manner, when the input voltage value is not less than the reference voltage value, it indicates that the input voltage value is in a normal state. When the system exits the standby mode, the switch tube turn-on signal Gate_on is at a high level, and the corresponding falling-edge sampling signal delay is at a low level. The auxiliary winding can perform normal sampling. At this time, the input voltage value Vsense is normal, the first signal Vcomp output by the comparison module is at a high level, and the timer in the timing module stops working, so the corresponding output second signal Timeout becomes at a low level. The falling-edge signal delay with a low level and the second signal Timeout with a low level are logically operated through the operation module to obtain the undervoltage protection signal Vbrown at a low level. Among them, the finally output undervoltage protection signal Vbrown is obtained by logically combining the output signal Timeout of the timing module and the falling-edge sampling signal delay of the switch tube conduction signal. Two signals need to be at a high level simultaneously for the Vbrown signal to be at a high level. In this working state, the Vbrown signal is always at a low level, and the judgment that the input voltage value is in a normal state is correct.

[0101] As another implementable manner, when the input voltage value is less than the reference voltage value, it indicates that the input voltage value is in an undervoltage state. When the system exits the standby mode, since the input voltage value is less than the reference voltage value, the input voltage value Vsense is too low. At this time, the first signal Vcomp output by the comparison module is at a low level. When the timer starts timing and reaches the preset detection time, the corresponding output second signal Timeout becomes at a high level. When the falling edge of the switch tube turn-on signal Gate_on arrives, the corresponding falling-edge sampling signal delay is at a high level. The falling-edge signal delay with a high level and the second signal Timeout with a high level are logically operated through the operation module to obtain the undervoltage protection signal Vbrown at a high level. In this working state, the Vbrown signal is at a high level, and the judgment that the input voltage value is in an undervoltage state is correct.

[0102] In this embodiment, by obtaining the falling-edge sampling signal in the switch-on signal of the main switch tube and combining it with the second signal, an undervoltage protection signal can be generated more comprehensively, and then the input voltage value of the chip can be accurately determined to be in an undervoltage state or a normal state. It can ensure that when the system jumps from the load state to the no-load state, it can enter the standby mode normally without generating an incorrect undervoltage protection signal that causes the system to shut down.

[0103] On the other hand, the embodiment of the present application provides a power supply system, which includes the undervoltage protection circuit of the switching power supply provided in the above embodiment.

[0104] Specifically, other chips may also be included in the above power supply system. The other chips may be processor chips, sensor chips, storage chips, communication chips or control chips, which are used to implement functions such as calculation, storage, communication, sensing and control.

[0105] Exemplarily, when the chip is a central processing unit chip, the logical operation can perform arithmetic and control tasks. When the chip is a graphics processing unit chip, the logical operation can process graphic data. It may also include a storage circuit for storing data required for computer operation. For example, when the chip is a random access memory chip, the storage circuit is used to temporarily store data required for computer operation. When the chip is a read-only memory chip, the storage circuit is used to store fixed programs and data. It may also include an analog conversion circuit for converting physical quantities into electrical signals or digital signals. For example, when the chip is a sound sensor chip, the analog conversion circuit is used to convert sound signals into electrical signals. When the chip is a photoelectric sensor chip, the analog conversion circuit is used to convert optical signals into electrical signals. It may also include a communication circuit for realizing communication and connection between devices. For example, when the chip is a wireless communication chip, the communication circuit is used to realize wireless network connection.

[0106] The power supply system provided in this embodiment includes the undervoltage protection circuit of the switching power supply. After obtaining the input voltage value of the chip, the undervoltage protection circuit of the switching power supply can compare the input voltage value with a reference voltage value, so that the timing module generates a second signal according to the comparison result to provide data guiding information for subsequent judgment of whether undervoltage protection occurs. The falling-edge acquisition module detects the falling edge in the switch-on signal of the main switch tube to obtain a falling-edge sampling signal. Thus, while considering the second signal, the falling-edge sampling signal in the switch-on signal of the main switch tube is also fully considered, and an undervoltage protection signal is generated more comprehensively. Then, the input voltage value of the chip can be accurately determined to be in an undervoltage state or a normal state. It can ensure that when the system jumps from the load state to the no-load state, it can enter the standby mode normally without generating an incorrect undervoltage protection signal that causes the system to shut down.

[0107] On the other hand, an embodiment of the present application also provides an undervoltage protection method, which is applied to the undervoltage protection circuit of the switching power supply provided in the above embodiment. Figure 7 The following is a schematic flowchart of the undervoltage protection method according to an embodiment of the present application. As Figure 7 shown, the method includes:

[0108] S101. The current processing module obtains the input voltage value of the chip and sends it to the comparison module.

[0109] S102. The comparison module compares the input voltage value with the reference voltage value, generates a first signal according to the comparison result, and sends it to the timing module.

[0110] S103. In response to the first signal, the timing module determines whether to perform a timing operation according to the first signal, generates a second signal, and sends it to the operation module.

[0111] S104. The falling edge acquisition module detects the falling edge in the switch-on signal of the main switch transistor in the chip, obtains the corresponding falling edge sampling signal, and sends it to the operation module.

[0112] S105. The operation module performs a logical operation on the second signal and the falling edge sampling signal to generate an undervoltage protection signal.

[0113] Specifically, the undervoltage protection circuit of the above switching power supply includes a current processing module, a comparison module, a timing module, a falling edge acquisition module, and an operation module. Different modules perform different functions.

[0114] Please refer to Figure 8 As shown, when the main switch transistor Q1 is turned on, the Vbulk terminal of the circuit provides a startup voltage to the chip. Based on the number of turns of the auxiliary winding and the number of turns of the primary winding, the voltage value corresponding to the same-name terminal of the auxiliary winding is obtained. This voltage value is optimized and converted by the current processing module to obtain the corresponding input voltage value Vsense, which is sent to the comparison module. The comparison module compares the input voltage value Vsense with the reference voltage value Vref, obtains the first signal Vcomp according to the comparison result, and then sends the first signal Vcomp to the timing module. The timing module receives and responds to the first signal Vcomp, determines whether to perform a timing operation according to the high and low level states of the first signal, and generates a second signal Timeout.

[0115] When the first signal Vcomp is at a low level, the timer starts timing. When the time reaches the detection time, the generated second signal Timeout is at a high level. When the first signal Vcomp is at a high level, the timer stops timing, and the generated second signal Timeout is at a low level.

[0116] The falling-edge acquisition module can detect the falling edge of the switch tube turn-on signal Gate_on. When the switch tube turn-on signal Gate_on is at a high level, the generated falling-edge sampling signal delay is at a low level and is sent to the operation module; when the falling edge of the switch tube turn-on signal Gate_on arrives, the generated falling-edge sampling signal delay is at a high level and is sent to the operation module. The operation module determines the corresponding undervoltage protection signal Vbrown according to the high and low level states of the second signal Vcomp and the high and low level states of the falling-edge sampling signal delay.

[0117] As an implementable manner, please refer to Figure 9 as shown in Figure 9 This is a waveform schematic diagram corresponding to the load jump when the input voltage value is in a normal state provided by the embodiment of the present application. When the input voltage value is not less than the reference voltage value, it indicates that the input voltage value is in a normal state. When the system jumps from a stable load state to an idle state, that is, when the system is in the standby mode, the main switch tube is in the off state, and the corresponding switch tube turn-on signal Gate_on is at a low level. The first signal Vcomp output by the comparison module remains at a low level, and the timer in the timing module starts timing. When the preset detection time is reached, the corresponding output second signal Timeout becomes high level. When the system exits the standby mode, the switch tube turn-on signal Gate_on is at a high level, the corresponding falling-edge sampling signal delay is at a low level, and the auxiliary winding can perform normal sampling. At this time, the input voltage value Vsense is normal, the first signal Vcomp output by the comparison module is at a high level, and the timer in the timing module stops working, and the corresponding output second signal Timeout becomes low level. The low-level falling-edge signal delay and the low-level second signal Timeout are logically operated by the operation module to obtain the undervoltage protection signal Vbrown at a low level. Among them, the final output signal Vbrown signal is obtained by logically combining the output signal Timeout of the timing module and the falling-edge sampling signal delay of the switch tube conduction signal. The two signals need to be at a high level at the same time for the Vbrown signal to be at a high level. In this working state, the Vbrown signal is always at a low level, and it is correct to judge that the input voltage value is in a normal state.

[0118] As another implementable manner, please refer to Figure 10 as shown in Figure 10This is a waveform schematic diagram corresponding to the load jump when the input voltage value in the embodiment of the present application is in the undervoltage state. When the input voltage value is less than the reference voltage value, it indicates that the input voltage value is in the undervoltage state. When the system jumps from the stable load state to the no-load state, that is, when the system is in the standby mode, the main switch tube is in the off state, and the corresponding switch tube turn-on signal Gate_on is at a low level. The first signal Vcomp output by the comparison module remains at a low level, and the timer in the timing module starts timing. When the preset detection time is reached, the corresponding second signal Timeout becomes high level. When the system exits the standby mode, since the input voltage value is less than the reference voltage value and the input voltage value Vsense is too low, at this time, the first signal Vcomp output by the comparison module is at a low level, the timer starts timing, and when the preset detection time is reached, the corresponding second signal Timeout output becomes high level. When the falling edge of the switch tube turn-on signal Gate_on arrives, the corresponding falling edge sampling signal delay is at a high level. The high-level falling edge signal delay and the high-level second signal Timeout are logically operated through the operation module to obtain the undervoltage protection signal Vbrown at a high level. Among them, the final output signal Vbrown signal is obtained by logically combining the output signal Timeout of the timing module and the falling edge sampling signal of the switch tube conduction signal. The two signals need to be at a high level simultaneously for the Vbrown signal to be at a high level. In this working state, the Vbrown signal is at a high level, and it is correct to judge that the input voltage value is in the undervoltage state.

[0119] The undervoltage protection method provided by the embodiment of the present application can compare the input voltage value with the reference voltage value after obtaining the input voltage value of the chip, so that the timing module generates a second signal according to the comparison result, providing data guiding information for subsequent judgment of whether undervoltage protection occurs. The falling edge sampling signal is obtained by detecting the falling edge in the switch tube turn-on signal of the main switch tube through the falling edge acquisition module. Thus, while considering the second signal, the falling edge sampling signal in the switch tube turn-on signal of the main switch tube is also fully considered, generating the undervoltage protection signal more comprehensively, and then accurately determining whether the input voltage value of the chip is in the undervoltage state or the normal state. It can ensure that when the system jumps from the load state to the no-load state, it can enter the standby mode normally without generating an incorrect undervoltage protection signal, resulting in the system being turned off.

[0120] It should be noted that although the operations of the method of the present invention are described in a specific order in the accompanying drawings, this does not require or imply that these operations must be performed in that specific order, or that all the operations shown must be performed to achieve the desired result. On the contrary, the order of execution of the steps depicted in the flowchart can be changed. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step for execution, and / or one step may be decomposed into multiple steps for execution.

[0121] In summary, the undervoltage protection circuit, power supply system, and undervoltage protection method of the switching power supply provided by the embodiments of the present application. The undervoltage protection circuit of the switching power supply includes: a current processing module, a comparison module, a timing module, a falling-edge acquisition module, and an arithmetic module. The input end of the current processing module is connected to the detection pin of the chip, the output end of the current processing module is connected to the first input end of the comparison module, the output end of the comparison module is connected to the input end of the timing module, the output end of the timing module is connected to the first end of the arithmetic module, the input end of the falling-edge acquisition module is connected to the main switching transistor of the chip, and the output end of the falling-edge acquisition module is connected to the second end of the arithmetic module; the current processing module is configured to obtain the input voltage value of the chip and send it to the comparison module, the comparison module is configured to compare the input voltage value with a reference voltage value, generate a first signal according to the comparison result and send it to the timing module; the timing module is configured to respond to the first signal, determine whether to perform a timing operation according to the first signal, generate a second signal and send it to the arithmetic module; the falling-edge acquisition module is configured to detect the falling edge in the switching transistor turn-on signal of the main switching transistor, obtain a falling-edge sampling signal and send it to the arithmetic module; the arithmetic module is configured to perform a logical operation on the second signal and the falling-edge sampling signal to generate an undervoltage protection signal. Compared with the prior art, after obtaining the input voltage value of the chip, the undervoltage protection circuit can compare the input voltage value with the reference voltage value, so that the timing module generates a second signal according to the comparison result, providing data guiding information for subsequent determination of whether undervoltage protection occurs, and detecting the falling edge in the switching transistor turn-on signal of the main switching transistor through the falling-edge acquisition module to obtain a falling-edge sampling signal. Thus, while considering the second signal, the falling-edge sampling signal in the switching transistor turn-on signal of the main switching transistor is also fully considered, generating an undervoltage protection signal more comprehensively, and then accurately determining whether the input voltage value of the chip is in an undervoltage state or a normal state. It can ensure that when the system jumps from the load state to the no-load state, it can normally enter the standby mode without generating an incorrect undervoltage protection signal, resulting in system shutdown.

[0122] The above description is only a preferred embodiment of the present application and an explanation of the applied technical principles. Those skilled in the art should understand that the scope of the invention involved in the present application is not limited to the technical solution formed by the specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept. For example, the technical solution formed by mutually replacing the above features with the technical features (but not limited to) disclosed in the present application that have similar functions.

Claims

1. An undervoltage protection circuit for a switching power supply, characterized in that, The undervoltage protection circuit of the switching power supply includes: a current processing module, a comparison module, a timing module, a falling edge acquisition module, and an operation module; The input end of the current processing module is connected to the detection pin of the chip, the output end of the current processing module is connected to the first input end of the comparison module, the output end of the comparison module is connected to the input end of the timing module, the output end of the timing module is connected to the first end of the operation module, and the input end of the falling edge acquisition module is connected to the main switching tube of the chip; the output end of the falling edge acquisition module is connected to the second end of the operation module; The current processing module is used to obtain the input voltage value of the chip and send it to the comparison module; The comparison module is used to compare the input voltage value with a reference voltage value, generate a first signal according to the comparison result and send it to the timing module; the reference voltage value is stored at the second input end of the comparison module; The timing module is used to respond to the first signal, judge whether to perform a timing operation according to the first signal, generate a second signal and send it to the operation module; The falling edge acquisition module is used to generate a low-level falling edge sampling signal and send it to the operation module when detecting that the switching tube turn-on signal is high, and is also used to generate a high-level falling edge sampling signal and send it to the operation module when detecting the arrival of the falling edge of the switching tube turn-on signal; The operation module is used to perform a logical operation on the second signal and the falling edge sampling signal to generate an undervoltage protection signal; The operation module includes: a first inverter, a second inverter, a first NAND gate, and a second NAND gate; the output end of the falling edge acquisition module is connected to the input end of the first inverter, the output end of the first inverter is connected to the first input end of the first NAND gate, the second input end of the first NAND gate is connected to the output end of the second NAND gate, the output end of the first NAND gate is connected to the first input end of the second NAND gate, the second input end of the second NAND gate is connected to the output end of the timing module, the output end of the second NAND gate is also connected to the input end of the second inverter, and the output end of the second inverter outputs the undervoltage protection signal; The operation module is further used for: When the input voltage value is not less than the reference voltage value, obtaining a low-level second signal, and when the system exits the standby mode, obtaining the low-level falling edge sampling signal; obtaining a low-level undervoltage protection signal according to the low-level second signal and the low-level falling edge sampling signal; or, When the input voltage value is less than the reference voltage value, obtaining a high-level second signal, and when the system exits the standby mode, obtaining the high-level falling edge sampling signal; obtaining a high-level undervoltage protection signal according to the high-level second signal and the high-level falling edge sampling signal.

2. The under-voltage protection circuit of the switching power supply according to claim 1, wherein The timing module is further used for: When the first signal is at a high level, a second signal at a low level is generated; the first signal being at a high level is generated when the comparison module determines that the input voltage value is not less than the reference voltage value; or, When the first signal is at a low level, a timing operation is performed and when the time reaches a preset detection time, a second signal at a high level is generated; the first signal being at a low level is generated when the comparison module determines that the input voltage value is less than the reference voltage value.

3. The undervoltage protection circuit of the switching power supply according to claim 1, wherein The falling edge acquisition module includes: a first switching transistor, a second switching transistor, a resistor, a capacitor, a Schmitt trigger, and a first NOR gate; The drain of the first switching transistor is connected to the power supply terminal of the chip, the source of the first switching transistor is connected to one end of the resistor, the other end of the resistor is respectively connected to the drain of the second switching transistor and the input terminal of the Schmitt trigger, the input terminal of the Schmitt trigger is further connected to one end of the capacitor, the output terminal of the Schmitt trigger is connected to the first input terminal of the first NOR gate, the main switching transistor is respectively connected to the gate of the first switching transistor, the gate of the second switching transistor, and the second input terminal of the first NOR gate, the other end of the capacitor and the source of the second switching transistor are both grounded, and the output terminal of the first NOR gate is connected to the input terminal of the first inverter.

4. The undervoltage protection circuit of the switching power supply according to claim 3, characterized in that, The falling edge acquisition module includes: a current mirror, a third inverter, a first NOR gate, a second NOR gate, a first switching transistor, a second switching transistor, a capacitor, and a Schmitt trigger; The main switching transistor is connected to the input terminal of the third inverter, the output terminal of the third inverter is connected to the first input terminal of the first NOR gate, the second input terminal of the first NOR gate is connected to the output terminal of the second NOR gate, the output terminal of the first NOR gate is connected to the first input terminal of the second NOR gate, the second input terminal of the second NOR gate is connected to the output terminal of the Schmitt trigger, the output terminal of the first NOR gate is respectively connected to the gate of the first switching transistor and the gate of the second switching transistor, the input terminal of the current mirror is connected to the power supply terminal, and the output terminal of the current mirror is connected to the drain of the first switching transistor; the source of the first switching transistor is respectively connected to the drain of the second switching transistor, one end of the capacitor, and the input terminal of the Schmitt trigger, the source of the second switching transistor and the other end of the capacitor are both grounded, and the output terminal of the second NOR gate is connected to the input terminal of the first inverter.

5. The undervoltage protection circuit of the switching power supply according to claim 4, characterized in that, The current mirror includes: a third switching transistor and a fourth switching transistor, the drain of the third switching transistor is respectively connected to the power supply terminal and the drain of the fourth switching transistor, the gate of the third switching transistor is connected to the gate of the fourth switching transistor, the source of the third switching transistor, the gate of the third switching transistor, and the gate of the fourth switching transistor are respectively connected to the second input terminal of the comparison module, and the source of the fourth switching transistor is connected to the drain of the first switching transistor.

6. A power supply system, characterized in that, The power supply system includes an undervoltage protection circuit of the switching power supply as described in any one of claims 1-5 above.

7. A undervoltage protection method, characterized in that, An undervoltage protection circuit applied to the switching power supply according to any one of claims 1-5, the undervoltage protection method comprising: The current processing module obtains the input voltage value of the chip and sends it to the comparison module; The comparison module compares the input voltage value with the reference voltage value, generates a first signal according to the comparison result and sends it to the timing module; The timing module responds to the first signal, determines whether to perform a timing operation according to the first signal, generates a second signal and sends it to the operation module; When the falling edge acquisition module detects that the switch tube turn-on signal is high, it generates a falling edge sampling signal of low level and sends it to the operation module; or, when detecting the arrival of the falling edge of the switch tube turn-on signal, it generates a falling edge sampling signal of high level and sends it to the operation module; The operation module performs a logical operation on the second signal and the falling edge sampling signal to generate an undervoltage protection signal; The operation module includes: a first inverter, a second inverter, a first NAND gate and a second NAND gate; the output end of the falling edge acquisition module is connected to the input end of the first inverter, the output end of the first inverter is connected to the first input end of the first NAND gate, the second input end of the first NAND gate is connected to the output end of the second NAND gate, the output end of the first NAND gate is connected to the first input end of the second NAND gate, the second input end of the second NAND gate is connected to the output end of the timing module, the output end of the second NAND gate is also connected to the input end of the second inverter, and the output end of the second inverter outputs the undervoltage protection signal; The operation module performs a logical operation on the second signal and the falling edge sampling signal to generate an undervoltage protection signal, including: When the input voltage value is not less than the reference voltage value, obtain a second signal of low level, and when the system exits the standby mode, obtain the falling edge sampling signal of low level; according to the second signal of low level and the falling edge sampling signal of low level, obtain an undervoltage protection signal of low level; or, When the input voltage value is less than the reference voltage value, obtain a second signal of high level, and when the system exits the standby mode, obtain the falling edge sampling signal of high level; according to the second signal of high level and the falling edge sampling signal of high level, obtain an undervoltage protection signal of high level.

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