High-speed high-linearity gate voltage bootstrap switching circuit with multiple paths and control method

Abstract

The application relates to a multi-path high-speed high-linearity gate voltage bootstrap switch circuit, which comprises MOS tubes MS, M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, M12, M13, M14, a capacitor C1, a capacitor C2 and an inverter I1, wherein the gate of the MOS tube MS is connected with the gate of the MOS tube M2, the drain of the MOS tube M5 and the drain of the MOS tube M9; the drain of the MOS tube MS is connected with the drain of the MOS tube M14, the upper plate of the capacitor C2 and an output signal VOUT; the source of the MOS tube MS is connected with the drain of the MOS tube M1, the source of the MOS tube M14 and an input signal VIN; and the substrate of the MOS tube MS is connected with the source of the MOS tube M1, the source of the MOS tube M2, the source of the MOS tube M3, the drain of the MOS tube M7, the substrate of the MOS tube M14 and the lower plate of the capacitor C1. The application can significantly accelerate the speed of gate voltage bootstrap and the speed of sampling of the gate voltage bootstrap switch circuit.

Description

Technical Field

[0001] This application relates to the field of analog integrated circuit technology, and in particular to a multi-path, high-speed, high-linearity gate voltage bootstrap switching circuit and control method. Background Technology

[0002] Gate bootstrap switches are crucial analog circuit modules in analog integrated circuits. They provide constant on-resistance during sampling and are widely used in analog-to-digital converter (ADC) systems. As an indispensable module in ADCs, the performance ceiling of the gate bootstrap switch determines the overall performance ceiling of the ADC system. Improving the gate bootstrap loop of the gate bootstrap switch circuit will significantly enhance the performance of the ADC.

[0003] Traditional gate-voltage bootstrap switching circuits have the following problems: First, during the sampling phase, the turn-on sequence of the MOSFETs limits the speed of gate-voltage bootstrapping; second, the turn-on and turn-off speeds of the MOSFETs charging the bootstrap capacitors are limited by the rate of change of the node voltage; third, the turn-on and turn-off speeds of the main sampling MOSFETs are limited by the rate of change of the node voltage; fourth, in traditional gate-voltage bootstrap switching circuits, the substrate of the main sampling MOSFET is grounded, which causes the threshold voltage of the MOSFET to change with the input signal due to the body effect during the sampling phase, thereby causing the on-resistance to change with the input signal and reducing the linearity of the circuit.

[0004] In summary, in order to address the limitations of the gate voltage bootstrap switching circuit in the existing technology, such as the turn-on sequence of the MOS transistors limiting the speed of gate voltage bootstrap and the limitation of the turn-on and turn-off speed of the MOS transistors charging the bootstrap capacitors by the speed of node voltage changes, the applicant has made corresponding explorations to solve these problems. Summary of the Invention

[0005] The purpose of this application is to solve the above-mentioned problems by providing a multi-path, high-speed, high-linearity gate voltage bootstrap switching circuit and control method, electronic equipment, computer equipment, and computer-readable storage medium.

[0006] To achieve the various objectives of this application, the following technical solution is adopted:

[0007] A multi-path, high-speed, high-linearity gate voltage bootstrap switching circuit proposed for one of the purposes of this application includes MOSFETs MS, M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, M12, M13, and M14, capacitors C1 and C2, and inverter I1, wherein the gate of MOSFET MS is connected to the gate of MOSFET M2 and the drains of MOSFETs M5 and M9;

[0008] The drain of the MOS transistor MS is connected to the drain of the MOS transistor M14, the upper stage of the capacitor C2, and the output signal VOUT; the source of the MOS transistor MS is connected to the drain of the MOS transistor M1, the source of the MOS transistor M14, and the input signal VIN; the substrate of the MOS transistor MS is connected to the source of the MOS transistor M1, the sources of the MOS transistors M2 and M3, the drain of the MOS transistor M7, the substrate of the MOS transistor M14, and the lower stage of the capacitor C1.

[0009] The gate of MOSFET M1 is connected to the gates of MOSFETs M8 and M14, and the drain of MOSFETs M10 and M11; the drain of MOSFET M2 is connected to the drain of MOSFETs M3 and M4, and the gate of MOSFET M9; the gates of MOSFETs M3 and M4 are connected to the clock signal CLKS; the source of MOSFET M4 is connected to the power supply voltage VDD; the gate of MOSFET M5 is connected to the power supply voltage VDD; the source of MOSFET M5 is connected to the drain of MOSFET M6.

[0010] The gate of MOSFET M6 is connected to the clock signal CLKSB; the source of MOSFET M6 is grounded; the gate of MOSFET M7 is connected to the clock signal CLKSB; the source of MOSFET M7 is grounded; the source of MOSFET M8 is connected to the power supply voltage VDD; the drain of MOSFET M8 is connected to the substrate of MOSFET M8, the sources of MOSFETs M9 and M10 are connected to the substrate, and the upper stage of capacitor C1 is connected; the gate of MOSFET M10 is connected to the clock signal CLKSB; the gate of MOSFET M11 and the source of MOSFET M12 are connected to the power supply voltage VDD; the source of MOSFET M11 is connected to the drain of MOSFETs M12 and M13; the gates of MOSFETs M12 and M13 are connected to the clock signal CLKSB; the source of MOSFET M13 is grounded; the lower stage of capacitor C2 is grounded; the input of inverter I1 is connected to the clock signal CLKS; the output of inverter I1 is connected to the clock signal CLKSB.

[0011] A multi-path, high-speed, high-linearity gate voltage bootstrap switching circuit control method, proposed to suit another objective of this application, is applied to the multi-path, high-speed, high-linearity gate voltage bootstrap switching circuit as described in claim 1, comprising:

[0012] The multi-path high-speed, high-linearity gate voltage bootstrap switching circuit includes a hold phase and a sampling phase;

[0013] During the holding phase, the clock signal CLKS is low and the clock signal CLKSB is high. MOSFETs M5, M6, M7, M11, and M13 are turned on, discharging nodes VB, VC, and VG to ground. The voltage of node VC discharges to ground preferentially over the voltage of node VG to accelerate the turn-on of MOSFET M8, which charges the upper-level board of capacitor C1 to the power supply voltage VDD.

[0014] When MOSFET M4 is turned on, it charges node VA to the power supply voltage VDD. When MOSFET M9 is turned off, MOSFETs MS, M1, M2, M3, M10, M12, and M14 are also turned off. The output signal VOUT maintains the value of the input signal VIN when MOSFETs MS and M14 are turned off.

[0015] Optionally, the multi-path high-speed, high-linearity gate voltage bootstrap switching circuit control method described above further includes:

[0016] During the sampling phase, the clock signal CLKS is high, the clock signal CLKSB is low, MOSFETs M4, M6, M7, and M13 are off, and MOSFETs M9, M10, M11, and M12 are on. Based on the accelerated charging of MOSFET M12, the voltage of node VC reaches VDD before the voltage of node VG, thereby accelerating the turn-off of MOSFET M8. MOSFET M14 is on before MOSFET MS for a sampling period of time.

[0017] When MOSFET M1 is turned on, the input signal VIN is transmitted to node VB. At the same time, the voltage of node VT rises further to the sum of the power supply voltage VDD and the voltage of the input signal VIN, so that the voltages of nodes VC and VG rise further to the sum of the power supply voltage VDD and the voltage of the input signal VIN. At this time, MOSFETs MS and M14 maintain a fixed gate-source voltage VDD for parallel sampling. The output signal VOUT samples the input signal VIN. The substrate terminals of MOSFETs MS and M14 are connected to the source of MOSFET M1 so that they are grounded during the holding phase and follow the changes of the input signal during the sampling phase.

[0018] An electronic device is proposed for another purpose of this application, which applies the above-described multi-path high-speed, high-linearity gate voltage bootstrap switching circuit.

[0019] A computer device is provided for another purpose of this application, comprising a memory and a processor, the memory storing a computer program implemented according to any one of the methods described above, the processor executing the computer program to implement a multi-path high-speed, high-linearity gate voltage bootstrap switching circuit control method as described in any one of the claims.

[0020] A computer-readable storage medium is provided for another purpose of this application, which stores, in the form of computer-readable instructions, a computer program implemented according to any one of the above methods, which, when invoked by a computer, performs the steps included in the corresponding method.

[0021] Compared to existing technologies, this application addresses the problems in existing technologies, such as the limitation on the speed of gate voltage bootstrapping caused by the turn-on sequence of MOSFETs in traditional gate voltage bootstrapping switching circuits, and the limitation on the turn-on and turn-off speeds of MOSFETs charging the bootstrap capacitors by the rate of node voltage change. This application provides, but is not limited to, the following beneficial effects:

[0022] Firstly, this application introduces a fast bootstrap path composed of MOSFETs M10, M11, M12, and M13, which makes the voltage charging and discharging speed of node VC faster than that of node VG. Therefore, it can change the order in which MOSFET M9 turns on first and then MOSFET M1 turns on in the traditional gate bootstrap switching circuit, so that the turn-on of MOSFET M1 takes precedence over the turn-on of MOSFET M9, which greatly speeds up the gate bootstrap speed.

[0023] Secondly, by biasing the gate of the capacitor-charged MOSFET M8 at node VC, compared to the bias at node VG in the traditional gate voltage bootstrap switching circuit, the turn-on and turn-off of the capacitor-charged MOSFET M8 are greatly accelerated.

[0024] Third, the introduction of the priority sampling MOSFET M14, whose gate is biased at node VC, allows it to conduct sampling for a period of time prior to the main sampling MOSFET MS during the sampling phase, which greatly speeds up the sampling speed of the gate voltage bootstrap switching circuit.

[0025] Fourth, connecting the substrate terminals of MOSFETs MS and M14 to the source terminal of MOSFET M1 allows them to be grounded during the hold phase and follow the changes in the input signal during the sampling phase. This can reduce the body effect of MOSFETs MS and M14 and improve the linearity of the gate voltage bootstrap switching circuit.

[0026] Furthermore, this application overcomes the shortcomings of existing gate-voltage bootstrap switching circuits, such as slow gate-voltage bootstrap loop turn-on speed, slow turn-on and turn-off speed of capacitor-charged MOSFETs, slow turn-on and turn-off speed of sampling MOSFETs, and the variation of the threshold voltage of the sampling MOSFET with the input signal due to body effect, which causes the on-resistance to vary with the input signal. It provides a multi-path, high-speed, high-linearity gate-voltage bootstrap switching circuit. To overcome the aforementioned shortcomings of existing gate-voltage bootstrap switching circuits, this application introduces another fast bootstrap path into the original gate-voltage bootstrap loop, changing the original turn-on sequence of the gate-voltage bootstrap loop and accelerating the gate-voltage bootstrap speed. Simultaneously, the gate voltage of the MOSFET charging the bootstrap capacitor is biased onto this path, accelerating the turn-on and turn-off speed of the charging MOSFET. Furthermore, a priority-conducting sampling MOSFET is introduced, with its gate voltage also biased onto this path, allowing it to conduct for a period of time before the main sampling transistor turns on, significantly accelerating the sampling speed of the gate-voltage bootstrap switch. Meanwhile, the substrates of the main sampling MOSFET and the priority conducting sampling MOSFET are connected to the lower stage board of the bootstrap capacitor, so that they are connected to the input signal during the sampling phase and to ground during the holding phase, which reduces the influence of the body effect and greatly improves the linearity of the circuit. Attached Figure Description

[0027] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein:

[0028] Figure 1 This is a schematic diagram of a conventional gate voltage bootstrap switching circuit in an embodiment of this application;

[0029] Figure 2 This is a circuit schematic diagram of a multi-path, high-speed, high-linearity gate voltage bootstrap switching circuit in an embodiment of this application.

[0030] Figure 3 This is a schematic diagram showing the curves of the input signal and output signal of a conventional bootstrap switch and the bootstrap switch of this application changing over time when the input signal frequency is 10.7421875MHz in an embodiment of this application.

[0031] Figure 4 This is a schematic diagram showing the curves of the input signal and output signal of the conventional bootstrap switch and the bootstrap switch of this application changing over time when the input signal frequency is 495.1171875MHz in the embodiments of this application.

[0032] Figure 5 This is a schematic diagram showing the change curves of the effective number of bits of a conventional bootstrap switch and the bootstrap switch of this application when the input signal frequency changes from 10.7421875MHz to 495.1171875MHz in an embodiment of this application.

[0033] Figure 6 This is a schematic diagram showing the variation curves of the spurious-free dynamic range of a conventional bootstrap switch and the bootstrap switch of this application when the input signal frequency changes from 10.7421875MHz to 495.1171875MHz in an embodiment of this application. Detailed Implementation

[0034] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0035] Those skilled in the art will understand that, unless specifically stated otherwise, the singular forms “a,” “an,” “the,” and “the” used herein may also include the plural forms. It should be further understood that the term “comprising” as used in this application means the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It should be understood that when we say an element is “connected” or “coupled” to another element, it can be directly connected or coupled to the other element, or there may be intermediate elements. Furthermore, “connected” or “coupled” as used herein can include wireless connections or wireless coupling. The term “and / or” as used herein includes all or any units and all combinations of one or more associated listed items.

[0036] Unless otherwise expressly stated, the various embodiments disclosed in this application can be combined in a cross-cutting manner to flexibly construct new embodiments, as long as such combination does not depart from the inventive spirit of this application and can meet the needs of the prior art or solve a certain deficiency in the prior art. Those skilled in the art should be aware of such modifications.

[0037] Please see Figure 1 , Figure 1The traditional gate voltage bootstrap switching circuit can be divided into two stages: the hold stage and the sampling stage.

[0038] During the hold phase, clock signal CLKS is low and clock signal CLKSB is high. MOSFETs M5, M6, and M7 are turned on, discharging the voltages at nodes VB and VG to 0V. MOSFET M8 is turned on, charging capacitor C1 to the power supply voltage VDD. MOSFET M4 is turned on, charging the voltage at point VA to the power supply voltage VDD. MOSFETs M1, M2, M3, M9, and MS are turned off. The output signal VOUT maintains the value of the input signal VIN when MOSFET MS is turned off.

[0039] During the sampling phase, clock signal CLKS is high and clock signal CLKSB is low. MOSFETs M4, M6, and M7 are off, and MOSFET M3 is on, discharging the voltage at node VA to 0V. This causes MOSFET M9 to turn on, charging the voltage at point VG to the power supply voltage VDD. Consequently, MOSFET M1 turns on, transmitting the input signal VIN to node VB. This further increases the voltage at point VT to the sum of the power supply voltage VDD and the input signal VIN. At this time, the voltage difference between VGS and VGS of the sampling MOSFET MS is: power supply voltage VDD + input signal VIN - input signal VIN = power supply voltage VDD. MOSFET MS is on and maintains a fixed on-resistance to sample the input signal VIN.

[0040] Traditional gate voltage bootstrap switching circuits have the following problems:

[0041] First, during the sampling phase, the gate voltage bootstrap loop requires MOSFET M9 to be turned on first, followed by MOSFET M1. This turn-on sequence of MOSFETs limits the speed of the gate voltage bootstrap.

[0042] Secondly, the turn-on and turn-off speeds of the MOSFET M8, which charges the bootstrap capacitor, are limited by the rate of change of the node VG voltage.

[0043] Third, the turn-on and turn-off speed of the main sampling MOS transistor MS is limited by the rate of change of the node VG voltage;

[0044] Fourth, in traditional gate voltage bootstrap switching circuits, the substrate of the main sampling MOSFET MS is grounded. During the sampling phase, the threshold voltage of the MOSFET MS will change with the input signal due to the body effect, which will cause the on-resistance to change with the input signal, thus reducing the linearity of the circuit.

[0045] Based on the above exemplary scenario, please refer to Figure 2In one embodiment of the multi-path high-speed, high-linearity gate voltage bootstrap switching circuit of this application, there are MOSFETs MS, M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, M12, M13, and M14, capacitors C1 and C2, and inverter I1, wherein the gate of MOSFET MS is connected to the gate of MOSFET M2 and the drain of MOSFET M5 and MOSFET M9;

[0046] The drain of the MOS transistor MS is connected to the drain of the MOS transistor M14, the upper stage of the capacitor C2, and the output signal VOUT; the source of the MOS transistor MS is connected to the drain of the MOS transistor M1, the source of the MOS transistor M14, and the input signal VIN; the substrate of the MOS transistor MS is connected to the source of the MOS transistor M1, the sources of the MOS transistors M2 and M3, the drain of the MOS transistor M7, the substrate of the MOS transistor M14, and the lower stage of the capacitor C1.

[0047] The gate of MOSFET M1 is connected to the gates of MOSFETs M8 and M14, and the drain of MOSFETs M10 and M11; the drain of MOSFET M2 is connected to the drain of MOSFETs M3 and M4, and the gate of MOSFET M9; the gates of MOSFETs M3 and M4 are connected to the clock signal CLKS; the source of MOSFET M4 is connected to the power supply voltage VDD; the gate of MOSFET M5 is connected to the power supply voltage VDD; the source of MOSFET M5 is connected to the drain of MOSFET M6.

[0048] The gate of MOSFET M6 is connected to the clock signal CLKSB; the source of MOSFET M6 is grounded; the gate of MOSFET M7 is connected to the clock signal CLKSB; the source of MOSFET M7 is grounded; the source of MOSFET M8 is connected to the power supply voltage VDD; the drain of MOSFET M8 is connected to the substrate of MOSFET M8, the sources of MOSFETs M9 and M10 are connected to the substrate, and the upper stage of capacitor C1 is connected; the gate of MOSFET M10 is connected to the clock signal CLKSB; the gate of MOSFET M11 and the source of MOSFET M12 are connected to the power supply voltage VDD; the source of MOSFET M11 is connected to the drain of MOSFETs M12 and M13; the gates of MOSFETs M12 and M13 are connected to the clock signal CLKSB; the source of MOSFET M13 is grounded; the lower stage of capacitor C2 is grounded; the input of inverter I1 is connected to the clock signal CLKS; the output of inverter I1 is connected to the clock signal CLKSB.

[0049] A multi-path, high-speed, high-linearity gate voltage bootstrap switching circuit control method is proposed to suit another objective of this application, applied to the aforementioned multi-path, high-speed, high-linearity gate voltage bootstrap switching circuit, comprising:

[0050] The multi-path high-speed, high-linearity gate voltage bootstrap switching circuit includes a hold phase and a sampling phase;

[0051] During the holding phase, the clock signal CLKS is low, the clock signal CLKSB is high, and MOSFETs M5, M6, M7, M11, and M13 are turned on, discharging nodes VB, VC, and VG to ground. The voltage of node VC discharges to ground preferentially over the voltage of node VG to accelerate the turn-on of MOSFET M8, which charges the upper-level board of capacitor C1 to the power supply voltage VDD. MOSFET M4 is turned on, charging node VA to the power supply voltage VDD. MOSFET M9 is turned off, and MOSFETs MS, M1, M2, M3, M10, M12, and M14 are turned off. The output signal VOUT maintains the value of the input signal VIN when MOSFETs MS and M14 are turned off.

[0052] During the sampling phase, the clock signal CLKS is high, the clock signal CLKSB is low, MOSFETs M4, M6, M7, and M13 are off, and MOSFETs M9, M10, M11, and M12 are on. Due to the accelerated charging of MOSFET M12, the voltage at node VC reaches VDD before the voltage at node VG, thus accelerating the turn-off of MOSFET M8. MOSFET M14 is on for a sampling period before MOSFET MS, significantly accelerating the sampling speed of the gate voltage bootstrap switching circuit. MOSFET M1 is on, transmitting the input signal VIN to node VB. The voltage at node VT rises further to the sum of the power supply voltage VDD and the input signal VIN, so that the voltages at nodes VC and VG rise further to the sum of the power supply voltage VDD and the input signal VIN. At this time, MOS transistors MS and M14 maintain a fixed gate-source voltage VDD for parallel sampling, and the output signal VOUT samples the input signal VIN. The substrate terminals of MOS transistors MS and M14 are connected to the source terminal of MOS transistor M1 so that they are grounded during the hold phase and follow the changes in the input signal during the sampling phase. This can reduce the body effect of MOS transistors MS and M14 and greatly improve the linearity of the gate voltage bootstrap switching circuit.

[0053] Specifically, the operation of the multi-path high-speed, high-linearity gate voltage bootstrap switching circuit proposed in this application can be divided into two processes: a hold phase and a sampling phase. During the hold phase, clock signal CLKS is low and clock signal CLKSB is high. MOSFETs M5, M6, M7, M11, and M13 are turned on, discharging nodes VB, VC, and VG to ground. The voltage at point VC discharges to ground preferentially over the voltage at point VG, accelerating the turn-on of MOSFET M8, which charges the upper stage of capacitor C1 to VDD. MOSFET M4 is turned on, charging node VA to VDD, and MOSFET M9 is turned off. MOSFETs MS, M1, M2, M3, M10, M12, and M14 are turned off, and the output signal VOUT maintains the value of the input signal VIN when MOSFETs MS and M14 are turned off.

[0054] During the sampling phase, clock signal CLKS is high and clock signal CLKSB is low. MOSFETs M4, M6, M7, and M13 are off, while MOSFETs M9, M10, M11, and M12 are on. Due to the accelerated charging effect of MOSFET M12, the voltage at node VC reaches VDD before the voltage at node VG, accelerating the turn-off of MOSFET M8. Furthermore, MOSFET M14 conducts sampling for a period of time before MOSFET MS, significantly accelerating the sampling speed of the gate voltage bootstrap switching circuit. MOSFET M1 turns on, transmitting the input signal VIN to node VB. Simultaneously, the voltage at node VT rises further to VDD+VIN, which in turn causes the voltages at nodes VC and VG to rise further to VDD+VIN. At this time, MOSFETs MS and M14 maintain a fixed gate-source voltage VDD for parallel sampling, and the output signal VOUT samples the input signal VIN. Connecting the substrate terminals of MOSFETs MS and M14 to the source terminal of MOSFET M1 allows them to be grounded during the hold phase and follow the changes in the input signal during the sampling phase. This reduces the body effect of MOSFETs MS and M14 and greatly improves the linearity of the gate voltage bootstrap switching circuit.

[0055] To further verify the technical effectiveness of this application, a standard 65nm CMOS process was used to conduct the same simulation experiments on a traditional gate-voltage bootstrap switching circuit and a multi-path high-speed, high-linearity gate-voltage bootstrap switching circuit of this application. The MOSFETs in the same parts used the same dimensions, and the load capacitors were also the same. The clock signal CLKS had a frequency of 1GHz, and the power supply voltage VDD was 1.1V. The common-mode voltage of the differential input signal was 0.55V, the amplitude was 0.55V, and the phase difference was 180°.

[0056] When the input signal frequency is 10.7421875MHz, the differential input waveform and differential output waveform of the conventional gate voltage bootstrap switching circuit and the gate voltage bootstrap switching circuit of this application change with time as shown in the following figures. Figure 3 As shown, it can be seen that during the sampling stage of low-frequency input signals, the sampling speed of the gate voltage bootstrap switching circuit of this application is faster than that of the conventional gate voltage bootstrap switching circuit.

[0057] When the input signal frequency is 495.1171875MHz, the differential input waveform and differential output waveform of the conventional gate voltage bootstrap switching circuit and the gate voltage bootstrap switching circuit of this application change with time as shown in the following figures. Figure 4 As shown, it can be seen that during the sampling stage when the input signal frequency is close to the Nyquist frequency, the sampling speed of the gate voltage bootstrap switching circuit of this application is faster than that of the conventional gate voltage bootstrap switching circuit.

[0058] The input signal frequency was scanned from 10.7421875MHz to 495.1171875MHz, and the curves showing the change in the effective number of bits (ENOB) of the conventional gate-voltage bootstrap switching circuit and the gate-voltage bootstrap switching circuit of this application are shown below. Figure 5 As shown, the ENOB of the gate-voltage bootstrap switching circuit of this application is higher than that of the conventional gate-voltage bootstrap switching circuit throughout the entire Nyquist bandwidth.

[0059] The input signal frequency was scanned from 10.7421875MHz to 495.1171875MHz, and the SFDR variation curves of the conventional gate voltage bootstrap switching circuit and the gate voltage bootstrap switching circuit of this application are shown below. Figure 6 As shown, the spurious-free dynamic range (SFDR) of the gate-voltage bootstrap switching circuit of this application is higher than that of the conventional gate-voltage bootstrap switching circuit throughout the entire Nyquist bandwidth. The simulation experiments above demonstrate that the gate-voltage bootstrap switching circuit of this application has the advantages of high speed and high linearity compared with the conventional gate-voltage bootstrap switching circuit.

[0060] As can be seen from the above embodiments, compared with the prior art, this application addresses the problems in the prior art where the turn-on sequence of the MOS transistors in the traditional gate voltage bootstrap switching circuit limits the speed of gate voltage bootstrapping, and the turn-on and turn-off speeds of the MOS transistors charging the bootstrap capacitor are limited by the node voltage change rate. This application has, but is not limited to, the following beneficial effects:

[0061] Firstly, this application introduces a fast bootstrap path composed of MOSFETs M10, M11, M12, and M13, which makes the voltage charging and discharging speed of node VC faster than that of node VG. Therefore, it can change the order in which MOSFET M9 turns on first and then MOSFET M1 turns on in the traditional gate bootstrap switching circuit, so that the turn-on of MOSFET M1 takes precedence over the turn-on of MOSFET M9, which greatly speeds up the gate bootstrap speed.

[0062] Secondly, by biasing the gate of the capacitor-charged MOSFET M8 at node VC, compared to the bias at node VG in the traditional gate voltage bootstrap switching circuit, the turn-on and turn-off of the capacitor-charged MOSFET M8 are greatly accelerated.

[0063] Third, the introduction of the priority sampling MOSFET M14, whose gate is biased at node VC, allows it to conduct sampling for a period of time prior to the main sampling MOSFET MS during the sampling phase, which greatly speeds up the sampling speed of the gate voltage bootstrap switching circuit.

[0064] Fourth, connecting the substrate terminals of MOSFETs MS and M14 to the source terminal of MOSFET M1 allows them to be grounded during the hold phase and follow the changes in the input signal during the sampling phase. This can reduce the body effect of MOSFETs MS and M14 and improve the linearity of the gate voltage bootstrap switching circuit.

[0065] Furthermore, this application overcomes the shortcomings of existing gate-voltage bootstrap switching circuits, such as slow gate-voltage bootstrap loop turn-on speed, slow turn-on and turn-off speed of capacitor-charged MOSFETs, slow turn-on and turn-off speed of sampling MOSFETs, and the variation of the threshold voltage of the sampling MOSFET with the input signal due to body effect, which causes the on-resistance to vary with the input signal. It provides a multi-path, high-speed, high-linearity gate-voltage bootstrap switching circuit. To overcome the aforementioned shortcomings of existing gate-voltage bootstrap switching circuits, this application introduces another fast bootstrap path into the original gate-voltage bootstrap loop, changing the original turn-on sequence of the gate-voltage bootstrap loop and accelerating the gate-voltage bootstrap speed. Simultaneously, the gate voltage of the MOSFET charging the bootstrap capacitor is biased onto this path, accelerating the turn-on and turn-off speed of the charging MOSFET. Furthermore, a priority-conducting sampling MOSFET is introduced, with its gate voltage also biased onto this path, allowing it to conduct for a period of time before the main sampling transistor turns on, significantly accelerating the sampling speed of the gate-voltage bootstrap switch. Meanwhile, the substrates of the main sampling MOSFET and the priority conducting sampling MOSFET are connected to the lower stage board of the bootstrap capacitor, so that they are connected to the input signal during the sampling phase and to ground during the holding phase, which reduces the influence of the body effect and greatly improves the linearity of the circuit.

[0066] This application also proposes an electronic device that applies the above-described multi-path, high-speed, high-linearity gate voltage bootstrap switching circuit.

[0067] This application also proposes a computer device, including a memory and a processor, wherein the memory stores a computer program implemented according to any one of the methods described above, and the processor executes the computer program to implement a multi-path high-speed, high-linearity gate voltage bootstrap switching circuit control method as described in any one of the claims.

[0068] This application also proposes a computer-readable storage medium that stores, in the form of computer-readable instructions, a computer program implemented according to any one of the above methods, which, when called by a computer, executes the steps included in the corresponding method.

[0069] The above description is only a partial embodiment of this application. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of this application, and these improvements and modifications should also be considered within the scope of protection of this application.

[0070] In summary, this application introduces an additional fast bootstrap path into the original gate bootstrap loop, changing the conduction sequence of the original gate bootstrap loop and accelerating the gate bootstrap speed. Simultaneously, the gate voltage of the MOSFET charging the bootstrap capacitor is biased onto this path, accelerating the turn-on and turn-off speed of the charging MOSFET. Furthermore, a priority sampling MOSFET is introduced, with its gate voltage also biased onto this path, allowing it to conduct for a period of time before the main sampling transistor, significantly accelerating the sampling speed of the gate bootstrap switch. Additionally, the substrates of both the main sampling MOSFET and the priority sampling MOSFET are connected to the lower stage of the bootstrap capacitor, connecting them to the input signal during the sampling phase and to ground during the hold phase, mitigating the body effect and greatly improving the circuit's linearity.

Claims

1. A multi-path, high-speed, high-linearity gate voltage bootstrap switching circuit, characterized in that, The system includes MOSFETs MS, M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, M12, M13, and M14, capacitors C1 and C2, and inverter I1. The gate of MOSFET MS is connected to the gate of MOSFET M2, and the drains of MOSFETs M5 and M9. The drain of the MOS transistor MS is connected to the drain of the MOS transistor M14, the upper stage of the capacitor C2, and the output signal VOUT; the source of the MOS transistor MS is connected to the drain of the MOS transistor M1, the source of the MOS transistor M14, and the input signal VIN; the substrate of the MOS transistor MS is connected to the source of the MOS transistor M1, the sources of the MOS transistors M2 and M3, the drain of the MOS transistor M7, the substrate of the MOS transistor M14, and the lower stage of the capacitor C1. The gate of MOSFET M1 is connected to the gates of MOSFETs M8 and M14, and the drain of MOSFETs M10 and M11; the drain of MOSFET M2 is connected to the drain of MOSFETs M3 and M4, and the gate of MOSFET M9; the gates of MOSFETs M3 and M4 are connected to the clock signal CLKS; the source of MOSFET M4 is connected to the power supply voltage VDD; the gate of MOSFET M5 is connected to the power supply voltage VDD; the source of MOSFET M5 is connected to the drain of MOSFET M6. The gate of MOSFET M6 is connected to the clock signal CLKSB; the source of MOSFET M6 is grounded; the gate of MOSFET M7 is connected to the clock signal CLKSB; the source of MOSFET M7 is grounded; the source of MOSFET M8 is connected to the power supply voltage VDD; the drain of MOSFET M8 is connected to the substrate of MOSFET M8, the sources of MOSFETs M9 and M10 are connected to the substrate, and the upper stage of capacitor C1 is connected; the gate of MOSFET M10 is connected to the clock signal CLKSB; the gate of MOSFET M11 and the source of MOSFET M12 are connected to the power supply voltage VDD; the source of MOSFET M11 is connected to the drain of MOSFETs M12 and M13; the gates of MOSFETs M12 and M13 are connected to the clock signal CLKSB; the source of MOSFET M13 is grounded; the lower stage of capacitor C2 is grounded; the input of inverter I1 is connected to the clock signal CLKS; the output of inverter I1 is connected to the clock signal CLKSB.

2. A control method for a multi-path high-speed, high-linearity gate voltage bootstrap switching circuit, applied to the multi-path high-speed, high-linearity gate voltage bootstrap switching circuit as described in claim 1, characterized in that, include: The multi-path high-speed, high-linearity gate voltage bootstrap switching circuit includes a hold phase and a sampling phase; During the holding phase, the clock signal CLKS is low and the clock signal CLKSB is high. MOSFETs M5, M6, M7, M11, and M13 are turned on, discharging nodes VB, VC, and VG to ground. The voltage of node VC discharges to ground preferentially over the voltage of node VG to accelerate the turn-on of MOSFET M8, which charges the upper-level board of capacitor C1 to the power supply voltage VDD. When MOSFET M4 is turned on, it charges node VA to the power supply voltage VDD. When MOSFET M9 is turned off, MOSFETs MS, M1, M2, M3, M10, M12, and M14 are also turned off. The output signal VOUT maintains the value of the input signal VIN when MOSFETs MS and M14 are turned off.

3. The multi-path high-speed, high-linearity gate voltage bootstrap switching circuit control method according to claim 2, characterized in that, Also includes: During the sampling phase, the clock signal CLKS is high, the clock signal CLKSB is low, MOSFETs M4, M6, M7, and M13 are off, and MOSFETs M9, M10, M11, and M12 are on. Based on the accelerated charging of MOSFET M12, the voltage of node VC reaches VDD before the voltage of node VG, thereby accelerating the turn-off of MOSFET M8. MOSFET M14 is on before MOSFET MS for a sampling period of time. When MOSFET M1 is turned on, the input signal VIN is transmitted to node VB. At the same time, the voltage of node VT rises further to the sum of the power supply voltage VDD and the voltage of the input signal VIN, so that the voltages of nodes VC and VG rise further to the sum of the power supply voltage VDD and the voltage of the input signal VIN. At this time, MOSFETs MS and M14 maintain a fixed gate-source voltage VDD for parallel sampling. The output signal VOUT samples the input signal VIN. The substrate terminals of MOSFETs MS and M14 are connected to the source of MOSFET M1 so that they are grounded during the holding phase and follow the changes of the input signal during the sampling phase.

4. An electronic device, characterized in that, The application uses a multi-path, high-speed, high-linearity gate voltage bootstrap switching circuit as described in claim 1.

5. A computer device, characterized in that, The device includes a memory and a processor, wherein the memory stores a computer program implemented according to the method of any one of claims 2 to 3, and the processor executes the computer program to implement a multi-path high-speed, high-linearity gate voltage bootstrap switching circuit control method as described in any one of the claims.

6. A computer-readable storage medium, characterized in that, It stores, in the form of computer-readable instructions, a computer program implemented according to any one of claims 2 to 3, which, when invoked by a computer, executes the steps included in the corresponding method.

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