Ldpc encoding method and apparatus, network device, and storage medium

Abstract

Embodiments of the present application provide an LDPC encoding method and device, network equipment and a storage medium. The method comprises: performing digital-to-analog conversion on to-be-encoded information to obtain voltage encoding data of the to-be-encoded information; performing calculation on the voltage encoding data using a memory-compute integrated array according to an LDPC check matrix to obtain check data for encoding the to-be-encoded information; performing binary parameter mapping on the check data to obtain check code corresponding to the to-be-encoded information; and generating LDPC encoding data of the to-be-encoded information according to the to-be-encoded information and the check code. The method is based on an LDPC check matrix and uses a memory-compute integrated array to perform LDPC encoding. The entire operation process does not need to repeatedly read a large number of model parameters from a memory, which can effectively improve the encoding computing power and encoding efficiency and solve the problem of high power consumption in the prior art.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of communication, in particular to an LDPC encoding method and device, network equipment and storage medium. BACKGROUND

[0002] Communication coding and decoding is an important part of wireless communication, and the application of communication coding and decoding can effectively improve the quality of signal transmission. Compared with 4G, 5G can greatly improve the data transmission rate to about 10 Gb / s, so higher requirements are put forward for channel coding technology. Since the performance of low-density parity check code (LDPC) is close to the Shannon limit, it is selected as the 5G communication coding and decoding technology for channel coding.

[0003] However, the chips in the current 5G base station are all based on the "von Neumann" architecture with separate storage units and computing units. In the face of large bandwidth, high speed scenarios, the LDPC communication coding and decoding task has the problems of insufficient computing power, low coding efficiency and high power consumption when transmitting and processing massive data. Therefore, it is urgent to improve the computing performance and self-controllability, build a new domestic computing power technology ecology, improve the LDPC coding capability of the 5G base station, improve the computing performance of the base station equipment, and promote the deep integration of computing power and network. SUMMARY

[0004] The technical scheme of the present application aims to provide an LDPC encoding method, device, network equipment and storage medium, which can solve the problems of insufficient computing power, low coding efficiency and high power consumption in the prior art LDPC encoding.

[0005] The present application provides a low-density parity check code (LDPC) encoding method, which comprises the following steps:

[0006] Analog-digital conversion is performed on the to-be-encoded information to obtain voltage encoding data of the to-be-encoded information;

[0007] According to the LDPC check matrix and the voltage encoding data, the storage-computing integrated array is used for calculation to obtain check data for encoding the to-be-encoded information;

[0008] Binary parameter mapping is performed on the check data to obtain a check code corresponding to the to-be-encoded information;

[0009] According to the to-be-encoded information and the check code, LDPC encoding data of the to-be-encoded information is generated.

[0010] Optionally, the LDPC encoding method, wherein the check data of the to-be-encoded information is obtained by using the memory-compute integrated array to perform computation according to the LDPC check matrix and the voltage encoded data, and the computation comprises:

[0011] The transposed matrix of the voltage encoded data is input into the memory-compute integrated array in which a plurality of sub-matrices are deployed, and computation is performed with the plurality of sub-matrices to obtain the check data.

[0012] The plurality of sub-matrices are generated by block division of the LDPC check matrix.

[0013] Optionally, the LDPC encoding method, wherein the check data of the to-be-encoded information is obtained by using the memory-compute integrated array to perform computation according to the LDPC check matrix and the voltage encoded data, and the computation comprises:

[0014] The transposed matrix of the voltage encoded data is input into the memory-compute integrated array in which a plurality of sub-matrices are deployed, and computation is performed with a first part of the plurality of sub-matrices to obtain first check data of the check data.

[0015] The transposed matrix of the voltage encoded data is input into the memory-compute integrated array in which a plurality of sub-matrices are deployed, and computation is performed with a first part of the plurality of sub-matrices to obtain first check data of the check data.

[0016] The first part of the sub-matrices is located in a first block row, the second part of the sub-matrices and the third part of the sub-matrices are located in a second block row, and the second part of the sub-matrices and the third part of the sub-matrices are arranged from left to right in the second block row.

[0017] Optionally, the LDPC encoding method, wherein the check data of the to-be-encoded information is obtained by using the memory-compute integrated array to perform computation according to the LDPC check matrix and the voltage encoded data, and the computation comprises:

[0018] The transposed matrix of the voltage encoded data is input into the memory-compute integrated array in which a plurality of sub-matrices are deployed, and computation is performed with a first part of the plurality of sub-matrices to obtain first check data of the check data.

[0019] The first computation data is sequentially subjected to analog-digital conversion and digital-analog conversion to obtain a first voltage signal of the first computation data.

[0020] The first voltage signal is computed with an inverse matrix of a second sub-matrix of the first part of the sub-matrices in the memory-compute integrated array to obtain second computation data.

[0021] analog-to-digital conversion on the second calculation data to obtain the first check data;

[0022] The first sub-matrix and the second sub-matrix are arranged from left to right in the first block row.

[0023] Optionally, the LDPC encoding method, wherein the transposed matrix of the voltage encoded data is calculated with a second part of the plurality of sub-matrices to obtain a third calculation data, and the first check data is calculated with a third part of the plurality of sub-matrices to obtain a second check data in the check data, comprising:

[0024] The transposed matrix of the voltage encoded data is calculated with a second part of the plurality of sub-matrices to obtain a third calculation data;

[0025] digital-to-analog conversion on the first check data to obtain a second voltage signal;

[0026] The transposed matrix of the second voltage signal is calculated with a third part of the plurality of sub-matrices to obtain a fourth calculation data;

[0027] analog-to-digital conversion on the third calculation data to obtain a first signal data, and analog-to-digital conversion on the fourth calculation data to obtain a second signal data;

[0028] The first signal data and the second signal data are added to obtain the second check data.

[0029] Optionally, the LDPC encoding method, wherein binary parameter mapping is performed on the check data to obtain a check code corresponding to the to-be-encoded information, comprising:

[0030] The parity of each data bit of the check data is determined in sequence, and in the case that the data bit of the check data is even, it is determined to perform binary parameter mapping on the check data, and the value of the corresponding bit of the mapped check code is 0; in the case that the data bit of the check data is odd, it is determined to perform binary parameter mapping on the check data, and the value of the corresponding bit of the mapped check code is 1.

[0031] Optionally, the LDPC encoding method, wherein the method further comprises:

[0032] The LDPC check matrix is divided into blocks to generate a plurality of sub-matrices;

[0033] Each of the sub-matrices is respectively arranged in a sub-array region of the storage-computing integrated array;

[0034] The number of rows and columns in the subarray region matches the number of rows and columns of the deployed submatrix.

[0035] Optionally, the LDPC encoding method, wherein each of the submatrices is respectively deployed in a subarray region of the memory-computing integrated array.

[0036] The first submatrix of the first part of the plurality of submatrices is deployed in a first subarray region of the memory-computing integrated array, and the inverse matrix of the second submatrix of the first part of the plurality of submatrices is deployed in a second subarray region of the memory-computing integrated array.

[0037] The second part of the plurality of submatrices is deployed in a third subarray region of the memory-computing integrated array, and the third part of the plurality of submatrices is deployed in a fourth subarray region of the memory-computing integrated array.

[0038] The first part of the plurality of submatrices is arranged in a first block row, the second part of the plurality of submatrices and the third part of the plurality of submatrices are arranged in a second block row, and the second part of the plurality of submatrices and the third part of the plurality of submatrices are arranged from left to right in the second block row; the first submatrix and the second submatrix are arranged from left to right in the first block row.

[0039] Optionally, the LDPC encoding method, wherein the first subarray region and the second subarray region are arranged from left to right in the memory-computing integrated array, the third subarray region and the fourth subarray region are arranged from left to right in the memory-computing integrated array, and the first subarray region and the third subarray region are arranged from top to bottom in the memory-computing integrated array.

[0040] Optionally, the LDPC encoding method, wherein the binary parameter mapping is performed on the check data to obtain corresponding check codes, comprising:

[0041] The binary parameter mapping is performed on the first check data in the check data to obtain a corresponding first check code.

[0042] The binary parameter mapping is performed on the second check data in the check data to obtain a corresponding second check code.

[0043] Optionally, the LDPC encoding method, wherein the LDPC encoding data of the to-be-encoded information is obtained according to the to-be-encoded information and the check code, comprising:

[0044] The to-be-encoded information is combined with the first check code and the second check code to obtain the LDPC encoding data.

[0045] The embodiment of the present application also provides a low-density parity-check code (LDPC) encoding device, which comprises:

[0046] a data processing unit, configured to perform digital-to-analog conversion on to-be-encoded information to obtain voltage encoding data of the to-be-encoded information;

[0047] a calculation unit, configured to perform calculation on the voltage encoding data and an LDPC check matrix by using a memory-compute integrated array to obtain check data for encoding the to-be-encoded information;

[0048] a mapping unit, configured to perform binary parameter mapping on the check data to obtain a check code corresponding to the to-be-encoded information;

[0049] a processing unit, configured to generate LDPC encoding data of the to-be-encoded information according to the to-be-encoded information and the check code.

[0050] The embodiment of the present application also provides a network device, which comprises a processor, a memory and a program stored in the memory and executable on the processor, and the program is executed by the processor to implement the LDPC encoding method according to any one of the above.

[0051] The embodiment of the present application also provides a readable storage medium, wherein the readable storage medium stores a program, and the program is executed by a processor to implement the steps of the LDPC encoding method according to any one of the above.

[0052] The above technical solution of the present application has at least one of the following beneficial effects:

[0053] The LDPC encoding method according to the embodiment of the present application is based on an LDPC check matrix and uses a memory-compute integrated array to perform LDPC encoding. By using the method, the memory-compute integrated array is used to realize matrix vector multiplication by using a cross array, and the characteristics of multiple dimension multiplication operations are realized. Since the entire operation process does not need to repeatedly read a large number of model parameters from a memory, the coding computing power and coding efficiency can be effectively improved, and the problem of high power consumption in the prior art LDPC encoding is solved. BRIEF DESCRIPTION OF DRAWINGS

[0054] Figure 1 The figure is a flowchart of the encoding method according to the embodiment of the present application.

[0055] Figure 2 The figure is a schematic diagram of the principle of calculation by using a memory-compute integrated array.

[0056] Figure 3 The figure is a schematic diagram of one of the embodiments of block processing of an LDPC check matrix.

[0057] Figure 4A flowchart of an embodiment of the encoding method according to the present application;

[0058] Figure 5 A flowchart of another embodiment of the encoding method according to the present application;

[0059] Figure 6 A structural diagram of the encoding device according to the present application. DETAILED DESCRIPTION

[0060] To make the technical problems, technical solutions and advantages of the present application clearer, specific embodiments will be described in detail below with reference to the accompanying drawings.

[0061] To solve the problems of insufficient computing power, low encoding efficiency and high power consumption of the existing LDPC encoding, the present application provides an LDPC encoding method based on an LDPC check matrix and using a memory-compute integrated array to perform LDPC encoding. This method uses the memory-compute integrated array to implement matrix-vector multiplication using a cross array, and realizes multiple-dimensional multiplication operations. Since the computing unit and the storage unit are combined in the entire operation process, there is no need to repeatedly read a large number of model parameters from the memory, so that the encoding computing power and the encoding efficiency can be effectively improved, and the problem of high power consumption of the existing LDPC encoding is solved.

[0062] One embodiment of the present application provides a low-density parity-check code (LDPC) encoding method, as shown in Figure 1 The method comprises the following steps:

[0063] S110, digital-to-analog conversion is performed on the information to be encoded to obtain voltage encoding data of the information to be encoded;

[0064] S120, according to the LDPC check matrix and the voltage encoding data, a memory-compute integrated array is used to perform calculation to obtain check data for encoding the information to be encoded;

[0065] S130, binary parameter mapping is performed on the check data to obtain a check code corresponding to the information to be encoded;

[0066] S140, according to the information to be encoded and the check code, LDPC encoding data of the information to be encoded is generated.

[0067] The LDPC encoding method according to the present application uses a memory-compute integrated array to perform calculation according to the LDPC check matrix and the information to be encoded, which can effectively improve the encoding computing power and the encoding efficiency of the LDPC encoding.

[0068] To clearly illustrate the specific implementation of the LDPC encoding method described in the embodiments of the present invention, the principle of using the LDPC encoding described in the embodiments of the present invention will be explained below.

[0069] LDPC codes can be represented as (n, k), where n represents the code length, k represents the number of information bits, and m = nk represents the number of parity bits. The encoding principle of LDPC codes is to map the input k-bit information to obtain n-bit information c using a generator matrix G, i.e., sG = c. For the generator matrix G, there exists a completely equivalent sparse parity check matrix H, and all codeword sequences c constitute the null space of H, i.e., Hc. T =0. The parity-check matrix H consists of 0s and 1s. Quasi-cyclic LDPC codes (QC-LDPC) exhibit quasi-cyclic properties compared to general LDPC codes.

[0070] Currently, QC-LDPC encoding can be implemented based on the QC-LDPC check matrix H.

[0071] Currently available LDPC encoding methods include:

[0072] 1) Matrix multiplication and addition encoding algorithm based on LDPC parity-check matrix H

[0073] This algorithm directly uses the LDPC parity-check matrix H for encoding, where the LDPC parity-check matrix H has the following structure. Then, it uses Hc... T =0, encoding is performed based on the submatrices A, B, C, and D after block division. The core operation in this method is XY. T Matrix multiplication and addition structure.

[0074]

[0075] Specifically, using Hc T =0 yields the following formula:

[0076] Formula 1:

[0077]

[0078] Formula 2:

[0079]

[0080] Where s is the information to be encoded, and p1 and p2 are the check codes for LDPC encoding. This is also the solution part of the LDPC encoding. The combination of s, p1, and p2, c = [s p1 p2], yields the encoded information c.

[0081] 2) Coding algorithms based on in-memory computing technology

[0082] The storage-computing integrated technology is a technology of realizing matrix vector multiplication by using a memory cross array, presetting a weight parameter to a storage array, inputting source data, realizing in-situ calculation in a storage unit, and obtaining a required calculation result. In the embodiment of the present application, the calculation principle of the storage-computing integration is introduced by taking a new type of nonvolatile memory device, a memristor, as an example, and the specific implementation is not limited thereto.

[0083] In combination Figure 2 As shown in the figure, the storage-computing integration based on the memristor utilizes the nonvolatile resistance characteristic of the device to encode a data matrix as a resistance value of the device, such as G 11 , G 21 ,..., and G n3 , utilizes Ohm's law to apply a voltage, such as v1, v2, and v3, on one side of the device, and reads out a current on the other side, that is, completes a multiplication operation between the voltage and the conductance, that is, the following calculation can be completed by the storage-computing integrated array:

[0084]

[0085] By using this principle, one memristor can be equivalent to the superposition of one adder, one multiplier, and one memory.

[0086] According to the above calculation principle, in the matrix multiplication and addition operation based on the storage-computing integrated technology, only one voltage adding operation is needed, and then the output current signals of each column are collected, and the operation result of one matrix vector multiplication can be obtained, and the process can be completed in one clock cycle. Since the entire operation process does not need to repeatedly read a large number of model parameters from the memory, the bottleneck of the von Neumann architecture based on the separation of the storage unit and the calculation unit in the prior art is bypassed, and therefore the energy efficiency ratio is significantly improved, and obvious advantages are obtained in AI computing, communication coding and decoding, video coding and other memory-intensive computing scenarios.

[0087] The LDPC encoding method described in the embodiment of the present application has the above advantages of encoding by using the storage-computing integrated technology, is based on an LDPC check matrix, and uses a storage-computing integrated array to perform LDPC encoding. By using this method, the calculation unit and the storage unit are combined in the entire operation process, and a large number of model parameters do not need to be repeatedly read from the memory, so that the encoding computing power and the encoding efficiency can be effectively improved, and the problem of high power consumption in the LDPC encoding of the prior art is solved.

[0088] In the embodiment of the present application, optionally, in step S120, the storage-computing integrated array is used to perform calculation according to the LDPC check matrix and the voltage encoded data, to obtain check data for encoding the to-be-encoded information, including:

[0089] Inputting the transposed matrix of the voltage encoded data into the memory-computing integrated array in which a plurality of sub-matrices are deployed, performing computation with the plurality of sub-matrices to obtain the check data.

[0090] The plurality of sub-matrices are generated by block processing the LDPC check matrix.

[0091] Optionally, the method further comprises:

[0092] Block processing the LDPC check matrix to generate a plurality of sub-matrices.

[0093] Deploying each of the sub-matrices in a sub-array region of the memory-computing integrated array.

[0094] The number of rows and columns in the sub-array region matches the number of rows and columns of the deployed sub-matrices.

[0095] Specifically, deploying each of the sub-matrices in a sub-array region of the memory-computing integrated array comprises:

[0096] Deploying a first sub-matrix of a first part of the plurality of sub-matrices in a first sub-array region of the memory-computing integrated array, and deploying an inverse matrix of a second sub-matrix of the first part of the plurality of sub-matrices in a second sub-array region of the memory-computing integrated array.

[0097] Deploying a second part of the plurality of sub-matrices in a third sub-array region of the memory-computing integrated array, and deploying a third part of the plurality of sub-matrices in a fourth sub-array region of the memory-computing integrated array.

[0098] The first part of the sub-matrices is located in a first block row, the second part of the sub-matrices and the third part of the sub-matrices are located in a second block row, and the second part of the sub-matrices and the third part of the sub-matrices are arranged from left to right in the second block row; the first sub-matrix and the second sub-matrix are arranged from left to right in the first block row.

[0099] The first sub-array region and the second sub-array region are arranged from left to right in the memory-computing integrated array, the third sub-array region and the fourth sub-array region are arranged from left to right in the memory-computing integrated array, and the first sub-array region and the third sub-array region are arranged from top to bottom in the memory-computing integrated array.

[0100] Specifically, deploying each of the sub-matrices in a sub-array region of the memory-computing integrated array comprises:

[0101] deploying a first sub-matrix of a first part of the plurality of sub-matrices in a corresponding position of 0th to (m-1)th rows and 0th to (g-1)th columns in the storage-computing integrated array (a first sub-array region), and deploying an inverse matrix of a second sub-matrix of the first part of the plurality of sub-matrices in a corresponding position of 0th to (m-1)th rows and (g)th to (g+m-1)th columns in the storage-computing integrated array (a second sub-array region);

[0102] deploying a second part of the plurality of sub-matrices in a corresponding position of (m)th to (m+t-1)th rows and 0th to (g-1)th columns in the storage-computing integrated array (a third sub-array region), and deploying a third part of the plurality of sub-matrices in a corresponding position of (m)th to (m+t-1)th rows and (g)th to (g+m-1)th columns in the storage-computing integrated array (a fourth sub-array region);

[0103] wherein the first part of the sub-matrices is located in a first block row, the second part of the sub-matrices and the third part of the sub-matrices are located in a second block row, and the second part of the sub-matrices and the third part of the sub-matrices are arranged from left to right in the second block row; the first sub-matrix and the second sub-matrix are arranged from left to right in the first block row; the number of rows of the first sub-matrix is m, and the number of columns is g; the number of rows of the second sub-matrix is m, and the number of columns is m; the number of rows of the second part of the sub-matrix is t, and the number of columns is g; the number of rows of the third part of the sub-matrix is t, and the number of columns is m;

[0104] wherein m, g, and t are each an integer greater than or equal to 1.

[0105]

[0106] For example, in combination with Figure 3 As shown in FIG. 6, the LDPC check matrix H is divided into a plurality of sub-matrices, and the obtained matrix structure can be as shown below: Specifically, the plurality of sub-matrices of the LDPC check matrix H includes a matrix A, a matrix B, a matrix C, and a matrix D. Wherein the matrix A and the matrix B form a first part of the sub-matrices, located in a first block row, the matrix A is a first sub-matrix, and the matrix B is a second sub-matrix; the matrix C forms a second part of the sub-matrices, and the matrix D forms a third part of the sub-matrices, located in a second block row, and the matrix C and the matrix D are arranged from left to right in the second block row. The first block row and the second block row are arranged in an up-down manner.

[0107] In this embodiment, the matrix A is deployed in the 0th to (m-1)th rows and 0th to (g-1)th columns of the storage-computing integrated array; wherein m is the number of rows of the matrix A, and g is the number of columns of the matrix A.

[0108] The inverse matrix B of the matrix B is calculated in advance -1 The inverse matrix B of the matrix B is calculated in advance-1 deployed in the 0th to the m-1th row and the gth to the g+m-1th column of the memory-computing integrated array; wherein m is the number of rows of the inverse matrix B -1 ;

[0109] deploy the matrix C in the mth to the m+t-1th row and the 0th to the g-1th column of the memory-computing integrated array; wherein t is the number of rows of the matrix C, and g is the number of columns of the matrix C;

[0110] deploy the matrix D in the mth to the m+t-1th row and the gth to the g+m-1th column of the memory-computing integrated array; wherein t is the number of rows of the matrix D, and m is the number of columns of the matrix D.

[0111] By using the LDPC encoding method described in the embodiment, based on the LDPC check matrix deployed in the memory-computing integrated array, after the analog-to-digital conversion of the to-be-encoded information is performed to obtain the voltage encoding data of the to-be-encoded information according to the above-mentioned formula one and formula two, the transposed matrix of the voltage encoding data is input into the memory-computing integrated array to be calculated with the plurality of sub-matrices, and the check data for encoding the to-be-encoded information can be obtained.

[0112] Specifically, inputting the transposed matrix of the voltage encoding data into the memory-computing integrated array to be calculated with the plurality of sub-matrices to obtain the check data includes:

[0113] inputting the transposed matrix of the voltage encoding data into the memory-computing integrated array to be calculated with a first part of the plurality of sub-matrices to obtain first check data in the check data;

[0114] calculating the transposed matrix of the voltage encoding data with a second part of the plurality of sub-matrices and calculating the first check data with a third part of the plurality of sub-matrices to obtain second check data in the check data;

[0115] wherein the first part of the sub-matrices is located in a first block row, the second part of the sub-matrices and the third part of the sub-matrices are located in a second block row, and the second part of the sub-matrices and the third part of the sub-matrices are arranged from left to right in the second block row.

[0116] Specifically, in combination with the method shown in Figure 4 , the LDPC encoding method described in the embodiment of the application includes the following steps:

[0117] S410, start;

[0118] S420, block the LDPC check matrix H to generate a plurality of sub-matrices, such as sub-matrices A, B, C and D, and deploy the plurality of sub-matrices into the memory-computing integrated array;

[0119] S430, inputting the transpose matrix S of the voltage encoded data S into the memory-computing integrated array, performing calculation based on the matrix A and the matrix B (the first partial sub-matrix) deployed in the memory-computing integrated array, and obtaining the first check data p1'; T Input into the memory-computing integrated array, calculate based on the matrix A and the matrix B (the first partial sub-matrix) deployed in the memory-computing integrated array, obtain the first check data p1';

[0120] S440, inputting the transpose matrix S of the voltage encoded data S into the memory-computing integrated array, performing calculation based on the matrix A and the matrix B (the first partial sub-matrix) deployed in the memory-computing integrated array, and obtaining the first check data p1'; T And calculate the first check data p1' with the matrix D (the third partial sub-matrix) in the plurality of sub-matrices, and obtain the second check data p2' in the check data;

[0121] S450, respectively, the first check data p1' and the second check data p2' are judged by parity, and binary parameter mapping is performed to obtain corresponding check codes p1 and p2;

[0122] S460, combining the to-be-encoded information with the check codes p1 and p2 to obtain the LDPC encoded data of the to-be-encoded information;

[0123] S470, end.

[0124] In the embodiment of the application, the LDPC encoding method, the transpose matrix of the voltage encoded data is input into the memory-computing integrated array, and the first partial sub-matrix in the plurality of sub-matrices is calculated to obtain the first check data in the check code, comprising:

[0125] The transpose matrix of the voltage encoded data is input into the memory-computing integrated array, and the first sub-matrix in the first partial sub-matrix is calculated to obtain the first calculation data;

[0126] The first calculation data is sequentially analog-digital converted and digital-analog converted to obtain the first voltage signal of the first calculation data;

[0127] The first voltage signal is calculated with the inverse matrix of the second sub-matrix in the first partial sub-matrix in the memory-computing integrated array to obtain the second calculation data;

[0128] The first check data is obtained after the second calculation data is analog-digital converted;

[0129] The first sub-matrix and the second sub-matrix are arranged from left to right in the first block row.

[0130] Optionally, the transposed matrix of the voltage encoded data is calculated with a second partial sub-matrix in the plurality of sub-matrices, and the first check code is calculated with a third partial sub-matrix in the plurality of sub-matrices, to obtain second check data in the check data, including:

[0131] The transposed matrix of the voltage encoded data is calculated with a second partial sub-matrix in the plurality of sub-matrices, to obtain third calculation data;

[0132] The first check data is converted from digital to analog, to obtain a second voltage signal;

[0133] The transposed matrix of the second voltage signal is calculated with a third partial sub-matrix in the plurality of sub-matrices, to obtain fourth calculation data;

[0134] The third calculation data is converted from analog to digital, to obtain first signal data, and the fourth calculation data is converted from analog to digital, to obtain second signal data;

[0135] The first signal data and the second signal data are added, to obtain the second check data. Specifically, in combination with Figure 5 The LDPC encoding method includes the following implementation steps:

[0136] S501, input of to-be-encoded information;

[0137] S502, digital-to-analog conversion DAC of the to-be-encoded information, that is, conversion of the to-be-encoded information input as a digital signal into a voltage signal, to obtain voltage encoded data of the to-be-encoded information, which can be represented as S; optionally, the voltage encoded data can be stored in a memory-computing integrated array;

[0138] S503, calculation of the transposed matrix S T of the voltage encoded data S with a first sub-matrix (matrix A) in a first partial sub-matrix, to obtain first calculation data As T ;

[0139] S504, analog-to-digital conversion ADC and digital-to-analog conversion DAC of the first calculation data As T in sequence, to obtain a first voltage signal of the first calculation data; that is, conversion of the operation result of the first calculation data As T into the first voltage signal, and input to the next calculation;

[0140] S505, calculation of the first voltage signal in the memory-computing integrated array with the inverse matrix (B -1 ) of a second sub-matrix (matrix B) in the first partial sub-matrix, to obtain second calculation data, that is, completion of B-1 AS T the calculation process;

[0141] S506, analog-to-digital conversion ADC is performed on the second calculation data B -1 AS T to obtain the first check data p1';

[0142] S507, the transpose matrix S T of the voltage encoding data S is calculated with a second partial sub-matrix (matrix C) in the plurality of sub-matrices to obtain third calculation data; that is, Cs T operation is completed.

[0143] S508, analog-to-digital conversion ADC is performed on the third calculation data Cs T to obtain the first signal data.

[0144] S509, digital-to-analog conversion DAC is performed on the first check data p1' obtained in step S506 to obtain a second voltage signal, so that the first check data p1' is converted into an input voltage.

[0145] S510, the transpose matrix p1 ’T of the second voltage signal is calculated with a third partial sub-matrix (matrix D) in the plurality of sub-matrices to obtain fourth calculation data; that is, Dp1 ’T operation is completed.

[0146] S511, analog-to-digital conversion is performed on the fourth calculation data Dp1 ’T to obtain the second signal data.

[0147] S512, the first signal data obtained in step S508 and the second signal data obtained in step S511 are added to obtain the second check data p2' = Cs T + Dp1 ’T .

[0148] S513, parity judgment and binary parameter mapping are performed on the first check data p1' to obtain the first check code p1, and parity judgment and binary parameter mapping are performed on the second check data p2' to obtain the second check code p2.

[0149] In the parity judgment, each data bit of the check data is sequentially subjected to parity judgment, in the case that the data bit of the check data is even, it is determined that binary parameter mapping is performed on the check data, and the value of the corresponding bit of the check code after mapping is 0; in the case that the data bit of the check data is odd, it is determined that binary parameter mapping is performed on the check data, and the value of the corresponding bit of the check code after mapping is 1.

[0150] Specifically, the parity of the first check data p1' is judged, if one data bit is even, the corresponding mapping bit of the first check code p1 is 0; if one data bit is odd, the corresponding mapping bit of the first check code p1 is 1; for example, if the first check data p1' is [3, 2, 6, 5, 7], after parity judgment and binary parameter mapping, the first check code p1 obtained by mapping is [1, 0, 0, 1, 1]. In this way, after the parity judgment is completed, the first check code p1 is obtained.

[0151] Similarly, the parity of the second check data p2' is judged, if one data bit is even, the corresponding mapping bit of the second check code p2 is 0; if one data bit is odd, the corresponding mapping bit of the second check code p2 is 1. In this way, after the parity judgment is completed, the second check code p2 is obtained.

[0152] The first check code p1 and the second check code p2 are combined to form the corresponding check code, that is, the check code of the to-be-encoded information.

[0153] S514, obtaining the LDPC encoded data of the to-be-encoded information according to the to-be-encoded information and the check code.

[0154] Specifically, the to-be-encoded information is combined with the first check code p1 and the second check code p2 to obtain the LDPC encoded data.

[0155] Taking the to-be-encoded information represented as S1 as an example, the combination of the first check code p1 and the second check code p2 can be represented as c=[s1 p1 p2], and the LDPC encoded data c of the to-be-encoded information after LDPC encoding is obtained.

[0156] By using the LDPC encoding method described in the embodiment of the present application, part of the calculation process in the calculation of the first check code and the second check code can be performed in parallel, which can improve the calculation efficiency. In addition, by using the method, only parity judgment needs to be performed when binary parameter mapping is performed on the check data, and parity judgment does not need to be performed at each step, which can further improve the encoding efficiency.

[0157] An embodiment of the present application also provides a low-density parity check code LDPC encoding device, as shown in the figure, comprising: Figure 6

[0158] The data processing unit 610 is configured to perform digital-to-analog conversion on the to-be-encoded information to obtain voltage encoded data of the to-be-encoded information.

[0159] The calculation unit 620 is configured to perform calculation on the voltage encoded data by using a storage-computation integrated array according to an LDPC check matrix to obtain check data for encoding the to-be-encoded information.​

[0160] a mapping unit 630, configured to perform binary parameter mapping on the check data to obtain check codes corresponding to the to-be-encoded information;

[0161] a processing unit 640, configured to generate LDPC encoded data of the to-be-encoded information according to the to-be-encoded information and the check codes.

[0162] Optionally, the LDPC encoding apparatus, wherein the computing unit 620 performs computation on the voltage encoded data and the LDPC check matrix by using a memory-compute integrated array to obtain check data for encoding the to-be-encoded information, including:

[0163] inputting a transposed matrix of the voltage encoded data into the memory-compute integrated array in which a plurality of sub-matrices are deployed, and performing computation on the plurality of sub-matrices to obtain the check data;

[0164] wherein the plurality of sub-matrices are generated by block processing of the LDPC check matrix.

[0165] Optionally, the LDPC encoding apparatus, wherein the computing unit 620 inputs the transposed matrix of the voltage encoded data into the memory-compute integrated array in which a plurality of sub-matrices are deployed, and performs computation on the plurality of sub-matrices to obtain the check data, including:

[0166] inputting the transposed matrix of the voltage encoded data into the memory-compute integrated array, and performing computation on a first part of the plurality of sub-matrices to obtain first check data in the check data;

[0167] performing computation on a second part of the plurality of sub-matrices on the transposed matrix of the voltage encoded data, and performing computation on a third part of the plurality of sub-matrices on the first check data to obtain second check data in the check data;

[0168] wherein the first part of the sub-matrices is located in a first block row, the second part of the sub-matrices and the third part of the sub-matrices are located in a second block row, and the second part of the sub-matrices and the third part of the sub-matrices are arranged from left to right in the second block row.

[0169] Optionally, the LDPC encoding apparatus, wherein the computing unit 620 inputs the transposed matrix of the voltage encoded data into the memory-compute integrated array, and performs computation on a first part of the plurality of sub-matrices to obtain first check data in the check data, including:

[0170] The transposed matrix of the voltage encoded data is input into the storage-computing integrated array, and a first sub-matrix in the first part of sub-matrices is calculated to obtain first calculation data;

[0171] The first calculation data is sequentially analog-digital converted and digital-analog converted to obtain a first voltage signal of the first calculation data;

[0172] The first voltage signal is calculated with an inverse matrix of a second sub-matrix in the first part of sub-matrices in the storage-computing integrated array to obtain second calculation data;

[0173] The second calculation data is analog-digital converted to obtain the first check data;

[0174] The first sub-matrix and the second sub-matrix are arranged from left to right in the first block row.

[0175] Optionally, the LDPC encoding device, wherein the calculation unit 620 calculates the transposed matrix of the voltage encoded data with a second part of sub-matrices in the plurality of sub-matrices, and calculates the first check data with a third part of sub-matrices in the plurality of sub-matrices to obtain second check data in the check data, comprising:

[0176] The transposed matrix of the voltage encoded data is input into the storage-computing integrated array, and a first sub-matrix in the first part of sub-matrices is calculated to obtain first calculation data;

[0177] The first calculation data is sequentially analog-digital converted and digital-analog converted to obtain a first voltage signal of the first calculation data;

[0178] The first calculation data is sequentially analog-digital converted and digital-analog converted to obtain a first voltage signal of the first calculation data;

[0179] The first calculation data is sequentially analog-digital converted and digital-analog converted to obtain a first voltage signal of the first calculation data;

[0180] The first calculation data is sequentially analog-digital converted and digital-analog converted to obtain a first voltage signal of the first calculation data;

[0181] Optionally, the LDPC encoding device, wherein the calculation unit 620 calculates the transposed matrix of the voltage encoded data with a second part of sub-matrices in the plurality of sub-matrices, and calculates the first check data with a third part of sub-matrices in the plurality of sub-matrices to obtain second check data in the check data, comprising:

[0182] The parity of each data bit of the check data is determined in sequence, and in the case that the data bit of the check data is even, it is determined to perform binary parameter mapping on the check data, and the value of the corresponding bit of the check code after mapping is 0; in the case that the data bit of the check data is odd, it is determined to perform binary parameter mapping on the check data, and the value of the corresponding bit of the check code after mapping is 1.

[0183] Optionally, the LDPC encoding apparatus, wherein the calculation unit 620 is further configured to:

[0184] The LDPC check matrix is divided into blocks to generate a plurality of sub-matrices;

[0185] Each of the sub-matrices is respectively deployed in a sub-array region of the memory-computing integrated array.

[0186] The number of rows and columns in the sub-array region matches the number of rows and columns of the deployed sub-matrices.

[0187] Optionally, the LDPC encoding apparatus, wherein the calculation unit 620 respectively deploys each of the sub-matrices in a sub-array region of the memory-computing integrated array, including:

[0188] The first sub-matrix of the first part of the sub-matrices is deployed in a first sub-array region of the memory-computing integrated array, and the inverse matrix of the second sub-matrix of the first part of the sub-matrices is deployed in a second sub-array region of the memory-computing integrated array.

[0189] The second part of the sub-matrices is deployed in a third sub-array region of the memory-computing integrated array, and the third part of the sub-matrices is deployed in a fourth sub-array region of the memory-computing integrated array.

[0190] The first part of the sub-matrices is located in a first block row, the second part of the sub-matrices and the third part of the sub-matrices are located in a second block row, and the second part of the sub-matrices and the third part of the sub-matrices are arranged from left to right in the second block row; the first sub-matrix and the second sub-matrix are arranged from left to right in the first block row.

[0191] Optionally, the LDPC encoding apparatus, wherein the first sub-array region and the second sub-array region are arranged from left to right in the memory-computing integrated array, the third sub-array region and the fourth sub-array region are arranged from left to right in the memory-computing integrated array, and the first sub-array region and the third sub-array region are arranged from top to bottom in the memory-computing integrated array.

[0192] Optionally, the LDPC encoding apparatus, wherein the mapping unit 630 performs binary parameter mapping on the check data to obtain corresponding check codes, including:

[0193] performing binary parameter mapping on the first check data in the check data to obtain a corresponding first check code;

[0194] performing binary parameter mapping on the second check data in the check data to obtain a corresponding second check code.

[0195] Optionally, the LDPC encoding apparatus, wherein the processing unit 640 obtains LDPC encoding data of the information to be encoded according to the information to be encoded and the check codes, including:

[0196] combining the information to be encoded with the first check code and the second check code to obtain the LDPC encoding data.

[0197] Another embodiment of the present application further provides a network device, comprising a processor, a memory and a program stored in the memory and executable on the processor, and the program is executed by the processor to implement the LDPC encoding method according to any one of the above.

[0198] Specifically, the network device is a device for implementing the above LDPC encoding method, and the LDPC encoding method implemented by the processor when executed can refer to the above detailed description, which will not be repeated here.

[0199] In addition, a readable storage medium is further provided in the embodiment of the present application, and the readable storage medium stores a computer program, wherein the program is executed by the processor to implement the steps in the LDPC encoding method according to any one of the above.

[0200] In the several embodiments provided in the present application, it should be understood that the disclosed method and device can be implemented in other ways. For example, the device embodiments described above are only schematic. The division of the units is only a logical function division. There can be another division manner in actual implementation. For example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections between the units can be indirect couplings or communication connections through some interfaces, devices or units, and can be electrical, mechanical or in other forms.

[0201] In addition, each function unit in each embodiment of the present application can be integrated in one processing unit, or each unit can be physically included separately, or two or more units can be integrated in one unit. The integrated unit can be realized in the form of hardware or in the form of hardware plus software function unit.

[0202] The integrated unit realized in the form of software function unit can be stored in a computer readable storage medium. The software function unit is stored in a storage medium, and includes a plurality of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute part of steps of the transceiving method according to each embodiment of the present application. The aforementioned storage medium includes a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various storage medium capable of storing program codes.

[0203] The above is the preferred embodiment of the present application, and it should be noted that for those skilled in the art, without departing from the principles of the present application, a number of improvements and refinements can be made, and these improvements and refinements should also be considered as the protection scope of the present application.

Claims

1. A low-density parity-check (LDPC) coding method, characterized in that, include: The information to be encoded is converted from digital to analog to obtain the voltage encoded data of the information to be encoded; Based on the LDPC check matrix and the voltage encoding data, a storage-computing array is used to perform calculations to obtain check data for encoding the information to be encoded. Binary parameter mapping is performed on the verification data to obtain the verification code corresponding to the information to be encoded; Based on the information to be encoded and the check code, generate LDPC encoded data of the information to be encoded; Specifically, based on the LDPC check matrix and the voltage encoding data, a memory-based computing array is used to calculate and obtain check data for encoding the information to be encoded, including: The transpose matrix of the voltage-encoded data is input into the in-memory computing array which is deployed with multiple sub-matrices, and is calculated with the first part of the multiple sub-matrices to obtain the first verification data in the verification data; wherein, the multiple sub-matrices are generated by dividing the LDPC verification matrix into blocks; The transpose matrix of the voltage encoded data is calculated with the second part of the submatrix among the plurality of submatrices, and the first verification data is calculated with the third part of the submatrix among the plurality of submatrices to obtain the second verification data in the verification data; The first submatrix is ​​located in the first block row, the second submatrix and the third submatrix are located in the second block row, and the second submatrix and the third submatrix are arranged from left to right in the second block row.

2. The LDPC encoding method according to claim 1, characterized in that, The transpose matrix of the voltage-encoded data is input into the in-memory computing array and calculated with the first part of the sub-matrix among the multiple sub-matrices to obtain the first verification data in the verification data, including: The transpose matrix of the voltage encoded data is input into the in-memory computing array and calculated with the first submatrix in the first part of the submatrix to obtain the first calculated data; The first calculated data is sequentially converted from analog to digital and from digital to analog to obtain the first voltage signal of the first calculated data; The first voltage signal is used in the in-memory computing array to perform calculations with the inverse matrix of the second submatrix in the first submatrix to obtain second calculation data; The first verification data is obtained by performing an analog-to-digital conversion on the second calculated data; The first submatrix and the second submatrix are arranged from left to right in the first block row.

3. The LDPC encoding method according to claim 1, characterized in that, The process involves calculating the second verification data from the verification data by combining the transpose matrix of the voltage-encoded data with the second sub-matrix of the plurality of sub-matrices, and calculating the first verification data with the third sub-matrix of the plurality of sub-matrices, including: The transpose matrix of the voltage-encoded data is calculated with the second part of the submatrix among the multiple submatrices to obtain the third calculated data; The first verification data is converted from digital to analog to obtain a second voltage signal; The transpose matrix of the second voltage signal is calculated together with the third part of the submatrix among the plurality of submatrices to obtain the fourth calculation data; The third calculated data is subjected to analog-to-digital conversion to obtain the first signal data, and the fourth calculated data is subjected to analog-to-digital conversion to obtain the second signal data; The first signal data is added to the second signal data to obtain the second verification data.

4. The LDPC encoding method according to claim 1, characterized in that, The verification data is mapped to binary parameters to obtain the check code corresponding to the information to be encoded, including: Each data bit of the verification data is sequentially checked for parity. If the number of data bits in the verification data is even, binary parameter mapping is performed on the verification data, and the corresponding bit of the mapped verification code is set to 0. If the number of data bits in the verification data is odd, binary parameter mapping is performed on the verification data, and the corresponding bit of the mapped verification code is set to 1.

5. The LDPC encoding method according to claim 1, characterized in that, The method further includes: The LDPC parity check matrix is ​​divided into blocks to generate multiple sub-matrices; Each of the sub-matrices is deployed in one of the sub-array regions of the in-memory computing array; The number of rows and columns in the subarray region matches the number of rows and columns in the deployed submatrix.

6. The LDPC encoding method according to claim 5, characterized in that, Each of the aforementioned sub-matrices is deployed in one of the sub-array regions of the in-memory computing array, including: The first submatrix of the first part of the multiple submatrixes is deployed in the first subarray region of the in-memory computing array, and the inverse matrix of the second submatrix of the first part of the multiple submatrixes is deployed in the second subarray region of the in-memory computing array. The second part of the multiple sub-matrices is deployed in the third sub-array region of the in-memory computing array, and the third part of the multiple sub-matrices is deployed in the fourth sub-array region of the in-memory computing array; Wherein, the first sub-matrix is ​​located in the first block row, the second sub-matrix and the third sub-matrix are located in the second block row, and the second sub-matrix and the third sub-matrix are arranged from left to right in the second block row; the first sub-matrix and the second sub-matrix are arranged from left to right in the first block row.

7. The LDPC encoding method according to claim 6, characterized in that, The first subarray region and the second subarray region are arranged from left to right in the in-memory computing array, the third subarray region and the fourth subarray region are arranged from left to right in the in-memory computing array, and the first subarray region and the third subarray region are arranged from top to bottom in the in-memory computing array.

8. The LDPC encoding method according to claim 1, characterized in that, The verification data is mapped to binary parameters to obtain the corresponding verification code, including: The first verification data in the verification data is mapped to binary parameters to obtain the corresponding first verification code; The second verification data in the verification data is mapped using binary parameters to obtain the corresponding second verification code.

9. The LDPC encoding method according to claim 8, characterized in that, Based on the information to be encoded and the checksum, LDPC encoded data of the information to be encoded is obtained, including: The information to be encoded is combined with the first check code and the second check code to obtain the LDPC encoded data.

10. A low-density parity-check (LDPC) encoding device, characterized in that, include: The data processing unit is used to perform digital-to-analog conversion on the information to be encoded to obtain the voltage-encoded data of the information to be encoded. The calculation unit is used to perform calculations using an in-memory computing array based on the LDPC check matrix and the voltage encoding data to obtain check data for encoding the information to be encoded. A mapping unit is used to perform binary parameter mapping on the verification data to obtain the verification code corresponding to the information to be encoded. The processing unit is configured to generate LDPC encoded data of the information to be encoded based on the information to be encoded and the check code. The calculation unit is used to perform calculations using an in-memory computing array based on the LDPC check matrix and the voltage encoding data to obtain check data for encoding the information to be encoded, including: The transpose matrix of the voltage-encoded data is input into the in-memory computing array which is deployed with multiple sub-matrices, and is calculated with the first part of the multiple sub-matrices to obtain the first verification data in the verification data; wherein, the multiple sub-matrices are generated by dividing the LDPC verification matrix into blocks; The transpose matrix of the voltage encoded data is calculated with the second part of the submatrix among the plurality of submatrices, and the first verification data is calculated with the third part of the submatrix among the plurality of submatrices to obtain the second verification data in the verification data; The first submatrix is ​​located in the first block row, the second submatrix and the third submatrix are located in the second block row, and the second submatrix and the third submatrix are arranged from left to right in the second block row.

11. A network device, characterized in that, include: A processor, a memory, and a program stored in the memory and executable on the processor, wherein the program, when executed by the processor, implements the LDPC encoding method as described in any one of claims 1 to 9.

12. A readable storage medium, characterized in that, The readable storage medium stores a program that, when executed by a processor, implements the steps of the LDPC encoding method as described in any one of claims 1 to 9.

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