Device fabrication method, storage device, and semiconductor device

Abstract

The present disclosure relates to a device manufacturing method, a memory device, and a semiconductor device. The device manufacturing method includes: providing a substrate; and sequentially forming a lower electrode material layer, a storage material layer, an upper electrode material layer, and an isolation material portion on the substrate from bottom to top to generate a first trench assembly and a second trench assembly, wherein the first trench assembly is configured to form a memory device, the second trench assembly is configured to form an isolation component, and the first trench assembly and the second trench assembly are electrically isolated from each other.

Description

Technical Field

[0001] The present disclosure relates to the field of storage technologies, and more particularly, to a device manufacturing method, a storage device, and a semiconductor device. Background Art

[0002] A storage device is a device with a memory function, whose electrical state can be controlled to record corresponding data. With the rapid development of information technology, storage devices are increasingly widely used, and the requirements for the performance of the storage devices themselves and other electronic devices that may exist and are related to the storage devices are also getting higher and higher. Therefore, there is a need to improve the existing device manufacturing technologies. Summary of the Invention

[0003] One object of the present disclosure is to provide a device manufacturing method, a storage device, and a semiconductor device.

[0004] According to a first aspect of the present disclosure, there is provided a device manufacturing method, including:

[0005] providing a substrate, wherein the substrate includes an active region, and a first trench and a second trench are formed in the active region; and

[0006] forming a lower electrode material layer, a storage material layer, an upper electrode material layer, and an isolation material portion on the substrate in sequence from bottom to top to generate a first trench assembly and a second trench assembly;

[0007] wherein the first trench assembly is formed by the portions of the lower electrode material layer, the storage material layer, the upper electrode material layer, and the isolation material portion located in the first trench, and the first trench assembly is configured to form a storage device,

[0008] the second trench assembly is formed by the portions of the lower electrode material layer, the storage material layer, the upper electrode material layer, and the isolation material portion located in the second trench, and the second trench assembly is configured to form an isolation component,

[0009] the first trench assembly and the second trench assembly are electrically isolated from each other.

[0010] In some embodiments, forming a lower electrode material layer, a storage material layer, an upper electrode material layer, and an isolation material portion on the substrate in sequence from bottom to top to generate a first trench assembly and a second trench assembly includes:

[0011] forming a patterned lower electrode material layer on the substrate, wherein the lower electrode material layer includes a first lower electrode material portion covering the inner wall of the first trench and a second lower electrode material portion covering the inner wall of the second trench, and the first lower electrode material portion and the second lower electrode material portion are disconnected from each other;

[0012] Deposit a continuous thin film of storage material, a continuous thin film of upper electrode material, and an isolation material in sequence;

[0013] Perform etching to remove at least a part of the isolation material, at least a part of the upper electrode material, and at least a part of the storage material outside the first trench and the second trench, so as to form a patterned storage material layer, an upper electrode material layer, and an isolation material portion. Among them, the storage material layer includes a first storage material portion located in the first trench and a second storage material portion located in the second trench, the upper electrode material layer includes a first upper electrode material portion located in the first trench and a second upper electrode material portion located in the second trench, and the isolation material portion includes a first isolation material portion filled in the first trench and a second isolation material portion filled in the second trench.

[0014] In some embodiments, forming a patterned lower electrode material layer on the substrate includes:

[0015] Deposit a continuous thin film of lower electrode material on the substrate;

[0016] Deposit an anti-etching agent layer, wherein at least a part of the anti-etching agent layer is filled in the first trench and the second trench;

[0017] Perform etching to remove at least a part of the lower electrode material outside the first trench and the second trench, so as to form a patterned lower electrode material layer; and

[0018] Remove the remaining anti-etching agent layer.

[0019] In some embodiments, the anti-etching agent layer includes a bottom anti-reflection layer.

[0020] In some embodiments, deposit at least one of the lower electrode material, the storage material, and the upper electrode material by atomic layer deposition.

[0021] In some embodiments, depositing the isolation material includes:

[0022] Deposit the isolation material by high density plasma chemical vapor deposition, wherein the isolation material covers the entire upper surface of the upper electrode material; and

[0023] Perform chemical mechanical polishing on the upper surface of the deposited isolation material.

[0024] In some embodiments, twice the total thickness of the lower electrode material layer, the storage material layer, and the upper electrode material layer is less than the minimum width of the first trench, and twice the total thickness of the lower electrode material layer, the storage material layer, and the upper electrode material layer is less than the minimum width of the second trench; and / or

[0025] The included angle between at least one side surface and the bottom surface of the first trench is greater than or equal to 90°, and the included angle between at least one side surface and the bottom surface of the second trench is greater than or equal to 90°.

[0026] In some embodiments, the depth of at least one of the first trench and the second trench is 300 - 400 nm or 400 - 500 nm; and / or

[0027] The width of at least one of the first trench and the second trench is 130 - 190 nm or 190 - 250 nm.

[0028] In some embodiments, at least one of the lower electrode material layer and the upper electrode material layer is formed of at least one of titanium, titanium nitride, titanium silicon nitride, titanium aluminum nitride, titanium carbonitride, tantalum nitride, tantalum silicon nitride, tantalum aluminum nitride, tungsten nitride, tungsten silicide, doped polysilicon, and transparent conductive oxide; and / or

[0029] The storage material layer is formed of at least one of phase change storage material, ferroelectric material, zirconium oxide, hafnium oxide, titanium oxide, aluminum oxide, nickel oxide, and iron oxide.

[0030] In some embodiments, after generating the first trench component and the second trench component, the device manufacturing method further includes:

[0031] Forming other electronic devices different from the storage device on the substrate, wherein at least two adjacent devices are respectively disposed on both sides of the second trench component serving as the isolation component.

[0032] In some embodiments, after generating the first trench component and the second trench component, the device manufacturing method further includes:

[0033] Forming a dielectric protection layer above the device, a conductive connection member inside the dielectric protection layer, and a wiring layer above the dielectric protection layer, wherein the conductive connection member includes a first conductive connection member and a second conductive connection member respectively electrically connected to the portions of the lower electrode material layer and the upper electrode material layer located in the first trench, and the wiring layer includes a first wiring layer and a second wiring layer respectively electrically connected to the first conductive connection member and the second conductive connection member.

[0034] In some embodiments, forming the first conductive connection member electrically connected to the portion of the lower electrode material layer located in the first trench includes:

[0035] Forming a contact portion in the portion of the substrate adjacent to the first trench component, wherein the contact portion is electrically connected to the first lower electrode material portion of the lower electrode material layer located in the first trench, and the contact portion is formed of metal silicide; and

[0036] A first conductive connection member is formed above the contact portion, wherein the first conductive connection member is configured to electrically connect the contact portion to a first wiring layer.

[0037] In some embodiments, forming a second conductive connection member electrically connected to a portion of the upper electrode material layer located in the first trench includes:

[0038] Etching at least a part of a first isolation material portion filled in the first trench of the isolation material portion until a part of the upper electrode material layer is exposed; and

[0039] Forming a second conductive connection member above the exposed portion of the upper electrode material layer, wherein the second conductive connection member is configured to electrically connect the upper electrode material layer to a second wiring layer.

[0040] In some embodiments, when the upper electrode material layer includes an upper electrode lead portion located outside the first trench and electrically connected to a portion of the upper electrode material layer located in the first trench, forming a second conductive connection member electrically connected to a portion of the upper electrode material layer located in the first trench includes:

[0041] Forming a second conductive connection member above the upper electrode lead portion, wherein the second conductive connection member is configured to electrically connect the upper electrode material layer to a second wiring layer.

[0042] According to a second aspect of the present disclosure, there is provided a storage device including a first lower electrode material portion, a first storage material portion, and a first upper electrode material portion stacked in sequence from bottom to top along an inner wall of a first trench in a substrate.

[0043] In some embodiments, the storage device is fabricated by the device fabrication method as described above.

[0044] According to a third aspect of the present disclosure, there is provided a semiconductor device including one or more storage devices as described above.

[0045] In some embodiments, the semiconductor device further includes other electronic devices different from the storage device.

[0046] Other features and advantages of the present disclosure will become clearer through the following detailed description of exemplary embodiments of the present disclosure with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] The drawings forming a part of the specification depict embodiments of the present disclosure and, together with the description, are used to explain the principles of the present disclosure.

[0048] With reference to the accompanying drawings, the present disclosure can be more clearly understood from the following detailed description, where:

[0049] Figure 1 A schematic cross-sectional structure diagram of a storage device is shown;

[0050] Figure 2 A photo of the cross-sectional structure of a storage device is shown;

[0051] Figure 3 A schematic flowchart of a device manufacturing method according to an exemplary embodiment of the present disclosure is shown;

[0052] Figures 4(a) to 4(j) A schematic diagram of the device manufacturing process according to a specific embodiment of the present disclosure is shown.

[0053] Note that in the following described embodiments, sometimes the same reference numerals are used commonly between different drawings to represent the same part or parts having the same function, and the repeated description thereof is omitted. In this specification, similar reference numerals and letters are used to represent similar items. Therefore, once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0054] For ease of understanding, the positions, sizes, ranges, etc. of the various structures shown in the drawings and the like sometimes do not represent the actual positions, sizes, ranges, etc. Therefore, the disclosed invention is not limited to the positions, sizes, ranges, etc. disclosed in the drawings and the like. In addition, the drawings do not have to be drawn to scale, and some features may be enlarged to show the details of specific components. Detailed Embodiments

[0055] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that unless otherwise specifically stated, the relative arrangements of components and steps, numerical expressions, and values set forth in these embodiments do not limit the scope of the present disclosure.

[0056] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way a limitation on the present disclosure or its application or use. Those skilled in the art will understand that they merely illustrate exemplary ways in which the present disclosure can be implemented, rather than exhaustive ways.

[0057] Techniques, methods, and devices known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, the techniques, methods, and devices should be considered as part of the specification.

[0058] Under normal circumstances, the device performance of a memory device is positively correlated or proportional to the effective area determined by its two electrodes and the memory material therebetween. In other words, the device performance of a memory device is related to the area of the overlapping region of the two electrodes and the memory material therebetween. The larger the area of the overlapping region, that is, the larger the effective area of the memory device, the larger its polarization area. Under the same voltage, more polarization charges can be stored, thus making the sensitivity, stability, and reliability of the memory device better, and helping to extend the device life. To increase the effective area of the memory device, as Figure 1 and Figure 2 shown, the memory device 100' can be set to have a three-dimensional (3D) structure. The memory device 100' may include a lower electrode material layer 120', a memory material layer 130', and an upper electrode material layer 140' that are sequentially stacked along the wall of the trench, thereby improving the storage density and achieving better cell performance and reliability under the same cell area.

[0059] However, this process for forming a 3D structure is generally carried out after the processes for forming the front-end device 200' (other electronic devices different from the memory device, such as logic devices, etc.) and the conductive connection member 410' are completed. Therefore, some problems may be brought. For example, during the process of forming the memory device 100', it may be necessary to heat it to activate the device, and the associated thermal budget may have an adverse impact on the already formed front-end device 200'. In addition, as Figure 1 and Figure 2 shown, in order to lead out the lower electrode material layer 120' of the memory device 100' for electrical connection with other electronic devices or external circuits, etc., the memory device 100' is generally disposed above the conductive connection member 410'. However, due to the difference in hardness between the conductive connection member 410' and its adjacent dielectric material 300', during the chemical mechanical polishing (CMP) process, over-polishing of the dielectric material 300' may occur, causing the conductive connection member 410' to protrude to a certain extent relative to its adjacent dielectric material 300' (clearly shown in region A in the photo of Figure 2 ), that is, the substrate for forming the memory device 100' may be uneven, which may further lead to step differences, or even discontinuities or breaks, in the corresponding film layers during the process of forming the memory device 100', resulting in a decrease in the performance of the memory device 100' or even the failure of the memory device 100'.

[0060] To solve the above problems, the present disclosure proposes a device manufacturing method. In an exemplary embodiment of the present disclosure, as Figure 3 and shown in FIG. 4(a), the device manufacturing method may include:

[0061] Step S910, providing a substrate 110.

[0062] Among them, the substrate 110 includes an active region 113. In a specific example, the substrate 110 can be based on a silicon material, and the active region 113 can be formed by doping silicon. However, it can be understood that a substrate 110 made of other materials can also be used, and the active region 113 can be formed accordingly, which is not limited herein. A first trench 111 and a second trench 112 can be formed in the active region 113. It can be understood that according to needs, more trenches can also be formed in the active region 113, which is not limited herein. Here, only the first trench 111 and the second trench 112 are taken as examples for illustration.

[0063] In some embodiments, the trenches in the active region can be formed based on photolithography and etching processes. Specifically, a patterned anti-etching agent layer (photoresist layer) can be formed on the substrate or the active region, and then an anti-etching material layer (such as silicon nitride, etc.) can be formed on the region outside the trenches on the substrate or the active region through deposition and lift-off processes. Then, dry etching or wet etching can be used to etch the exposed part of the substrate or the active region that is not covered by the anti-etching material layer to remove the substrate or the active region material in the corresponding region, thereby forming the trenches. Finally, the anti-etching material layer can be selectively removed or retained according to needs (in the case of retaining the anti-etching material layer, it can exist as a part of the substrate) to form the structure shown in FIG. 4(a).

[0064] Furthermore, as Figure 3 and Figures 4(b) to 4(g) shown, the device manufacturing method may further include:

[0065] Step S920, forming a lower electrode material layer 120, a storage material layer 130, an upper electrode material layer 140, and an isolation material part 150 on the substrate 110 in sequence from bottom to top to generate a first trench assembly 101 and a second trench assembly 102.

[0066] Among them, the first trench assembly 101 can be formed by the parts of the lower electrode material layer 120, the storage material layer 130, the upper electrode material layer 140, and the isolation material part 150 located in the first trench 111, and the first trench assembly 101 can be configured to form a storage device. Specifically, the parts of the lower electrode material layer 120, the storage material layer 130, and the upper electrode material layer 140 in the first trench assembly 101 can form a storage device and can be electrically connected to other electronic devices or external circuits through conductive connectors and the like as described later, so as to achieve the desired storage function.

[0067] In addition, the second trench component 102 may be formed by a portion of the lower electrode material layer 120, the storage material layer 130, the upper electrode material layer 140, and the isolation material portion 150 located in the second trench 112, and the second trench component 102 may be configured to form an isolation component. Specifically, at least a portion of the isolation material portion 150 in the second trench component 102 may be used to achieve electrical isolation between devices. In addition, in some embodiments, a portion of the storage material layer 130 in the second trench component 102 is also formed of an electrically insulating material, and thus can also help achieve electrical isolation between devices.

[0068] Here, in order to avoid mutual influence between the storage device and the isolation component, the first trench component 101 and the second trench component 102 may be electrically isolated from each other. For example, electrical isolation between the first trench component 101 and the second trench component 102 may be achieved by disconnecting a portion of the lower electrode material located between the first trench component 101 and the second trench component 102, or by disconnecting a portion of the upper electrode material located between the first trench component 101 and the second trench component 102, or by disconnecting both a portion of the lower electrode material and a portion of the upper electrode material located between the first trench component 101 and the second trench component 102, as will be described in detail later.

[0069] In a specific embodiment, as Figures 4(b) to 4(d) shown, a lower electrode material layer 120, a storage material layer 130, an upper electrode material layer 140, and an isolation material portion 150 are sequentially formed on the substrate 110 from bottom to top, so that the first trench component 101 and the second trench component 102 may include: forming a patterned lower electrode material layer 120 on the substrate 110. Among them, the lower electrode material layer 120 may include a first lower electrode material portion 121 covering the inner wall (including the bottom wall and the side wall) of the first trench 111 and a second lower electrode material portion 122 covering the inner wall (including the bottom wall and the side wall) of the second trench 112, and the first lower electrode material portion 121 and the second lower electrode material portion 122 are disconnected from each other. In some embodiments, the patterned lower electrode material layer 120 may only exist on the inner wall of the trench. Or, in other embodiments, the patterned lower electrode material layer 120 may not only cover the inner wall of the trench, but also extend to the upper surface of the region of the active region 113 adjacent to the trench for subsequent electrical connection and the like.

[0070] In a specific example, forming the patterned lower electrode material layer 120 on the substrate 110 may include: depositing a continuous film-like lower electrode material on the substrate 110 (as shown in FIG. 4(b)); depositing an anti-etchant layer 160 (as shown in FIG. 4(c)), wherein at least a part of the anti-etchant layer 160 fills in the first trench 111 and the second trench 112; performing etching to remove at least a part of the lower electrode material outside the first trench 111 and the second trench 112, thereby forming the patterned lower electrode material layer 120; and removing the remaining anti-etchant layer 160 (as shown in FIG. 4(d)).

[0071] In some embodiments, after depositing the anti-etchant layer 160, etching can be directly performed. This is because generally the difference in thickness between the part of the anti-etchant layer located in the trench and the part located outside the trench is large enough, so during the etching process, even if the anti-etchant and the lower electrode material in the area outside the trench have been completely removed, there is still enough anti-etchant remaining in the trench to protect the lower electrode material in the trench. Alternatively, in some other embodiments, as needed, after depositing the anti-etchant layer 160, at least a part of the anti-etchant above the lower electrode material outside the trench can also be removed based on a photolithography process, and then etching is performed to form the desired patterned lower electrode material layer 120. Or, in some other embodiments, similar to the process of forming trenches in the active region as described above, a corresponding anti-etching material layer can also be formed as needed to further increase the etching ratio to form the desired patterned lower electrode material layer 120.

[0072] In some embodiments, the anti-etchant layer 160 can be formed only by photoresist. Or, in some other embodiments, the anti-etchant layer 160 can be a bottom anti-reflection coating (BARC). BARC is formed by first coating an anti-reflection coating and then coating a photoresist layer, and its purpose is to reduce the amount of light reflected back from the substrate surface to the photoresist layer to reduce the standing wave effect and improve the photolithography effect.

[0073] Generally, the anti-etchant layer 160 can be formed of a polymer material with good fluidity, so the anti-etchant layer 160 can be deposited by spin coating or the like, such that a part of it fills in the first trench 111 and the second trench 112, and the other part is distributed on the upper surface of the lower electrode material outside the trench. Correspondingly, after the etching is completed, the remaining anti-etchant layer 160 can be removed by high temperature or solution dissolution. For example, most of the anti-etchant can be removed first by heating in an oxygen-containing environment, and then the remaining anti-etchant can be cleaned up by a wet process.

[0074] Furthermore, as Figures 4(e) to 4(g)As shown, a lower electrode material layer 120, a storage material layer 130, an upper electrode material layer 140, and an isolation material portion 150 are sequentially formed on a substrate 110 from bottom to top. To generate a first trench component 101 and a second trench component 102 may include: sequentially depositing a continuous film-like storage material, a continuous film-like upper electrode material, and an isolation material; and performing etching to remove at least a part of the isolation material, at least a part of the upper electrode material, and at least a part of the storage material located outside the first trench 111 and the second trench 112, so as to form a patterned storage material layer 130, an upper electrode material layer 140, and an isolation material portion 150. Among them, the storage material layer 130 may include a first storage material portion 131 located in the first trench 111 and a second storage material portion 132 located in the second trench 112. The upper electrode material layer 140 may include a first upper electrode material portion 141 located in the first trench 111 and a second upper electrode material portion 142 located in the second trench 112. And the isolation material portion 150 may include a first isolation material portion 151 filled in the first trench 111 and a second isolation material portion 152 filled in the second trench 112.

[0075] In some embodiments, the storage material layer 130 may be formed of a phase change storage material. Accordingly, the storage device is a phase change memory (PCM). Here, as a non-volatile storage device, the phase change memory utilizes the conductivity difference exhibited when the material transforms between the crystalline state and the amorphous state to store data. It has excellent characteristics such as non-loss of data when powered off, low power consumption, high read / write speed, high integration, etc., and is compatible with complementary metal oxide semiconductor (CMOS) processes. It is expected to replace current mainstream products such as static random access memory (SRAM), dynamic random access memory (DRAM), and flash memory and become the future commercial mainstream product. Further, in some embodiments, the storage material layer 130 may be formed of a ferroelectric material. Ferroelectric materials have ferroelectricity, which means that spontaneous polarization occurs in the material within a certain temperature range, and when the temperature is higher than a certain critical value, the spontaneous polarization disappears. Therefore, data storage can be achieved by utilizing this phase change of ferroelectric materials. In some specific examples, at least one of zirconium oxide, hafnium oxide, titanium oxide, aluminum oxide, nickel oxide, and iron oxide may be used as the material of the storage material layer 130.

[0076] In addition, in some embodiments, the storage material layer 130 can be formed by atomic layer deposition (ALD). The storage material layer 130 formed in this way can conformally grow on the substrate 110 on which the lower electrode material layer 120 has been formed, and form good contact with the underlying lower electrode material layer 120, which can help improve the performance of the storage device and avoid process contamination, etc.

[0077] In some embodiments, the lower electrode material layer 120 and the upper electrode material layer 140 can be formed of the same electrode material. Alternatively, in some other embodiments, the lower electrode material layer 120 and the upper electrode material layer 140 can also be formed of different electrode materials. Among them, the electrode material is a conductive material, such as a conductive metal or a conductive compound, etc. In a specific example, at least one of the lower electrode material layer 120 and the upper electrode material layer 140 can be formed of at least one of titanium, titanium nitride, titanium silicon nitride, titanium aluminum nitride, titanium carbonitride, tantalum nitride, tantalum silicon nitride, tantalum aluminum nitride, tungsten nitride, tungsten silicide, doped polysilicon, and transparent conductive oxide. For example, the titanium nitride material has a certain adhesiveness, which helps to form a conductive film with higher quality, thereby improving the device performance.

[0078] In addition, in some embodiments, at least one of the lower electrode material and the upper electrode material can be deposited by ALD to help improve the performance of the storage device and avoid process contamination, etc. Alternatively, in some other embodiments, at least one of the lower electrode material and the upper electrode material can also be deposited by physical vapor deposition (PVD) to effectively increase the deposition rate and improve the device fabrication efficiency, etc.

[0079] In some embodiments, as shown in FIGS. 4(f) and 4(g), depositing the isolation material can include: depositing the isolation material by high density plasma chemical vapor deposition (HDP CVD); and chemically mechanically polishing the upper surface of the deposited isolation material to form an isolation material having a flat upper surface. In some specific examples, the isolation material can cover the entire upper surface of the upper electrode material. Alternatively, in some other specific examples, the isolation material can exactly fill the trench and be substantially flush with the upper surface of the upper electrode material. In both cases, the upper surface can be further flattened by the CMP process as described above to facilitate subsequent processes. In some specific examples, the isolation material can be formed of an electrically insulating oxide, nitride, oxynitride, etc., which is not limited herein.

[0080] In some embodiments, the isolation material, the upper electrode material, and the storage material can be etched in the same process operation to form the structure shown in FIG. 4(g). Considering that the etching stops when reaching the substrate 110 and the differences in etching rates between different materials, in a specific example, the first trench assembly 101 and the second trench assembly 102 may protrude slightly relative to the upper surface of the substrate 110, as presented in FIG. 4(g). Additionally, in some embodiments, the portion of the upper electrode material located outside the first trench 111 and the second trench 112 can be completely removed by etching, as shown in FIG. 4(g), that is, the upper electrode material layer 140 only includes the first upper electrode material portion 141 and the second upper electrode material portion 142. Alternatively, in some other embodiments, at least a part of the upper electrode material located outside the first trench 111 and connected to the first upper electrode material portion 141 can also be retained for subsequent electrical connection of the storage device to other electronic devices or external circuits, as will be described in detail later.

[0081] According to the above description, the first lower electrode material portion 121 located in the first trench 111 and the second lower electrode material portion 122 located in the second trench 112 can be formed synchronously, the first storage material portion 131 located in the first trench 111 and the second storage material portion 132 located in the second trench 112 can be formed synchronously, the first upper electrode material portion 141 located in the first trench 111 and the second upper electrode material portion 142 located in the second trench 112 can be formed synchronously, and the first isolation material portion 151 filled in the first trench 111 and the second isolation material portion 152 filled in the second trench 112 can be formed synchronously. Correspondingly, the first trench assembly 101 that can be used to form the storage device and the second trench assembly 102 that can be used to form the isolation component can be formed synchronously, that is, the storage device in the present application can be formed synchronously with the isolation component, rather than being separately prepared before or after forming the isolation component.

[0082] In some embodiments, to ensure the performance of the memory device, twice the total thickness of the lower electrode material layer 120, the memory material layer 130, and the upper electrode material layer 140 can be less than the minimum width of the first trench 111, and twice the total thickness of the lower electrode material layer 120, the memory material layer 130, and the upper electrode material layer 140 can be less than the minimum width of the second trench 112. In this way, on the one hand, it avoids the undesired connection or short circuit of the memory material or the electrode material deposited on the opposite sidewalls of the trench, and on the other hand, the wider trench also helps the lower electrode material layer 120, the memory material layer 130, and the upper electrode material layer 140 to conformally grow on the inner wall of the trench. For example, in some specific examples, the thickness of at least one of the lower electrode material layer 120 and the upper electrode material layer 140 can be on the order of several nanometers to several tens of nanometers (e.g., 10 - 20 nm or 20 - 40 nm), and the thickness of the memory material layer 130 can also be on the order of several nanometers to several tens of nanometers (e.g., 5 - 10 nm or 10 - 20 nm). In addition, to ensure the electrical isolation effect of the isolation component, the depth and width of the trench should be large enough. For example, in some specific examples, the depth of at least one of the first trench 111 and the second trench 112 can be 300 - 400 nm or 400 - 500 nm. In addition, the width of at least one of the first trench 111 and the second trench 112 can be 130 - 190 nm or 190 - 250 nm. It can be understood that, according to needs, memory devices and trenches with other dimensions can also be set, which are not limited herein.

[0083] In addition, as shown in FIG. 4(a), the angle α between at least one side surface and the bottom surface of the first trench 111 can be greater than or equal to 90°, and similarly, the angle α between at least one side surface and the bottom surface of the second trench 112 can be greater than or equal to 90°. When the angle α is equal to 90°, the planar area occupied by the memory device can be reduced while maintaining the quality of the subsequent film deposition as much as possible. When the angle α is greater than 90°, it can help the film layer to grow better into the trench, form a more reliable connection between the film layers deposited on the inner wall of the trench, and also help to avoid generating voids between the upper film layer and the lower film layer when performing the deposition of the subsequent film layer by methods such as physical vapor deposition, so that one or more film layers can be formed with high quality.

[0084] Further, as shown in FIG. 4(h), after the first trench component 101 and the second trench component 102 are generated, the device manufacturing method may further include: forming other electronic devices 200 different from the memory device on the substrate 110. Among the formed multiple devices, at least two adjacent devices may be respectively disposed on both sides of the second trench component 102 serving as an isolation component to achieve electrical isolation between the devices. In some embodiments, the other electronic devices may include logic devices, etc., which may cooperate with the memory device to achieve a desired function. In a specific example, after the logic device 100 shown in FIG. 4(g) is formed, CMOS logic devices 200, etc. may be fabricated based on CMOS processes, etc., as illustrated in FIG. 4(h).

[0085] In addition, in some embodiments, as shown in FIGS. 4(i) and 4(j), after the first trench component 101 and the second trench component 102 are generated, the device manufacturing method may further include: forming a dielectric protection layer 300 above the device, a conductive connection member inside the dielectric protection layer 300, and a wiring layer above the dielectric protection layer 300. The devices here may include all the devices formed on the substrate 110, including the memory device 100 and other possible electronic devices 200. The dielectric protection layer 300 may be formed of a dielectric material the same as or different from the isolation material to prevent oxygen, water, dust, etc. in the air from having an adverse effect on the devices, thereby extending the service life of the devices. In addition, the dielectric protection layer 300 may also serve as a carrier for components such as the subsequently formed conductive connection member and wiring layer. For example, the dielectric protection layer 300 may be formed of insulating oxides, insulating nitrides, insulating oxynitrides, etc., including silicon oxide, aluminum oxide, silicon nitride, aluminum nitride, etc. Among them, the conductive connection member may include a first conductive connection member 410 and a second conductive connection member 420 that are respectively electrically connected to the portions of the lower electrode material layer 120 and the upper electrode material layer 140 located in the first trench 111, and the wiring layer may include a first wiring layer 510 and a second wiring layer 520 that are respectively electrically connected to the first conductive connection member 410 and the second conductive connection member 420 to connect the memory device to other electronic devices or an external circuit. It can be understood that in the presence of other electronic devices, more conductive connection members and / or wiring layers may also be included to guide the corresponding electronic devices to other devices or an external circuit. Among them, the conductive connection member and the wiring layer may be formed of a conductive material, such as metal materials like copper and tungsten, or other conductive compound materials, etc.

[0086] It can be understood that the conductive connection members associated with multiple devices may be formed synchronously to simplify the process. Hereinafter, the preparation of the conductive connection members connected to the memory device will be described as an example. Specifically, as Figures 4(h) to 4(j)As shown, the first conductive connector 410 formed to be electrically connected to the portion of the lower electrode material layer 120 located in the first trench 111 may include: forming a contact portion 600 in a portion of the substrate 110 adjacent to the first trench assembly 101, wherein the contact portion 600 may be electrically connected to the first lower electrode material portion 121 of the lower electrode material layer 120 located in the first trench 111; and forming the first conductive connector 410 above the contact portion 600, wherein the first conductive connector 410 may be configured to electrically connect the contact portion 600 to the first wiring layer 510.

[0087] Specifically, the contact portion 600 may be prepared based on a process such as silicide or salicide (metal silicide). For example, the active region 113 may be etched to form a space for accommodating the contact portion 600, and then a metal (such as cobalt, etc.) may be filled in this space, and then heated so that the metal and silicon in the active region 113 react at a high temperature to generate a metal silicide (such as cobalt silicide compound) as the contact portion 600. Such a contact portion of the metal silicide can effectively reduce the contact barrier, thereby reducing the contact resistance and improving the stability and performance of the device.

[0088] In some embodiments, as shown in FIGS. 4(i) and 4(j), the second conductive connector 420 formed to be electrically connected to the portion of the upper electrode material layer 140 located in the first trench 111 may include: etching at least a portion of the first isolation material portion 151 filled in the first trench 111 of the isolation material portion 150 until a portion of the upper electrode material layer 140 is exposed; and forming the second conductive connector 420 above the exposed portion of the upper electrode material layer 140, wherein the second conductive connector 420 may be configured to electrically connect the upper electrode material layer 140 to the second wiring layer 520.

[0089] Alternatively, in some other embodiments, in the case where the upper electrode material layer includes an upper electrode lead portion located outside the first trench and electrically connected to the portion of the upper electrode material layer located in the first trench, the second conductive connector formed to be electrically connected to the portion of the upper electrode material layer located in the first trench may include: forming the second conductive connector above the upper electrode lead portion, wherein the second conductive connector may be configured to electrically connect the upper electrode material layer to the second wiring layer. For example, the upper electrode lead portion may be located on the side of the first trench assembly opposite to the contact portion, such as on the left side of the first trench assembly 101 in FIG. 4(i), and the second conductive connector may be directly formed on the upper electrode lead portion located on the upper surface of the substrate 110 without etching the first isolation material portion to expose the upper electrode material layer, thereby helping to simplify the process.

[0090] In some embodiments, as shown in FIG. 4(i), vias can be formed by etching at corresponding positions of the dielectric protection layer 300, and then conductive materials such as tungsten can be filled in the vias to form corresponding conductive connectors. In addition, it can be understood that after the dielectric protection layer and the conductive connectors are formed, CMP processing can also be performed to make the upper surfaces of the dielectric protection layer 300 and the conductive connectors flat, thereby improving the quality of subsequent processes.

[0091] Further, as shown in FIG. 4(j), one or more patterned wiring layers can be formed at corresponding positions of the dielectric protection layer 300 through processes such as photolithography and etching, or through processes such as photolithography, deposition, and stripping. The one or more wiring layers can be electrically connected to corresponding one or more conductive connectors.

[0092] In addition, in the embodiments of the present disclosure, since the second trench component 102 is used as an isolation component, generally no conductive connectors or the like are provided to connect the second trench component 102 to other electronic devices or external circuits to ensure its electrical isolation effect.

[0093] The present disclosure also provides a storage device. As described above, the storage device 100 can include a first lower electrode material portion 121, a first storage material portion 131, and a first upper electrode material portion 141 that are sequentially stacked from bottom to top along the inner wall of the first trench 111 in the substrate 110. Among them, the first lower electrode material portion 121 and the first upper electrode material portion 141 serve as the two electrodes of the storage device 100, respectively, and the first storage material portion 131 serves as the functional layer of the storage device. By applying a corresponding voltage to the first storage material portion 131 between the first lower electrode material portion 121 and the first upper electrode material portion 141, the electrical state of the first storage material portion 131 can be changed as needed, thereby enabling data storage. In addition, various parameters related to the structure of the device described in the above device preparation method can be applied to the storage device described here individually or in combination. In addition, it can be understood that the storage device of the present disclosure can be prepared by the device preparation method described above.

[0094] Further, the present disclosure also provides a semiconductor device. As shown in FIG. 4(j), the semiconductor device can include one or more storage devices 100 as described above. For example, the semiconductor device can be a storage device, and the storage device can include a plurality of storage devices arranged in an array to achieve the storage of a large amount of data. In a specific example, the storage device can be a non-volatile memory used in a computer or the like.

[0095] Further, in some embodiments, as shown in FIG. 4(j), the semiconductor device may further include other electronic devices 200 different from the memory device 100. For example, the other electronic devices 200 may include logic devices, etc., which may work together with the memory device 100 to achieve a desired function. For example, the logic device may include a CMOS device, etc. It can be understood that, according to needs, the other electronic devices may also be other types of devices different from the memory device and the logic device, which are not limited herein.

[0096] In the technical solution of the present disclosure, the memory device may be formed synchronously with the isolation component in advance, or rather, in the semiconductor device, the first trench component where the memory device is located may be formed synchronously with the second trench component for forming the isolation component, and then other electronic devices, dielectric protection layers, conductive connection members, and / or wiring layers, etc. may be formed according to needs. In this way, the other electronic devices may be formed after the memory device is formed, so that the thermal budget associated with the formation process of the memory device can be avoided from having an adverse impact on the other electronic devices, thereby contributing to improving the performance in the entire semiconductor device, enhancing the reliability of the devices and the semiconductor device, and extending the lifespan of the devices and the semiconductor device. In addition, the device manufacturing method of the present disclosure can effectively reduce the process steps required in the manufacturing process of the entire semiconductor device. For example, at least three photomasks and their associated processes can be saved, thereby reducing the production cost and improving the production efficiency. Moreover, since the memory device is formed synchronously with the isolation component, the substrate is basically flat at this time, so that the introduction of steps, or even discontinuities or breaks, etc. in the film layer of the memory device can be avoided, which helps to improve the performance of the memory device. Additionally, the memory device of the present disclosure is at least integrated on the bottom wall and side wall of the trench, forming a 3D-structured memory device, which helps to increase the effective area of the memory device, thereby enhancing the performance of the memory device. Further, since the memory material layer in the memory device itself can be electrically insulating, its presence in the isolation component can help achieve electrical isolation between devices, and will not damage the original trench isolation performance, and even can improve the trench isolation performance to a certain extent.

[0097] The terms "left", "right", "front", "rear", "top", "bottom", "upper", "lower", "higher", "lower", etc. in the specification and claims, if any, are used for descriptive purposes and not necessarily to describe an invariant relative position. It should be understood that such terms are interchangeable under appropriate circumstances so that the embodiments of the present disclosure described herein, for example, can operate in other orientations different from those shown or otherwise described herein. For example, when the device in the drawings is inverted, a feature originally described as "above" other features can then be described as "below" the other features. The device can also be oriented in other ways (rotated 90 degrees or in other orientations), and the relative spatial relationships will be interpreted accordingly.

[0098] In the specification and claims, when an element is referred to as being "above", "attached" to, "connected" to, "coupled" to, or "in contact" with another element, etc., the element can be directly above, directly attached to, directly connected to, directly coupled to, or directly in contact with the other element, or there can be one or more intervening elements. In contrast, when an element is referred to as being "directly" above, "directly attached" to, "directly connected" to, "directly coupled" to, or "directly in contact" with another element, there will be no intervening elements. In the specification and claims, a feature being arranged "adjacent" to another feature can mean that the feature has an overlapping portion with the adjacent feature or a portion that is above or below the adjacent feature.

[0099] As used herein, the term "exemplary" means "serving as an example, instance, or illustration", rather than as a "model" to be precisely replicated. Any implementation described herein as exemplary is not necessarily to be construed as preferred or advantageous over other implementations. Moreover, the present disclosure is not limited by any theory expressed or implied in the technical field, background art, summary of the invention, or detailed description.

[0100] As used herein, the term "substantially" means including any minor variations caused by design or manufacturing defects, tolerances of devices or components, environmental effects, and / or other factors. The term "substantially" also allows for differences from a perfect or ideal situation due to parasitic effects, noise, and other practical considerations that may exist in an actual implementation.

[0101] Additionally, for reference purposes only, terms such as "first", "second", and the like may also be used herein and are not intended to be limiting. For example, unless the context clearly indicates otherwise, the words "first", "second", and other such numerical words referring to a structure or element do not imply an order or sequence.

[0102] It should also be understood that when the term "comprising / including" is used herein, it indicates the presence of the stated features, wholes, steps, operations, units, and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, units, and / or components and / or their combinations.

[0103] In this disclosure, the term "provide" is used in a broad sense to cover all ways of obtaining an object. Thus, "providing an object" includes, but is not limited to, "purchasing", "preparing / manufacturing", "arranging / setting", "installing / assembling", and / or "ordering" the object, etc.

[0104] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit this disclosure. As used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms unless the context clearly indicates otherwise.

[0105] Those skilled in the art should realize that the boundaries between the above operations are merely illustrative. Multiple operations can be combined into a single operation, a single operation can be distributed among additional operations, and operations can be performed at least partially overlapped in time. Moreover, alternative embodiments can include multiple instances of a particular operation, and the order of operations can be changed in various other embodiments. However, other modifications, variations, and substitutions are also possible. The aspects and elements of all the embodiments disclosed above can be combined in any manner and / or in combination with aspects or elements of other embodiments to provide multiple additional embodiments. Therefore, this specification and the drawings should be regarded as illustrative rather than restrictive.

[0106] Although some specific embodiments of this disclosure have been described in detail by way of examples, those skilled in the art should understand that the above examples are for illustrative purposes only and not for limiting the scope of this disclosure. The embodiments disclosed herein can be combined arbitrarily without departing from the spirit and scope of this disclosure. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of this disclosure. The scope of this disclosure is defined by the appended claims.

Claims

1. A device preparation method, characterized in that: The device preparation method comprises: providing a substrate, wherein the substrate includes an active region, a first trench and a second trench being formed in the active region; and Forming a lower electrode material layer, a storage material layer, an upper electrode material layer and an isolation material portion on the substrate in order from bottom to top to produce a first trench component and a second trench component; wherein the first trench assembly is formed by a lower electrode material layer, a storage material layer, an upper electrode material layer and a portion of the isolation material portion located in the first trench, and the first trench assembly is configured to form a memory device, The second trench assembly is formed by a lower electrode material layer, a storage material layer, an upper electrode material layer and a portion of the isolation material portion located in the second trench, and the second trench assembly is configured to form an isolation component, The first trough assembly and the second trough assembly are electrically isolated from each other, and no conductive connector is provided to connect the second trough assembly to other electronic devices or external circuits.

2. The device preparation method according to claim 1, characterized in that: Sequentially forming a lower electrode material layer, a storage material layer, an upper electrode material layer and an isolation material portion on the substrate from bottom to top to produce a first trench component and a second trench component includes: forming a patterned lower electrode material layer on the substrate, wherein the lower electrode material layer includes a first lower electrode material portion covering an inner wall of the first groove and a second lower electrode material portion covering an inner wall of the second groove, and the first lower electrode material portion and the second lower electrode material portion are disconnected from each other; sequentially depositing a continuous thin film storage material, a continuous thin film upper electrode material and an isolation material; Etching is performed to remove at least a portion of the isolation material, at least a portion of the upper electrode material, and at least a portion of the storage material located outside the first trench and the second trench, thereby forming a patterned storage material layer, an upper electrode material layer, and an isolation material portion, wherein the storage material layer includes a first storage material portion located in the first trench and a second storage material portion located in the second trench, the upper electrode material layer includes a first upper electrode material portion located in the first trench and a second upper electrode material portion located in the second trench, and the isolation material portion includes a first isolation material portion filled in the first trench and a second isolation material portion filled in the second trench.

3. The device preparation method according to claim 2, characterized in that: Forming a patterned lower electrode material layer on the substrate comprises: Depositing a continuous thin film of lower electrode material on the substrate; Depositing an anti-etchant layer, wherein at least a portion of the anti-etchant layer fills the first trench and the second trench; performing etching to remove at least a portion of the lower electrode material outside the first trench and the second trench, thereby forming a patterned lower electrode material layer; and The remaining resist layer is removed.

4. The device preparation method according to claim 3, characterized in that: The resist layer includes a bottom anti-reflective layer.

5. The device preparation method according to claim 2, characterized in that: At least one of the lower electrode material, the storage material, and the upper electrode material is deposited by atomic layer deposition.

6. The device preparation method according to claim 2, characterized in that: Deposition isolation materials include: Depositing the isolation material by high density plasma chemical vapor deposition, wherein the isolation material covers the entire upper surface of the upper electrode material; and The upper surface of the deposited isolation material is chemically mechanically polished.

7. The device preparation method according to claim 1, characterized in that: Two times the total thickness of the lower electrode material layer, the storage material layer and the upper electrode material layer is less than the minimum width of the first groove, and two times the total thickness of the lower electrode material layer, the storage material layer and the upper electrode material layer is less than the minimum width of the second groove; and / or An angle between at least one side surface of the first groove and its bottom surface is greater than or equal to 90°, and an angle between at least one side surface of the second groove and its bottom surface is greater than or equal to 90°.

8. The device preparation method according to claim 1, characterized in that: A depth of at least one of the first groove and the second groove is 300-400 nm or 400-500 nm; and / or A width of at least one of the first trench and the second trench is 130-190 nm or 190-250 nm.

9. The device preparation method according to claim 1, characterized in that: At least one of the lower electrode material layer and the upper electrode material layer is formed of at least one of titanium, titanium nitride, titanium silicon nitride, titanium aluminum nitride, titanium carbonitride, tantalum nitride, tantalum silicon nitride, tantalum aluminum nitride, tungsten nitride, tungsten silicide, doped polysilicon and transparent conductive oxide; and / or The storage material layer is formed of at least one of a phase change storage material, a ferroelectric material, zirconium oxide, hafnium oxide, titanium oxide, aluminum oxide, nickel oxide, and iron oxide.

10. The device preparation method according to claim 1, characterized in that: After producing the first trench component and the second trench component, the device preparation method further includes: Other electronic devices different from the memory device are formed on the substrate, wherein at least two adjacent devices are respectively arranged on both sides of the second trench component serving as the isolation component.

11. The device preparation method according to claim 1, characterized in that: After producing the first trench component and the second trench component, the device preparation method further includes: A dielectric protective layer located above the device, a conductive connector located inside the dielectric protective layer, and a wiring layer located above the dielectric protective layer are formed, wherein the conductive connector includes a first conductive connector and a second conductive connector respectively electrically connected to the portions of the lower electrode material layer and the upper electrode material layer located in the first groove, and the wiring layer includes a first wiring layer and a second wiring layer respectively electrically connected to the first conductive connector and the second conductive connector.

12. The device preparation method according to claim 11, characterized in that: Forming a first conductive connection electrically connected to a portion of the lower electrode material layer located in the first trench includes: forming a contact portion in a portion of the substrate adjacent to the first trench assembly, wherein the contact portion is electrically connected to a first lower electrode material portion of the lower electrode material layer located in the first trench, and the contact portion is formed of metal silicide; and A first conductive connection is formed over the contact portion, wherein the first conductive connection is configured to electrically connect the contact portion to a first wiring layer.

13. The device preparation method according to claim 11, characterized in that: Forming a second conductive connection electrically connected to a portion of the upper electrode material layer located in the first trench includes: Etching at least a portion of the first isolation material portion of the isolation material part filled in the first trench until a portion of the upper electrode material layer is exposed; and A second conductive connection is formed over the exposed portion of the upper electrode material layer, wherein the second conductive connection is configured to electrically connect the upper electrode material layer to the second wiring layer.

14. The device preparation method according to claim 11, characterized in that: In the case where the upper electrode material layer includes an upper electrode lead portion located outside the first groove and electrically connected to the portion of the upper electrode material layer located in the first groove, forming a second conductive connection electrically connected to the portion of the upper electrode material layer located in the first groove includes: A second conductive connection is formed over the upper electrode lead portion, wherein the second conductive connection is configured to electrically connect the upper electrode material layer to the second wiring layer.

15. A storage device, characterized in that: The memory device is manufactured by the device manufacturing method according to any one of claims 1 to 14.

16. A semiconductor device, characterized in that: The semiconductor arrangement includes one or more memory devices according to claim 15 .

17. The semiconductor device according to claim 16, wherein: The semiconductor device further includes other electronic devices other than the memory device.

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