Interconnects for modular die designs

Abstract

Interconnects for modular die designs are disclosed. In one aspect, a die is designed as a chiplet and tested for suitability. After the chiplet design is approved, multiple dies or chiplets can be coupled together within a multi-die package to form a package with the desired computing power. After assembly, each chiplet is provided with a unique identifier, such as by setting a fuse. Based on the unique identifier, each chiplet is made aware of how its interfaces to the other chiplets are configured so that signals can be routed appropriately. Using modular chiplets in this manner reduces testing requirements and non-recurring expenses while increasing the flexibility of design options.

Description

[0001] Priority application

[0002] This application claims priority to U.S. patent application serial number 17 / 655,823, filed on March 22, 2022, entitled “INTERCONNECTIONS FOR MODULARDIE DESIGNS,” which is incorporated herein by reference in its entirety. background

[0003] I. Technical Field

[0004] The technology of the present disclosure generally relates to interconnects for modular integrated circuit (IC) die designs.

[0005] II. Background Technology

[0006] Computing devices are ubiquitous in modern society, providing countless functions to meet different needs. As the number of functional possibilities increases, computing needs are also increasing (for example, the need for greater processing power). In the past, such increased computing needs could be met by increasing the number of transistors within an integrated circuit (IC) die or by increasing the size of the die. As transistor size approaches some theoretical limits of the low nanometer scale, adding transistors within a given space is becoming increasingly challenging. Similarly, the size of the die is approaching some practical limits imposed by current manufacturing processes. That is, as the size of the die increases, the yield of a given run may decrease, and there may be process differences across the die, which may lead to problems with managing internal delays and bias requirements. Therefore, there is still a need for better ways to design dies that allow flexibility in meeting various computing needs. Summary of the Invention

[0007] Aspects disclosed in the detailed description include interconnections for modular die designs. Specifically, dies are designed as chiplets and tested for suitability. After the chiplet design is approved, multiple dies or chiplets can be coupled together within a multi-die package to form a package with the desired computing power. After assembly, each chiplet is provided with a unique identifier, such as by setting a fuse. Based on the unique identifier, each chiplet is made aware of how the interface to the other chiplets is configured so that signals can be routed appropriately. Using modular chiplets in this manner reduces testing requirements and non-recurring expenses while increasing the flexibility of design options.

[0008] In this regard, in one aspect, a method of forming a package is disclosed. The method includes placing a plurality of chiplets on a substrate. The method also includes providing a unique identifier for each chiplet. The method also includes forming a lookup table (LUT) for each chiplet for routing communications between the chiplets based on the unique identifier. The method also includes configuring a port to route communications between the chiplets based on the unique identifier.

[0009] In another aspect, a method for communicating between chiplets in a package is disclosed. The method includes generating a signal at a logic block within a first chiplet in the package. The method also includes comparing an address of the signal to a LUT to determine a physical address. The method also includes routing the signal to a selected port based on the LUT.

[0010] In another aspect, a package is disclosed. The package includes a substrate. The package also includes a plurality of chiplets mounted on the substrate and interconnected with each other. Each chiplet in the plurality of chiplets includes a unique identifier. Each chiplet also includes a plurality of ports. Each chiplet also includes a LUT. Each chiplet also includes control circuitry configured to distinguish, based on the LUT, whether a signal generated within the chiplet is local or directed to a different chiplet.

[0011] In another aspect, a package is disclosed. The package includes a substrate. The package also includes a plurality of chiplets mounted on the substrate and interconnected with each other. Each chiplet in the plurality of chiplets includes a unique identifier. Each chiplet also includes a plurality of ports. Each chiplet also includes control circuitry configured to route a signal generated within the chiplet to a local address or to a different chiplet within the plurality of chiplets based on the chiplet identifier within the signal.

[0012] In another aspect, a package is disclosed. The package includes a substrate. The package also includes a plurality of chiplets mounted on the substrate and interconnected with each other. Each chiplet in the plurality of chiplets includes a unique identifier. Each chiplet also includes a plurality of ports. Each chiplet also includes control circuitry configured to route signals generated within the chiplet to a local address or to an egress port based on the chiplet identifier. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a stylized diagram of an exemplary chiplet integrated into a multi-chiplet package;

[0014] Figure 2 is a block diagram of an exemplary chiplet having ports for interconnecting with other chiplets according to exemplary aspects of the present disclosure;

[0015] Figure 3 is a block diagram of an exemplary package using four homogenous chiplets with interconnections therebetween according to exemplary aspects of the present disclosure;

[0016] Figure 4 is a table showing how addressing may function for interconnected chiplets within a die;

[0017] Figure 5 A table is provided showing how memory mapping may function for interconnected chiplets within a die;

[0018] Figure 6 is a flow chart illustrating an exemplary process for fabricating and interconnecting dies from chiplets according to the present disclosure;

[0019] Figure 7 is a block diagram of an exemplary processor-based system that may include a die formed of chiplets having interconnects according to the present disclosure; and

[0020] Figure 8 is a block diagram of exemplary transceiver circuitry that may be present in a processor-based system including a die formed in accordance with the present disclosure. DETAILED DESCRIPTION

[0021] With reference now to the accompanying drawings, several exemplary aspects of the present disclosure are described. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0022] Aspects disclosed in the detailed description include interconnects for modular die designs. Specifically, dies are designed as chiplets and tested for suitability. After the chiplet design is approved, multiple dies or chiplets can be coupled together within a multi-die package to form a package with the desired computing capabilities. After assembly, each chiplet is provided with a unique identifier, such as by setting a fuse. Based on the unique identifier, each chiplet is made aware of how the interface to the other chiplets is configured so that signals can be routed appropriately. Using modular chiplets in this manner reduces testing requirements and non-recurring expenses while increasing the flexibility of design options.

[0023] In this regard, Figure 11 is a stylized illustration of a package 100 formed from a plurality of homogenous chiplets 102(1)-102(4). The chiplets 102(1)-102(4) may be mounted on a substrate 104, such as a laminate (e.g., a printed circuit board (PCB)) having a metallization layer (not shown) therein. The metallization layer may include vias and conductors that interconnect pins on the chiplets 102(1)-102(4). The package 100 may include a molded overlay (not shown), etc.

[0024] It is also noted that while four chiplets 102(1)-102(4) are shown in the package 100, exemplary aspects of the present disclosure are not limited to only four. For example, a package may be formed with two to ten (or more) chiplets 102. In the case where the chiplets 102 are homogeneous, it makes sense geometrically to use an even number of chiplets 102, and more logically, the number of chiplets 102 may be a power of two (e.g., two, four, eight, etc.).

[0025] Although all of the chiplets 102(1)-102(4) are formed from a common chiplet 102, it should be understood that the package 100 may be formed from heterogeneous chiplets (not shown). As another possibility, multiple chiplets 102 may be homogeneous with one or more heterogeneous chiplets on the same package (e.g., three identical and one different, two sets of two different chiplets, etc.). The advantage of using homogeneous chiplets 102(1)-102(4) is that only a single design and test cycle is required. Each additional possible chiplet design will add additional design and test cycles, which may increase non-recurring expenses, increase the average unit cost and / or delay time to market.

[0026] Figure 2 Additional details are provided regarding an exemplary chiplet 200 that may correspond to Figure 1 1 . The chiplet 200 may include various logic blocks 202(1)-202(N) coupled to an internal interconnect 204. The internal interconnect 204 may be associated with and / or controlled by a control circuit 206, which may control the routing of communications based in part on the contents of a lookup table (LUT) 208. A plurality of input / output (I / O) ports 210(0)-210(M) may be coupled to the internal interconnect 204 to allow communications from the logic blocks 202(1)-202(N) to external elements, such as logic blocks within another chiplet 102. Fuses 212 may be externally accessible and may be used to help designate a unique identifier for the chiplet 200, as will be explained in more detail below.

[0027] When multiple chiplets 102 or 200 are assembled into a package, there will be situations where a logic block in one chiplet needs to communicate with a logic block in another chiplet. If there are multiple identical chiplets, it may be necessary to distinguish between them for inter-chiplet communication. Exemplary aspects of the present disclosure contemplate the use of fuses 212 to help address this communication challenge. Specifically, fuses 212 can be used to set a unique identifier (e.g., a unique bit sequence) for a chiplet 200, as shown in FIG. Figures 3 to 5 Better explained.

[0028] In this regard, Figure 3 Illustrated with Figure 1 Package 300 is similar to package 100. Package 300 includes four chiplets 200(0)-200(3). Respective fuses 212(0)-212(3) can be set during integration into package 300 to indicate a particular die identifier (Die_ID). As illustrated, chiplet 200(0) has a Die_ID of 00; chiplet 200(1) has a Die_ID of 01; chiplet 200(2) has a Die_ID of 10 (a binary representation of 2); and chiplet 200(3) has a Die_ID of 11 (a binary representation of 3). Respective control circuits 206(0)-206(3) can read fuses 212(0)-212(3) and configure port 302 based on the contents of corresponding LUTs 208(0)-208(3). Specifically, each chiplet 200(0)-200(3) has three ports 3020(0)-3020(2) to 3023(0)-3023(2) (corresponding to Figure 2 2 (M)). Before setting fuses 212(0)-212(3), ports 3020(0)-3020(2) to 3023(0)-3023(2) appear identical to corresponding internal interconnects 204(0)-204(3). By setting fuses 212(0)-212(3) to provide unique Die_IDs, control circuits 206(0)-206(3) now treat ports 3020(0)-3020(2) to 3023(0)-3023(2) differently based on the Die_ID. Thus, for chiplet 200(0), control circuitry 206(0) knows that port 3020(0) is coupled to chiplet 200(1), port 3020(1) is coupled to chiplet 200(2), and port 3020(2) is coupled to chiplet 200(3). Therefore, if a communication from logic blocks 2020(1)-2020(N) within chiplet 200(0) is destined for logic block 2022(3) within chiplet 200(2), control circuitry 206(0) directs the communication through internal interconnect 204(0) to port 3020(1).

[0029] For completeness, for chiplet 200(1), control circuitry 206(1) knows that port 3021(0) is coupled to chiplet 200(0), port 3021(1) is coupled to chiplet 200(3), and port 3021(2) is coupled to chiplet 200(2). For chiplet 200(2), control circuitry 206(2) knows that port 3022(0) is coupled to chiplet 200(3), port 3022(1) is coupled to chiplet 200(0), and port 3022(2) is coupled to chiplet 200(1). For chiplet 200(3), control circuitry 206(3) knows that port 3023(0) is coupled to chiplet 200(2), port 3023(1) is coupled to chiplet 200(1), and port 3023(2) is coupled to chiplet 200(0). It should be understood that these connections may depend on the positioning of the chiplets 200(0)-200(3) such that in most cases, the chiplets 200(0)-200(3) are mirrored about different axes. For example, chiplet 200(3) is mirrored about the y-axis relative to chiplet 200(0), and chiplet 200(1) is mirrored about the x-axis relative to chiplet 200(0). This mirroring causes ports 3020(0)-3020(2) to 3023(0)-3023(2) to be aligned as shown. If the chiplets 200(0)-200(3) are rotated or are not homogenous, then ports 3020(0)-3020(2) to 3023(0)-3023(2) may be aligned differently and have different inter-chiplet connections. Although not required, a general goal would be to minimize the distance between such inter-chiplet connections to reduce latency and potentially reduce the chance of crosstalk or other forms of electromagnetic interference.

[0030] It should be understood that if there are fewer or more chiplets than four, fewer or more bits may be needed in fuse 212. Similarly, fewer or more ports 302 may be needed for corresponding entries in LUT 208.

[0031] Figure 4 and Figure 5 Further nuances for routing are illustrated. For example, assume that each chiplet 200 has sixty-four gigabytes (64 GB) of memory in logic block 202. Figure 44 and Table 400 therein, the control circuitry 206(0)-206(3) may pre-set a chiplet identifier 402 to a physical address 404 used by the logic block 202, where the number of bits in the chiplet identifier 402 may be equal to one plus the number of bits required to uniquely identify the chiplet. Thus, for four chiplets 200(0)-200(3), the chiplet identifier 402 may be three bits (one plus two bits to identify four chiplets). If there are more chiplets, the chiplet identifier 402 may be more than three bits. The first bit may be a local or remote identifier. That is, for example, a first bit of 0 may indicate that the communication is local. Thus, as shown in row 404, a chiplet identifier of 000 would reference a memory element of a local chiplet. Other chiplet identifiers 402 with a leading 0 may be reserved for future use. If the first bit is 1, this usage may indicate that subsequent bits identify which chiplet (and corresponding port) the communication is addressed to. It should be noted that there will be cases where the chiplet identifier begins with 1 but is still used for a local address (shown generally at 406).

[0032] Figure 5 Expanded Figure 4 400 and illustrates how there may be a default configuration memory map 500(0) that is saved for the chiplet 200(0) and the modified configuration after fuses 212(0)-212(3) are set, as shown in memory maps 500(1)-500(3).

[0033] While fuses are specifically contemplated as a means of providing a configuration for controlling circuitry, it should be understood that other means of achieving the same result are possible. For example, software may reside in firmware that provides a logical to physical address mapping function. Other hardware mechanisms (e.g., jumpers, shorts, or opens, etc.) may also be used if desired.

[0034] Figure 6A flow chart illustrating a process 600 associated with the design and manufacture of a package having multiple modular dies with interconnections according to the present disclosure is illustrated. Specifically, process 600 begins with the design of a chiplet 200 (block 602). The chiplet 200 is tested and verified (block 604). Then, computational requirements are identified, and a package is designed using the chiplet 200 (block 606). The designer can then check to see if the package can work as expected with existing chiplets (block 608). That is, the first chiplet 200 designed may be optimized for either a neural processor or a graphics processor, but may not be optimized for both. If the package cannot be built using existing chiplets 200, more chiplets 200 are designed, tested, and verified (block 610), and the designer determines whether the package can now be built using existing chiplets 200. In this way, the package can be a combination of homogeneous chiplets 200, or heterogeneous chiplets 200.

[0035] Once the designer is satisfied with the design of the package, the package is formed by assembling the chiplets 200 on the substrate 104 (block 612). As part of this step, each chiplet 200 may be assigned and set with a unique identifier (block 612A). Setting the unique identifier may be accomplished by setting fuses 212, grounding certain connections, setting jumpers, through software, etc. The ports on the chiplets 200 are interconnected (block 612B). That is, the chiplets 200 may be soldered to contact points in the metallization layer of the substrate 104 so that the conductors and vias in the metallization layer interconnect the pins of the ports of the chiplets 200. Note that it is possible that blocks 612A and 612B could be reversed in time and the interconnections formed before the unique identifiers are set.

[0036] Once the unique identifier is set, the control circuitry may use the unique identifier to configure the port (block 614). That is, the control circuitry 206 may use the LUT 208 to determine which ports are connected to which other chiplets. The control circuitry 206 may also form an address table (block 616) including local addresses and global addresses based on the unique identifier (e.g., Figure 5 Table 400 or memory map).

[0037] The interconnects for the modular die designs according to the various aspects disclosed herein and the packages assembled therefrom may be provided in or integrated into any processor-based device. Non-limiting examples include: a set-top box, an entertainment unit, a navigation device, a communication device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smartphone, a Session Initiation Protocol (SIP) phone, a tablet device, a phablet, a server, a computer, a portable computer, a mobile computing device, a wearable computing device (e.g., a smartwatch, a health or fitness tracker, eyeglasses, etc.), a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle assembly, an avionics system, a drone, and a multirotor aircraft.

[0038] As noted, the modular die design of the present disclosure may be incorporated into a processor-based system. In this regard, Figure 7 Examples of Figure 3 An example of a processor-based system 700 of the illustrated package 300. In this example, the processor-based system 700 includes one or more central processing units (CPUs) 702, each of which includes one or more processors 704. The processor 704 may include the package 300. The CPU 702 may have a cache memory 706 coupled to the processor 704 for fast access to temporarily stored data. The CPU 702 is coupled to a system bus 708 and may interactively couple master devices and slave devices included in the processor-based system 700. As is well known, the CPU 702 communicates with these other devices by exchanging address, control, and data information on the system bus 708. For example, the CPU 702 may communicate a bus transaction request to a memory controller 710, which is an example of a slave device. Although in Figure 7 Not illustrated, but multiple system buses 708 may be provided.

[0039] like Figure 7As illustrated, these devices may include, by way of example, a memory system 712, one or more input devices 716, one or more output devices 718, one or more network interface devices 720, and one or more display controllers 722. Input devices 716 may include any type of input device, including, but not limited to, input keys, switches, voice processors, and the like. Output devices 718 may include any type of output device, including, but not limited to, audio, video, other visual indicators, and the like. Network interface device 720 may be any device configured to allow data exchange to and from a network 724. Network 724 may be any type of network, including, but not limited to, a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), Bluetooth, or the like. TM Network and Internet. The network interface device # can be configured to support any type of communication protocol desired. The memory system 712 can include one or more memory units 714 (0-N).

[0040] The CPU 702 may also be configured to access a display controller 722 on the system bus 708 to control information transmitted to one or more displays 726. The display controller 722 transmits information to be displayed to the display 726 via one or more video processors 728, which processes the information to be displayed into a format suitable for the display 726. The display 726 may include any type of display, including but not limited to a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, a light emitting diode (LED) display, and the like.

[0041] Figure 8 An exemplary wireless communication device 800 is illustrated that includes a radio frequency (RF) component formed of one or more ICs 802, wherein any of the ICs 802 may include multiple modular dies according to the present disclosure or be a package including multiple modular dies according to the present disclosure. As an example, the wireless communication device 800 may include or be provided in any of the above-mentioned devices. Figure 8 As shown, wireless communication device 800 includes a transceiver 804 and a data processor 806. Data processor 806 may include memory to store data and program codes. Transceiver 804 includes a transmitter 808 and a receiver 810 that support bidirectional communication. In general, wireless communication device 800 may include any number of transmitters 808 and / or receivers 810 for any number of communication systems and frequency bands. All or a portion of transceiver 804 may be implemented on one or more analog ICs, RF ICs (RFICs), mixed-signal ICs, etc.

[0042] The transmitter 808 or the receiver 810 may be implemented using a superheterodyne architecture or a direct conversion architecture. In a superheterodyne architecture, the signal is converted between RF and baseband in multiple stages, for example, from RF to an intermediate frequency (IF) in one stage and then from IF to baseband in another stage. In a direct conversion architecture, the signal is converted between RF and baseband in one stage. Superheterodyne and direct conversion architectures may use different circuit blocks and / or have different requirements. Figure 8 In the wireless communication device 800 in FIG. 8 , the transmitter 808 and the receiver 810 are implemented using a direct conversion architecture.

[0043] In the transmit path, the data processor 806 processes the data to be transmitted and provides I and Q analog output signals to the transmitter 808. In the exemplary wireless communication device 800, the data processor 806 includes digital-to-analog converters (DACs) 812(1), 812(2) to convert the digital signals generated by the data processor 806 into I and Q analog output signals (e.g., I and Q output currents) for further processing.

[0044] Within transmitter 808, low-pass filters 814(1), 814(2) filter the I and Q analog output signals, respectively, to remove undesired signals caused by the preceding digital-to-analog conversion. Amplifiers (AMPs) 816(1), 816(2) amplify the signals from low-pass filters 814(1), 814(2), respectively, and provide I and Q baseband signals. An up-converter 818 up-converts the I and Q baseband signals using I and Q TX local oscillator (LO) signals from a transmit (TX) local oscillator (LO) signal generator 622 via mixers 820(1), 820(2) to provide an up-converted signal 824. A filter 826 filters the up-converted signal 824 to remove undesired signals caused by the up-conversion and noise in the receive band. A power amplifier (PA) 828 amplifies the up-converted signal 824 from filter 826 to obtain a desired output power level and provide a transmit RF signal. The transmit RF signal is routed through a duplexer or switch 830 and transmitted via an antenna 832 .

[0045] In the receive path, antenna 832 receives the signal transmitted by the base station and provides a received RF signal that is routed through a duplexer or switch 830 and provided to a low noise amplifier (LNA) 834. The duplexer or switch 830 is designed to operate with a specific receive (RX) and TX duplexer frequency separation so that the RX signal is isolated from the TX signal. The received RF signal is amplified by LNA 834 and filtered by filter 836 to obtain the desired RF input signal. Down-conversion mixers 838(1), 838(2) mix the output of filter 836 with the I and Q RX LO signals (i.e., LO_I and LO_Q) from RX LO signal generator 840 to generate I and Q baseband signals. The I and Q baseband signals are amplified by AMPs 842(1), 842(2) and further filtered by low-pass filters 844(1), 844(2) to obtain I and Q analog input signals, which are provided to the data processor 806. In this example, the data processor 806 includes analog-to-digital converters (ADCs) 846(1), 846(2) to convert the analog input signals into digital signals to be further processed by the data processor 806.

[0046] In wireless communication device 800 of FIG. Y, TX LO signal generator 822 generates I and Q TX LO signals for upconversion, while RX LO signal generator 840 generates I and Q RX LO signals for downconversion. Each LO signal is a periodic signal having a specific fundamental frequency. TX phase-locked loop (PLL) circuit 848 receives timing information from data processor 806 and generates a control signal for adjusting the frequency and / or phase of the TX LO signal from TX LO signal generator 822. Similarly, RX PLL circuit 850 receives timing information from data processor 806 and generates a control signal for adjusting the frequency and / or phase of the RX LO signal from RX LO signal generator 840.

[0047] Those skilled in the art will further understand that the various illustrative logic blocks, modules, circuits, and algorithms described in conjunction with the various aspects disclosed herein can be implemented as electronic hardware, instructions stored in a memory or another computer-readable medium and executed by a processor or other processing device, or a combination of the two. As an example, the master device and slave device described herein can be used in any circuit, hardware component, integrated circuit (IC), or IC chip. The memory disclosed herein can be a memory of any type and size and can be configured to store any type of information desired. In order to clearly illustrate this interchangeability, the functionality of various illustrative components, blocks, modules, circuits, and steps has been generally described above. How such functionality is implemented depends on the specific application, design choice, and / or design constraints imposed on the overall system. Those skilled in the art can implement the described functionality in different ways for each specific application, but such specific implementation decisions should not be interpreted as causing a departure from the scope of this disclosure.

[0048] The various illustrative logical blocks, modules, and circuits described in conjunction with the various aspects disclosed herein may be implemented or performed with a processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic components, discrete hardware components, or any combination thereof designed to perform the functions described herein. The processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0049] The various aspects disclosed herein may be embodied in hardware and instructions stored in hardware and may reside in, for example, random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, a hard disk, a removable disk, a CD-ROM, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from and write information to the storage medium. In an alternative embodiment, the storage medium may be integral to the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a remote station. In an alternative embodiment, the processor and storage medium may reside as discrete components in a remote station, a base station, or a server.

[0050] It is also noted that the operational steps described in any exemplary aspects herein are described for the purpose of providing examples and discussion. The described operations may be performed in many different orders other than the order illustrated. In addition, the operations described in a single operational step may actually be performed in a plurality of different steps. In addition, one or more operational steps discussed in the exemplary aspects may be combined. It should be understood that, as will be apparent to those skilled in the art, many different modifications may be made to the operational steps illustrated in the flow chart. Those skilled in the art will also understand that any of a variety of different technologies and techniques may be used to represent information and signals. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof.

[0051] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations. Therefore, the disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0052] Specific implementation examples are described in the following numbered clauses:

[0053] 1. A method of forming a package, the method comprising:

[0054] placing a plurality of chiplets on a substrate;

[0055] Set a unique identifier for each chiplet;

[0056] forming a lookup table (LUT) for each chiplet for routing communications between the chiplets based on the unique identifier; and

[0057] The ports are configured to route communications between the chiplets based on the unique identifier.

[0058] 2. The method of clause 1 , wherein the plurality of chiplets are homogenous.

[0059] 3. The method of clause 1 , wherein the plurality of chiplets are heterogeneous.

[0060] 4. The method of clauses 1 to 3, wherein setting the unique identifier comprises setting at least one fuse.

[0061] 5. The method of clauses 1 to 3, wherein setting the unique identifier comprises connecting a circuit to ground.

[0062] 6. The method of clauses 1 to 3, wherein setting the unique identifier comprises setting the unique identifier using software.

[0063] 7. The method of any of the preceding clauses, wherein placing the plurality of chiplets on the substrate comprises forming interconnections between the plurality of chiplets using vias and conductors within a metallization layer within the substrate.

[0064] 8. A method according to any preceding clause, further comprising: assigning the unique identifier to each chiplet before setting.

[0065] 9. The method of any preceding clause, further comprising loading the lookup table (LUT) with global-to-local address information based on the unique identifier.

[0066] 10. The method of any preceding clause, wherein placing the plurality of chiplets on the substrate comprises coupling a first port of a first chiplet to a first port of a second chiplet.

[0067] 11. A method of communicating between chiplets in a package, the method comprising:

[0068] generating a signal at a logic block within a first chiplet in the package;

[0069] comparing the address of the signal to a lookup table (LUT) to determine a physical address; and

[0070] The signal is transferred to a selected port based on the LUT.

[0071] 12. A package, comprising:

[0072] substrate; and

[0073] a plurality of chiplets mounted on the substrate and interconnected with each other;

[0074] Each chiplet of the plurality of chiplets comprises:

[0075] unique identifier;

[0076] Multiple ports;

[0077] Look-up table (LUT); and

[0078] A control circuit is configured to distinguish whether a signal generated within the chiplet is local or directed to a different chiplet based on the LUT.

[0079] 13. The package of clause 12, wherein the plurality of chiplets are homogenous.

[0080] 14. The package of clause 12, wherein the plurality of chiplets are heterogeneous.

[0081] 15. The package of any of clauses 12 to 14, wherein the substrate comprises a metallization layer comprising conductors and vias, and the plurality of chiplets are interconnected using the conductors and the vias.

[0082] 16. A package, comprising:

[0083] substrate; and

[0084] a plurality of chiplets mounted on the substrate and interconnected with each other;

[0085] Each chiplet of the plurality of chiplets comprises:

[0086] unique identifier;

[0087] Multiple ports; and

[0088] A control circuit is configured to route a signal generated within the chiplet to a local address or to a different chiplet within the plurality of chiplets based on a chiplet identifier within the signal.

[0089] 17. The package of clause 16, wherein the chiplet identifier is pre-set to an address within the signal.

[0090] 18. The package of clause 16 or 17, wherein the chiplet identifier has a number of bits equal to one plus the number of bits required to uniquely identify the plurality of chiplets.

[0091] 19. A package, comprising:

[0092] substrate; and

[0093] a plurality of chiplets mounted on the substrate and interconnected with each other;

[0094] Each chiplet of the plurality of chiplets comprises:

[0095] unique identifier;

[0096] Multiple ports; and

[0097] A control circuit is configured to route a signal generated within the chiplet to a local address or to an egress port based on the chiplet identifier.

Claims

1. A method of forming a package, the method comprising: placing a plurality of chiplets on a substrate; setting a unique identifier for each chiplet by setting at least one fuse; forming a lookup table (LUT) for each chiplet for routing communications between the chiplets based on the unique identifier; as well as The ports are configured to route communications between the chiplets based on the unique identifier.

2. The method of claim 1, wherein the plurality of chiplets are homogenous. The method of claim 1 , wherein the plurality of chiplets are heterogeneous. The method of claim 1 , wherein setting the unique identifier comprises grounding a circuit. The method of claim 1 , wherein setting the unique identifier comprises setting the unique identifier using software.

6. The method of claim 1 , wherein placing the plurality of chiplets on the substrate comprises: Interconnections are formed between the plurality of chiplets using vias and conductors within metallization layers within the substrate.

7. The method according to claim 1, further comprising: Prior to setup, each chiplet is assigned the unique identifier.

8. The method according to claim 1, further comprising: The lookup table (LUT) is loaded with global-to-local address information based on the unique identifier.

9. The method of claim 1 , wherein placing the plurality of chiplets on the substrate comprises: The first port of the first chiplet is coupled to the first port of the second chiplet.

10. A method of communicating between chiplets in a package, the method comprising: generating a signal at a logic block within a first chiplet in the package; comparing an address of the signal to a lookup table (LUT) to determine a physical address, wherein each of the chiplets has a unique identifier defined by at least one fuse, and wherein the LUT includes routing communications between the chiplets based on the unique identifiers; as well as The signal is transferred to a selected port based on the LUT.

11. A package, comprising: substrate; and a plurality of chiplets mounted on the substrate and interconnected with each other; Each chiplet of the plurality of chiplets comprises: unique identifier; Multiple ports; Look-up table (LUT); and A control circuit is configured to distinguish whether a signal generated within the chiplet is local or directed to a different chiplet based on the LUT. The package of claim 11 , wherein the plurality of chiplets are homogenous. The package of claim 11 , wherein the plurality of chiplets are heterogeneous.

14. The package of claim 11, wherein the substrate comprises a metallization layer including conductors and vias, and the plurality of chiplets are interconnected using the conductors and the vias.

15. A package, comprising: substrate; and a plurality of chiplets mounted on the substrate and interconnected with each other; Each chiplet of the plurality of chiplets comprises: unique identifier; Multiple ports; and A control circuit is configured to route a signal generated within the chiplet to a local address or to a different chiplet within the plurality of chiplets based on a chiplet identifier within the signal.

16. The package of claim 15, wherein the chiplet identifier is pre-set to an address within the signal.

17. The package of claim 15, wherein the chiplet identifier has a number of bits equal to one plus a number of bits required to uniquely identify the plurality of chiplets.

18. A package, comprising: substrate; and a plurality of chiplets mounted on the substrate and interconnected with each other; Each chiplet of the plurality of chiplets comprises: unique identifier; Multiple ports; and A control circuit is configured to route a signal generated within the chiplet to a local address or to an egress port based on the chiplet identifier.

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