Method, system and electronic device for GPU BOX logically controlling power-on reset timing

Abstract

The present application relates to a method, system, and electronic device for controlling the power-on reset timing of a GPU BOX logic. The method comprises: powering on the microcontroller and the motherboard editable logic module on the GPU BOX motherboard; the microcontroller collecting the in-place status of each UBB board and controlling the corresponding UBB editable logic module to power on; after the UBB editable logic module is successfully powered on, controlling the motherboard editable logic module to send a GPU power-on signal to each UBB editable logic module; each UBB editable logic module controls the power-on of the corresponding GPU card based on the GPU power-on signal; after each GPU card is successfully powered on, controlling the motherboard editable logic module to receive a power-on reset success signal sent by each UBB editable logic module; the power-on reset success signal is generated by each UBB editable logic module based on a power-on completion signal sent by each GPU editable logic module. This method implements the power-on reset timing of the GPU BOX logic control, ensuring that each board and GPU card is properly powered on.

Description

Technical Field

[0001] The present application relates to the field of device communication technology, and in particular to a method, system, and electronic device for logically controlling power-on reset timing of a GPU BOX. Background Art

[0002] With the widespread adoption of GPUs, market demands for higher performance from GPU servers are becoming increasingly stringent. Limited by traditional GPU server architecture, currently available GPU servers can only accommodate a maximum of eight GPU cards. Consequently, a specialized high-density server device, the GPU BOX, has emerged.

[0003] Each GPU BOX consists of a mainboard and multiple UBB boards. The GPU connected to the server is structurally independent and integrated onto the GPU BOX's UBB board. As an independent power supply system, the GPU BOX must ensure proper power-on and power-off reset timing for each board, as well as proper timing between the GPU BOX and the server, to ensure device communication. Timing anomalies in the design can easily lead to board failures, device damage, loss of communication, and even serious product failures. Summary of the Invention

[0004] Based on this, it is necessary to provide a new approach to GPU BOX power-on and power-off reset timing processing to address the above technical issues. This approach can ensure the power-on and power-off timing logic of each board and each GPU on the board in the GPU BOX, and prevent the board from being damaged when an abnormality occurs on the board or GPU. This approach provides a method, system, and electronic device for GPU BOX logic control of power-on and power-off reset timing.

[0005] In a first aspect, the present application provides a method for logically controlling power-on reset timing of a GPU BOX. The GPU BOX includes a mainboard and multiple UBB boards, the mainboard is electrically connected to each of the UBB boards, the mainboard includes a microcontroller and a mainboard editable logic module in communication with each other; the UBB board includes multiple GPU cards and a UBB editable logic module connected to each of the GPU cards, the GPU card including a GPU editable logic module; after the GPU BOX is connected to an external power supply, the microcontroller and the mainboard editable logic module on the mainboard are powered on. The method includes:

[0006] The microcontroller collects the in-place status of each UBB board and controls the corresponding UBB editable logic module to power on according to the in-place status;

[0007] When the UBB editable logic module is powered on successfully, controlling the mainboard editable logic module to send a GPU power-on signal to each of the UBB editable logic modules; each of the UBB editable logic modules controls the corresponding GPU card to power on according to the GPU power-on signal;

[0008] When each GPU card is powered on successfully, the mainboard editable logic module is controlled to receive a power-on reset success signal sent by each UBB editable logic module; the power-on reset success signal is generated by each UBB editable logic module based on a power-on completion signal sent by each GPU editable logic module.

[0009] In one embodiment, the UBB board further includes a UBB power supply and a GPU card power supply; when the UBB editable logic module is successfully powered on, controlling the mainboard editable logic module to send a GPU power-on signal to each of the UBB editable logic modules further includes:

[0010] When the UBB editable logic module is powered on successfully, the mainboard editable logic module is controlled to send a GPU power-on signal to each of the UBB editable logic modules; each of the UBB editable logic modules controls the UBB power supply and GPU power supply of the corresponding UBB board to power on;

[0011] If the UBB board is abnormally powered off, the corresponding UBB editable logic module controls the UBB board to turn off the UBB power supply and the GPU power supply, and sends a UBB abnormal power-off signal to the mainboard editable logic module.

[0012] In one embodiment, when each GPU card is powered on successfully, controlling the mainboard editable logic module to receive a power-on reset success signal sent by each UBB editable logic module further comprises:

[0013] When each GPU card is powered on successfully, controlling the mainboard editable logic module to receive a power-on reset success signal sent by each UBB editable logic module;

[0014] If the GPU card is abnormally powered off, the corresponding GPU editable logic module triggers a level jump signal; the UBB editable logic module receives the level jump signal, controls the GPU power of the GPU card to turn off, and sends a GPU card abnormal power-off signal to the mainboard editable logic module.

[0015] In one embodiment, when each GPU card is powered on successfully, after controlling the mainboard editable logic module to receive a power-on reset success signal sent by each UBB editable logic module, the method further includes:

[0016] The motherboard editable module is controlled to send a GPU power-off signal; the UBB editable logic module controls each UBB board to turn off the UBB power supply and all GPU power supplies according to the GPU power-off signal and sends a GPU normal power-off signal to the motherboard editable logic module.

[0017] In one embodiment, the mainboard further includes a mainboard power supply and mainboard components;

[0018] After the GPU BOX is connected to an external power supply, the microcontroller and the motherboard editable logic module on the motherboard are powered on; the motherboard editable logic module controls the motherboard power supply and the power-on of the motherboard components;

[0019] If the mainboard is abnormally powered off, the mainboard editable logic module is controlled to turn off the mainboard power supply.

[0020] In one embodiment, the UBB editable logic module is successfully powered on including:

[0021] If the mainboard editable logic module receives the power-on preparation signal sent by the UBB editable logic module within the set time period, the UBB editable logic module is powered on successfully.

[0022] In one embodiment, the UBB board further includes an HSC hybrid switch capacitor; and each of the UBB editable logic modules controls the corresponding GPU card to power on according to the GPU power-on signal, comprising:

[0023] Each of the UBB editable logic modules controls the HSC hybrid switch capacitor to be turned on, and the corresponding GPU card is powered on.

[0024] In one embodiment, after the mainboard editable logic module receives the power-on reset success signal sent by each of the UBB editable logic modules, the method further includes:

[0025] The motherboard editable logic module is controlled to send a GPU BOX power-on success signal to the server. The server sends a global reset signal to the GPU BOX based on the GPU BOX power-on success signal. The global reset signal is transparently transmitted through the UBB editable logic modules of each UBB board, synchronously initializes the registers and status of the PCIE devices corresponding to each GPU card, establishes a communication channel between the server and each GPU card, and initializes the working status between the server and each GPU card.

[0026] In a second aspect, the present application further provides a system for logically controlling a power-on reset timing of a GPU BOX, the system comprising a GPU BOX and a server, the GPU BOX being communicatively connected to the server;

[0027] The GPU BOX includes a mainboard and multiple UBB boards. The mainboard is electrically connected to each of the UBB boards. The mainboard includes a microcontroller and a mainboard editable logic module that are communicatively connected. The UBB board includes multiple GPU cards and a UBB editable logic module connected to each of the GPU cards. The GPU card includes a GPU editable logic module.

[0028] After the GPU BOX is connected to an external power supply, the microcontroller and the motherboard editable logic module on the motherboard are powered on;

[0029] The microcontroller of the mainboard is configured to collect the in-place status of each UBB board and control the corresponding UBB editable logic module to power on according to the in-place status; if the UBB editable logic module is successfully powered on, control the mainboard editable logic module to send a GPU power-on signal to each UBB editable logic module; each UBB editable logic module controls the corresponding GPU card to power on according to the GPU power-on signal; if each GPU card is successfully powered on, control the mainboard editable logic module to receive a power-on reset success signal sent by each UBB editable logic module; the power-on reset success signal is generated by each UBB editable logic module based on a power-on completion signal sent by each GPU editable logic module.

[0030] In a third aspect, the present application further provides an electronic device comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps corresponding to the method described in the first aspect when executing the computer program.

[0031] In the method, system, and electronic device for logically controlling the power-on reset sequence of a GPU BOX, after the GPU BOX is connected to an external power supply, the microcontroller and the motherboard editable logic module on the motherboard are powered on, the motherboard microcontroller collects the in-place status of each UBB board, and controls the corresponding UBB editable logic module to power on based on the in-place status. If the UBB editable logic module is successfully powered on, the motherboard editable logic module is controlled to send a GPU power-on signal to each UBB editable logic module. Each UBB editable logic module controls the corresponding GPU card to power on based on the GPU power-on signal. If each GPU card is successfully powered on, the motherboard editable logic module is controlled to receive a power-on reset success signal sent by each UBB editable logic module. The power-on reset success signal is generated by each UBB editable logic module based on the power-on completion signal sent by each GPU editable logic module, thereby implementing the power-on reset sequence controlled by the GPU BOX logic and ensuring that each board and GPU card is powered on normally. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 A block diagram of a system for controlling power-on reset timing by logic of a GPU BOX according to an embodiment;

[0033] Figure 2 A flowchart of a method for GPU BOX logic control of power-on reset timing in one embodiment;

[0034] Figure 3 FIG. 4 is a diagram showing the internal structure of an electronic device in one embodiment. DETAILED DESCRIPTION

[0035] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0036] Unless otherwise defined, the technical or scientific terms used in this application should have the ordinary meaning understood by a person of ordinary skill in the technical field to which this application belongs. The words "one", "a", "the" and the like used in this application do not indicate a limit on quantity and may indicate the singular or plural. The terms "include", "comprise", "have" and any variations thereof used in this application are intended to cover non-exclusive inclusions; for example, a process, method, system, product or device that includes a series of steps or modules (units) is not limited to the listed steps or units, but may also include steps or units that are not listed, or may also include other steps or units that are inherent to these processes, methods, products or devices. The words "connect", "connected", "coupled" and the like used in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The word "multiple" used in this application refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships can exist. For example, "A and / or B" can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects before and after are in an "or" relationship. The terms "first", "second", "third", etc. involved in this application are only used to distinguish similar objects and do not represent a specific order for the objects.

[0037] The method for GPU BOX logic control power-on reset timing provided in the embodiment of the present application can be applied to Figure 1 In the system shown, the GPU BOX logic controls the power-on reset timing. The GPU BOX terminal 102 communicates with the server 104 via a network. The server 104 can be implemented as an independent server or a server cluster consisting of multiple servers.

[0038] The GPU BOX includes a mainboard and a plurality of UBB boards, wherein the mainboard is electrically connected to the UBB boards and the GPU BOX is connected to the retimer card of the server via the mainboard.

[0039] The mainboard includes a microcontroller and a mainboard editable logic module, i.e., a mainboard CPLD, in communication with each other. The UBB board includes multiple GPU cards and a UBB editable logic module, i.e., a UBB CPLD, connected to each GPU card. The GPU card includes a GPU editable logic module, i.e., a GPU CPLD.

[0040] After the GPU BOX is connected to an external power source, the microcontroller and the motherboard editable logic module on the motherboard are powered on. The motherboard microcontroller is configured to: collect the in-place status of each UBB board and control the power-on of the corresponding UBB editable logic module based on the in-place status; if the UBB editable logic module is successfully powered on, control the motherboard editable logic module to send a GPU power-on signal to each UBB editable logic module; each UBB editable logic module controls the power-on of the corresponding GPU card based on the GPU power-on signal; if each GPU card is successfully powered on, control the motherboard editable logic module to receive a power-on reset success signal sent by each UBB editable logic module; the power-on reset success signal is generated by each UBB editable logic module based on the power-on completion signal sent by each GPU editable logic module.

[0041] In one embodiment, Figure 2 As shown, a method for GPU BOX logic control power-on reset timing is provided, and this method is applied to Figure 1 Taking the microcontroller of the motherboard as an example, the following steps are included:

[0042] Step 201 : collecting the in-place status of each UBB board, and controlling the corresponding UBB editable logic module to power on according to the in-place status.

[0043] Specifically, after the GPU BOX is connected to an external primary power supply, the microcontroller and the motherboard programmable logic module (CPLD) on the motherboard are directly powered on. However, the UBB boards are not powered on. After the motherboard CPLD is powered on and loaded, the motherboard checks whether the in-place status of each UBB board is at a low level. If so, the electrical connection between the UBB board and the motherboard is normal. The motherboard's microcontroller then inputs the external primary power supply to the corresponding UBB programmable logic module (UBB CPLD), powering it on.

[0044] Step 202 : When the UBB editable logic module is powered on successfully, control the mainboard editable logic module to send a GPU power-on signal to each of the UBB editable logic modules.

[0045] Specifically, when the UBB editable logic module, i.e., the UBB CPLD, is powered on successfully, the UBB CPLD will send a ready signal to the mainboard CPLD. The mainboard's microcontroller controls the mainboard CPLD to send a GPU power-on signal to each UBB CPLD. At this time, each UBB CPLD controls the corresponding GPU card to power on according to the GPU power-on signal.

[0046] Step 203 : When each GPU card is powered on successfully, control the mainboard editable logic module to receive a power-on reset success signal sent by each UBB editable logic module.

[0047] The power-on reset success signal is generated by each of the UBB editable logic modules based on the power-on completion signal sent by each of the GPU editable logic modules.

[0048] Specifically, after each GPU card is powered on, the GPU editable logic module (GPU CPLD) sends a power-on completion signal to the corresponding UBB editable logic module on the UBB board. Based on the power-on completion signal from each GPU card, the UBB editable logic module generates a power-on reset success signal corresponding to that UBB board. The motherboard editable logic module on the mainboard receives the power-on reset success signal from each UBB editable logic module, confirming that each GPU BOX board has completed the logic-controlled power-on sequence.

[0049] In the above-mentioned method for logically controlling power-on reset timing of a GPU BOX, after the GPU BOX is connected to an external power supply, the microcontroller and the motherboard editable logic module on the motherboard are powered on, the motherboard microcontroller collects the in-place status of each UBB board, and controls the corresponding UBB editable logic module to power on based on the in-place status; if the UBB editable logic module is successfully powered on, the motherboard editable logic module is controlled to send a GPU power-on signal to each UBB editable logic module; each UBB editable logic module controls the corresponding GPU card to power on based on the GPU power-on signal; if each GPU card is successfully powered on, the motherboard editable logic module is controlled to receive a power-on reset success signal sent by each UBB editable logic module; the power-on reset success signal is generated by each UBB editable logic module based on the power-on completion signal sent by each GPU editable logic module, thereby implementing the power-on reset timing controlled by the GPU BOX logic and ensuring that each board and GPU card is powered on normally.

[0050] In one embodiment, after the mainboard editable logic module receives the power-on reset success signal sent by each of the UBB editable logic modules in step 203, the method further includes:

[0051] The microcontroller controls the mainboard editable logic module to send a GPU BOX power-on success signal to the server. The server, in response to the GPU BOX power-on success signal, sends a global reset signal to the GPU BOX. This global reset signal is transparently transmitted through the UBB editable logic modules of each UBB board, synchronously resetting the PCIE devices corresponding to each GPU card, establishing and initializing communication channels between the server and each GPU card, and enabling normal operation between the server and each GPU card.

[0052] In this embodiment, after the GPU BOX is successfully powered on, a GPU BOX power-on success signal is sent to the server through the mainboard editable logic module. The global reset signal sent by the server initializes the registers and states of the PCIE devices corresponding to each GPU card on the GPU BOX, establishes a communication channel between the server and each GPU card, ensures normal timing between the GPU BOX and the server, and realizes normal communication between the GPU BOX and the server CPU.

[0053] In one embodiment, the UBB board further includes a UBB power supply and a GPU card power supply. Step 202 controls the motherboard editable logic module to send a GPU power-on signal to each of the UBB editable logic modules if the UBB editable logic module is successfully powered on, specifically including the following:

[0054] When the UBB editable logic module is powered on successfully, the mainboard editable logic module is controlled to send a GPU power-on signal to each of the UBB editable logic modules; each of the UBB editable logic modules controls the UBB power supply and GPU power supply of the corresponding UBB board to power on.

[0055] If the UBB board is abnormally powered off, the corresponding UBB editable logic module controls the UBB board to turn off the UBB power supply and the GPU power supply, and sends a UBB abnormal power-off signal to the mainboard editable logic module.

[0056] Specifically, after the UBB editable logic module is powered on, it powers on the UBB power supply and GPU card power supply on the UBB board. If a power failure occurs after the UBB power supply is powered on, the corresponding UBB editable logic module controls the UBB board to shut down the UBB power supply and GPU power supply. Simultaneously, the UBB editable logic module sends a UBB abnormal power-off signal to the mainboard editable logic module.

[0057] It should be noted that if the UBB power supply has a power-off abnormality after the server and the GPU card establish a communication connection, it is necessary to first pull down the global reset signal sent by the server to disable the clock output, and then control the UBB board to turn off the UBB power supply and the GPU power supply.

[0058] In this embodiment, when a UBB board is abnormally powered off, the UBB editable logic module responds promptly to protect the board from damage and receives the UBB abnormal power-off signal, so that the mainboard can read the abnormal point of the UBB board and quickly locate the abnormal position.

[0059] In one embodiment, step 203, when each GPU card is powered on successfully, controls the mainboard editable logic module to receive a power-on reset success signal sent by each UBB editable logic module, and further includes the following:

[0060] If each GPU card is successfully powered on, the motherboard editable logic module is controlled to receive a power-on reset success signal from each UBB editable logic module. If any GPU card experiences an abnormal power-off, the corresponding GPU editable logic module triggers a level transition signal. Upon receiving the level transition signal, the UBB editable logic module controls the GPU power supply of the GPU card to be turned off and transmits a GPU card abnormal power-off signal to the motherboard editable logic module.

[0061] Specifically, after each GPU card is powered on, if any GPU card experiences an abnormal power loss, the corresponding GPU editable logic module triggers a level transition signal. The UBB editable logic module on the corresponding UBB board then controls the GPU power supply of the GPU card and sends a GPU card abnormal power-off signal to the motherboard editable logic module on the mainboard. The other GPU cards on the UBB board are powered normally. When the abnormality is resolved, the UBB CPLD logic exits the fault state and powers the GPU card back on.

[0062] It should be noted that if the GPU card experiences a power-off exception after the server and the GPU card establish a communication connection, it is necessary to first pull down the global reset signal sent by the server to disable the clock output, and then the UBB editable logic module on the corresponding UBB board will turn off the GPU power supply.

[0063] In this embodiment, when a GPU card is abnormally powered off, the UBB editable logic module responds promptly to protect the entire UBB board from being affected, and receives the GPU card abnormal power-off signal, so that the mainboard can quickly locate the abnormal GPU card.

[0064] In one embodiment, in step 203, after the GPU cards are powered on successfully, controlling the mainboard editable logic module to receive a power-on reset success signal sent by each UBB editable logic module, the method further includes the following steps:

[0065] The motherboard editable module is controlled to send a GPU power-off signal; the UBB editable logic module controls each UBB board to turn off the UBB power supply and all GPU power supplies according to the GPU power-off signal and sends a GPU normal power-off signal to the motherboard editable logic module.

[0066] Specifically, after the server and the GPU card establish a communication connection and initialize and enter the working state, if the motherboard needs to actively close the communication connection, the microcontroller controls the motherboard editable module to send a GPU power-off signal to each UBB editable logic module, pulls down the global reset signal sent by the server, and prohibits clock output. The UBB editable logic module controls each UBB board in turn to turn off all GPU power supplies and UBB power supplies according to the GPU power-off signal, and at the same time sends a normal GPU power-off signal to the motherboard editable logic module.

[0067] In this embodiment, the GPU BOX is normally powered off by sending a GPU power-off signal via a mainboard microcontroller.

[0068] In one embodiment, the motherboard further includes a motherboard power supply and motherboard components. After the GPU BOX is connected to an external power source, the microcontroller and the motherboard editable logic module on the motherboard are powered on. The motherboard editable logic module then controls the motherboard power supply and the powering on of the motherboard components. If an abnormal power outage is detected after the motherboard power supply is powered on, the motherboard editable logic module is controlled to shut down the motherboard power supply.

[0069] It should be noted that no matter whether the motherboard power is turned off due to abnormal power failure of the motherboard or the motherboard power is turned off normally, the microcontroller and the motherboard editable logic control module on the motherboard will not be powered off.

[0070] In one embodiment, the UBB editable logic module is successfully powered on in step 202, specifically including:

[0071] If the mainboard editable logic module receives the power-on preparation signal sent by the UBB editable logic module within the set time period, the UBB editable logic module is powered on successfully.

[0072] In one embodiment, the UBB board further includes an HSC hybrid switched capacitor. Step 203 wherein each of the UBB editable logic modules controls the corresponding GPU card to power on according to the GPU power-on signal includes:

[0073] Each of the UBB editable logic modules controls the HSC hybrid switch capacitor to be turned on, and the corresponding GPU card is powered on.

[0074] In an exemplary embodiment, a method for controlling the power-on and power-off reset timing of a GPU BOX is provided, which is applied to the following example: Figure 1 The system shown includes the following:

[0075] After the GPU BOX is connected to an external primary power supply (PSU), the motherboard's microcontroller (BMC) and programmable logic module (CPLD) are powered directly. After the motherboard CPLD is loaded, the motherboard components are powered up sequentially according to the device design requirements. After the motherboard components are powered up, the BMC checks whether the in-place status of each UBB board is low. If so, the external primary power supply (PSU) is input to the corresponding UBB programmable logic module (UBBCPLD) to power it up.

[0076] After the UBB CPLD is successfully powered on, it sends a READY signal to the mainboard CPLD. The microcontroller BMC instructs the mainboard CPLD to send a GPU power-on signal to each UBB CPLD. Each UBB CPLD then powers on the corresponding UBB and GPU power supplies based on the GPU power-on signal. Powering on the GPU power supply also powers on the corresponding GPU CPLD and, consequently, the GPU card. If a power outage occurs after the UBB power supply is powered on, the corresponding UBB CPLD controls the UBB board to shut down both the UBB and GPU power supplies. Each UBB board has an I2C connection to the microcontroller BMC. The microcontroller BMC displays the health status of the UBB card in real time. If a UBB card fails, the corresponding UBB on the microcontroller BMC interface triggers a UBB exception event, facilitating quick and subsequent troubleshooting.

[0077] When each GPU card is powered on, the GPU CPLD sends a power-on completion signal to the UBBCPLD of the corresponding UBB board. The UBB CPLD generates a power-on reset success signal corresponding to the UBB board based on each power-on completion signal and sends it to the mainboard CPLD. If any GPU card loses power abnormally, the corresponding GPU CPLD triggers a level jump signal, and the UBB CPLD on the corresponding UBB board controls the GPU power of the GPU card to shut down. Each GPU card has a set of I2C connections to the microcontroller BMC. The microcontroller BMC will display the health status of the GPU card in real time. When the GPU card is abnormal, the corresponding GPU icon on the BMC interface will be suspended, and a GPU abnormality event will be triggered at the same time, facilitating subsequent rapid troubleshooting.

[0078] After all UBB boards send power-on reset success signals to the mainboard CPLD, the microcontroller controls the mainboard CPLD to send a GPU BOX power-on success signal to the server. Based on the GPU BOX power-on success signal, the server sends a global reset signal to the GPU BOX. This signal is transparently transmitted through the UBB editable logic modules of each UBB board, synchronously resetting the PCIe protocol corresponding to each GPU card, initializing the communication channel between the server and each GPU card, and entering normal communication mode.

[0079] It should be understood that, although the various steps in the flowcharts involved in the various embodiments described above are displayed in sequence according to the instructions of the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be executed in other orders. Moreover, at least a portion of the steps in the flowcharts involved in the various embodiments described above can include multiple steps or multiple stages, and these steps or stages are not necessarily executed and completed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a portion of steps or stages in other steps.

[0080] In one embodiment, an electronic device is provided. The electronic device may be a terminal, and its internal structure diagram may be as follows: Figure 3As shown. The electronic device includes a processor, a memory, an input / output interface, a communication interface, a display unit and an input device. The processor, the memory and the input / output interface are connected via a system bus, and the communication interface, the display unit and the input device are connected to the system bus via the input / output interface. The processor of the electronic device is used to provide computing and control capabilities. The memory of the electronic device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The input / output interface of the electronic device is used to exchange information between the processor and an external device. The communication interface of the electronic device is used to communicate with an external terminal in a wired or wireless manner, and the wireless manner can be achieved through WIFI, a mobile cellular network, NFC (near field communication) or other technologies. When the computer program is executed by the processor, a method for GPU BOX logic to control the power-on reset timing is implemented. The display unit of the electronic device is used to form a visually visible picture, which can be a display screen, a projection device or a virtual reality imaging device. The display screen can be a liquid crystal display screen or an electronic ink display screen, and the input device of the electronic device can be a touch layer covering the display screen, or a button, trackball or touchpad set on the electronic device casing, or an external keyboard, touchpad or mouse.

[0081] Those skilled in the art will understand that Figure 3 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the electronic device to which the solution of the present application is applied. The specific electronic device may include more or fewer components than shown in the figure, or combine certain components, or have a different component arrangement.

[0082] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps corresponding to the methods described in the above embodiments are implemented.

[0083] Those skilled in the art will appreciate that all or part of the processes in the above-mentioned embodiment methods can be implemented by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, database or other media used in the embodiments provided in this application may include at least one of non-volatile and volatile memory. Non-volatile memory may include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory may include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in the various embodiments provided herein may include at least one of a relational database and a non-relational database. Non-relational databases may include, but are not limited to, distributed databases based on blockchains. The processor involved in the various embodiments provided herein may be, but are not limited to, a general-purpose processor, a central processing unit, a graphics processing unit, a digital signal processor, a programmable logic unit, a data processing logic unit based on quantum computing, and the like.

[0084] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0085] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present application shall be determined by the appended claims.

Claims

1. A method for logically controlling power-on reset timing of a GPU box, wherein the GPU box comprises a mainboard and multiple UBB boards, the mainboard being electrically connected to the UBB boards, the mainboard comprising a microcontroller and a mainboard editable logic module in communication with each other; the UBB board comprising multiple GPU cards and a UBB editable logic module connected to each GPU card, the GPU card comprising a GPU editable logic module; after the GPU box is connected to an external power supply, the microcontroller and the mainboard editable logic module on the mainboard are powered on, characterized in that: The method comprises: The microcontroller collects the in-place status of each UBB board and controls the corresponding UBB editable logic module to power on according to the in-place status; When the UBB editable logic module is powered on successfully, controlling the mainboard editable logic module to send a GPU power-on signal to each of the UBB editable logic modules; each of the UBB editable logic modules controls the corresponding GPU card to power on according to the GPU power-on signal; When each GPU card is powered on successfully, the mainboard editable logic module is controlled to receive a power-on reset success signal sent by each UBB editable logic module; the power-on reset success signal is generated by each UBB editable logic module based on a power-on completion signal sent by each GPU editable logic module.

2. The method for GPU BOX logic control power-on reset timing according to claim 1, characterized in that: The UBB board further includes a UBB power supply and a GPU card power supply; when the UBB editable logic module is powered on successfully, controlling the mainboard editable logic module to send a GPU power-on signal to each of the UBB editable logic modules further includes: When the UBB editable logic module is powered on successfully, the mainboard editable logic module is controlled to send a GPU power-on signal to each of the UBB editable logic modules; each of the UBB editable logic modules controls the UBB power supply and GPU power supply of the corresponding UBB board to power on; If the UBB board is abnormally powered off, the corresponding UBB editable logic module controls the UBB board to turn off the UBB power supply and the GPU power supply, and sends a UBB abnormal power-off signal to the mainboard editable logic module.

3. The method for GPU BOX logic control power-on reset timing according to claim 2, characterized in that: When each GPU card is powered on successfully, controlling the mainboard editable logic module to receive a power-on reset success signal sent by each UBB editable logic module further comprises: When each GPU card is powered on successfully, controlling the mainboard editable logic module to receive a power-on reset success signal sent by each UBB editable logic module; If the GPU card is abnormally powered off, the corresponding GPU editable logic module triggers a level jump signal; the UBB editable logic module receives the level jump signal, controls the GPU power of the GPU card to turn off, and sends a GPU card abnormal power-off signal to the mainboard editable logic module.

4. The method for GPU BOX logic control power-on reset timing according to claim 3, characterized in that: When each GPU card is powered on successfully, after controlling the mainboard editable logic module to receive a power-on reset success signal sent by each UBB editable logic module, the method further includes: The motherboard editable logic module is controlled to send a GPU power-off signal; the UBB editable logic module controls each UBB board to turn off the UBB power supply and all GPU power supplies according to the GPU power-off signal and sends a GPU normal power-off signal to the motherboard editable logic module.

5. The method for GPU BOX logic control power-on reset timing according to claim 1, characterized in that: The mainboard also includes a mainboard power supply and mainboard components; After the GPU BOX is connected to an external power supply, the microcontroller and the motherboard editable logic module on the motherboard are powered on; the motherboard editable logic module controls the motherboard power supply and the power-on of the motherboard components; If the mainboard is abnormally powered off, the mainboard editable logic module is controlled to turn off the mainboard power supply.

6. The method for GPU BOX logic control power-on reset timing according to claim 1, characterized in that: The UBB editable logic module is successfully powered on including: If the mainboard editable logic module receives the power-on preparation signal sent by the UBB editable logic module within the set time period, the UBB editable logic module is powered on successfully.

7. The method for GPU BOX logic control power-on reset timing according to claim 1, characterized in that: The UBB board also includes an HSC hybrid switch capacitor; each of the UBB editable logic modules controls the corresponding GPU card to power on according to the GPU power-on signal, including: Each of the UBB editable logic modules controls the HSC hybrid switch capacitor to be turned on, and the corresponding GPU card is powered on.

8. The method for GPU BOX logic control power-on reset timing according to claim 1, characterized in that: After the mainboard editable logic module receives the power-on reset success signal sent by each of the UBB editable logic modules, the method further includes: The motherboard editable logic module is controlled to send a GPU BOX power-on success signal to the server. The server sends a global reset signal to the GPU BOX based on the GPU BOX power-on success signal. The global reset signal is transparently transmitted through the UBB editable logic modules of each UBB board, synchronously initializes the registers and status of the PCIE devices corresponding to each GPU card, establishes a communication channel between the server and each GPU card, and initializes the working status between the server and each GPU card.

9. A GPU BOX logic control power-on reset timing system, characterized in that: The system includes a GPU BOX and a server, wherein the GPU BOX is in communication with the server; The GPU BOX includes a mainboard and multiple UBB boards. The mainboard is electrically connected to each of the UBB boards. The mainboard includes a microcontroller and a mainboard editable logic module that are communicatively connected. The UBB board includes multiple GPU cards and a UBB editable logic module connected to each of the GPU cards. The GPU card includes a GPU editable logic module. After the GPU BOX is connected to an external power supply, the microcontroller and the motherboard editable logic module on the motherboard are powered on; The microcontroller of the mainboard is configured to collect the in-place status of each UBB board and control the corresponding UBB editable logic module to power on according to the in-place status; if the UBB editable logic module is successfully powered on, control the mainboard editable logic module to send a GPU power-on signal to each UBB editable logic module; each UBB editable logic module controls the corresponding GPU card to power on according to the GPU power-on signal; if each GPU card is successfully powered on, control the mainboard editable logic module to receive a power-on reset success signal sent by each UBB editable logic module; the power-on reset success signal is generated by each UBB editable logic module based on a power-on completion signal sent by each GPU editable logic module.

10. An electronic device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 8 are implemented.

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