A pre-stored pixel driving circuit for a dual-array substrate of a VA / TN panel

CN118747996BActive Publication Date: 2026-06-30CHENGDU JIUTIAN HUAXIN TECH CO LTD
View PDF 1 Cites 0 Cited by

Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
CHENGDU JIUTIAN HUAXIN TECH CO LTD
Filing Date
2024-08-21
Publication Date
2026-06-30

AI Technical Summary

Technical Problem

Traditional pixel driving circuits have difficulty in simultaneously achieving high refresh rates, long lamp duration, and high image quality consistency. In particular, in field sequence display technology, insufficient liquid crystal deflection time leads to inaccurate grayscale, excessive power consumption, and difficulty in achieving low-power dot reversal.

Method used

The pre-stored pixel driving circuit of the dual-array substrate used in VA/TN panels is adopted. By setting the pre-stored capacitor and the transistor, the gray level voltage is synchronously transferred when the backlight is off. Data signal writing and reset are performed on the upper and lower substrates respectively, reducing the liquid crystal deflection time and reducing power consumption by polarity reversal.

Benefits of technology

It achieves improved lighting time and image quality consistency at high refresh rates, reduces power consumption, enhances display effects and light transmittance, and simplifies driver complexity.

✦ Generated by Eureka AI based on patent content.

Smart Images

  • Figure CN118747996B_ABST
    Figure CN118747996B_ABST
Patent Text Reader

Abstract

This invention discloses a pre-stored pixel driving circuit for a dual-array substrate of a VA / TN panel, comprising: a first sub-circuit disposed on an upper substrate and a second sub-circuit disposed on a lower substrate, wherein both the upper and lower substrates are array substrates; the first sub-circuit is configured such that: the first source-drain of a first transistor is coupled to a first data signal line, and the second source-drain of a first transistor is coupled to the first source-drain of a second transistor and one end of a first pre-stored capacitor; the second source-drain of the second transistor is coupled to one end of a pixel capacitor; the second sub-circuit is configured such that: the first source-drain of a fourth transistor is coupled to a second data signal line, and the second source-drain of a fourth transistor is coupled to the first source-drain of a third transistor and one end of a second pre-stored capacitor; the second source-drain of the third transistor is coupled to the other end of the pixel capacitor.
Need to check novelty before this filing date? Find Prior Art