Multiphase Cross-Coupled Charge Pump IC

Abstract

The present invention relates to a multi-phase cross-coupled charge pump integrated circuit, comprising: an internal voltage stabilizing circuit and a charge pump system; wherein the charge pump system comprises: a charge pump core circuit and an output establishing circuit, the charge pump core circuit comprising a plurality of pump-up capacitors; the internal voltage stabilizing circuit is connected to an external battery voltage HV_VDD and is connected to an input end of the charge pump system, the charge pump system is connected to the external battery voltage HV_VDD, and the output end of the charge pump core circuit is connected to a first input end of the output establishing circuit; through the above technical scheme, a low potential voltage HV_GND is generated by using the internal voltage stabilizing circuit, the voltage difference is kept unchanged, and the working domain is increased to a high voltage, so that other circuits are designed by using low-voltage devices, the chip area is reduced, and the establishment state of the charge pump core circuit is output through the output establishing circuit, the charge pump core circuit can also be applied to a low-voltage domain to realize the function of voltage pumping, and the clock logic remains unchanged.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a multi-phase cross-coupled charge pump integrated circuit. Background Art

[0002] In analog circuits, the power module is a crucial part that directly affects the operation of the entire circuit. Currently, power chips can be divided into three categories: charge pumps (Gharge Pump), switching DC / DC converters, and low-dropout linear regulators.

[0003] The charge pump is also called a capacitive switching converter. Whether it is boosting or bucking, the capacitive switching converter can achieve the same effect as the inductive switching converter. However, due to the higher manufacturing cost, larger size, and electromagnetic interference of inductive components, the capacitive switching converter, namely the charge pump, will be more widely used in switching power supply circuits with smaller size, lower power consumption, and higher efficiency. Today, simple charge pump circuit modules with single output and single function can no longer meet market demand, and gradually tend to integrate more functions and provide more output circuit modules. From low-level industrial products to high-precision electronic products including automotive electronic products, medical electronic equipment, etc., charge pump systems are integrated internally. In the research of charge pump circuit systems, many researchers tend to consider how to increase the output voltage, improve pump efficiency and output stability when designing circuits. Summary of the invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a multi-phase cross-coupled charge pump integrated circuit.

[0005] According to a first aspect of an embodiment of the present invention, there is provided a multi-phase cross-coupled charge pump integrated circuit, the integrated circuit comprising: an internal voltage stabilization circuit and a charge pump system; wherein the charge pump system comprises: a charge pump core circuit and an output establishment circuit, the charge pump core circuit comprising a plurality of pump-up capacitors; the internal voltage stabilization circuit is connected to an external battery voltage HV_VDD, the output end of the internal voltage stabilization circuit is connected to the input end of the charge pump system, the charge pump system is connected to the external battery voltage HV_VDD, and the output end of the charge pump core circuit is connected to the first input end of the output establishment circuit;

[0006] The internal voltage stabilizing circuit is used to provide a low potential voltage HV_GND for the charge pump system by adjusting the values ​​of the internal resistance and the internal voltage; wherein the low potential voltage HV_GND is lower than the external battery voltage HV_VDD;

[0007] The charge pump core circuit is used to pump the external battery voltage HV_VDD through the multiple pump-up capacitors to obtain an output voltage CP_OUT;

[0008] The output establishment circuit is used to obtain the sampling voltage CP_SENSE1 and output a high-level judgment voltage CP_FLAG when the sampling voltage CP_SENSE1 is higher than a preset reference voltage to indicate that the charge pump establishment is completed.

[0009] Optionally, the charge pump core circuit includes: a first sub-circuit, a second sub-circuit, a third sub-circuit, a diode MP7, a diode MP8 and a diode MP9; wherein, the first sub-circuit is connected to the external battery voltage HV_VDD, the first sub-circuit, the second sub-circuit and the third sub-circuit are connected in series in sequence, the diode MP7 is connected in parallel at both ends of the first sub-circuit, the diode MP8 is connected in parallel at both ends of the second sub-circuit, and the diode MP9 is connected in parallel at both ends of the third sub-circuit.

[0010] Optionally, the first sub-circuit, the second sub-circuit and the third sub-circuit have the same structure, and all include: a diode MP1, a diode MN1, a diode MP2, a diode MN2, a diode MP3, a diode MN3, a diode MP4, a diode MN4, a diode MP5, a diode MN5, a diode MP6, a diode MN6, a capacitor C1, a pump-up capacitor C2, a capacitor C3, a capacitor C4, a pump-up capacitor C5, a capacitor C6, an inverter INV1, an inverter INV2, an inverter INV3 and an inverter INV4;The drain of the diode MN1 is connected to the drain of the diode MP1 and connected to the lower plate of the pumping capacitor C2, the source of the diode MP1 is connected to the external battery voltage HV_VDD, the gate of the diode MP1 is connected to the signal CPA0, the source of the diode MN1 is connected to the low potential voltage HV_GND, the gate of the diode MN1 is connected to the signal CPA1, the drain of the diode MN2 is connected to the drain of the diode MP2 and connected to the lower plate of the pumping capacitor C5, the source of the diode MP2 is connected to the external battery voltage HV_VDD, the gate of the diode MP2 is connected to the signal CPNA1, and the The source is connected to the low potential voltage HV_GND, the gate of the diode MN2 is connected to the signal CPNA0, the input of the inverter INV1 is connected to the signal CPNA1, the output of the inverter INV1 is connected to the lower plate of the capacitor C1, the input of the inverter INV2 is connected to the signal CPNA0, the output of the inverter INV2 is connected to the lower plate of the capacitor C3, the input of the inverter INV3 is connected to the signal CPA0, the output of the inverter INV3 is connected to the lower plate of the capacitor C4, the input of the inverter INV4 is connected to the signal CPA1, the output of the inverter INV4 is connected to the lower plate of the capacitor C6, and the The upper plate of capacitor C1 is connected to the drain of diode MN3, the upper plate of capacitor C1 is connected to the gate of diode MN4, the upper plate of capacitor C1 is connected to the gate of diode MN5, the upper plate of capacitor C3 is connected to the drain of diode MP3, the upper plate of capacitor C3 is connected to the gate of diode MP4, the upper plate of capacitor C3 is connected to the gate of diode MP5, the upper plate of capacitor C4 is connected to the drain of diode MN4, the upper plate of capacitor C4 is connected to the gate of diode MN3, the upper plate of capacitor C4 is connected to the gate of diode MN6, the upper plate of capacitor C6 is connected to the drain of diode MP ... gate of diode MN4, the upper plate of capacitor C4 is connected to the gate of diode MN3, the upper plate of capacitor C4 is connected to the gate of diode MN6, the upper plate of capacitor C6 is connected to the drain of diode MP4, the upper plate of capacitor C4 is connected to the gate of diode MN3, the upper plate of capacitor C4 is connected to the gate of diode MN6, the upper plate of capacitor C6 is connected to the drain of diode MP4, the upper plate of capacitor C4 is connected to the gate of diode MN The upper plate of capacitor C6 is connected to the gate of diode MP3, the upper plate of capacitor C6 is connected to the gate of diode MP6, the sources of diode MN3, diode MN4, diode MN5 and diode MN6 are all connected to the external battery voltage HV_VDD, the sources of diode MP3, diode MP4, diode MP5 and diode MP6 are all connected to the output voltage CP_OUT, the drain of diode MN5 is connected to the drain of diode MP5 and connected to the upper plate of pumping capacitor C2, the drain of diode MN6 is connected to the drain of diode MP6 and connected to the upper plate of pumping capacitor C5. ;

[0011] Optionally, the charge pump core circuit is further used to pump up the external battery voltage HV_VDD through respective pumping capacitors in the first sub-circuit, the second sub-circuit and the third sub-circuit to obtain the output voltage CP_OUT.

[0012] Optionally, the output establishing circuit includes: a sampling circuit and a judgment circuit;

[0013] The sampling circuit is used to sample according to the voltage D1 and the voltage D2 to obtain the sampled voltage CP_SENSE1; wherein the voltage D1 is the upper plate voltage of the capacitor C3 of the first sub-circuit in the charge pump core circuit, the voltage D2 is the upper plate voltage of the capacitor C6 of the first sub-circuit in the charge pump core circuit, and the voltage values ​​of the voltage D1 and the voltage D2 are obtained according to the output voltage of the first sub-circuit in the charge pump core circuit;

[0014] The judgment circuit is used to output the judgment voltage CP_FLAG of high potential when the sampling voltage CP_SENSE1 is higher than a preset reference voltage, so as to indicate that the charge pump is established.

[0015] Optionally, the charge pump system further comprises: an oscillator circuit; wherein the oscillator circuit is connected to the external battery voltage HV_VDD;

[0016] The oscillator circuit is used to obtain an initial voltage according to the external battery voltage HV_VDD and the low potential voltage HV_GND, and then use a multi-stage inverter to obtain a periodic square wave OSC_OUT to control a clock control circuit.

[0017] Optionally, the integrated circuit further comprises: a digital logic circuit; an input end of the digital logic circuit is connected to an input end of the charge pump system;

[0018] The digital logic circuit is used to generate an enable signal for controlling the charge pump system.

[0019] Optionally, the charge pump system further comprises: a clock control circuit; wherein the output end of the clock control circuit is respectively connected to the input end of the charge pump core circuit and the input end of the output establishment circuit, and the input end of the clock control circuit is connected to the output end of the oscillator circuit;

[0020] The clock control circuit is used to generate a 6-phase clock signal and a 4-phase clock signal according to the periodic square wave OSC_OUT; wherein the 6-phase clock signal is used to control the charge pump core circuit, and the 4-phase clock signal is used to control the output establishment circuit.

[0021] The technical solution provided by the present invention may include the following beneficial effects:

[0022] Through the above technical solution, compared with the traditional design for high-side switch drive, the present invention uses an internal voltage stabilization circuit to generate a low potential voltage as the high-voltage "ground" potential, keeps the voltage difference unchanged, and raises the working domain to high voltage, so that other circuits can use low-voltage devices for circuit design, which greatly reduces the chip area. The present invention outputs the establishment state of the charge pump core circuit through the output establishment circuit. In addition to the application in the high-voltage domain, the charge pump core circuit of the present invention can also be applied to the low-voltage domain to realize the function of voltage pumping, and the clock logic remains unchanged.

[0023] Other features and advantages of the present invention will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present invention but do not constitute a limitation of the present invention. In the accompanying drawings:

[0025] Figure 1 The diagram is a schematic structural diagram of a multi-phase cross-coupled charge pump integrated circuit according to an exemplary embodiment.

[0026] Figure 2 It is a schematic structural diagram of an internal voltage stabilization circuit according to an exemplary embodiment.

[0027] Figure 3 is a schematic structural diagram of a charge pump core circuit according to an exemplary embodiment.

[0028] Figure 4 It is a schematic structural diagram of a sub-circuit of a charge pump core circuit according to an exemplary embodiment.

[0029] Figure 5 The diagram is a timing relationship diagram of a 6-phase clock of a charge pump core circuit according to an exemplary embodiment.

[0030] Figure 6 It is a schematic diagram showing the structure of a sampling circuit according to an exemplary embodiment.

[0031] Figure 7 It is a schematic diagram showing the structure of a judgment circuit according to an exemplary embodiment.

[0032] Figure 8 The diagram is a schematic diagram showing the timing relationship of four-phase clocks of a sampling circuit according to an exemplary embodiment.

[0033] Fig. 9is a schematic structural diagram of an oscillator circuit according to an exemplary embodiment.

[0034] Fig.10 The diagram is a schematic structural diagram of a clock control circuit according to an exemplary embodiment.

[0035] Fig.11 is a schematic diagram of a simulation result according to an exemplary embodiment. DETAILED DESCRIPTION

[0036] Figure 1 is a schematic diagram showing the structure of a multi-phase cross-coupled charge pump integrated circuit according to an exemplary embodiment. Figure 1 As shown, the multi-phase cross-coupled charge pump integrated circuit 10 includes: an internal voltage regulator circuit 101 and a charge pump system 102; wherein the charge pump system 102 includes: a charge pump core circuit 1021 and an output establishment circuit 1022, and the charge pump core circuit 1021 includes a plurality of pump-up capacitors; the internal voltage regulator circuit 101 is connected to an external battery voltage HV_VDD, the output end of the internal voltage regulator circuit 101 is connected to the input end of the charge pump system 102, the charge pump system 1021 is connected to the external battery voltage HV_VDD, and the output end of the charge pump core circuit 1021 is connected to the first input end of the output establishment circuit 1022;

[0037] The internal voltage stabilization circuit 101 is used to provide a low potential voltage HV_GND for the charge pump system 102 by adjusting the values ​​of the internal resistance and the internal voltage; wherein the low potential voltage HV_GND is lower than the external battery voltage HV_VDD;

[0038] The charge pump core circuit 1021 is used to pump the external battery voltage HV_VDD through a plurality of pump-up capacitors to obtain an output voltage CP_OUT;

[0039] The output establishing circuit 1022 is used to obtain the sampling voltage CP_SENSE1 and output a high potential determination voltage CP_FLAG when the sampling voltage CP_SENSE1 is higher than a preset reference voltage to indicate that the charge pump establishment is completed.

[0040] It is understandable that if Figure 1 As shown, a multi-phase cross-coupled charge pump circuit structure is provided, which can be applied to a high-voltage drive switch. The voltage of the input 12 batteries is used as the external battery voltage HV_VDD and its voltage is pumped up through the charge pump core circuit to obtain an output voltage CP_OUT for driving the high-side charge and discharge switch tube.

[0041] Understandably, Figure 2 is a schematic diagram of the structure of an internal voltage stabilizing circuit according to an exemplary embodiment. Figure 2As shown, the internal voltage stabilizing circuit includes: diode MN1', diode MN2', diode MN3', diode MN4', diode MP1', diode MP2', diode MP3', diode MP4', diode MP5', diode MP6', diode MP7', current I1, capacitor C1', resistor R1', resistor R2', resistor R3', resistor R4', resistor R5', resistor R6'; the circuit mainly relies on negative feedback to clamp the voltage at point B' and point A' to be equal, and the voltage at point A' is:

[0042] V A' =HV_VDD-I1'·R1';

[0043] Due to the clamping effect of negative feedback, the voltage at point B' is equal to the voltage at point A'. A' Equal to the voltage V at point B' B' , so we can get the expression of low potential voltage HV_GND:

[0044]

[0045] It can be seen that the output voltage obtained by the circuit, that is, the low potential voltage HV_GND is a fixed value lower than the external battery voltage HV_VDD. By adjusting the size of the resistance current in the internal voltage stabilization circuit 101, the low potential voltage HV_GND can be made lower than the external battery voltage HV_VDD by a certain voltage. For example, the low potential voltage HV_GND can be made 5V lower than the external battery voltage HV_VDD, which serves as the "ground" potential of other modules, so that other modules can be designed using low-voltage devices.

[0046] Optionally, Figure 3 is a schematic diagram of a charge pump core circuit according to an exemplary embodiment. Figure 3 As shown, the charge pump core circuit includes: a first sub-circuit, a second sub-circuit, a third sub-circuit, a diode MP7, a diode MP8 and a diode MP9; wherein the first sub-circuit is connected to an external battery voltage HV_VDD, the first sub-circuit, the second sub-circuit and the third sub-circuit are connected in series in sequence, the diode MP7 is connected in parallel at both ends of the first sub-circuit, the diode MP8 is connected in parallel at both ends of the second sub-circuit, and the diode MP9 is connected in parallel at both ends of the third sub-circuit.

[0047] It can be understood that the first subcircuit, the second subcircuit and the third subcircuit are three 6-phase clock-controlled cross-coupled charge pumps, the first subcircuit, the second subcircuit and the third subcircuit are cascaded to form a charge pump core circuit, and the diodes MP7, MP8 and MP9 play a role in electrostatic protection.

[0048] Figure 4is a schematic diagram of a sub-circuit of a charge pump core circuit according to an exemplary embodiment. Figure 4As shown, the first sub-circuit, the second sub-circuit and the third sub-circuit have the same structure, and all include: a diode MP1, a diode MN1, a diode MP2, a diode MN2, a diode MP3, a diode MN3, a diode MP4, a diode MN4, a diode MP5, a diode MN5, a diode MP6, a diode MN6, a capacitor C1, a pump-up capacitor C2, a capacitor C3, a capacitor C4, a pump-up capacitor C5, a capacitor C6, an inverter INV1, an inverter INV2, an inverter INV3 and an inverter INV4; wherein, the drain of the diode MN1 is connected to the drain of the diode MP1 and connected to the lower plate of the pump-up capacitor C2, the source of the diode MP1 is connected to the external battery voltage HV_VDD, the gate of the diode MP1 is connected to the signal CPA0, the source of the diode MN1 is connected to the low potential voltage HV_GND, the gate of the diode MN1 is connected to the signal CPA1, the drain of the diode MN2 is connected to the drain of the diode MP2 and connected to the pump The lower plate of the pumping capacitor C5, the source of the diode MP2 is connected to the external battery voltage HV_VDD, the gate of the diode MP2 is connected to the signal CPNA1, the source of the diode MN2 is connected to the low potential voltage HV_GND, and the gate of the diode MN2 is connected to the signal CPNA0, which is used to control the pull-up and pull-down of the voltage of the lower plates of the pumping capacitor C2 and the pumping capacitor C5; the input end of the inverter INV1 is connected to the signal CPNA1, the output end of the inverter INV1 is connected to the lower plate of the capacitor C1, the input end of the inverter INV2 is connected to the signal CPNA0, the output end of the inverter INV2 is connected to the lower plate of the capacitor C3, the input end of the inverter INV3 is connected to the signal CPA0, the output end of the inverter INV3 is connected to the lower plate of the capacitor C4, the input end of the inverter INV4 is connected to the signal CPA1, and the output end of the inverter INV4 is connected to the lower plate of the capacitor C6, which is used to control the pull-up and pull-down of the voltage of the lower plates of the capacitors C1, C3, C4 and C6;The upper plate of capacitor C1 is connected to the drain of diode MN3, the upper plate of capacitor C1 is connected to the gate of diode MN4, the upper plate of capacitor C1 is connected to the gate of diode MN5, the upper plate of capacitor C3 is connected to the drain of diode MP3, the upper plate of capacitor C3 is connected to the gate of diode MP4, the upper plate of capacitor C3 is connected to the gate of diode MP5, the upper plate of capacitor C4 is connected to the drain of diode MN4, the upper plate of capacitor C4 is connected to the gate of diode MN3, the upper plate of capacitor C4 is connected to the gate of diode MN6, the upper plate of capacitor C6 is connected to the drain of diode MP4, and the upper plate of capacitor C6 is connected to diode The gate of MP3 and the upper plate of capacitor C6 are connected to the gate of diode MP6. The sources of diodes MN3, MN4, MN5 and MN6 are all connected to the external battery voltage HV_VDD. The sources of diodes MP3, MP4, MP5 and MP6 are all connected to the output voltage CP_OUT. The drain of diode MN5 is connected to the drain of diode MP5 and connected to the upper plate of pumping capacitor C2. The drain of diode MN6 is connected to the drain of diode MP6 and connected to the upper plate of pumping capacitor C5. D1 and D2 output the voltage of the upper plates of capacitors C3 and C6. Signals CPA0, CPA1, CPNA0, CPNA1, CP1 and CP2 are 6-phase clocks. The high levels of these six signals are all HV_VDD and the low levels are all HV_GND. ;

[0049] Optionally, the charge pump core circuit 1021 is further configured to pump up the external battery voltage HV_VDD through respective pumping capacitors in the first sub-circuit, the second sub-circuit and the third sub-circuit to obtain an output voltage CP_OUT.

[0050] Figure 5 is a schematic diagram showing the timing relationship of a 6-phase clock of a charge pump core circuit according to an exemplary embodiment, combined with Figure 4 and Figure 5Now let's briefly describe the basic principle of the charge pump core circuit. Before time t1, signal CPA0 is low, so the lower plate of capacitor C4 is high. The voltage at point B is charged to HV_VDD through diode MN4 in the previous cycle. When the voltage at the lower plate of capacitor C4 increases by 5V, the voltage at point B also increases by 5V. So at this time, the voltage at point B is HV_VDD+5V. Diodes MN6 and MN3 are turned on, and HV_VDD is input to charge point A. At the same time, signal CPNA1 is high at this time, so capacitor C 1 The lower plate voltage is low, and the potential of point A is maintained at HV_VDD. Diodes MN5 and MN4 are turned off. Similarly, the signal CPNA0 is high, so the voltage at point C is the output voltage CP_OUT'-5V of the sub-circuit. Diodes MP4 and MP5 are turned on, and the output CP_OUT' charges point D. At the same time, the signal CPA1 is low at this time, so the lower plate of capacitor C6 is high voltage, and the potential of point D is maintained at CP_OUT', so diodes MP6 and MP3 are turned off. Signal CP1 is connected to a low level through diode MN2 at this time, and signal CP2 is connected to a high level through diode MP1, so the voltage at point F is low, and the voltage at point E is high. For the cross-coupled tube, diodes MN6 and MP5 are turned on, and diodes MN5 and MP6 are turned off. The input HV_VDD charges point F, and point E charges the output CP_OUT'.

[0051] At time t1, signal CPA0 changes from low level to high level, and signal CPNA0 changes from high level to low level. Since the voltage across the capacitor cannot change suddenly, the voltage at point B drops to HV_VDD, and the voltage at point C rises to CP_OUT', so diodes MN6 and MN3 are turned off, and diodes MP5 and MP4 are turned off. At this time, signal CPA1 and signal CPNA1 remain unchanged, diodes MN1, MP1, MN2, and MP2 are all turned off, and signals CP1 and signal CP2 remain unchanged. Therefore, the potentials at points E and F remain unchanged, and there will be no reverse charge leakage during the shutdown process.

[0052] At time t2, signal CPA1 changes from low level to high level, and signal CPNA1 changes from high level to low level. Since the voltage across the capacitor cannot change suddenly, the voltage at point D drops to CP_OUT-5V, and the voltage at point A rises to HV_VDD+5V. Therefore, diodes MN5 and MN4 are turned on, and diodes MP6 and MP3 are turned on. At this time, signal CP2 decreases and signal CP1 increases. Therefore, the voltage at point E decreases to HV_VDD, and the potential at point F rises to HV_VDD+5V. The input HV_VDD charges point E, and point F charges the output CP_OUT'.

[0053] Similarly, at time t3, diodes MN4, MN5, MP6, and MP3 are turned off, the voltage at point A drops to HV_VDD, and the voltage at point D rises to CP_OUT'. At time t4, diodes MP5 and MN6 are turned on, the rising edge of CP2 arrives, and point E charges the output.

[0054] In summary, after the alternating pumping of the pumping capacitor C2 and the pumping capacitor C5, the output voltage CP_OUT' of each sub-circuit and the external battery voltage HV_VDD satisfy the following equation under ideal conditions:

[0055] CP_OUT'=HV_VDD+5V;

[0056] Among them, since three sub-circuits are cascaded, the final output voltage CP_OUT is 15V higher than the external battery voltage. Through the control of the 6-phase clock, all energy transmission paths are from input to output, which can greatly reduce reverse loss and improve the voltage conversion ratio.

[0057] Optionally, the output establishing circuit 1022 includes: a sampling circuit and a judgment circuit;

[0058] A sampling circuit, used for sampling according to voltage D1 and voltage D2 to obtain a sampling voltage CP_SENSE1; wherein voltage D1 is an upper plate voltage of capacitor C3 of the first sub-circuit in the charge pump core circuit, voltage D2 is an upper plate voltage of capacitor C6 of the first sub-circuit in the charge pump core circuit, and voltage values ​​of voltage D1 and voltage D2 are obtained according to the output voltage of the first sub-circuit;

[0059] The judgment circuit is used to output a high-potential judgment voltage CP_FLAG when the sampling voltage CP_SENSE1 is higher than a preset reference voltage, so as to indicate that the charge pump is established.

[0060] In one embodiment, Figure 6 is a schematic structural diagram of a sampling circuit according to an exemplary embodiment. Figure 7 is a schematic structural diagram of a judgment circuit according to an exemplary embodiment. Figure 8 FIG. 4 is a schematic diagram showing a timing relationship of a 4-phase clock of a sampling circuit according to an exemplary embodiment. Figure 6 , Figure 7 and Figure 8As shown, the output establishment circuit 1022 includes two parts: sampling and judging. The sampling circuit includes: diode MN7", diode MN8", diode MP7", diode MP8", diode MP9", diode MP10", diode MP11", capacitor C7", capacitor C8", capacitor C9", capacitor C10", capacitor C11", resistor R", inverter INV1", inverter INV2", inverter INV3" and inverter INV4"; the judging circuit includes: comparator comp, SMT, inverter INV1"'; CP_OUT' is the output voltage of the first sub-circuit, and the sampling circuit only samples the first sub-circuit of the charge pump core circuit, and D1 and D2 correspond to Figure 4 The high and low levels of D1, D2, D1, and D2 are CP_OUT' and CP_OUT'-5V respectively. By controlling the alternate conduction of diode MN7 and diode MN8, the low levels of D1 and D2 at CP_SENSE can be sampled. Resistors R'' and C11'' filter the output. The working principle of the sampling circuit is as follows: at time t4, the falling edge of the signal HI1 arrives, and the lower plate voltage of the capacitor C8" rises by 5V, so the upper plate voltage of the capacitor C8" rises from CP_OUT'-5V to CP_OUT'. At this time, D2 is CP_OUT'-5V, MN7 is turned on, and after clamp filtering, CP_SENSE1 is equal to CP_OUT'-5V; at time t5, the rising edge of the signal LO1 arrives, and the diode MP8" is turned on so that CP_OUT' charges the capacitor C8" to prevent the upper plate voltage from decreasing due to capacitor leakage. After the high level of the signal LO1 ends, the diode MP8" is turned off; at time t6, the rising edge of the signal HI1 arrives, the upper plate voltage of the capacitor C8" drops to CP_OUT'-5V, the diode MN7" is turned off, the diode MP7" is turned on, and CP_OUT' charges the capacitor C7" Electricity is prevented from decreasing the voltage on the upper plate due to capacitor leakage. Similarly, during t7-t9, the switch control circuit composed of capacitors C9", C10", diodes MP9", and diodes MP10" is controlled by clock signals HI0 and LO0, and diode MN8 is turned on, sampling the low-level voltage of D1 to make the sampled voltage CP_SENSE1 equal to CP_OUT'-5V. By alternately conducting diodes MN7 and MN8, the low levels of D1 and D2 are sampled. Ideally, the low levels of D1 and D2 are equal to CP_OUT'-5V, i.e., HV_VDD. The judgment circuit compares the sampled voltage CP_SENSE1 with the preset reference voltage ref_trim. If it is higher than the preset reference voltage ref_trim, the judgment voltage CP_FLAG outputs a high voltage, indicating that the charge pump has been established, otherwise it has not been established.

[0061] Optionally, the charge pump system further comprises: an oscillator circuit; wherein the oscillator circuit is connected to an external battery voltage HV_VDD;

[0062] The oscillator circuit is used to obtain an initial voltage according to an external battery voltage HV_VDD and a low potential voltage HV_GND, and then use a multi-stage inverter to obtain a periodic square wave OSC_OUT to control a clock control circuit.

[0063] Understandably, Fig. 9 is a schematic structural diagram of an oscillator circuit according to an exemplary embodiment. Fig. 9 As shown, the oscillator circuit includes: diode MN1"', diode MN2"', diode MN3"', diode MN4"', diode MN5"', diode MN6"', diode MN7"', diode MN8"', diode MN9"', diode MP1"', diode MP2"', diode MP3"', diode MP4"', diode MP5"', diode MP6"', diode MP7"', diode MP8"', diode MP9"', diode MP10"', diode MP11"', current Ibi as, current I1'', current I2'', switch S1'', switch S2'', switch S3'', switch S4'' and capacitor C1''; the oscillator circuit is composed of a three-level comparator, and the specific principle is as follows: Assuming that the voltage at point B'' is equal to HV_GND at the beginning, the voltage at point A'' is higher than that at point B'', the comparator outputs a low level, S1'', S4'' are turned on, S2'', S3'' are turned off, I1'' charges capacitor C1'', the voltage at point B'' rises, and the slope slope_rise is I1'' / C1''. At this time, the voltage at point A'' is recorded as VA1:

[0064]

[0065] When the voltage at point B”’ rises to VA1, the comparator outputs a high level, S2”’, S3”’ are turned on, S1”’, S4”’ are turned off, C1”’ discharges to the ground, and the voltage at point B”’ drops. The slope slope_fall is I2”’ / C1”’. At this time, the voltage at point A”’ is recorded as VA2:

[0066]

[0067] Therefore, the voltage at point B'' changes between VA1 and VA2, and becomes a periodic triangle wave. The comparator output is connected to a multi-stage inverter to increase the output drive capability of the circuit, and finally a periodic square wave is output with a period of T:

[0068]

[0069] After the period T is obtained, a periodic square wave OSC_OUT can be obtained, and the periodic square wave OSC_OUT is used to control the clock control circuit.

[0070] Optionally, the integrated circuit further comprises: a digital logic circuit; an input terminal of the digital logic circuit is connected to an input terminal of the charge pump system;

[0071] A digital logic circuit is used to generate an enable signal for controlling a charge pump system.

[0072] Optionally, the charge pump system further comprises: a clock control circuit; wherein the output end of the clock control circuit is respectively connected to the input end of the charge pump core circuit and the input end of the output establishment circuit, and the input end of the clock control circuit is connected to the output end of the oscillator circuit;

[0073] The clock control circuit is used to generate a 6-phase clock signal and a 4-phase clock signal according to the periodic square wave OSC_OUT; wherein the 6-phase clock signal is used to control the charge pump core circuit, and the 4-phase clock signal is used to control the output establishment circuit.

[0074] Understandably, Fig.10 is a schematic structural diagram of a clock control circuit according to an exemplary embodiment. Fig.10 As shown, the clock control circuit can generate a 6-phase clock in the charge pump core circuit and a 4-phase clock in the output establishment detection circuit.

[0075] In one embodiment, Fig.11 is a schematic diagram of a simulation result according to an exemplary embodiment. Fig.11 As shown in the simulation waveform diagram when the charge pump core circuit is mounted with a 10MΩ resistor, the output of the charge pump reaches 57V at 13.7ms. At this time, the output establishment circuit determines that the charge pump establishment is completed, and the voltage CP_FLAG outputs a high level. The charge pump output voltage is finally stabilized at 57.318V.

[0076] Through the above technical solution, compared with the traditional design for high-side switch drive, the present invention uses an internal voltage stabilization circuit to generate a low potential voltage as the high-voltage "ground" potential, keeps the voltage difference unchanged, and raises the working domain to high voltage, so that the submodule can use low-voltage devices for circuit design, greatly reducing the chip area. Compared with the general gate cross-coupled charge pump structure, the present invention uses a 6-phase clock to control each switch tube and pump-up capacitor, thereby avoiding reverse charge loss, and outputs the establishment state of the charge pump core circuit through sampling and judgment circuits. In addition to the application in the high-voltage domain, the charge pump core circuit of the present invention can also be applied to the low-voltage domain to realize the voltage pumping function, and the clock logic remains unchanged.

[0077] The preferred embodiments of the present invention are described in detail above in conjunction with the accompanying drawings. However, the present invention is not limited to the specific details in the above embodiments. Within the technical concept of the present invention, a variety of simple modifications can be made to the technical solution of the present invention, and these simple modifications all belong to the protection scope of the present invention.

[0078] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any appropriate manner without contradiction.

[0079] In order to avoid unnecessary repetition, the present invention will not further explain various possible combinations.

[0080] In addition, various embodiments of the present invention may be arbitrarily combined, and as long as they do not violate the concept of the present invention, they should also be regarded as the contents disclosed by the present invention.

Claims

1. A multi-phase cross-coupled charge pump integrated circuit, characterized in that: The integrated circuit includes: an internal voltage stabilizing circuit and a charge pump system; wherein the charge pump system includes: a charge pump core circuit and an output establishing circuit, the charge pump core circuit includes a plurality of pump-up capacitors; the internal voltage stabilizing circuit is connected to an external battery voltage HV_VDD, the output end of the internal voltage stabilizing circuit is connected to the input end of the charge pump system, the charge pump system is connected to the external battery voltage HV_VDD, and the output end of the charge pump core circuit is connected to the first input end of the output establishing circuit; the charge pump core circuit includes: a first sub-circuit, a second sub-circuit, a third sub-circuit, a diode MP7, a diode MP8 and a diode MP9; wherein the first sub-circuit is connected to the external battery voltage HV_VDD, the first sub-circuit, the third sub-circuit, a diode MP7, a diode MP8 and a diode MP9 The second subcircuit and the third subcircuit are connected in series in sequence, the diode MP7 is connected in parallel at both ends of the first subcircuit, the diode MP8 is connected in parallel at both ends of the second subcircuit, and the diode MP9 is connected in parallel at both ends of the third subcircuit; the first subcircuit, the second subcircuit and the third subcircuit have the same structure, and all include: diode MP1, diode MN1, diode MP2, diode MN2, diode MP3, diode MN3, diode MP4, diode MN4, diode MP5, diode MN5, diode MP6, diode MN6, capacitor C1, pump-up capacitor C2, capacitor C3, capacitor C4, pump-up capacitor C5, capacitor C6, inverter INV1, inverter INV2, inverter INV3 and inverter INV4;The drain of the diode MN1 is connected to the drain of the diode MP1 and connected to the lower plate of the pumping capacitor C2, the source of the diode MP1 is connected to the external battery voltage HV_VDD, the gate of the diode MP1 is connected to the signal CPA0, the source of the diode MN1 is connected to the low potential voltage HV_GND, the gate of the diode MN1 is connected to the signal CPA1, the drain of the diode MN2 is connected to the drain of the diode MP2 and connected to the lower plate of the pumping capacitor C5, the source of the diode MP2 is connected to the external battery voltage HV_VDD, the gate of the diode MP2 is connected to the signal CPNA1, the source of the diode MN2 is connected to the external battery voltage HV_VDD, the gate of the diode MP2 is connected to the signal CPNA1, and the source of the diode MN2 is connected to the external battery voltage HV_VDD. The gate of the diode MN2 is connected to the low potential voltage HV_GND, the gate of the diode MN2 is connected to the signal CPNA0, the input of the inverter INV1 is connected to the signal CPNA1, the output of the inverter INV1 is connected to the lower plate of the capacitor C1, the input of the inverter INV2 is connected to the signal CPNA0, the output of the inverter INV2 is connected to the lower plate of the capacitor C3, the input of the inverter INV3 is connected to the signal CPA0, the output of the inverter INV3 is connected to the lower plate of the capacitor C4, the input of the inverter INV4 is connected to the signal CPA1, the output of the inverter INV4 is connected to the lower plate of the capacitor C6, and the The upper plate of capacitor C1 is connected to the drain of diode MN3, the upper plate of capacitor C1 is connected to the gate of diode MN4, the upper plate of capacitor C1 is connected to the gate of diode MN5, the upper plate of capacitor C3 is connected to the drain of diode MP3, the upper plate of capacitor C3 is connected to the gate of diode MP4, the upper plate of capacitor C3 is connected to the gate of diode MP5, the upper plate of capacitor C4 is connected to the drain of diode MN4, the upper plate of capacitor C4 is connected to the gate of diode MN3, the upper plate of capacitor C4 is connected to the gate of diode MN6, the upper plate of capacitor C6 is connected to the drain of diode MP4, and the The upper plate of the capacitor C6 is connected to the gate of the diode MP3, the upper plate of the capacitor C6 is connected to the gate of the diode MP6, the sources of the diode MN3, the diode MN4, the diode MN5 and the diode MN6 are all connected to the external battery voltage HV_VDD, the sources of the diode MP3, the diode MP4, the diode MP5 and the diode MP6 are all connected to the output voltage CP_OUT, the drain of the diode MN5 is connected to the drain of the diode MP5 and connected to the upper plate of the pumping capacitor C2, the drain of the diode MN6 is connected to the drain of the diode MP6 and connected to the upper plate of the pumping capacitor C5; The internal voltage stabilizing circuit is used to provide a low potential voltage HV_GND for the charge pump system by adjusting the values ​​of the internal resistance and the internal voltage; wherein the low potential voltage HV_GND is lower than the external battery voltage HV_VDD; The charge pump core circuit is used to pump the external battery voltage HV_VDD through the multiple pump-up capacitors to obtain an output voltage CP_OUT; The output establishment circuit is used to obtain the sampling voltage CP_SENSE1 and output a high-level judgment voltage CP_FLAG when the sampling voltage CP_SENSE1 is higher than a preset reference voltage to indicate that the charge pump establishment is completed.

2. The multi-phase cross-coupled charge pump integrated circuit according to claim 1, characterized in that: The charge pump core circuit is further used to pump the external battery voltage HV_VDD through respective pumping capacitors in the first sub-circuit, the second sub-circuit and the third sub-circuit to obtain the output voltage CP_OUT.

3. The multi-phase cross-coupled charge pump integrated circuit according to claim 1, characterized in that: The output establishing circuit comprises: a sampling circuit and a judgment circuit; The sampling circuit is used to sample according to the voltage D1 and the voltage D2 to obtain the sampled voltage CP_SENSE1; wherein the voltage D1 is the upper plate voltage of the capacitor C3 of the first sub-circuit in the charge pump core circuit, the voltage D2 is the upper plate voltage of the capacitor C6 of the first sub-circuit in the charge pump core circuit, and the voltage values ​​of the voltage D1 and the voltage D2 are obtained according to the output voltage of the first sub-circuit in the charge pump core circuit; The judgment circuit is used to output the judgment voltage CP_FLAG of high potential when the sampling voltage CP_SENSE1 is higher than a preset reference voltage, so as to indicate that the charge pump is established.

4. The multi-phase cross-coupled charge pump integrated circuit according to claim 1, characterized in that: The charge pump system further comprises: an oscillator circuit; wherein the oscillator circuit is connected to the external battery voltage HV_VDD; The oscillator circuit is used to obtain an initial voltage according to the external battery voltage HV_VDD and the low potential voltage HV_GND, and then use a multi-stage inverter to obtain a periodic square wave OSC_OUT to control a clock control circuit.

5. The multi-phase cross-coupled charge pump integrated circuit according to claim 1, characterized in that: The integrated circuit further comprises: a digital logic circuit; an input end of the digital logic circuit is connected to an input end of the charge pump system; The digital logic circuit is used to generate an enable signal for controlling the charge pump system.

6. The multi-phase cross-coupled charge pump integrated circuit according to claim 4, characterized in that: The charge pump system further comprises: a clock control circuit; wherein the output end of the clock control circuit is respectively connected to the input end of the charge pump core circuit and the input end of the output establishment circuit, and the input end of the clock control circuit is connected to the output end of the oscillator circuit; The clock control circuit is used to generate a 6-phase clock signal and a 4-phase clock signal according to the periodic square wave OSC_OUT; wherein the 6-phase clock signal is used to control the charge pump core circuit, and the 4-phase clock signal is used to control the output establishment circuit.

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