A U-shaped temperature compensation reference voltage circuit

Abstract

The present invention relates to a U-shaped temperature compensation reference voltage circuit. The U-shaped temperature compensation reference voltage circuit includes a positive and negative temperature coefficient current generation circuit, a high temperature segment curvature compensation current generation circuit, a low temperature segment curvature compensation current generation circuit, and a reference voltage generation circuit. The positive and negative temperature coefficient current generation circuit generates currents with positive and negative temperature coefficients respectively, and the output is connected to the inputs of the high temperature segment curvature compensation current generation circuit and the low temperature segment curvature compensation current generation circuit. The high temperature segment curvature compensation current generation circuit and the low temperature segment curvature compensation current generation circuit can generate curvature compensation currents acting on different temperature segments, and the output currents are connected to the inputs of the reference voltage generation circuit. The reference voltage generation circuit adds the high and low temperature segment curvature compensation currents to generate a U-shaped temperature compensation current to compensate the reference voltage, so that the circuit can output a reference voltage with low temperature correlation.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and particularly relates to a U-shaped temperature compensation reference voltage circuit. Background Art

[0002] A reference voltage source is a circuit that can provide a stable output voltage when the process, power supply voltage, and temperature change. The reference voltage source is an important part of analog integrated circuits. In many integrated circuits, an accurate and stable voltage reference is required. The temperature stability design of the reference voltage circuit mainly adopts temperature compensation technology. A stable positive temperature coefficient voltage depends on being controlled in proportion to the thermal voltage V T , and a negative temperature coefficient voltage usually adopts the base-emitter conduction voltage V BE of a triode. By compensating the positive temperature coefficient voltage and the negative temperature coefficient voltage with each other, a reference voltage output with a nearly zero temperature coefficient can be obtained.

[0003] The positive temperature coefficient voltage and the negative temperature coefficient voltage are non-linear in the actual circuit, which results in the reference voltage curve often being in the shape of a parabola opening downward. In order to make the correlation between the reference voltage and temperature as small as possible, we need to perform curvature compensation on the reference voltage curve. The curvature compensation methods in the prior art usually use MOS transistors in the subthreshold region to generate a compensation curve. This method often cannot perform separate compensation according to the curvature at different temperatures. At the same time, the process consistency of this method is poor, and the correlation between the reference voltage and the process increases significantly. Summary of the Invention

[0004] Aiming at the technical problems of the prior art, the present invention provides a method for generating a U-shaped temperature compensation curve by combining the base-emitter conduction voltage of a triode and the gate-source voltage of a MOS transistor.

[0005] The technical solution adopted by the present invention to solve its technical problems is: a U-shaped temperature compensation reference voltage circuit, including a positive and negative temperature coefficient current generation circuit, a high-temperature section curvature compensation current generation circuit, a low-temperature section curvature compensation current generation circuit, and a reference voltage generation circuit;

[0006] The positive and negative temperature coefficient current generation circuit module is used to generate the positive and negative temperature coefficient currents required in the curvature compensation current. The first output terminal of the positive and negative temperature coefficient current generation circuit module is connected to the first input terminal of the low-temperature section curvature compensation current generation circuit. The second output terminal of the positive and negative temperature coefficient current generation circuit module is connected to the first input terminal of the high-temperature section curvature compensation current generation circuit. The third output terminal of the positive and negative temperature coefficient current generation circuit module is connected to the second input terminal of the low-temperature section curvature compensation current generation circuit. The fourth output terminal of the positive and negative temperature coefficient current generation circuit module is connected to the second input terminal of the high-temperature section curvature compensation current generation circuit;

[0007] The output terminal of the low-temperature section curvature compensation current generation circuit is connected to the first input terminal of the reference voltage generation circuit;

[0008] The output terminal of the high-temperature section curvature compensation current generation circuit is connected to the second input terminal of the reference voltage generation circuit;

[0009] The output terminal of the reference voltage generation circuit generates a reference voltage with low temperature drift characteristics.

[0010] Further, the positive and negative temperature coefficient current generation circuit module includes PMOS transistor M I1 , PMOS transistor M I2 , PMOS transistor M I3 , PMOS transistor M I4 , PMOS transistor M I5 , PMOS transistor M I6 , PMOS transistor M I7 , PMOS transistor M I8 , PMOS transistor M I9 , PMOS transistor M I10 , resistor R I1 , resistor R I2 , operational amplifier A1, operational amplifier A2, PNP transistor Q I1 and PNP transistor Q I2 . Among them, the source electrodes of PMOS transistor M I1 , PMOS transistor M I2 , PMOS transistor M I3 , PMOS transistor M I4 , PMOS transistor M I5 , PMOS transistor M I6 , PMOS transistor M I7 , PMOS transistor M I8 , PMOS transistor M I9 , PMOS transistor M I10 are connected to the power supply VDD, the drain electrode of PMOS transistor M I1 inputs the start-up current I start of the circuit module, the gate electrode of PMOS transistor M I1 is connected to the gate electrode of PMOS transistor M I2 and the drain electrode of PMOS transistor M I3 , the gate electrode of PMOS transistor M I3 is connected to the gate electrode of PMOS transistor M I4 , the gate electrode of PMOS transistor M I5 , the gate electrode of NMOS transistor M I6 , the gate electrode of PMOS transistor M I7is connected to the gate and the output terminal of the operational amplifier A1, and the drain of the PMOS transistor M I4 outputs the first output current I of the positive and negative temperature coefficient current generation circuit module PTAT1 , and the drain of the PMOS transistor M I5 outputs the second output current I of the positive and negative temperature coefficient current generation circuit module PTAT2 , and the drain of the PMOS transistor M I6 is connected to the positive input terminal of the operational amplifier A1 and one end of the resistor R I1 , and the other end of the resistor R I1 is connected to the drain of the PMOS transistor M I2 and the emitter of the PNP transistor Q I1 , and the drain of the PMOS transistor M I7 is connected to the negative input terminal of the operational amplifier A1, the negative input terminal of the operational amplifier A2, and the emitter of the PNP transistor Q I2 , and the emitter of the PNP transistor Q I1 , the base of the PNP transistor Q I1 , the collector of the PNP transistor Q I2 , the base of the PNP transistor Q I2 , and the collector of the PNP transistor Q are grounded, and the gate of the PMOS transistor M I8 is connected to the gate of the PMOS transistor M I9 , the gate of the PMOS transistor M I10 , and the output terminal of the operational amplifier A2, and the drain of the PMOS transistor M I8 is connected to the positive input terminal of the operational amplifier A2 and one end of the resistor R I2 , and the other end of the resistor R I2 is grounded, and the drain of the PMOS transistor M I9 outputs the third output current I of the positive and negative temperature coefficient current generation circuit module CTAT1 , and the drain of the PMOS transistor M I10 outputs the fourth output current I of the positive and negative temperature coefficient current generation circuit module PTAT2 .

[0011] Furthermore, the high temperature section curvature compensation current generation circuit and the low temperature section curvature compensation current generation circuit have the same structure. The module includes NMOS transistors M T1 , NMOS transistors M T2 , NMOS transistors M T3 , NMOS transistors M T4 , PMOS transistors M T5 , PMOS transistors M T6 , NMOS transistors M T7 , NMOS transistors M T8 , PMOS transistors M T9 , PMOS transistors MT10 and NMOS transistor M T11 and NMOS transistor M T12 and NPN transistor Q T1 and NPN transistor Q T2 and NPN transistor Q T3 . Among them, the source of NMOS transistor M T1 , the source of NMOS transistor M T2 , the source of NMOS transistor M T3 , the source of NMOS transistor M T4 , the source of NMOS transistor M T11 , the source of NMOS transistor M T12 , the source of NPN transistor Q T1 , the emitter of NPN transistor Q T2 , the emitter of NPN transistor Q T3 and the emitter are grounded. The source of PMOS transistor M T5 , the source of PMOS transistor M T6 , the drain of NMOS transistor M T7 , the drain of NMOS transistor M T8 , the source of PMOS transistor M T9 , the source of PMOS transistor M T10 is connected to the power supply VDD. The drain of NMOS transistor M T1 is connected to the gate of NMOS transistor M T1 and the gate of NMOS transistor M T2 . The drain of NMOS transistor M T3 is connected to the gate of NMOS transistor M T3 and the gate of NMOS transistor M T4 . The drain of NMOS transistor M T4 is connected to the drain of PMOS transistor M T5 , the gate of PMOS transistor M T5 and the gate of PMOS transistor M T6 . The drain of PMOS transistor M T6 is connected to the drain of PMOS transistor M T7 , the gate of PMOS transistor M T7 and the gate of PMOS transistor M T8 . The source of NMOS transistor M T7 is connected to the collector of NPN transistor Q T1 , the base of NPN transistor Q T1 and the base of NPN transistor Q T2 . The source of NMOS transistor M T8 is connected to the drain of NMOS transistor M T2 , the collector of NPN transistor Q T2 and the base of NPN transistor Q T3 . The NPN transistor QT3 The collector of is connected to the drain of PMOS transistor M T9 , the gate of PMOS transistor M T9 , and the gate of PMOS transistor M T10 . The drain of PMOS transistor M is connected to the drain of NMOS transistor M T10 , the gate of NMOS transistor M T11 , and the gate of NMOS transistor M T11 . Further, in the high-temperature-section curvature compensation current generation circuit, NMOS transistor M T12 inputs a negative temperature coefficient current, NMOS transistor M T1 inputs a positive temperature coefficient current, and NMOS transistor M T3 outputs a high-temperature-section curvature compensation current; further, in the low-temperature-section curvature compensation current generation circuit, NMOS transistor M T12 inputs a positive temperature coefficient current, NMOS transistor M T1 inputs a negative temperature coefficient current, and NMOS transistor M T3 outputs a low-temperature-section curvature compensation current. T12

[0012] Further, the reference voltage generation circuit module includes PMOS transistors M1, M2, M3, M4, M5, PNP transistors Q1, Q2, resistors R1, R2, R3, R4, R5, and operational amplifier A. The sources of PMOS transistors M1, M2, M3, M4, and M5 are connected to the power supply VDD. The gates of PMOS transistors M1, M2, and M3 and the output terminal of operational amplifier A are connected. The negative input terminal of the operational amplifier is connected to the drain of PMOS transistor M1, the emitter of PNP transistor Q1, and one end of resistor R3. The other end of resistor R3 is grounded. The bases and collectors of PNP transistors Q1 and Q2 are grounded. The positive input terminal of the operational amplifier is connected to the drain of PMOS transistor M2, one end of resistor R1, and one end of resistor R2. The other end of resistor R1 is connected to the emitter of PNP transistor Q2. The other end of resistor R2 is grounded. The drain of PMOS transistor M3 is the reference voltage output terminal, which is connected to one end of resistor R4. The other end of resistor R4 is connected to the drain of PMOS transistor M4 and one end of resistor R5. The other end of resistor R5 is grounded. The gates of PMOS transistors M4 and M5 and the drain of PMOS transistor M5 are connected. The drain of PMOS transistor M5 inputs positive and negative temperature coefficient currents and generates a U-shaped compensation current at the drain of PMOS transistor M4. Description of the Drawings

[0013] Figure 1 : Block diagram of the U-shaped temperature compensation reference voltage circuit provided by the embodiment of the present invention

[0014] Figure 2 : Schematic diagram of the positive and negative temperature coefficient current generation circuit provided by the embodiment of the present invention

[0015] Figure 3 : Schematic diagram of the high temperature segment curvature compensation current generation circuit and the low temperature segment curvature compensation current generation circuit provided by the embodiment of the present invention

[0016] Figure 4 : Schematic diagram of the reference voltage generation circuit provided by the embodiment of the present invention

[0017] Figure 5 : Simulation waveform diagram of the U-shaped compensation current provided by the embodiment of the present invention

[0018] Figure 6 : Simulation waveform diagram of the output voltage of the reference source of the embodiment of the present invention changing with temperature before and after compensation Detailed implementation manners

[0019] The following are specific embodiments of the present invention and, in combination with the accompanying drawings, the technical solutions of the present invention are further described, but the present invention is not limited to these embodiments.

[0020] The present invention provides a U-shaped temperature compensation reference voltage circuit. The U-shaped temperature compensation reference voltage circuit includes a positive and negative temperature coefficient current generation circuit, a high temperature segment curvature compensation current generation circuit, a low temperature segment curvature compensation current generation circuit, and a reference voltage generation circuit; the first output end of the positive and negative temperature coefficient current generation circuit module is connected to the first input end of the low temperature segment curvature compensation current generation circuit, and the second output end of the positive and negative temperature coefficient current generation circuit module is connected to the first input end of the high temperature segment curvature compensation current generation circuit; the third output end of the positive and negative temperature coefficient current generation circuit module is connected to the second input end of the low temperature segment curvature compensation current generation circuit, and the fourth output end of the positive and negative temperature coefficient current generation circuit module is connected to the second input end of the high temperature segment curvature compensation current generation circuit; the output end of the low temperature segment curvature compensation current generation circuit is connected to the first input end of the reference voltage generation circuit; the output end of the high temperature segment curvature compensation current generation circuit is connected to the second input end of the reference voltage generation circuit; the output end of the reference voltage generation circuit outputs the reference voltage after U-shaped current compensation.

[0021] As shown in the attached Figure 1As shown, the positive and negative temperature coefficient current generation circuit is used to generate two positive temperature coefficient currents and two negative temperature coefficient currents. One positive temperature coefficient current and one negative temperature coefficient current flow through the low temperature section curvature compensation current generation circuit to generate the exponentially decreasing current I acting on the low temperature section. exp1 The other positive temperature coefficient current and negative temperature coefficient current flow through the high temperature section curvature compensation current generation circuit to generate the exponentially increasing current I acting on the high temperature section. exp2 I exp1 and I exp2 flow into the reference voltage generation circuit to generate a U-shaped temperature compensation current, and a compensated reference voltage is obtained at the output terminal.

[0022] As shown in the appendix Figure 2 the positive and negative temperature coefficient current generation circuit module includes PMOS transistor M I1 , PMOS transistor M I2 , PMOS transistor M I3 , PMOS transistor M I4 , PMOS transistor M I5 , PMOS transistor M I6 , PMOS transistor M I7 , PMOS transistor M I8 , PMOS transistor M I9 , PMOS transistor M I10 , resistor R I1 , resistor R I2 , operational amplifier A1, operational amplifier A2, PNP transistor Q I1 and PNP transistor Q I2 . Among them, the source electrodes of PMOS transistor M I1 , PMOS transistor M I2 , PMOS transistor M I3 , PMOS transistor M I4 , PMOS transistor M I5 , PMOS transistor M I6 , PMOS transistor M I7 , PMOS transistor M I8 , PMOS transistor M I9 , PMOS transistor M I10 are connected to the power supply VDD, and the drain electrode of PMOS transistor M I1 inputs the start-up current I start of the circuit module. The gate electrode of PMOS transistor M I1 is connected to the gate electrode of PMOS transistor M I2 and the drain electrode of PMOS transistor M I3 . The gate electrode of PMOS transistor M I3 is connected to the gate electrode of PMOS transistor M I4 , the gate electrode of PMOS transistor MI5 and the gate of NMOS transistor M I6 and the gate of PMOS transistor M I7 are connected to the output terminal of operational amplifier A1. The drain of PMOS transistor M I4 outputs the first output current I of the positive and negative temperature coefficient current generation circuit module PTAT1 ; the drain of PMOS transistor M I5 outputs the second output current I of the positive and negative temperature coefficient current generation circuit module PTAT2 ; the drain of PMOS transistor M I6 is connected to the positive input terminal of operational amplifier A1 and one end of resistor R I1 . One end of resistor R I1 is connected to the drain of PMOS transistor M I2 and the emitter of PNP transistor Q I1 . The drain of PMOS transistor M I7 is connected to the negative input terminal of operational amplifier A1, the negative input terminal of operational amplifier A2 and the emitter of PNP transistor Q I2 . The base of PNP transistor Q I1 , the collector of PNP transistor Q I1 , the base of PNP transistor Q I2 and the collector of PNP transistor Q I2 are grounded. The gate of PMOS transistor M I8 is connected to the gate of PMOS transistor M I9 , the gate of PMOS transistor M I10 and the output terminal of operational amplifier A2. The drain of PMOS transistor M I8 is connected to the positive input terminal of operational amplifier A2 and one end of resistor R I2 . One end of resistor R I2 is grounded. The drain of PMOS transistor M I9 outputs the third output current I of the positive and negative temperature coefficient current generation circuit module CTAT1 ; the drain of PMOS transistor M I10 outputs the fourth output current I of the positive and negative temperature coefficient current generation circuit module PTAT2 .

[0023] In the attached Figure 2 circuit shown, PMOS transistors M I4 , PMOS transistors M I5 , PMOS transistors M I6 and PMOS transistors M I7 are of exactly the same size. The emitter area of PNP transistor Q I2 is n times that of PNP transistor Q I1 , where n = 8. Then the current flowing through PMOS transistor M I4, PMOS transistor M I5 , PMOS transistor M I6 and PMOS transistor M I7 has a current of

[0024]

[0025] where R I1 is the resistance value of resistor R I1 , V T is the thermal voltage proportional to temperature. Therefore, the current is a current with a positive temperature coefficient.

[0026] PMOS transistor M I8 , PMOS transistor M I9 and PMOS transistor M I10 have exactly the same size. Then the currents flowing through PMOS transistor M I8 , PMOS transistor M I9 , PMOS transistor M I10 are

[0027]

[0028] where V BEI2 is the base-emitter voltage of PNP transistor Q I2 , R I2 is the resistance value of resistor R I2 . The base-emitter voltage has a negative temperature characteristic. Therefore, the current is a current with a negative temperature coefficient.

[0029] As shown in the appendix Figure 3 , the high-temperature section curvature compensation current generation circuit and the low-temperature section curvature compensation current generation circuit have the same structure. The module includes NMOS transistor M T1 , NMOS transistor M T2 , NMOS transistor M T3 , NMOS transistor M T4 , PMOS transistor M T5 , PMOS transistor M T6 , NMOS transistor M T7 , NMOS transistor M T8 , PMOS transistor M T9 , PMOS transistor M T10 , NMOS transistor M T11 , NMOS transistor M T12 , NPN transistor Q T1 , NPN transistor Q T2 and NPN transistor Q T3 . Among them, the source of NMOS transistor M T1 , the source of NMOS transistor M T2 , the source of NMOS transistor M T3The source of, NMOS transistor M T4 The source of, NMOS transistor M T11 The source of, NMOS transistor M T12 The source of, NPN transistor Q T1 The emitter of, NPN transistor Q T2 The emitter and NPN transistor Q T3 The emitter is grounded. PMOS transistor M T5 The source of, PMOS transistor M T6 The source of, NMOS transistor M T7 The drain of, NMOS transistor M T8 The drain of, PMOS transistor M T9 The source of, PMOS transistor M T10 The source is connected to the power supply VDD, NMOS transistor M T1 The drain of is connected to the NMOS transistor M T1 The gate of and NMOS transistor M T2 The gates are connected, NMOS transistor M T3 The drain of is connected to the NMOS transistor M T3 The gate of and NMOS transistor M T4 The gates are connected, NMOS transistor M T4 The drain of is connected to the PMOS transistor M T5 The drain of, PMOS transistor M T5 The gate of and PMOS transistor M T6 The gates are connected, PMOS transistor M T6 The drain of and PMOS transistor M T7 The drain of, PMOS transistor M T7 The gate of and PMOS transistor M T8 The gates are connected, NMOS transistor M T7 The source of is connected to the NPN transistor Q T1 The collector of, NPN transistor Q T1 The base of and NPN transistor Q T2 The bases are connected, NMOS transistor M T8 The source of is connected to the NMOS transistor M T2 The drain of, NPN transistor Q T2 The collector of and NPN transistor Q T3 The bases are connected, NPN transistor Q T3 The collector of is connected to the PMOS transistor M T9 The drain of, PMOS transistor M T9 The gate of and PMOS transistor M T10 The gates are connected, PMOS transistor M T10 The drain of is connected to the NMOS transistor M T11 The drain of, NMOS transistor M T11 The gate of and NMOS transistor M T12is connected to the gate. Further, in the high-temperature section curvature compensation current generation circuit, the NMOS transistor M T1 inputs a negative temperature coefficient current, and the NMOS transistor M T3 inputs a positive temperature coefficient current. The NMOS transistor M T12 outputs a high-temperature section curvature compensation current. Further, in the low-temperature section curvature compensation current generation circuit, the NMOS transistor M T1 inputs a positive temperature coefficient current, and the NMOS transistor M T3 inputs a negative temperature coefficient current. The NMOS transistor M T12 outputs a low-temperature section curvature compensation current.

[0030] Attached Figure 3 In the shown circuit, the width-to-length ratio of the NMOS transistor M T2 is m1 times that of the NMOS transistor M T1 . The width-to-length ratio of the PMOS transistor M T6 is m2 times that of the PMOS transistor MT5, where m1 = 8 and m2 = 13. The NMOS transistors M T3 and M T4 have exactly the same size. The NMOS transistors M T7 and M T8 have exactly the same size. The emitter area of the NPN transistor Q T1 is k times that of the NPN transistor Q I2 , where k = 8. The NPN transistors Q T1 and Q T3 have exactly the same size. The gate-source voltage difference V T7 of the NMOS transistor M GST7 and the gate-source voltage difference V T8 of the NMOS transistor M GST8 have the following relationship

[0031] V GST7 + V BET1 = V GST8 + V BET3

[0032] In the formula, V BET1 is the base-emitter voltage of the NPN transistor Q T1 , and V BET3 is the base-emitter voltage of the NPN transistor Q T3 . Further,

[0033]

[0034] In the formula, I CT1 is the collector current of the NPN transistor Q T1 , and I CT3 is the collector current of the NPN transistor QT3 collector current, I T7 is the current flowing through NMOS transistor M T7 current, I T9 is the current flowing through NMOS transistor M T9 Current flowing through NMOS transistor M T8 current I T8 is

[0035]

[0036] where I T1 is the current flowing through NMOS transistor M T1 current, I T3 is the current flowing through NMOS transistor M T3 current, I BT3 is the base current of NPN transistor Q T3 where

[0037]

[0038] where β is the common-emitter current gain

[0039] Furthermore, the relationship between the gate-source voltage difference V T7 of NMOS transistor M GST7 and the gate-source voltage difference V GST8 of NMOS transistor MT8 can be expressed as

[0040]

[0041] where μ n is the electron mobility, C ox is the gate oxide capacitance per unit area, W n / L n is the width-to-length ratio of NMOS transistor M T7 and M T8 Current flowing through NMOS transistor M T9 current I T9 can be expressed as

[0042]

[0043] Current flowing through NMOS transistor M T9 current I T9 can be expressed as a combination of input current I T1 and I T3 By adjusting the values of m1 and m2, a current with an exponential shape with respect to temperature change can be obtained.

[0044] In the low-temperature section curvature compensation current generation circuit, the current I T1 input to NMOS transistor M T1is a positive temperature coefficient current and the current I input by the NMOS transistor MT3 T3 is a negative temperature coefficient current. At this time, the NMOS transistor M T12 outputs the current I T12 is a compensation current that decreases exponentially and acts on the low temperature end.

[0045] In the curvature compensation current generation circuit in the high temperature section, the current I input by the NMOS transistor M T1 is a negative temperature coefficient current and the current I input by the NMOS transistor M T1 is a positive temperature coefficient current. At this time, the NMOS transistor M T3 outputs the current I T3 is a compensation current that increases exponentially and acts on the high temperature end. T12 is a compensation current that increases exponentially and acts on the high temperature end. T12 As shown in the attached

[0046] As shown in the attached Figure 4 figure, the reference voltage generation circuit module includes PMOS transistors M1, M2, M3, M4, M5, PNP transistors Q1, Q2, resistors R1, R2, R3, R4, R5, and operational amplifier A. The sources of PMOS transistors M1, M2, M3, M4, and M5 are connected to the power supply VDD. The gates of PMOS transistors M1, M2, and M3 and the output terminal of the operational amplifier A are connected. The negative input terminal of the operational amplifier is connected to the drain of PMOS transistor M1, the emitter of PNP transistor Q1, and one end of resistor R3. The other end of resistor R3 is grounded. The bases and collectors of PNP transistors Q1 and Q2 are grounded. The positive input terminal of the operational amplifier is connected to the drain of PMOS transistor M2, one end of resistor R1, and one end of resistor R2. The other end of resistor R1 is connected to the emitter of PNP transistor Q2. The other end of resistor R2 is grounded. The drain of PMOS transistor M3 is the reference voltage output terminal, which is connected to one end of resistor R4. The other end of resistor R4 is connected to the drain of PMOS transistor M4 and one end of resistor R5. The other end of resistor R5 is grounded. The gates of PMOS transistors M4 and M5 and the drain of PMOS transistor M5 are connected. The drain of PMOS transistor M5 inputs positive and negative temperature coefficient currents and generates a U-shaped compensation current at the drain of PMOS transistor M4.

[0047] Attached Figure 4In the shown circuit, the sizes of PMOS transistor M1, PMOS transistor M2, and PMOS transistor M3 are exactly the same, the sizes of PMOS transistor M4 and PMOS transistor M5 are exactly the same, and the emitter area of PNP transistor Q2 is m times that of PNP transistor Q1, where m = 8. The reference voltage V without U-shaped current compensation REF0 can be expressed as

[0048]

[0049] where R1 is the resistance value of resistor R1, R2 is the resistance value of resistor R2, R3 is the resistance value of resistor R3, R4 is the resistance value of resistor R4, R5 is the resistance value of resistor R5, and V BE1 is the base-emitter voltage of PNP transistor Q1. The curvature compensation current in the high temperature section and the curvature compensation current in the low temperature section are added at PMOS transistor M5 to obtain the U-shaped curvature compensation current I U , and the U-shaped current acts on resistor R5 through the current mirror to obtain the compensated reference voltage V REF which can be expressed as

[0050]

[0051] The U-shaped curvature compensation current generated in the reference voltage generation circuit provided by the embodiment of the present invention refers to Appendix Figure 5 . Where the abscissa is the temperature T and the ordinate is the value of the U-shaped temperature compensation current. In the operating temperature range, the current shows an exponential decreasing trend in the low temperature section and an exponential increasing trend in the high temperature section, presenting an overall U-shaped curve.

[0052] Appendix Figure 6 is the temperature characteristic simulation curve of a reference voltage circuit with U-shaped temperature compensation based on BCD process of the present invention, where the abscissa is the temperature T and the ordinate is the output voltage of the reference voltage. V REF0 and V REF are the reference output voltages before and after compensation respectively. After compensation by the U-shaped curvature compensation current, the fluctuation of the reference voltage with temperature is significantly suppressed. Thus, it can be seen that the U-shaped temperature compensation circuit provided by the present invention can effectively reduce the temperature dependence of the reference output voltage.

[0053] The specific embodiments described herein are merely illustrative of the spirit of the present invention. Those skilled in the art of the present invention can make various modifications or supplements to the described specific embodiments or use similar ways to substitute, but will not deviate from the spirit of the present invention or exceed the scope defined by the appended claims.

Claims

1. A U-shaped temperature compensation reference voltage circuit, characterized in that, Comprising: A positive and negative temperature coefficient current generation circuit, a high temperature section curvature compensation current generation circuit, a low temperature section curvature compensation current generation circuit, and a reference voltage generation circuit; The positive and negative temperature coefficient current generation circuit module is used to be connected to the high temperature section curvature compensation current generation circuit and the low temperature section curvature compensation current generation circuit to generate the positive and negative temperature coefficient currents required in the high and low temperature curvature compensation currents; the output end of the high temperature section curvature compensation current generation circuit is connected to the first input end of the reference voltage generation circuit to generate a curvature compensation current acting on the high temperature section; the output end of the low temperature section curvature compensation current generation circuit is connected to the second input end of the reference voltage generation circuit to generate a curvature compensation current acting on the low temperature section; The reference voltage generation circuit generates a U-shaped temperature compensation current by adding the high and low temperature section curvature compensation currents to compensate the reference voltage, so as to generate a reference voltage with low temperature drift characteristics at the output end; The positive and negative temperature coefficient current generation circuit module includes PMOS transistor M I1 , PMOS transistor M I2 , PMOS transistor M I3 , PMOS transistor M I4 , PMOS transistor M I5 , PMOS transistor M I6 , PMOS transistor M I7 , PMOS transistor M I8 , PMOS transistor M I9 , PMOS transistor M I10 , resistor R I1 , resistor R I2 , operational amplifier A1, operational amplifier A2, PNP transistor Q I1 , PNP transistor Q I2 ; The source electrodes of the PMOS transistor M I1 , the source electrodes of the PMOS transistor M I2 , the source electrodes of the PMOS transistor M I3 , the source electrodes of the PMOS transistor M I4 , the source electrodes of the PMOS transistor M I5 , the source electrodes of the PMOS transistor M I6 , the source electrodes of the PMOS transistor M I7 , the source electrodes of the PMOS transistor M I8 , the source electrodes of the PMOS transistor M I9 , the source electrodes of the PMOS transistor M I10 are connected to the power supply VDD. The drain electrode of the PMOS transistor M I1 inputs the start current I start . The gate electrode of the PMOS transistor M I1 is connected to the gate electrode of the PMOS transistor M I2 and the drain electrode of the PMOS transistor M I3 . The gate electrode of the PMOS transistor M I3 is connected to the gate electrode of the PMOS transistor M I4 , the gate electrode of the PMOS transistor M I5 , the gate electrode of the PMOS transistor M I6 , the gate electrode of the PMOS transistor M I7 , and the output terminal of the operational amplifier A1. The drain electrode of the PMOS transistor M I4 outputs the first output current I PTAT1 . The drain electrode of the PMOS transistor M I5 outputs the second output current I PTAT2 . The drain electrode of the PMOS transistor M I6 is connected to one end of the resistor R I1 at the positive input terminal of the operational amplifier A1. Resistor R I1 The other end is connected to the PMOS transistor M I2 's drain, the PNP transistor Q I1 's emitter. The drain of the PMOS transistor M I7 is connected to the negative input terminal of the operational amplifier A1, the negative input terminal of the operational amplifier A2, and the emitter of the PNP transistor Q I2 's emitter. The base of the PNP transistor Q I1 is grounded, the collector of the PNP transistor Q I1 is grounded, the base of the PNP transistor Q I2 is grounded, the collector of the PNP transistor Q I2 is grounded. The gate of the PMOS transistor M I8 is connected to the gate of the PMOS transistor M I9 is connected to the gate of the PMOS transistor M I10 is connected to the output terminal of the operational amplifier A2. The drain of the PMOS transistor M I8 is connected to the positive input terminal of the operational amplifier A2 and one end of the resistor R I2 One end of the resistor R I2 is grounded. The drain of the PMOS transistor M I9 outputs the third output current I CTAT1 The drain of the PMOS transistor M I10 outputs the fourth output current I PTAT2 .

2. The U-shaped temperature compensation reference voltage circuit according to claim 1, wherein The emitter area of the PNP transistor Q I2 is n times that of the PNP transistor Q I1 . The current flowing through the PMOS transistors M I4 , M I5 , M I6 and M I7 is a current with a positive temperature coefficient, and the current flowing through the PMOS transistors M I8 , M I9 and M I10 is a current with a negative temperature coefficient.

3. A U-shaped temperature compensation reference voltage circuit according to claim 1, characterized in that, The high-temperature curvature compensation current generation circuit and the low-temperature curvature compensation current generation circuit both include NMOS transistor M T1 , NMOS transistor M T2 , NMOS transistor M T3 , NMOS transistor M T4 , PMOS transistor M T5 , PMOS transistor M T6 , NMOS transistor M T7 , NMOS transistor M T8 , PMOS transistor M T9 , PMOS transistor M T10 , NMOS transistor M T11 , NMOS transistor M T12 , NPN transistor Q T1 , NPN transistor Q T2 , NPN transistor Q T3 ; the source of the NMOS transistor M T1 , the source of the NMOS transistor M T2 , the source of the NMOS transistor M T3 , the source of the NMOS transistor M T4 , the source of the NMOS transistor M T11 , the source of the NMOS transistor M T12 , the emitter of the NPN transistor Q T1 , the emitter of the NPN transistor Q T2 , the emitter of the NPN transistor Q T3 are grounded, the source of the PMOS transistor M T5 , the source of the PMOS transistor M T6 , the drain of the NMOS transistor M T7 , the drain of the NMOS transistor M T8 , the source of the PMOS transistor M T9 , the source of the PMOS transistor M T10 are connected to the power supply VDD, the drain of the NMOS transistor M T1 is connected to the gate of the NMOS transistor M T1 , the gate of the NMOS transistor M T2 ; the drain of the NMOS transistor M T3 is connected to the gate of the NMOS transistor M T3 , the gate of the NMOS transistor M T4 ; the drain of the NMOS transistor M T4 is connected to the drain of the PMOS transistor M T5 , the gate of the PMOS transistor M T5 , the gate of the PMOS transistor M T6 ; the PMOS transistor M T6 The drain of and PMOS transistor M T7 The drain of, the PMOS transistor M T7 The gate of, PMOS transistor M T8 The gate is connected to, the NMOS transistor M T7 The source of is connected to the NPN transistor Q T1 The collector of, the NPN transistor Q T1 The base of, the NPN transistor Q T2 The base is connected to, the NMOS transistor M T8 The source of is connected to the NMOS transistor M T2 The drain of, the NPN transistor Q T2 The collector of, the NPN transistor Q T3 The base is connected to, the NPN transistor Q T3 The collector of is connected to the PMOS transistor M T9 The drain of, the PMOS transistor M T9 The gate of, and the gate of the PMOS transistor M T10 The gate is connected to, the PMOS transistor M T10 The drain of is connected to the NMOS transistor M T11 The drain of, the NMOS transistor M T11 The gate of, the NMOS transistor M T12 The gate is connected.

4. A U-shaped temperature compensation reference voltage circuit according to claim 3, characterized in that, The width-to-length ratio of the NMOS transistor M T2 is m1 times that of the NMOS transistor M T1 . The width-to-length ratio of the PMOS transistor MT6 is m2 times that of the PMOS transistor M T5 . The emitter area of the NPN transistor Q T1 is k times that of the NPN transistor Q T2 . The current I T9 flowing through the NMOS transistor M T9 varies exponentially with temperature.

5. A U-shaped temperature compensation reference voltage circuit according to claim 4, characterized in that, In the low-temperature section curvature compensation current generation circuit, NMOS transistor M T1 The input current I T1 is a positive temperature coefficient current, and the input current I of NMOS transistor M T3 is a negative temperature coefficient current. The output current I of NMOS transistor M T3 is a compensation current that exponentially decreases and acts on the low-temperature end. T12 The output current I T12 is a compensation current that exponentially decreases and acts on the low-temperature end.

6. The U-shaped temperature compensation reference voltage circuit according to claim 4, wherein In the high-temperature section curvature compensation current generation circuit, the current I input by the NMOS transistor MT1 T1 is a negative temperature coefficient current, and the current I input by the NMOS transistor M T3 is a positive temperature coefficient current. The current I output by the NMOS transistor MT12 T3 is a compensation current that exponentially increases and acts on the high-temperature end. T12 ​ 7. A U-shaped temperature compensation reference voltage circuit according to claim 1, characterized in that The reference voltage generation circuit includes PMOS transistor M1, PMOS transistor M2, PMOS transistor M3, PMOS transistor M4, PMOS transistor M5, PNP transistor Q1, PNP transistor Q2, resistor R1, resistor R2, resistor R3, resistor R4, resistor R5, and operational amplifier A. The source electrodes of PMOS transistor M1, PMOS transistor M2, PMOS transistor M3, PMOS transistor M4, and PMOS transistor M5 are connected to power supply VDD. The gate electrode of PMOS transistor M1 is connected to the gate electrodes of PMOS transistor M2, PMOS transistor M3, and the output end of operational amplifier A. The negative input terminal of operational amplifier A is connected to the drain electrode of PMOS transistor M1, the emitter electrode of PNP transistor Q1, and one end of resistor R3. The other end of resistor R3 is grounded. The base electrode and collector electrode of PNP transistor Q1, and the base electrode and collector electrode of PNP transistor Q2 are grounded. The positive input terminal of operational amplifier A is connected to the drain electrode of PMOS transistor M2, one end of resistor R1, and one end of resistor R2. The other end of resistor R1 is connected to the emitter electrode of PNP transistor Q2. The other end of resistor R2 is grounded. The drain electrode of PMOS transistor M3 is the reference voltage output terminal, which is connected to one end of resistor R4. The other end of resistor R4 is connected to the drain electrode of PMOS transistor M4 and one end of resistor R5. The other end of resistor R5 is grounded. The gate electrode of PMOS transistor M4 is connected to the gate electrode and drain electrode of PMOS transistor M5. The drain electrode of PMOS transistor M5 inputs the positive and negative temperature coefficient current and generates a U-shaped compensation current at the drain electrode of PMOS transistor M4.

8. The U-shaped temperature compensation reference voltage circuit according to claim 7, wherein The emitter area of the PNP transistor Q2 is m times that of the PNP transistor Q1, and the high-temperature section curvature compensation current and the low-temperature section curvature compensation current are added at the PMOS transistor M5 to obtain the U-shaped curvature compensation current I U , and the U-shaped compensation current acts on the resistor R5 through a current mirror to obtain the compensated reference voltage V REF .

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