An inverter circuit and a TTL circuit

Abstract

The application discloses a kind of inverter circuit and TTL circuit, including transistor one, transistor two, transistor three and resistance one, transistor one, transistor two, transistor three all adopt enhancement mode pseudo high electron mobility transistor;The gate of transistor one is connected with the gate of transistor three, and serves as the input end of inverter circuit, the source of transistor one is connected with power supply voltage V EE , the drain of transistor one is respectively connected with one end of resistance one and the gate of transistor two, the other end of resistance one and the drain of transistor two are connected with ground, the source of transistor two and the drain of transistor three are connected, and serve as the output end of inverter circuit, the source of transistor three is connected with power supply voltage.The advantages are: greatly improve the reliability of circuit, shape waveform, make output voltage more close to 0V and-5V, improve driving load capacity;Reduce cost, reduce system complexity, while the driving circuit power consumption is lower, provide good driving ability.

Description

TECHNICAL FIELD

[0001] The present application relates to an inverter circuit and a TTL circuit, and belongs to the technical field of microwave integrated circuits. BACKGROUND

[0002] In recent years, with the continuous development of microwave technology, monolithic microwave integrated circuits are widely used in military and civilian electronic fields due to their excellent stability, strong anti-interference ability and relatively low cost. Among them, MMICs with GaAs substrate as the carrier have high damping coefficient and high electron mobility, and are widely used in the field of monolithic microwave integrated circuits. In the application of microwave integrated circuits, we often need TTL circuits to control the modules in radio frequency communication with digital signals, such as radio frequency switches, digitally controlled attenuators and digitally controlled phase shifters, to realize the switching of the on-off, attenuation and phase shift of the switch, and other logic control functions.

[0003] In the application of GaAs pHEMT radio frequency switches, digitally controlled attenuators and digitally controlled phase shifters, depletion mode field effect transistors are often used, which are a kind of negative voltage control devices with a turn-off voltage of-0.8V. A set of-5V and 0V voltages are needed to control the turn-off and turn-on of the depletion mode, and when the input voltage is-5V, the transistor is turned off, and when the input voltage is 0V, the transistor is turned on. In life, we often use +5V TTL level, and need to design a driving circuit to convert the externally input +5V and 0V voltage into 0V and-5V to control the turn-on and turn-off of the depletion mode.

[0004] The TTL circuit based on the GaAs enhancement mode field effect transistor is composed of a level shift circuit unit, an inverting logic output circuit unit and a non-inverting logic output circuit unit. The inverting logic output circuit unit and the non-inverting logic output circuit unit are mainly composed of an inverting unit. The simplest inverting unit can be composed of an NMOS and a PMOS transistor, which is made based on CMOS technology, but it cannot be integrated with chips based on GaAs pHEMT technology, which leads to the increase of cost, the improvement of system complexity and the deterioration of performance. The traditional GaAs inverting unit is composed of an enhancement mode E transistor and a depletion mode D transistor. The E transistor is used as a switching transistor, and the D transistor is used as a load transistor. This structure has low driving load capacity and needs two different types of pHEMT transistors, which has low applicability. SUMMARY

[0005] The technical problem to be solved by the present application is to overcome the defects of the prior art and provide an inverter circuit and a TTL circuit.

[0006] To solve the above technical problems, the present application adopts the following technical scheme.

[0007] In one aspect, the application provides an inverter circuit comprising transistor one, transistor two, transistor three and resistor one, wherein the transistor one, transistor two and transistor three are all enhancement mode pseudo-high electron mobility transistors;

[0008] The gate of the transistor one is connected to the gate of the transistor three, and serves as an input terminal of the inverter circuit, the source of the transistor one is connected to a power supply voltage V EE , the drain of the transistor one is connected to one end of the resistor one and the gate of the transistor two, the other end of the resistor one and the drain of the transistor two are connected to ground, the source of the transistor two and the drain of the transistor three are connected, and serve as an output terminal of the inverter circuit, and the source of the transistor three is connected to the power supply voltage V EE .

[0009] Further, the application further comprises a voltage waveform stabilizing circuit, wherein the voltage waveform stabilizing circuit comprises a diode one and a resistor two, the positive electrode of the diode one is connected to the input terminal of the inverter circuit, the negative electrode of the diode one is connected to one end of the resistor two, and the other end of the resistor two is connected to the source of the transistor one.

[0010] A diode and a resistor are connected in series between the gate and the source of the transistor one, which ensures the voltage difference between the source and the gate when the switch tube is turned on, reduces waveform distortion and aberration, and makes the output voltage waveform more stable.

[0011] Further, the application further comprises a resistor three, one end of the resistor three is connected to the gate of the transistor one and the gate of the transistor three, and the other end of the resistor three serves as an input terminal of the inverter circuit, which plays a current limiting role and reduces the overall circuit power consumption.

[0012] In a second aspect, the application provides a TTL circuit comprising a level shift circuit unit, an inverting logic output circuit unit and a non-inverting logic output circuit unit.

[0013] The level shift circuit unit converts an input voltage into a target voltage and transmits the target voltage to the inverting logic output circuit unit and the non-inverting logic output circuit unit.

[0014] The inverting logic output circuit unit comprises an inverter circuit, the input terminal of the inverter circuit in the inverting logic output circuit unit is connected to the target voltage, and the output terminal of the inverter circuit in the inverting logic output circuit unit serves as a first output terminal of the TTL circuit.

[0015] The non-inverting logic output circuit unit comprises two inverters connected in series, the input terminal of the first inverter in the non-inverting logic output circuit unit is connected to the target voltage, and the output terminal of the second inverter in the non-inverting logic output circuit unit serves as a second output terminal of the TTL circuit.

[0016] The signals outputted by the first output end and the second output end constitute complementary negative voltage logic signals.

[0017] Further, the level shift circuit unit comprises a fourth resistor and a plurality of positive-negative series connected diodes, wherein the positive electrode of the first diode is connected to the input voltage V in The negative electrode of the last diode is respectively connected to one end of the fourth resistor, the input end of the non-inverted logic output circuit unit and the input end of the inverted logic output circuit unit.

[0018] The external 5V and 0V control input signals can be lowered to the required 0V and -5V, thereby controlling the turn-on and turn-off of the E tube.

[0019] Further, the input voltage V in is 5V / 0V, the power supply voltage V EE is -5V, the negative voltage logic signal outputted by the first output end is -5V / 0V, and the negative voltage logic signal outputted by the second output end is 0V / -5V.

[0020] Further, the level shift circuit unit specifically comprises a first diode D1, a second diode D2, a third diode D3, a fourth diode D4, a fifth diode D5, a sixth diode D6 and a first resistor R1.

[0021] The first diode D1, the second diode D2, the third diode D3, the fourth diode D4, the fifth diode D5 and the sixth diode D6 are connected in series, the positive electrode of the first diode D1 is connected to the input voltage, the negative electrode of the sixth diode D6 is connected to the input end of the non-inverted logic output circuit unit, the input end of the inverted logic output circuit unit and one end of the first resistor R1, and the other end of the first resistor R1 is connected to the power supply voltage V EE .

[0022] Further, the non-inverted logic output circuit unit specifically comprises a seventh diode D7, a second resistor R2, a third resistor R3, a fourth resistor R4, a first transistor M1, a second transistor M2 and a third transistor M3.

[0023] One end of the second resistor R2 is connected to the negative electrode of the sixth diode D6, the other end of the second resistor R2 is respectively connected to the gate of the first transistor M1, the positive electrode of the seventh diode D7 and the gate of the third transistor M3, the source of the first transistor M1 is respectively connected to the power supply voltage V EEThe drain of the first transistor M1 is connected to one end of the third resistor R3 and the gate of the second transistor M2, respectively, one end of the fourth resistor R4 is connected to the negative electrode of the seventh diode D7, the other end of the third resistor R3 and the drain of the second transistor M2 are connected to ground, the source of the second transistor M2 and the drain of the third transistor M3 are connected, and the source of the third transistor M3 is connected to the power supply voltage V EE .

[0024] Further, the in-phase logic output circuit unit specifically comprises an eighth diode D8, a ninth diode D9, a second resistor R2, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8 and a ninth transistor M9.

[0025] One end of the second resistor R2 is connected to the negative electrode of the sixth diode D6, and the other end of the second resistor R2 is connected to the gate of the fourth transistor M4, the positive electrode of the eighth diode D8 and the gate of the sixth transistor M6, respectively. EE The drain of the fourth transistor M4 is connected to one end of the fifth resistor R5 and the gate of the fifth transistor M5, respectively, the other end of the sixth resistor R6 is connected to the negative electrode of the eighth diode D8, the other end of the fifth resistor R5 and the drain of the fifth transistor M5 are connected to ground, the source of the fifth transistor M5 is connected to the drain of the sixth transistor M6 and one end of the seventh resistor R7, respectively, and the source of the sixth transistor M6 is connected to the power supply voltage V EE ;

[0026] The other end of the seventh resistor R7 is connected to the gate of the seventh transistor M7, the positive electrode of the ninth diode D9 and the gate of the ninth transistor M9, respectively, the source of the seventh transistor M7 is connected to the power supply voltage V EE The drain of the seventh transistor M7 is connected to one end of the eighth resistor R8 and the gate of the eighth transistor M8, respectively, the other end of the ninth resistor R9 is connected to the negative electrode of the ninth diode D9, the other end of the eighth resistor R8 and the drain of the eighth transistor M8 are connected to ground, the source of the eighth transistor M8 and the drain of the ninth transistor M9 are connected as the output end of the in-phase logic output circuit unit, and the source of the ninth transistor M9 is connected to the power supply voltage V EE .

[0027] The present application has the following beneficial effects:

[0028] The reverse unit of the application carries out twice reverse action to input signal, one way is directly outputted through reverse logic of switch tube, another way is connected with a common-drain amplifier, i.e. source follower, after the switch tube, following the output logic voltage signal of switch tube, two ways are connected to the same node output, this structure can greatly improve the reliability of circuit, shape waveform, make output voltage more close to 0V and -5V, improve driving load capacity.

[0029] The reverse logic output circuit unit in the TTL circuit of the application is connected in series by one reverse unit, the same phase logic output circuit unit is connected in series by two reverse units, which greatly improves the driving load capacity of the circuit; only enhancement E tube is used in the TTL circuit of the application, without using depletion D tube, which improves the applicability, and can be directly integrated with microwave integrated circuit chips such as radio frequency switch, digital control attenuator and digital control phase shifter, reduces the cost, reduces the system complexity, at the same time, the driving circuit has low power consumption, provides good driving capacity. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figure 1 is the circuit structure schematic diagram of reverse unit in example 1;

[0031] Figure 2 is the circuit structure schematic diagram of reverse unit in example 2;

[0032] Figure 3 is the module schematic diagram of TTL circuit in example 3 and example 4;

[0033] Figure 4 is the circuit structure schematic diagram of TTL circuit in example 3 and example 4;

[0034] Figure 5 is the simulation result schematic diagram of TTL circuit in example 3 and example 4. DETAILED DESCRIPTION

[0035] The application will be further described below in combination with the drawings. The following examples are only used to more clearly illustrate the technical solutions of the application, and cannot limit the protection scope of the application.

[0036] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0037] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art will understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0038] Example 1, as Figure 1 As shown, this embodiment introduces an inverting circuit, including a first transistor M1, a second transistor M2, a third transistor M3, a second resistor R2, and a third resistor R3. The first transistor M1, the second transistor M2, and the third transistor M3 are all enhancement-type pseudo-high electron mobility transistors.

[0039] One end of the second resistor R2 serves as the input terminal of the inverting circuit, connected to the external voltage. The other end of the second resistor R2 is connected to the gate of the first transistor M1 and the gate of the third transistor M3, respectively. The source of the first transistor M1 is connected to the power supply voltage V. EE The drain of the first transistor M1 is connected to one end of the third resistor R3 and the gate of the second transistor M2. The other end of the third resistor R3 is connected to the drain of the second transistor M2 and grounded. The source of the second transistor M2 and the drain of the third transistor M3 are connected to serve as the output terminal of the inverting circuit.

[0040] In this embodiment, the inverting unit performs two inversions on the input signal. One path is directly output through the inverting logic of the first transistor M1, while the other path is connected to a second transistor M2 after the first transistor M1 as a common-drain amplifier, i.e., a source follower, which follows the output logic voltage signal of the first transistor M1. Both paths are connected to the same node for output. This structure can greatly improve the reliability of the circuit, shape the waveform, make the output voltage closer to 0V and -5V, and improve the driving load capability. The third transistor M3 is used as a logic transistor and performs the inverting logic function.

[0041] Example 2, as Figure 2 As shown, this embodiment introduces an inverting circuit, which adds a voltage waveform stabilizing circuit to the basis of embodiment 1. The voltage waveform stabilizing circuit includes a seventh diode D7 and a fourth resistor R4. The positive terminal of the seventh diode D7 is connected to the other end of the second resistor R2, and the negative terminal of the seventh diode D7 is connected to one end of the fourth resistor R4. The other end of the fourth resistor R4 is connected to the source of the first transistor M1.

[0042] A diode and a resistor connected in series were added between the gate and source of the first transistor M1. When the switching transistor is turned on, the voltage difference between the source and the gate is guaranteed, reducing waveform distortion and making the output voltage waveform more stable.

[0043] Example 3, as Figure 3 As shown, based on the same inventive concept as Embodiment 2, this embodiment introduces a TTL circuit, including a level shifting circuit unit, an inverting logic output circuit unit, and a non-inverting logic output circuit unit;

[0044] The level shifting circuit unit converts the input voltage into the target voltage and transmits it to the inverting logic output circuit unit and the non-inverting logic output circuit unit respectively.

[0045] The inverting logic output circuit unit includes an inverting circuit. The input terminal of the inverting circuit in the inverting logic output circuit unit is connected to the target voltage, and the output terminal of the inverting circuit in the inverting logic output circuit unit serves as the first output terminal of the TTL circuit.

[0046] The non-inverting logic output circuit unit includes two inverting circuits connected in series. The input terminal of the first inverting circuit in the non-inverting logic output circuit unit is connected to the target voltage, and the output terminal of the second inverting circuit in the non-inverting logic output circuit unit serves as the second output terminal of the TTL circuit.

[0047] The signals output from the first output terminal and the second output terminal constitute complementary negative voltage logic signals.

[0048] The TTL circuit of the embodiment converts the input positive voltage logic signal into a negative voltage logic signal through a level shift, and then adjusts the phase through the in-phase logic output circuit unit and the inverse-phase logic output circuit unit, and finally outputs the complementary negative voltage logic signal.

[0049] The input voltage V in is 5V / 0V, the power voltage V EE is -5V, the negative voltage logic signal output by the first output end is -5V / 0V, and the negative voltage logic signal output by the second output end is 0V / -5V.

[0050] As shown in Figure 4 , the level shift circuit unit specifically comprises a first diode D1, a second diode D2, a third diode D3, a fourth diode D4, a fifth diode D5, a sixth diode D6, and a first resistor R1.

[0051] The first diode D1, the second diode D2, the third diode D3, the fourth diode D4, the fifth diode D5, and the sixth diode D6 are connected in series, the anode of the first diode D1 is connected to the input voltage, the cathode of the sixth diode D6 is connected to the input end of the inverse-phase logic output circuit unit, the input end of the in-phase logic output circuit unit, and one end of the first resistor R1, and the other end of the first resistor R1 is connected to the power voltage V EE .

[0052] The voltage signal input into the TTL circuit is a high level of +5V, and the voltage difference between the two ends of the first diode D1, the second diode D2, the third diode D3, the fourth diode D4, the fifth diode D5, and the sixth diode D6 is large enough, so the first diode D1, the second diode D2, the third diode D3, the fourth diode D4, the fifth diode D5, and the sixth diode D6 are all turned on, and the logic voltage signal of the node a is V a =5-6*V T =-600mV.

[0053] The inverse-phase logic output circuit unit specifically comprises a seventh diode D7, a second resistor R2, a third resistor R3, a fourth resistor R4, a first transistor M1, a second transistor M2, and a third transistor M3.

[0054] One end of the second resistor R2 is connected to the negative pole of the sixth diode D6, the other end of the second resistor R2 is connected to the gate of the first transistor M1, the positive pole of the seventh diode D7 and the gate of the third transistor M3 respectively, the source of the first transistor M1 is connected to one end of the third resistor R3 and the gate of the second transistor M2 respectively, the other end of the fourth resistor R4 is connected to the negative pole of the seventh diode D7, the other end of the third resistor R3 and the drain of the second transistor M2 are connected to ground, the source of the second transistor M2 and the drain of the third transistor M3 are connected, and the output end of the inverter circuit, the source of the third transistor M3 is connected to the power supply voltage V EE . EE .

[0055] The gate voltage of the first transistor M1 is V b ≈V a =-600mV, the gate-source voltage of the first transistor M1 is V gs1 =V b -V EE =-0.6V-(-5V)=4.4V>V th1 , the drain-source of the first transistor M1 is turned on, the diode D7 ensures the voltage difference between the gate and the source, so that the output voltage waveform is more stable, the logic voltage signal V c =V EE =-5V at node c. The input of the second transistor M2 is the gate, and the output is the source. The second transistor M2 is a common-drain amplifier, that is, the source follower follows the gate voltage output. The logic voltage signal V out1 =V d =V c =-5V at node d.

[0056] The gate voltage of the third transistor M3 is V b ≈V a =-600mV, the gate-source voltage of the third transistor M3 is V gs3 =V b -V EE =-0.6V-(-5V)=4.4V>V th3 , the drain-source of the third transistor M3 is turned on, the diode D7 ensures the voltage difference between the gate and the source, so that the output voltage waveform is more stable, the logic voltage signal V out1 =V d = V EE =-5V at node d.

[0057] Both reverse logic outputs are at the same node d, and the output voltage logic signals are all-5V. Such a structure can greatly improve the reliability of the circuit and better shape the waveform and stabilize the output.

[0058] As Figure 4 shown, the in-phase logic output circuit unit specifically comprises an eighth diode D8, a ninth diode D9, a second resistor R2, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, and a ninth transistor M9;

[0059] One end of the second resistor R2 is connected to the negative electrode of the sixth diode D6, and the other end of the second resistor R2 is connected to the gate of the fourth transistor M4, the positive electrode of the eighth diode D8, and the gate of the sixth transistor M6, respectively. The source of the fourth transistor M4 is connected to one end of the fifth resistor R5 and the gate of the fifth transistor M5, respectively. The drain of the fourth transistor M4 is connected to the other end of the sixth resistor R6 and the negative electrode of the eighth diode D8, respectively. The other end of the fifth resistor R5 and the drain of the fifth transistor M5 are connected to ground in common. The source of the fifth transistor M5 is connected to the drain of the sixth transistor M6 and one end of the seventh resistor R7, respectively. The source of the sixth transistor M6 is connected to the power supply voltage V EE . EE ;

[0060] The other end of the seventh resistor R7 is connected to the gate of the seventh transistor M7, the positive electrode of the ninth diode D9, and the gate of the ninth transistor M9, respectively. The source of the seventh transistor M7 is connected to one end of the ninth resistor R9 and the power supply voltage V EE , respectively. The drain of the seventh transistor M7 is connected to one end of the eighth resistor R8 and the gate of the eighth transistor M8, respectively. The other end of the ninth resistor R9 is connected to the negative electrode of the ninth diode D9. The other end of the eighth resistor R8 and the drain of the eighth transistor M8 are connected to ground in common. The source of the eighth transistor M8 and the drain of the ninth transistor M9 are connected in common as the output end of the in-phase logic output circuit unit. The source of the ninth transistor M9 is connected to the power supply voltage V EE .

[0061] The first reverse unit of the in-phase logic output circuit unit has the same working principle as the reverse unit in the inverse logic output circuit. Finally, the logic voltage signal at node g is V g =-5V.

[0062] The gate voltage of the seventh transistor M7 is V h ≈V g =-5V, and the gate-source voltage of the seventh transistor M7 is V gs7 =V h -V EE =-5V-(-5V)=0V<V th7 , and the drain-source of the seventh transistor M7 is off. The logic voltage signal V i = VGND =0V. The input of the eighth transistor M8 is the gate, the output is the source, and the eighth transistor M8 is a common-drain amplifier, i.e. a source follower, following the gate voltage, and the logic voltage signal Vj of the node j is V out2 =V j =V i =0V.

[0063] The gate voltage of the ninth transistor M9 is V h ≈V g =-5V, and the gate-source voltage of the ninth transistor M9 is V gs9 =V h -V EE =-5V-(-5V)=0V<V th9 , and the ninth transistor M9 is off, and the logic voltage signal Vj of the node j is V out2 =V j =V GND =0V.

[0064] Both of the two reverse logic outputs are at the same node j, and the output voltage logic signals are both 0V. Such a structure can greatly improve the reliability of the circuit and better shape the waveform and stabilize the output.

[0065] Embodiment 4: The circuit structure is the same as that of the TTL circuit in Embodiment 3, but the voltage signal input into the TTL circuit is a low level of 0V. The voltage difference between the two ends of the first-stage diode D1, the second-stage diode D2, the third-stage diode D3, the fourth-stage diode D4, the fifth-stage diode D5, and the sixth-stage diode D6 is not large enough, so the first-stage diode D1, the second-stage diode D2, the third-stage diode D3, the fourth-stage diode D4, the fifth-stage diode D5, and the sixth-stage diode D6 are all cut off, and the logic voltage signal of the node a is V a = V EE =-5V.

[0066] The gate voltage of the first transistor M1 is V b ≈V a =-5V, and the gate-source voltage of the first transistor M1 is V gs1 =V b -V EE =-5V-(-5V)=0V<V th1 , and the first transistor M1 is off, and the logic voltage signal Vc of the node c is V c =V GND =0V. The input of the second transistor M2 is the gate, the output is the source, and the second transistor M2 is a common-drain amplifier, i.e. a source follower, following the gate voltage output, and the logic voltage signal Vd of the node d is V out1 =V d =Vc =0V.

[0067] The gate voltage of the third transistor M3 is V b ≈V a =-5V, and the gate-source voltage of the third transistor M3 is V gs3 =V b -V EE =-5V-(-5V)=0V<V th3 , the third transistor M3 is off, and the logic voltage signal V out1 =V d = V GND =0V.

[0068] Both the two-way reverse logic are output at the same node d, and the output voltage logic signals are all 0V, which can greatly improve the reliability of the circuit and better shape the waveform and stabilize the output.

[0069] The first reverse unit of the in-phase logic output circuit unit and the reverse unit in the inverse logic output circuit have the same working principle, and finally the logic voltage signal V g =0V at the node g.

[0070] The gate voltage of the seventh transistor M7 is V h ≈V g =0V, and the gate-source voltage of the seventh transistor M7 is V gs7 =V h -V EE =0V-(-5V)=5V>V th7 , the seventh transistor M7 is on, and the diode D9 ensures the voltage difference between the gate and the source, so that the output voltage waveform is more stable, and the logic voltage signal V i =V EE =-5V at the node i. The eighth transistor M8 has a gate as an input and a source as an output, and the eighth transistor M8 is used as a common-drain amplifier, i.e., a source follower following the gate voltage, and the logic voltage signal V out2 =V j =V i =-5V.

[0071] The gate voltage of the ninth transistor M9 is V h ≈V g =0V, and the gate-source voltage of the ninth transistor M9 is V gs9 =V h -V EE =0V-(-5V)=5V>V th9 , the ninth transistor M9 is on, and the diode D9 ensures the voltage difference between the gate and the source, so that the output voltage waveform is more stable, and the logic voltage signal Vout2 =V j =V EE =-5V.

[0072] Both two-way reverse logic are output at the same node j, and the output voltage logic signal is the same -5V, which can greatly improve the reliability of the circuit, better shaping waveform, and stable output.

[0073] The above is the TTL circuit in the embodiment 3 and the embodiment 4 proposed by the application, when the input 5V and 0V logic voltage signal, the output simulation result is as shown in Figure 5

[0074] The above is only the preferred embodiment of the application, it should be noted that for those skilled in the art, without departing from the technical principles of the application, can make a number of improvements and deformation, these improvements and deformation should also be considered as the protection scope of the application.​

Claims

1. A TTL circuit, characterized in that, It includes a level shifting circuit unit, an inverting logic output circuit unit, and a non-inverting logic output circuit unit; The level shifting circuit unit converts the input voltage into the target voltage and transmits it to the inverting logic output circuit unit and the non-inverting logic output circuit unit respectively. The inverting logic output circuit unit includes an inverting circuit. The input terminal of the inverting circuit in the inverting logic output circuit unit is connected to the target voltage, and the output terminal of the inverting circuit in the inverting logic output circuit unit serves as the first output terminal of the TTL circuit. The non-inverting logic output circuit unit includes two inverting circuits connected in series. The input terminal of the first inverting circuit in the non-inverting logic output circuit unit is connected to the target voltage, and the output terminal of the second inverting circuit in the non-inverting logic output circuit unit serves as the second output terminal of the TTL circuit. The signals output from the first output terminal and the second output terminal constitute complementary negative voltage logic signals; The level shifting circuit unit specifically includes: a first diode D1, a second diode D2, a third diode D3, a fourth diode D4, a fifth diode D5, a sixth diode D6, and a first resistor R1; Diodes D1, D2, D3, D4, D5, and D6 are connected in series. The anode of diode D1 is connected to the input voltage. The cathode of diode D6 is connected to the input terminals of the inverting logic output circuit unit, the non-inverting logic output circuit unit, and one end of resistor R1. The other end of resistor R1 is connected to the power supply voltage V. EE ; The inverting logic output circuit unit specifically includes: a seventh diode D7, a second resistor R2, a third resistor R3, a fourth resistor R4, a first transistor M1, a second transistor M2, and a third transistor M3; One end of the second resistor R2 is connected to the cathode of the sixth diode D6, and the other end of the second resistor R2 is connected to the gate of the first transistor M1, the anode of the seventh diode D7, and the gate of the third transistor M3, respectively. The source of the first transistor M1 is connected to the power supply voltage V. EE One end of the fourth resistor R4 and the drain of the first transistor M1 are connected to one end of the third resistor R3 and the gate of the second transistor M2, respectively. The other end of the fourth resistor R4 is connected to the cathode of the seventh diode D7. The other end of the third resistor R3 and the drain of the second transistor M2 are grounded together. The source of the second transistor M2 and the drain of the third transistor M3 are connected together and serve as the output of the inverting circuit. The source of the third transistor M3 is connected to the power supply voltage V. EE ; The in-phase logic output circuit unit specifically includes: an eighth diode D8, a ninth diode D9, a second resistor R2, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, and a ninth transistor M9. One end of the second resistor R2 is connected to the cathode of the sixth diode D6, and the other end of the second resistor R2 is connected to the gate of the fourth transistor M4, the anode of the eighth diode D8, and the gate of the sixth transistor M6, respectively. The source of the fourth transistor M4 is connected to the power supply voltage V. EE One end of the sixth resistor R6 and the drain of the fourth transistor M4 are connected to one end of the fifth resistor R5 and the gate of the fifth transistor M5, respectively. The other end of the sixth resistor R6 is connected to the cathode of the eighth diode D8. The other end of the fifth resistor R5 and the drain of the fifth transistor M5 are grounded together. The source of the fifth transistor M5 is connected to the drain of the sixth transistor M6 and one end of the seventh resistor R7. The source of the sixth transistor M6 is connected to the power supply voltage V. EE ; The other end of the seventh resistor R7 is connected to the gate of the seventh transistor M7, the anode of the ninth diode D9, and the gate of the ninth transistor M9, respectively. The source of the seventh transistor M7 is connected to the power supply voltage VEE and one end of the ninth resistor R9, respectively. The drain of the seventh transistor M7 is connected to one end of the eighth resistor R8 and the gate of the eighth transistor M8, respectively. The other end of the ninth resistor R9 is connected to the cathode of the ninth diode D9. The other end of the eighth resistor R8 and the drain of the eighth transistor M8 are grounded together. The source of the eighth transistor M8 and the drain of the ninth transistor M9 are connected together as the output terminal of the non-inverting logic output circuit unit. The source of the ninth transistor M9 is connected to the power supply voltage VEE. EE ; The input voltage V in The power supply voltage V is 5V / 0V. EE The voltage is -5V. The negative voltage logic signal output by the first output terminal is -5V / 0V, and the negative voltage logic signal output by the second output terminal is 0V / -5V.

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