Improved inter-memory movement in multi-memory systems

Abstract

This application relates to improved inter-memory movement in a multi-memory system. A memory device can receive from a host device a command to move data from a first memory controlled by a first controller to a second memory controlled by a second controller. The memory device can use the first and second controllers to facilitate the movement of the data from the first memory to the second memory via a path external to the host device. The memory device can instruct the host device when to suspend activity in the first or second memory and when to resume activity in the first or second memory.

Description

[0001] Information related to divisional application

[0002] This application is a divisional application of Chinese invention patent application No. 202111001696.6, filed on August 30, 2021, entitled "Improved Inter-Memory Movement in a Multi-Memory System".

[0003] Cross-reference

[0004] This patent application claims priority to U.S. Patent Application No. 17 / 018,570, filed September 11, 2020, entitled "Improved Inter-Memory Movement in a Multi-Memory System," and to U.S. Provisional Patent Application No. 63 / 072,604, filed August 31, 2020, entitled "Improved Inter-Memory Movement in a Multi-Memory System," each of which has been assigned to its assignee, and each of which is expressly incorporated herein by reference in its entirety. Technical Field

[0005] The technical field relates to improved inter-memory movement in multi-memory systems. Background Technology

[0006] The following text generally refers to one or more systems for memory, and more specifically to improved inter-memory movement in multi-memory systems.

[0007] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, and digital displays. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed to support one of two states, often indicated by logic 1 or logic 0. In some instances, a single memory cell can support more than two states, any of which can be stored. To access the stored information, a component can read or sense at least one stored state in the memory device. To store information, a component can write states into the memory device or program states.

[0008] Various types of memory devices and memory cells exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), auto-select memory, chalcogenide memory technology, etc. Memory cells can be volatile or non-volatile. For example, non-volatile FeRAM can maintain its stored logic state for a long time even without external power. Volatile DRAM devices, on the other hand, may lose their stored state when disconnected from external power. Summary of the Invention

[0009] Describe an apparatus. The apparatus may include a first memory, a second memory, and a controller coupled to the first memory and the second memory, the controller being configured such that the apparatus: receives from a host device and at a first controller for the first memory an address for the second memory and a command to move data between the first memory and the second memory; transmits a second address and an access command from the first controller to the second controller for the second memory, at least in part based on the command; and transmits data between the first memory and the second memory via a data path external to the host device, at least in part based on the transmission of the second address and the access command.

[0010] Describe a method. The method may include: receiving from a host device and at a first controller for a first memory an address for a second memory and a command to move data between the first memory and the second memory; transmitting a second address and an access command from the first controller to a second controller for the second memory, at least in part based on the command; and transmitting data between the first memory and the second memory via a data path outside the host device, at least in part based on the transmission of the second address and the access command.

[0011] A non-transitory computer-readable medium storing code is described. The non-transitory computer-readable medium storing code may include instructions that, when executed by a processor of an electronic device, cause the electronic device to: receive from a host device and a first controller for a first memory an address for a second memory and a command to move data between the first and second memories; transfer a second address and an access command from the first controller to a second controller for the second memory, at least in part based on the command; and transfer data between the first and second memories via a data path external to the host device, at least in part based on the transfer of the second address and access command. Attached Figure Description

[0012] Figure 1Examples of systems that support improved inter-memory movement, based on examples disclosed herein.

[0013] Figure 2 Examples of systems that support improved inter-memory movement, based on examples disclosed herein.

[0014] Figure 3 This document describes an example of a process flow that supports improved inter-memory movement in a multi-memory system, based on examples disclosed herein.

[0015] Figure 4 A block diagram illustrating an improved memory device for inter-memory movement in a multi-memory system according to various aspects of this disclosure.

[0016] Figure 5 The flowchart illustrates one or more methods for improving inter-memory movement in a multi-memory system, based on examples disclosed herein. Detailed Implementation

[0017] For example, an electronic device may include multiple memories with different characteristics, and the device may be used for different purposes. For instance, the device may include memory for long-term data storage, memory acting as main memory (e.g., primary memory for storing data being accessed by a host device), and memory acting as cache (e.g., secondary memory for storing frequently accessed or high-priority data), as well as other purposes or configurations. To achieve latency and power consumption advantages, the device may transfer data between memories; this transaction may be referred to herein as inter-memory data movement. In other different systems, for inter-memory data movement, the host device may retrieve data from one memory and transfer it to another memory for storage. Thus, data involved in inter-memory data movement can be routed via the host device. However, among other disadvantages, routing data via the host device for inter-memory data movement can increase latency (e.g., because of longer data paths) and increase power consumption (e.g., because of the numerous operations performed).

[0018] According to the techniques described herein, a device can reduce the latency and power consumption associated with inter-memory data movement by transferring data from one memory to another without routing the data through a host device. For example, a controller coupled to and controlling multiple memories can use data paths (e.g., internal to the controller, external to the host device) to move data from one memory to another. Because the host device does not participate in inter-memory data movement, it can inadvertently attempt to access one of the memories while the memories are busy with inter-memory data movement. To prevent this, the controller can provide the host device with instructions regarding the pause and resumption of recommended activities associated with one or more memories involved in inter-memory movement.

[0019] As per reference Figure 1 and 2 The features of this disclosure are initially described within the context of the system described. (See references...) Figure 3 The features of this disclosure are described in the context of the process flow described herein. These and other features of this disclosure are illustrated by reference to, for example, [reference needed]. Figure 4 and 5 The device diagrams and flowcharts describing improved inter-memory data movement in multi-memory systems are further illustrated and described.

[0020] Figure 1 This document describes an example of a system 100 supporting improved inter-memory data movement, based on examples disclosed herein. System 100 may be contained in an electronic device, such as a computer or telephone. System 100 may include a host device 105 and a memory subsystem 110. Memory subsystem 110 may store information (electronic information, digital information, data) for host device 105 in cache memory 120, main memory 125, and storage device 130. Memory subsystem 110 may access data in various memories using a controller 115 that can interface with host device 105. In some instances, controller 115, cache memory 120, main memory 125, and storage device 130 may be contained in the same physical package. However, one or more of controller 115, cache memory 120, main memory 125, and storage device 130 may be disposed on different, respective dies (e.g., silicon dies). Thus, the memory subsystem may represent a multi-chip package.

[0021] Devices in system 100 can be coupled via various wires (e.g., traces, printed circuit board (PCB) routes, redistribution layer (RDL) routes), which enables the transmission of information (e.g., commands, addresses, data) between devices. Wires can form channels, data buses, command buses, address buses, etc.

[0022] In some instances, system 100 may be contained in, or coupled to, a computing device, electronic device, mobile computing device, or wireless device. The device may be a portable electronic device. For example, the device may be a computer, laptop computer, tablet computer, smartphone, cellular phone, wearable device, Internet-connected device, etc. In some instances, the device may be configured for bidirectional wireless communication via a base station or access point. In some instances, the device associated with system 100 may be capable of machine-type communication (MTC), machine-to-machine (M2M) communication, or device-to-device (D2D) communication. In some instances, the device associated with system 100 may be referred to as a user equipment (UE), station (STA), mobile terminal, etc.

[0023] The host device 105 may be a processor or system-on-a-chip (SoC) that interfaces with the controller 115 and other components of the electronic device containing the system 100. To access information in cache memory 120, main memory 125, or storage device 130, the host device 105 may transmit access commands (e.g., activation commands, read commands, write commands, precharge commands) to the controller 115. The host device 105 knows the address of each memory location and the data stored at each address. Therefore, access commands transmitted by the host device 105 may target certain addresses in the memory. The host device 105 may be or include a processor, SoC, general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or combinations thereof. In some instances, the host device 105 may be referred to as a host.

[0024] Controller 115 may be configured to interface with cache memory 120, main memory 125, and storage device 130 in response to commands from host device 105 (e.g., based on one or more commands or requests issued by host device 105). For example, controller 115 may facilitate the retrieval of data from cache memory 120, main memory 125, and storage device 130 and the storage of data to cache memory 120, main memory 125, and storage device 130 in response to commands from host device 105. Therefore, controller 115 may facilitate data transfers between various sub-components, such as data transfers between at least some of host device 105, cache memory 120, main memory 125, and storage device 130. Controller 115 may interface with host device 105, cache memory 120, main memory 125, and storage device 130 using one or more protocols.

[0025] Storage device 130 may include one or more memory cell arrays and one or more local memory controllers configured to operate the one or more memory cell arrays. In some instances, the memory cells in storage device 130 may be or include NAND memory cells (e.g., main memory 125 may be managed NAND (mNAND) memory). The access latency of storage device 130 may be very long (e.g., orders of magnitude larger) relative to the access latency of other memories in memory subsystem 110. Furthermore, the access latency of storage device 130 may be nondeterministic (e.g., unknown, unpredictable, varying between accesses). Therefore, controller 115 may use one or more flags to notify host device 105 of the status of storage device 130, so that host device 105 can issue access commands for storage device 130 in appropriate timing. It should be understood that in some instances, the power consumed by storage device 130 may be lower than the power consumed by other memories in memory subsystem 110.

[0026] Main memory 125 may include one or more memory cell arrays and one or more local memory controllers configured to operate the one or more memory cell arrays. In some instances, the memory cells in main memory 125 may be or include FeRAM cells (e.g., main memory 125 may be FeRAM). Therefore, main memory 125 may have shorter access operation latency than storage device 130. For example, retrieving data from main memory 125 may take less time than retrieving data from storage device 130. However, unlike the access timing used for storage device 130, the access timing of main memory 125 may be deterministic (e.g., known, predictable, and fixed for certain access operations). Therefore, host device 105 may use one or more internal timers or clocks to determine the appropriate time to issue access commands to main memory 125. As mentioned, main memory 125 may consume more power than storage device 130 but less power than cache memory 120.

[0027] Cache memory 120 may include one or more memory cell arrays and one or more local memory controllers configured to operate the one or more memory cell arrays. In some instances, the memory cells in cache memory 120 may be or include DRAM cells (e.g., main memory 125 may be DRAM). Therefore, cache memory 120 may have shorter access operation latency than main memory 125 and storage device 130. Similar to the access timing of main memory 125, the access timing of cache memory 120 may be deterministic. Therefore, host device 105 may use one or more internal timers or clocks to determine the appropriate time to issue access commands to cache memory 120. It should be understood that cache memory 120 may consume more power than main memory 125 and storage device 130.

[0028] Therefore, the memory in memory subsystem 110 can be a different memory technology with different characteristics (e.g., latency, power consumption, density). For example, storage device 130 can be a flash memory technology, such as mNAND memory, that provides a large amount of long-term storage at low power (compared to other memories). Therefore, host device 105 can use storage device 130 to store information that is not used by system 100 but that host device 105 ultimately wants to retain. For example, host device 105 can use storage device 130 to store the operating system (OS) of system 100, applications, files, images, videos, etc. that host device 105 wants to retain for later access.

[0029] However, storage device 130 may have slow (relative to other memories) and nondeterministic access times. Therefore, when host device 105 wants to access specific information stored in storage device 130, host device 105 can move the information from storage device 130 to main memory 125, allowing the information to be quickly supplied to host device 105. If host device 105 expects to access information relatively frequently or has a specific data rate requirement for obtaining information, then host device 105 can move the information from storage device 130 or main memory 125 to cache memory 120, making access even faster. However, cache memory 120 may have higher power consumption than main memory 125, and main memory 125 may have higher power consumption than storage device 130.

[0030] Therefore, host device 105 can shuffle information between the memories of memory subsystem 110 to optimize latency and power consumption. For example, to reduce latency, among other advantages, host device 105 can move information from storage device 130 to main memory 125 or cache memory when host device 105 needs information (e.g., when opening an application, file, image, video, etc.). And to reduce power consumption, among other advantages, host device 105 can move information from cache memory 120 or main memory 125 to storage device 130 when information is no longer needed.

[0031] In other systems, to move information between memories (referred to herein as the process of inter-memory data movement), host device 105 may first retrieve information from an initial memory (e.g., storage device 130) and then provide the information to a target memory (e.g., main memory 125). That is, information can be routed from one memory to another via host device 105. However, routing information from one memory to another via host device 105 consumes time and power, thereby reducing the performance of system 100.

[0032] According to the techniques described herein, information from one memory can be routed to another memory via a data path within the memory subsystem 110. Therefore, routing information through the host device 105 can be avoided, which improves the latency and power consumption of system 100. As described herein and referenced... Figure 2 This technology may involve multiple controllers in controller 115 and flags that indicate to host device 105 when access commands to certain memory should be suspended.

[0033] System 100 may include any number of non-transitory computer-readable media that support improved inter-memory data movement. For example, host device 105, memory subsystem 110, controller 115, or memory may include or additionally access one or more non-transitory computer-readable media storage instructions (e.g., firmware) for performing functions attributed herein to host device 105, memory subsystem 110, controller 115, and / or memory. For example, such instructions, when executed by host device 105 (e.g., by a host system controller), by memory subsystem 110, by controller 115, or by memory, may cause host device 105, memory subsystem 110, controller 115, or memory to perform the associated functions as described herein.

[0034] Figure 2 This describes an example of a system 200 that supports improved inter-memory data movement, based on examples disclosed herein. System 200 may be used as a reference. Figure 1An instance of the described system 100. Therefore, system 200 may include, as referenced... Figure 1 The described host device 205 and memory subsystem 210 are used for interaction. The memory subsystem 210 may include components that can be referenced. Figure 1 Examples of the corresponding components described herein include controller 215, cache memory 220, main memory 225, and storage device 230. According to the techniques described herein, controller 215 can receive commands to move data between memories and route data from an initial memory to a target memory via a path within memory subsystem 210 (and outside host device 205). To prevent host device 205 from attempting to access one memory while the memory is busy moving data between memories, controller 215 can instruct host device 205 on appropriate times to pause and resume memory activity.

[0035] Controller 215 may include one or more sub-controllers capable of controlling one or more corresponding memories. For example, controller 215 may include a memory device controller 240 that controls memory device 230 (e.g., by issuing access commands and addresses to memory device 230), and a memory controller 235 that controls cache memory 220 and main memory 225 (e.g., by issuing access commands and addresses to cache memory 220 and main memory 225, respectively). Memory device controller 240 and memory controller 235 may use different protocols to access the corresponding memories, which may have different architectures, densities, latency, and other characteristics. Memory device controller 240 and memory controller 235 may be or include logic, circuitry, a processor, a controller, or other components capable of performing the functions described herein.

[0036] In addition to controlling the corresponding memory, the controllers (memory controller 235, storage device controller 240) can also control the routing circuitry that guides the transfer of data within the memory subsystem 210. For example, for inter-memory data movement between cache memory 220 and storage device 230, memory controller 235 can control routing circuitry 275 and routing circuitry 280 (and storage device controller 240 can control routing circuitry 285), so that data is transferred from cache memory 220 to storage device 230 via data path 290 (or vice versa). Similarly, for inter-memory data movement between main memory 225 and storage device 230, memory controller 235 can control routing circuitry 280 (and storage device controller 240 can control routing circuitry 285), so that data is transferred from main memory 225 to storage device 230 (or vice versa).

[0037] The host device 205 can obtain data from cache memory 220 or main memory 225, or both, by instructing the memory controller 235 to perform access operations on cache memory 220 and main memory 225. For example, the host device 205 can transmit control information (e.g., access commands for cache memory 220 and / or main memory 225, addresses for cache memory 220 and / or main memory 225) to the memory controller 235. Similarly, the host device 205 can obtain data from storage device 230, or store data in storage device 230, by instructing the storage device controller 240 to perform access operations on storage device 230. For example, the host device 205 can transmit control information (e.g., access commands for storage device 230, addresses for storage device 230) to the storage device controller 240. For non-memory data movement, control information sent to the controller (e.g., memory controller 235, storage device controller 240) can be used for the memory controlled by the controller. However, for inter-memory data movement, the host device 205 can send control information for cache memory 220 and main memory 225 to storage device controller 240 (in contrast to memory controller 235).

[0038] The storage device controller 240 facilitates inter-memory data communication between storage device 230 and cache memory 220, or between storage device 230 and main memory 225. For example, the storage device controller 240 enables the memory subsystem 210 to move data from one memory to another using data path 290 or data path 295. By using data paths within the memory subsystem 210—as opposed to routing data via host device 205—the memory subsystem 210 can reduce the latency and power consumption associated with inter-memory data movement.

[0039] As an example, memory controller 235 may receive a command (e.g., an inter-memory data move command) from host device 205, the command instructing memory controller 235 to move data from storage device 230 to main memory 225. Memory controller 235 may also receive an initial address (e.g., the starting address of a memory cell in storage device 230 for storing data) and a destination address (e.g., the starting address of a memory cell in main memory 225 for storing data) for the inter-memory data move. Therefore, storage device controller 240 may receive addresses of memories (e.g., main memory 225) that storage device controller 240 does not directly control.

[0040] In response to a command for inter-memory data movement, memory device controller 240 may transmit a destination address and one or more access commands (e.g., write commands) to memory controller 235. Memory device controller 240 may also transmit a start address and one or more access commands (e.g., read commands) to memory device 230. Access commands transmitted by memory device controller 240 may cause data to be read from memory device 230, transferred via data path 295 to main memory 225, and stored in main memory 225 (or vice versa for inter-memory data movement from main memory to memory device 230). Data path 295 may traverse or include routing circuitry 285, routing circuitry 280, one or more input / output channels 230 (IO_S) for memory devices, or one or more I / O channels 225 (IO_M) for main memory, or any combination thereof.

[0041] A routing circuit system can refer to a combination of components, circuit systems, logic, and / or other hardware capable of guiding the transfer of data within the memory subsystem 210. An I / O channel can refer to conductive traces, buses, bus interfaces, buffers, etc., capable of transferring data in and out of memory. In some instances, a dataset from one memory can be moved to another memory in the form of a subset of information (e.g., a subset of bits). For example, a 2kB dataset can be moved from storage device 230 to main memory 225 in the form of 64B data subsets, meaning that multiple rounds of reads, transfers, and writes at a 64B granularity can occur.

[0042] As mentioned, storage device 230 may have nondeterministic access latency, meaning that the access timing for storage device 230 may be variable, fall outside a defined duration, and / or be unpredictable. Although main memory 225 may have deterministic access latency, host device 205 may not know when main memory 225 is busy with inter-memory data movement because the operation of main memory 225 may depend on various factors or other components, such as storage device 230. For example, during inter-memory data movement from main memory 225 to storage device 230, main memory 225 may be prevented from transferring data to storage device 230 until storage device 230 is ready, which may not occur within an unpredictable amount of time. Furthermore, during inter-memory data movement from storage device 230 to main memory 225, main memory 225 may receive data according to the timeline of storage device 230, which may be unpredictable because there is no fixed latency for accessing data and preparing it for communication. Therefore, even if the main memory has deterministic access latency, the host device 205 may not know when the main memory 225 is busy moving data between memory locations.

[0043] To prevent host device 205 from attempting to access main memory 225 while it is busy with inter-memory data transfer, memory subsystem 210 may send an instruction to host device 205 when main memory 225 is (e.g., anticipated) or currently busy. For example, storage device controller 240 may send an instruction to host device 205 that it should suspend activities related to main memory 225 (e.g., issuing access commands) in the future (during a given duration from time x to time y) or for a set duration from the time the control signal is received. After receiving the control signal, host device 205 may suspend activity with main memory 225. When main memory 225 completes inter-memory data transfer, storage device controller 240 may modify the control signal to indicate that host device 205 may resume activity with main memory 225. The control signal may be referred to herein as a Memory Activity Flag (MAF).

[0044] As described in this article and see Figure 3 The assertion of MAF (e.g., indicating a pause in activity) may depend on the direction of the data movement and may occur after different triggers. For example, if the data movement is from main memory 225 to storage device 230, then the MAF may be asserted when the storage device controller 240 receives a command to perform an inter-memory move. However, if the data movement is from storage device 230 to main memory 225, then the storage device controller 240 may delay asserting the MAF until storage device 230 is ready for data transfer. This strategy of asserting the MAF allows the host device 205 to continue accessing main memory 225 while storage device 230 is ready for inter-memory data movement, thereby increasing system performance. Therefore, the storage device controller 240 can use the MAF to ensure that the host device 205 accesses main memory 225 in an appropriate manner (e.g., in a manner that does not conflict with inter-memory data movement).

[0045] Therefore, system 200 can perform inter-memory data movement with reduced latency, power consumption, and to prevent conflicting access attempts by host device 205. Although described with reference to inter-memory data movement between storage device 230 and main memory 225, the techniques described herein can be implemented for inter-memory data movement between storage device 230 and cache memory 220. However, in this scenario, data can be transferred using data path 290, which may traverse or include routing circuitry 275, routing circuitry 280, routing circuitry 285, one or more input / output channels 230 (IO_S) for the storage device, and one or more I / O channels 220 (IO_C) for the cache memory.

[0046] It should be understood that controller 215 can communicate with host device 205 via one or more interfaces through one or more buses. For example, memory controller 235 can receive commands and addresses from cache memory 220 and main memory 225 via interface 265 through command and address (C / A) bus 245. Memory controller 235 can also transfer data read from cache memory 220 and main memory 225 to host device 205 via data bus 255 through interface 265; and receive data from cache memory 220 and main memory 225 via data bus 255. Similarly, storage device controller 240 can receive commands and addresses for storage device 230 via interface 270 through C / A bus 250. Storage device controller 240 can also transfer data read from storage device 230 to host device 205 via data bus 260 through interface 270; and receive data for storage device 230 via data bus 260. In some instances, the protocol used for communication between host device 205 and memory controller 235 differs from the protocol used for communication between host device and storage device controller 240. For example, memory controller 235 may support the Low Power Double Data Rate (LPDDR) protocol, and storage device controller 240 may support the Universal Flash Storage (UFS) protocol.

[0047] Figure 3 This describes an example of a process flow supporting improved inter-memory data movement, based on examples disclosed herein. Process flow 300 may be derived from, as referenced... Figure 1 and 2 The memory subsystem described herein is an implementation. However, other types of devices may implement process flow 300. For ease of reference, process flow 300 is described with reference to memory subsystem 210. Alternatively or additionally, aspects of process flow 300 may be implemented as instructions stored in memory (e.g., firmware stored in storage devices 130, 230 and / or main memory 125, 225). For example, instructions, when executed by a controller, may cause the controller to perform the operation of process flow 300. Although described with reference to inter-memory data movement between storage devices and main memory, aspects of process flow 300 may be implemented for inter-memory data movement between storage devices and cache memory.

[0048] At 305, the device may be in a standby mode. For example, one or more components of the memory subsystem 210 may be in a low-power mode awaiting commands from the host device 205. At 310, commands and one or more addresses may be received. For example, the memory controller 240 may receive commands, a first address of the main memory 225, and a second address of the memory device 230. Commands, the first address, and the second address may be transmitted from the host device 205 to the memory device controller 204. In some instances, the command may be an inter-memory data movement command.

[0049] It should be understood that host device 205 may first determine to perform an inter-memory data move before issuing an inter-memory data move command. For example, when host device 205 determines that it wishes to access data in storage device 230 quickly and deterministically, host device 205 may determine to perform an inter-memory data move from storage device 230 to main memory 225. Alternatively, when host device 205 determines that it wishes to retain (e.g., in a power-efficient manner) data that is no longer used by host device 205, host device 205 may determine to perform an inter-memory data move from main memory 225 to storage device. Similar determinations may prompt an inter-memory data move between storage device 230 and cache memory 220, where possible additional considerations include access frequency, data priority, and error correction requirements.

[0050] At point 315, it can be determined whether the command is an access command for a storage device. For example, storage device controller 240 can determine whether the command is an access command for storage device 230. In some instances, the operation at point 315 can be described as storage device controller 240 determining whether the command is a data movement command between memories. Alternatively, the operation at point 315 can be described as storage device controller 240 determining whether the command implies multiple memories.

[0051] If at 315 it is determined that the command is an access command for storage device 230 (e.g., the command is not for inter-memory data movement), then memory subsystem 210 can satisfy the access command at 320 and the process can proceed to 305. For example, memory subsystem 210 can read data from storage device 230 and transfer the data back to host device 205. Alternatively, memory subsystem 210 can write the provided data to storage device 230. If at 315 it is determined that the command is not an access command for storage device 230 (e.g., the command is for inter-memory data movement), then the process can proceed to 325. At 325, the direction of the inter-memory data movement can be determined. For example, storage device controller 240 can determine whether the direction of the data movement is from main memory 225 to storage device 230 or from storage device 230 to main memory 225.

[0052] If it is determined at 325 that the data movement is from main memory 225 to storage device 230, the process can proceed to 330. At 330, an instruction to suspend activity in main memory 225 can be transmitted. For example, storage device controller 240 can instruct host device 205 to suspend activity by asserting MAF. By instructing a suspension after receiving the command, storage device controller 240 can prevent host device 205 from interfering with data movement between memories. In effect, host device 205 can suspend activity in main memory 225 after receiving the instruction. Suspension of memory activity may involve buffering one or more additional access commands for memory that will be issued later. At 335, the access command and a first address can be transmitted to the controller for main memory. For example, storage device controller 240 can transmit a read command and a first address to storage controller 235. Storage device controller 240 can also transmit a write command and a second address to storage device 230.

[0053] At 340, data can be transferred from main memory to storage device. For example, memory subsystem 210 can transfer data from main memory 225 to storage device 230. To do this, data (or at least a subset of data) can be read from a first memory address in main memory 225, transferred via data path 295, and written to a second memory address in storage device 230. In some instances, multiple subsets of data can be transferred serially in this manner. At 345, it can be determined that the transfer of data from main memory to storage device is complete. For example, storage device controller 240 can determine that the transfer of data from main memory 225 to storage device 230 is complete (e.g., the last subset of data has been transferred to and / or stored in storage device 230). Therefore, at 350, an indication that main memory activity can be restored can be transmitted. For example, storage device controller 240 can indicate to host device 205 (by disabling MAF) that main memory 225 activity can be restored. Therefore, host device 205 can resume activity on main memory 225 by issuing one or more access commands for main memory 225. After 350, the process can proceed to 305. Thus, memory subsystem 210 can facilitate inter-memory data movement from main memory 225 to storage device 230.

[0054] If it is determined at 325 that the data movement is from storage device 230 to main memory 225, the process can proceed to 355. At 355, an access command and a second address can be transmitted to the storage device. For example, the storage device controller 240 can transmit a read command and a second address to storage device 230. In response to the read command, storage device 230 can prepare data (or at least a subset of data) for transmission to main memory 225. For example, storage device 230 can read data (or at least a subset of data) from the second address of storage device 230 and transmit the data (or at least a subset of data) to a buffer for forwarding to main memory 225.

[0055] Because the amount of time required to prepare data at storage device 230 is unknown (due to the nondeterministic access latency of storage device 230), memory subsystem 210 avoids asserting MAF until the data is ready for transmission. This technique allows host device 205 to continue accessing main memory 225 while storage device 230 is busy. At 360, it can be determined that data is ready for communication to main memory. For example, storage device controller 240 can determine that data from storage device 230 is ready for communication to main memory 225. If data is buffered or held at a position where it can be easily transmitted (e.g., within a threshold amount of time), then the data can be considered ready for communication. At 365, an indication that activity in main memory should be suspended can be transmitted. For example, storage device controller 240 can indicate a suspension of activity to host device 205 by asserting MAF. By indicating a suspension after receiving a command, storage device controller 240 prevents host device 205 from interfering with data movement between memories. In effect, host device 205 can suspend activity in main memory 225 after receiving the indication.

[0056] At 370, an access command and a first address can be transmitted to the controller for main memory. For example, memory device controller 240 can transmit a write command and a first address to memory controller 235. At 375, data can be transferred from the storage device to main memory. For example, memory subsystem 210 can transfer data from storage device 230 to main memory 225. To do this, data (or at least a subset of data) can be transferred from a second memory address in storage device 230, via data path 295, and written to a first memory address in main memory 225. In some instances, multiple subsets of data can be transferred serially in this manner.

[0057] After 375, the process can proceed to 345. At 345, it can be determined that the transfer of data from the storage device to the main memory is complete. For example, the storage device controller 240 can determine that the transfer of data from the storage device 230 to the main memory 225 is complete (e.g., the last subset of data has been transferred to and / or stored in the main memory 225). Therefore, at 350, an indication that the activity of the main memory can be restored can be transmitted. For example, the storage device controller 240 can indicate to the host device 205 (by disabling MAF) that activity on the main memory 225 can be restored. Therefore, the host device 205 can restore activity on the main memory 225 by issuing one or more access commands for the main memory 225. After 350, the process can proceed to 305. Therefore, the memory subsystem 210 can satisfy the inter-memory data movement from the storage device 230 to the main memory 225.

[0058] Although described with reference to the inter-memory data movement between storage device 230 and main memory 225, it should be understood that the operation of process flow 300 may be similar to the inter-memory data movement between storage device 230 and main memory 225. It should also be understood that alternative instances of process flow 300 may be implemented, some of which may be performed in a different order than described or not at all. Furthermore, operations may include additional features not mentioned, or additional operations may be added. Additionally, certain operations may be performed multiple times, or certain combinations of repeatable or cyclical operations may be performed.

[0059] Various aspects of process flow 300 may be implemented by a controller and other components. Alternatively, aspects of process flow 300 may be implemented as instructions stored in memory (e.g., firmware stored in memory coupled to a memory subsystem 210, such as main memory 225, cache memory 220, or another memory). For example, when executed by a controller (e.g., memory controller 235, storage device controller 240), the instructions may cause the controller to perform the operations of block diagram 400.

[0060] Figure 4 A block diagram 400 illustrates a memory device 405 supporting improved inter-memory movement in a multi-memory system, according to an example disclosed herein. The memory device 405 may be as described in the references... Figure 1 and 2Examples of various aspects of the described memory subsystem. Memory device 405 may include a first controller 410, a routing circuitry 415, a first memory 420, a second memory 425, and a second controller 430. Each of these modules may communicate directly or indirectly with each other (e.g., via one or more buses). The first controller 410 may be used with the first memory 420, and the second controller 430 may be used with at least the second memory 425. In some cases, the first memory 420 has greater access latency and lower power consumption than the second memory 425, and wherein the first memory 420 operates as a longer-term storage device compared to the second memory 425, while the second memory 425 operates as main memory or cache.

[0061] The first controller 410 may be or include logic, circuitry, a processor, a controller, or other components capable of performing the functions described herein. The routing circuitry 415 may be or include a data bus, a data bus interface, a switch, a multiplexer, an I / O channel, logic, a buffer, or other components capable of performing the functions described herein. The first memory 420 may be or include a memory, a memory array, a memory die, or other components capable of performing the functions described herein. The second memory 425 may be or include a memory, a memory array, a memory die, or other components capable of performing the functions described herein. The second controller 430 may be or include logic, circuitry, a processor, a controller, or other components capable of performing the functions described herein.

[0062] The first controller 410 may receive from the host device an address for the second memory 425 and commands for moving data between the first memory 420 and the second memory 425. In some instances, the first controller 410 may transmit a second address and access commands to a second controller for the second memory 425 based on the commands. In some instances, the first controller 410 may receive from the host device an address for the second memory 425 and commands for moving data between the first memory 420 and the second memory 425.

[0063] In some instances, the first controller 410 may transmit a second address and an access command to a second controller for the second memory 425 based on a command. In some instances, the first controller 410 may transmit an instruction from the host device to suspend activity on the second memory 425 after receiving the command and before transmitting the access command to the second controller.

[0064] In some instances, the first controller 410 may transmit an instruction to the host device to resume activity on the second memory 425 based on storing data in the first memory 420. In some instances, the first controller 410 may determine that at least a portion of the data is ready to be transferred from the first memory 420. In some instances, the first controller 410 may transmit an instruction to the host device to suspend activity on the second memory 425 based on determining that at least a portion of the data is ready to be transferred from the first memory 420.

[0065] In some instances, the first controller 410 may transmit an instruction from the host device to resume activity in the second memory 425 based on data stored in the second memory 425. In some instances, the first controller 410 may transmit an instruction from the host device to suspend activity in the second memory 425 after receiving a command and before transmitting the access command to the second controller.

[0066] In some instances, the first controller 410 may transmit an instruction to the host device that the host device can restore activity to the second memory 425 based on storing data in the first memory 420. In some instances, the first controller 410 may transmit a read command for the second memory 425 to the second controller. In some instances, the first controller 410 may determine that at least a portion of the data is ready to be transferred from the first memory 420.

[0067] In some instances, the first controller 410 may transmit an instruction from the host device to suspend activity on the second memory 425 based on determining that at least a portion of the data is ready to be transferred from the first memory 420. In some instances, the first controller 410 may transmit an instruction from the host device to resume activity on the second memory 425 based on data stored in the second memory 425. In some instances, the first controller 410 may transmit a write command for the second memory to a second controller for the second memory 425.

[0068] The routing circuit system 415 can transfer data between the first memory 420 and the second memory 425 via a data path external to the host device, at least in part based on the transmission of the second address and access command. In some instances, the routing circuit system 415 can transfer data between the first memory 420 and the second memory 425 via a data path external to the host device, at least in part based on the transmission of the second address and access command.

[0069] The first memory 420 can store data. In some instances, the first memory 420 can perform write operations on one or more memory cells at a first address to write a portion of data to the first memory 420. In some instances, the first memory 420 can perform read operations on one or more memory cells at a first address to read at least a portion of data from the first memory 420. In some instances, the first memory 420 can store data. In some instances, the first memory 420 can perform write operations on one or more memory cells at a first address to write a portion of data to the first memory 420. In some instances, the first memory 420 can perform read operations on one or more memory cells at a first address to read at least a portion of data from the first memory 420.

[0070] In some cases, the first memory 420 has greater access latency and lower power consumption than the second memory 425, and wherein the first memory 420 operates as a longer-term storage device compared to the second memory 425, and the second memory 425 operates as main memory or cache.

[0071] The second memory 425 can perform read operations on one or more memory cells at a second address based on a read command to read at least a portion of the data from the second memory 425. In some instances, the second memory 425 can store data in the second memory 425. In some instances, the second memory 425 can perform write operations on one or more memory cells at a second address based on a write command to write a portion of the data into the second memory 425. In some instances, the second memory 425 can perform read operations on one or more memory cells at a second address based on a read command to read at least a portion of the data from the second memory 425. In some instances, the second memory 425 can store data in the second memory 425. In some instances, the second memory 425 can perform write operations on one or more memory cells at a second address based on a write command to write a portion of the data into the second memory 425.

[0072] The second controller 430 may receive one or more access commands for the second memory 425 from the host device during the duration during which the first memory 420 prepares data for communication. In some instances, the second controller 430 may service one or more access commands at the second memory 425 during the duration during which data is prepared by the first memory 420.

[0073] Figure 5The flowchart illustrates one or more methods 500 for improved inter-memory movement in a multi-memory system according to various aspects of this disclosure. Operation of method 500 may be implemented by a memory device or its components as described herein. For example, operation of method 500 may be performed as described in reference... Figure 4 The described memory device performs the functions described herein. In some instances, the memory device may execute a set of instructions to control the functional elements of the memory device to perform the described functions. Alternatively, the memory device may use dedicated hardware to perform aspects of the described functions.

[0074] At point 505, the method may include receiving an address for a second memory and a command to move data between the first memory and the second memory from a host device and a first controller for the first memory. Operation of point 505 may be performed according to the method described herein. In some instances, aspects of the operation of point 505 may be derived from, as referenced... Figure 4 The first controller described is used.

[0075] At point 510, the method may include, based on a command, transmitting a second address and an access command from a first controller to a second controller for a second memory. Operation of 510 may be performed according to the method described herein. In some instances, aspects of the operation of 510 may be derived from, as referenced... Figure 4 The first controller described is used.

[0076] At point 515, the method may include transferring data between the first and second memories via a data path external to the host device, based at least in part on a transfer second address and access command. Operation of point 515 may be performed according to the method described herein. In some instances, aspects of the operation of point 515 may be derived from, as referenced... Figure 4 The described data path components are used.

[0077] In some instances, the apparatus as described herein may perform one or more methods, such as method 500. The apparatus may include features, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: receiving an address for a second memory and a command to move data between the first and second memories from a host device and at a first controller for the first memory; transmitting a second address and access command from the first controller to a second controller for the second memory based on the command; and transferring data between the first and second memories via a data path external to the host device, at least in part based on the transmission of the second address and access command.

[0078] Some examples of the method 500 and device described herein may further include operations, features, components, or instructions for: transmitting an indication from the first controller to the host device that the host device can suspend activity of the second memory after receiving a command and before transmitting the access command to the second controller.

[0079] Some examples of the methods 500 and devices described herein may further include operations, features, components, or instructions for: storing data in a first memory, and having a first controller transmit an indication to the host device that the host device can restore activity to a second memory based on storing data in the first memory.

[0080] In some instances of the method 500 and apparatus described herein, the command may be to move data from a second memory that may have deterministic access timing to a first memory that may have nondeterministic access timing, and wherein the transfer access command may include operations, features, components, or instructions for transferring a read command for the second memory to a second controller.

[0081] In some instances of the method 500 and apparatus described herein, receiving may include operations, features, components, or instructions for: performing a read operation on one or more memory cells at a second address based on a read command to read at least a portion of data from the second memory, and performing a write operation on one or more memory cells at a first address to write a portion of the data into the first memory.

[0082] Some examples of the methods 500 and devices described herein may further include operations, features, components, or instructions for: determining that at least a portion of data is ready to be transferred from the first memory, and, based on the determination that at least a portion of the data is ready to be transferred from the first memory, transmitting an indication from the first controller that the host device may suspend activity on the second memory to the host device.

[0083] Some examples of the methods 500 and devices described herein may further include operations, features, components, or instructions for: receiving one or more access commands for a second memory from a host device during a duration during which data can be prepared by the first memory for communication, and servicing one or more access commands at the second memory during the duration during which data can be prepared by the first memory.

[0084] Some examples of the methods 500 and devices described herein may further include operations, features, components, or instructions for: storing data in a second memory, and transmitting an indication from a first controller to a host device that the host device can restore activity to the second memory based on the data stored in the second memory.

[0085] In some instances of the method 500 and apparatus described herein, the command may be to move data from a first memory that may have nondeterministic access timing to a second memory that may have deterministic access timing, and wherein the transfer access command may include operations, features, components, or instructions for transferring a write command for the second memory to a second controller for the second memory.

[0086] In some instances of the method 500 and apparatus described herein, receiving may include operations, features, components, or instructions for: performing a read operation on one or more memory cells at a first address to read at least a portion of data from the first memory, and performing a write operation on one or more memory cells at a second address based on a write command to write a portion of the data into the second memory.

[0087] In some instances of the method 500 and apparatus described herein, the first memory may have greater access latency and lower power consumption than the second memory, and wherein the first memory may operate as a longer-term storage device compared to the second memory, and the second memory may operate as main memory or cache.

[0088] It should be noted that the methods described herein describe possible implementations, and that the operations and steps may be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more parts from the methods may be combined.

[0089] The device may include a first memory, a second memory, and a controller coupled to the first memory and the second memory, the controller being configured such that the device: receives from a host device and at a first controller for the first memory an address for the second memory and a command to move data between the first memory and the second memory; transmits a second address and an access command from the first controller to the second controller for the second memory, at least in part based on the command; and transmits data between the first memory and the second memory via a data path outside the host device, at least in part based on the transmission of the second address and the access command.

[0090] In some cases, the command is to move data from a second memory with deterministic access timing to a first memory with nondeterministic access timing, and wherein the controller is further configured such that the device, after receiving the command and before transmitting the access command to the second controller, transmits an instruction from the host device to the host device to suspend activity in the second memory via the first controller.

[0091] In some cases, the controller is further configured such that the device stores data in the first memory, and the first controller transmits an indication to the host device that the host device can restore activity to the second memory, based at least in part on the storage of data in the first memory.

[0092] In some cases, the access command includes a read command and receiving includes receiving a first address for the first memory, wherein the controller is further configured to cause the device to perform a read operation on one or more memory cells at a second address at least in part based on the read command to read at least a portion of the data from the second memory, and to perform a write operation on one or more memory cells at the first address to write a portion of the data into the first memory.

[0093] In some cases, the command is to move data from a first memory with nondeterministic access timing to a second memory with deterministic access timing, and wherein the controller is further configured to cause the device to determine that at least a portion of the data is ready to be transferred from the first memory, and the first controller transmits an instruction from the host device to the host device to suspend activity in the second memory based at least in part on the determination that at least a portion of the data is ready to be transferred from the first memory.

[0094] In some cases, the controller is further configured such that the device stores data in a second memory, and the first controller transmits an indication to the host device that the host device can restore activity to the second memory, based at least in part on the data stored in the second memory.

[0095] In some cases, the access command includes a write command and receiving includes receiving a first address for the first memory, wherein the controller is further configured to cause the device to perform a read operation on one or more memory cells at the first address to read at least a portion of the data from the first memory, and to perform a write operation on one or more memory cells at a second address, at least in part, based on the write command, to write a portion of the data to the second memory.

[0096] In some cases, the first memory has greater access latency and lower power consumption than the second memory, and wherein the first memory operates as a longer-term storage device compared to the second memory, while the second memory operates as main memory or cache.

[0097] The information and signals described herein can be represented using any of a variety of techniques and methods. For example, voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof, can be used to represent data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing description. Some diagrams may show signals as single signals; however, those skilled in the art will understand that the signals may represent signal buses, where the buses may have various bit widths.

[0098] The terms "electronic communication," "conductive contact," "connection," and "coupling" can refer to a relationship between components that supports the flow of signals between them. Components are considered to be in electronic communication (or in conductive contact, connected, or coupled) with each other if there exists any conductive path between them that supports the flow of signals at any given time. At any given time, the conductive path between components that are in electronic communication (or in conductive contact, connected, or coupled) can be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components can be a direct conductive path between the components, or an indirect conductive path between connected components that may include intermediate components such as switches, transistors, or other components. In some instances, one or more intermediate components, such as switches or transistors, can be used to interrupt the signal flow between connected components for a period of time.

[0099] The term "coupling" refers to a shift from an open-circuit relationship between components to a closed-circuit relationship. In an open-circuit relationship, signals cannot currently travel between components via conductive paths, while in a closed-circuit relationship, signals can travel between components via conductive paths. When a component, such as a controller, couples other components together, it represents a change in the flow of the component's startup signal between those components via conductive paths that were previously not permitted.

[0100] The term "isolation" refers to a relationship between components where signals are currently not allowed to flow between them. If there is an open circuit between components, then the components are isolated from each other. For example, when a switch is open, the components separated by the switch positioned between them are isolated from each other. When a controller isolates two components, it prevents signals from flowing between the components using previously permitted conductive paths.

[0101] As used herein, the term "layer" or "level" refers to a layer or sheet of geometry (e.g., relative to a substrate). Each layer or level may have three dimensions (e.g., height, width, and depth) and may cover at least a portion of a surface. For example, a layer or level may be a three-dimensional structure in which two dimensions are greater than the third, such as a thin film. A layer or level may contain different elements, components, and / or materials. In some instances, a layer or level may consist of two or more sublayers or sublevels.

[0102] As used in this article, the term “generally” means that a modified feature (e.g., a verb or adjective modified by the term “generally”) does not have to be absolute but must be close enough to achieve the advantage of the feature.

[0103] As used herein, the term "electrode" can refer to an electrical conductor and, in some instances, can serve as an electrical contact to a memory cell or other component of a memory array. An electrode may comprise traces, wires, conductive lines, conductive layers, etc., that provide a conductive path between elements or components of the memory array.

[0104] The devices containing memory arrays discussed herein can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, and gallium nitride. In some instances, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemicals including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0105] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include a three-terminal device comprising a source, drain, and gate. The terminals may be connected to other electronic components via a conductive material, such as a metal. The source and drain may be conductive and may comprise heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., the majority of charge carriers are electrons), then the FET may be called an n-type FET. If the channel is p-type (i.e., the majority of charge carriers are holes), then the FET may be called a p-type FET. The channel may be end-capped by an insulating gate oxide. The conductivity of the channel can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, makes the channel conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "on" or "activated." When a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "off" or "deactivated."

[0106] The description herein, illustrated with reference to the accompanying drawings, describes example configurations and does not represent all implementable or within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description" and is not "preferred" or "superior" to other examples. The embodiments include specific details that provide an understanding of the described techniques. However, these techniques may be practiced without these details. In some examples, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0107] In the accompanying drawings, similar components or features may have the same reference label. Additionally, various components of the same type can be distinguished by a dash following the reference label and a second label that differentiates them among similar components. If only the first reference label is used in the specification, the description applies to any similar component that has the same first reference label but is independent of the second reference label.

[0108] The information and signals described herein can be represented using any of a variety of techniques and methods. For example, voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof, can be used to represent data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing description.

[0109] The various illustrative blocks and modules described herein can be implemented or performed using a general-purpose processor, DSP, ASIC, FPGA, or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The general-purpose processor may be a microprocessor; however, alternatively, the processor may be any processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such device).

[0110] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored as one or more instructions or codes on or transmitted via a computer-readable medium. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described herein can be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functions can also be physically located in various locations, including distributions such that portions of the functions are implemented in different physical locations. Furthermore, as used herein (included in the claims), "or" as used in a list of items (e.g., a list of items beginning with phrases such as "at least one of" or "one or more of") indicates an inclusive list, such that a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be construed as referring to a set of closing conditions. For example, without departing from the scope of this disclosure, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should also be interpreted as the phrase "at least partially based on".

[0111] Computer-readable media includes both non-transitory computer storage media and communication media, with communication media encompassing any media that facilitates the transfer of a computer program from one place to another. Non-transitory storage media can be any available media accessible by a general-purpose or special-purpose computer. By way of example, and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code components in the form of instructions or data structures and is accessible by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then such coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of media. As used herein, disks and optical discs include CDs, laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, where disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of these are also included within the scope of computer-readable media.

[0112] The description herein is provided to enable those skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but is given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus comprising: a first controller for a first memory; a second controller for a second memory; and one or more controllers coupled with the first memory and the second memory, the one or more controllers configured to cause the apparatus to: receive a move data command from a host device; determine a direction of a data move is from the first memory to the second memory based on the command being an inter-memory data move command for a data move between the first memory and the second memory via a data path external to the host device; transmit, from the first controller to the host device, an indication that the host device is to suspend access activity to the second memory based on the command being an inter-memory data move command, wherein the indication to suspend access activity is transmitted after a read command to the first controller to transmit the data is transmitted based on the direction of the data move being from the first memory to the second memory; and transmit, based on transmitting the read command, the data from the first memory to the second memory via the data path external to the host device.

2. The apparatus of claim 1, wherein the second memory has deterministic access timing and the first memory has non-deterministic access timing, and wherein the indication to suspend access activity is transmitted after transmitting the read command based on the first memory having the non-deterministic access timing.

3. The apparatus of claim 1, wherein the one or more controllers are further configured to cause the apparatus to: determine that the data is ready to be transmitted from the first memory to the second memory, wherein the indication to suspend access activity is transmitted based on determining that the data is ready to be transmitted.

4. The apparatus of claim 1, wherein the one or more controllers are further configured to cause the apparatus to: determine that the move data command is associated with a plurality of memories of the apparatus, wherein the command is determined to be an inter-memory data move command based on determining that the command is associated with the plurality of memories.

5. The apparatus of claim 1, wherein the one or more controllers are further configured to cause the apparatus to: transmit, by the first controller, an indication that the host device is to resume activity to the second memory based on determining that the data has been transmitted from the first memory to the second memory.

6. The apparatus of claim 1, wherein the move data command is associated with a first address of the first memory, and wherein the one or more controllers are further configured to cause the apparatus to: transmit the first address from the first controller to the first memory, wherein the indication to suspend access activity is transmitted after transmitting the first address based on the direction of the data move being from the first memory to the second memory.

7. The apparatus of claim 6, wherein the move data command is associated with a second address of the second memory, and wherein the one or more controllers are further configured to cause the apparatus to: ​ transmitting the indication to suspend access activity prior to transmitting the second address based on the direction of the data movement being from the first memory to the second memory.

8. A method comprising: receiving a command to move data at a device comprising a first memory and a second memory; determining a direction of the data movement is from the first memory to the second memory based on the command being an inter-memory data movement command for data movement between the first memory and the second memory via a data path external to a host device; transmitting, by a host device, an indication that the host device is to suspend access activity to the second memory from a first controller for the first memory to the host device based on the command being the inter-memory data movement command, wherein the indication to suspend access activity is transmitted after a read command to transmit the data to a first controller for the first memory based on the direction of the data movement being from the first memory to the second memory; and transmitting the data from the first memory to the second memory via the data path external to the host device based on transmitting the read command.

9. The method of claim 8, wherein the second memory has deterministic access timing and the first memory has non-deterministic access timing, and wherein the indication to suspend access activity is transmitted after transmitting the read command based on the first memory having the non-deterministic access timing.

10. The method of claim 8, further comprising: determining that the data is ready to be transmitted from the first memory to the second memory, wherein the indication to suspend access activity is transmitted based on determining that the data is ready to be transmitted.

11. The method of claim 8, further comprising: determining that the command to move data is associated with a plurality of memories of the device, wherein the command is determined to be an inter-memory data movement command based on determining that the command is associated with a plurality of memories.

12. The method of claim 8, wherein the command to move data is associated with a first address of the first memory and a second address of the second memory.

13. The method of claim 12, further comprising: transmitting, by the first controller for the first memory and prior to transmitting the indication to suspend access activity, the first address to the first memory; and transmitting, by the first controller after transmitting the indication to suspend access activity, the second address to a second controller for the second memory.

14. The method of claim 8, further comprising: transmitting an indication that the host device is to resume activity to the second memory based on determining that the data has been transmitted from the first memory to the second memory.

15. A device comprising: a first controller for a first memory; a second controller for a second memory; and a host device coupled to the first controller and the second controller. ​ one or more controllers coupled with the first memory and the second memory, the one or more controllers configured to cause the device to: based on the received command being a memory-to-memory data movement command, determine a direction of data movement is from the second memory to the first memory; based on the received command being a memory-to-memory data movement command, transmit, from the first controller to a host device, an indication that the host device is to suspend access activity to the second memory, wherein the indication to suspend access activity is transmitted prior to transmitting a read command for the data to the second controller based on the direction of data movement being from the second memory to the first memory; and based on transmitting the indication of the read command, transmit the data from the second memory to the first memory via a data path external to the host device.

16. The device of claim 15, wherein the second memory has deterministic access timing and the first memory has non-deterministic access timing, and wherein the indication to suspend access activity is transmitted prior to transmitting the read command based on the first memory having the non-deterministic access timing.

17. The device of claim 15, wherein the one or more controllers are further configured to cause the device to: determine that the received command is associated with a plurality of memories of the device, wherein determining that the received command is a memory-to-memory data movement command is based on determining that the received command is associated with a plurality of memories.

18. The device of claim 15, wherein the received command is associated with a first address of the first memory and a second address of the second memory, and wherein the one or more controllers are further configured to cause the device to: transmit, by the first controller to the second controller, the second address after transmitting the indication to suspend access activity.

19. The device of claim 18, wherein the one or more controllers are further configured to cause the device to: based on transmitting the second address to the second controller, transmit, by the first controller to the first memory, the first address.

20. The device of claim 15, wherein the one or more controllers are further configured to cause the device to: based on determining that the data has been transmitted from the second memory to the first memory, transmit, by the first controller, an indication that the host device is to resume active access to the second memory.

21. The device of claim 15, wherein the one or more controllers are further configured to cause the device to: based on the received command being a memory-to-memory data movement command, transmit, from the first controller to a host device, an indication that the host device is to suspend access activity to the second memory, wherein the indication to suspend access activity is transmitted prior to transmitting a read command for the data to the second controller based on the direction of data movement being from the second memory to the first memory; and based on transmitting the indication of the read command, transmit the data from the second memory to the first memory via a data path external to the host device.

Images