Storage unit circuit and shift sorting circuit and electronic device including the same

Abstract

The present disclosure provides a storage unit circuit, which includes: a data valid signal input terminal receiving a data valid signal; a data input terminal receiving input data; a shift signal output terminal outputting a shift signal; a data output terminal outputting stored data; a clear signal input terminal receiving a clear signal; a first storage module for updating stored data with data to be stored; and a control circuit for generating a shift signal based on the data valid signal and the clear signal. The present disclosure also relates to a shift sorting circuit including the storage unit circuit, and an electronic device including the shift sorting circuit.

Description

Technical Field

[0001] The present disclosure relates to the field of electronic technology, and in particular, to a memory cell circuit, and also to a shift sorting circuit including the memory cell circuit and an electronic device including the shift sorting circuit. Background Art

[0002] Currently, in the field of data processing, there is an increasing need to sort and manage data based on the degree of aging of the data. For example, in applications involving ray tracing, it is usually hoped that the old light data can be traversed as quickly as possible so that the cache space can be released after the traversal is completed, so that the cache space can be allocated to new light data. However, in the conventional scheme of the related art, it is necessary to record the degree of aging of each light data and the corresponding storage location during the entire traversal process. Therefore, in the case where a large amount of light data (for example, more than 64) needs to be sorted and managed based on the degree of aging, the conventional scheme cannot achieve the sorting and management of the light data based on the degree of aging, or it requires excessive resource costs.

[0003] Therefore, it is desirable to provide a sorting circuit that can implement aging-based sorting management of data at a relatively low resource cost. Summary of the invention

[0004] According to a first aspect of the present disclosure, a storage unit circuit is provided, comprising: a data input terminal configured to receive input data; a data output terminal configured to output storage data; a data valid signal input terminal configured to receive a data valid signal, wherein the data valid signal indicates that the input data can be stored in the storage unit circuit when it is valid; a shift signal output terminal configured to output a shift signal, wherein the shift signal indicates that the storage data can be output to the next level storage unit circuit through the data output terminal when it is valid; a clear signal input terminal configured to receive a clear signal, wherein the clear signal indicates that the storage data is invalid when it is valid; a first storage module configured to store input data, or to update the storage data stored in the first storage module with the input data when the data valid signal is valid, or to output the storage data to the next level storage unit circuit through the data output terminal when the shift signal is valid; and a control circuit configured to invalidate the shift signal in response to at least one of the following situations, including: the data valid signal is invalid, and the clear signal is valid.

[0005] According to some example embodiments, the control circuit is further configured to: in response to the data valid signal being valid and the clear signal being invalid, enable the shift signal.

[0006] According to some exemplary embodiments, the memory cell circuit further includes a data strobe circuit configured to: in response to the data valid signal being valid, output the input data as data to be stored to the first memory module.

[0007] According to some exemplary embodiments, the data selection circuit includes a controlled switch element, and the controlled switch element includes an input terminal, an output terminal and a control terminal, wherein the input terminal is electrically connected to the data input terminal, the control terminal is electrically connected to the data valid signal input terminal, and the output terminal is electrically connected to the input terminal of the first storage module; wherein the controlled switch element is configured to: in response to the data valid signal applied to the control terminal being valid, connect the input terminal and the output terminal of the controlled switch element; in response to the data valid signal applied to the control terminal being invalid, disconnect the conduction between the input terminal and the output terminal of the controlled switch element.

[0008] According to some exemplary embodiments, the storage unit circuit also includes a data selection circuit, which is configured to: in response to the data valid signal being valid, output the input data as the data to be stored to the first storage module; in response to the data valid signal being invalid, transmit the storage data output from the data output end to the first storage module as the data to be stored.

[0009] According to some exemplary embodiments, the data selection circuit includes a selector, which includes a first input terminal, a second input terminal, a control terminal and an output terminal, wherein the first input terminal is electrically connected to the data input terminal, the second input terminal is electrically connected to the data output terminal, the control terminal is electrically connected to the data valid signal input terminal, and the output terminal is electrically connected to the input terminal of the first storage module; wherein the selector is configured to: in response to the data valid signal applied to the control terminal being valid, the first input terminal and the output terminal are turned on; in response to the data valid signal applied to the control terminal being invalid, the second input terminal and the output terminal are turned on.

[0010] According to some exemplary embodiments, the storage unit circuit also includes a second storage module, which is configured to: receive storage unit occupancy update information, update the storage unit occupancy information stored in the second storage module with the storage unit occupancy update information, and output the storage unit occupancy information to the control circuit, wherein the storage unit occupancy information indicates that the first storage module has been occupied when it is valid.

[0011] According to some example embodiments, the control circuit is further configured to: in response to the memory cell occupancy information being invalid, invalidate the shift signal.

[0012] According to some exemplary embodiments, the control circuit is further configured to: validate the storage unit occupancy update information in response to at least one of the following situations, including: the data valid signal is valid, the storage unit occupancy information is valid and the clear signal is invalid; invalidate the storage unit occupancy update information in response to the data valid signal being invalid and the storage unit occupancy information being invalid or the clear signal being valid.

[0013] According to some exemplary embodiments, the first storage module and / or the second storage module includes a memory constituted by a D flip-flop.

[0014] According to some example embodiments, the first storage module and / or the second storage module includes a register.

[0015] According to some exemplary embodiments, the control circuit also includes a shift signal generating circuit, wherein the shift signal generating circuit includes: an inversion gate circuit, whose input terminal is electrically connected to the clear signal input terminal; an AND gate circuit, whose first input terminal is electrically connected to the data valid signal input terminal, whose second input terminal is electrically connected to the output terminal of the second storage module, whose third input terminal is electrically connected to the output terminal of the inversion gate circuit, and whose output terminal is electrically connected to the shift signal output terminal.

[0016] According to some exemplary embodiments, the control circuit includes a storage unit occupancy information update circuit, wherein the storage unit occupancy information update circuit includes: an inversion gate circuit, whose input end is electrically connected to the clear signal input end; an AND gate circuit, whose first input end is electrically connected to the output end of the second storage module, and whose second input end is electrically connected to the output end of the inversion gate circuit; and an OR gate circuit, whose first input end is electrically connected to the data valid signal input end, whose second input end is electrically connected to the output end of the AND gate circuit, and whose output end is electrically connected to the input end of the second storage module.

[0017] According to some exemplary embodiments, the control circuit includes: an inversion gate circuit, whose input end is electrically connected to the clear signal input end to generate an inversion signal of the clear signal; an AND gate circuit, whose first input end is electrically connected to the data valid signal input end, whose second input end is electrically connected to the output end of the second storage module, whose third input end is electrically connected to the output end of the inversion gate circuit, and whose output end is electrically connected to the shift signal output end; a first AND gate circuit, whose first input end is electrically connected to the data valid signal input end, whose second input end is electrically connected to the output end of the second storage module, whose third input end is electrically connected to the output end of the inversion gate circuit, and whose output end is electrically connected to the shift signal output end; a second AND gate circuit, whose first input end is electrically connected to the output end of the second storage module, whose second input end is electrically connected to the output end of the inversion gate circuit; an OR gate circuit, whose first input end is electrically connected to the data valid signal input end, whose second input end is electrically connected to the output end of the AND gate circuit, and whose output end is electrically connected to the input end of the second storage module.

[0018] According to some exemplary embodiments, the memory cell circuit further includes a data strobe circuit, the data strobe circuit including a selector, the selector including a first selector input terminal, a second selector input terminal, a selector control terminal and a selector output terminal, wherein the first selector input terminal is electrically connected to the data input terminal, the second selector input terminal is electrically connected to the data output terminal, the selector control terminal is electrically connected to the data valid signal input terminal, the selector output terminal is electrically connected to the input terminal of the first memory module, and wherein the selector is configured to: in response to the data valid signal applied to the selector control terminal being valid, the first selector input terminal is turned on and the selector output terminal is turned on, and in response to the data valid signal applied to the selector control terminal being invalid, the second selector input terminal is turned on and the selector output terminal is turned on. The selector output end is turned on; the control circuit includes: a first inverter circuit, whose input end is electrically connected to the clear signal input end; a first AND gate circuit, whose first input end is electrically connected to the data valid signal input end, whose second input end is electrically connected to the output end of the second storage module, whose third input end is electrically connected to the output end of the second inverter circuit, and whose output end is electrically connected to the shift signal output end; a second inverter circuit, whose input end is electrically connected to the clear signal input end; a second AND gate circuit, whose first input end is electrically connected to the output end of the second storage module, and whose second input end is electrically connected to the output end of the first inverter circuit; and an OR gate circuit, whose first input end is electrically connected to the data valid signal input end, whose second input end is electrically connected to the output end of the first AND gate circuit, and whose output end is electrically connected to the input end of the second storage module.

[0019] According to a second aspect of the present disclosure, a shift sorting circuit is provided, comprising N cascaded storage unit circuits according to the first aspect of the present disclosure and each exemplary embodiment thereof, wherein N is an integer greater than 1, and wherein the shift signal output terminal of the mth storage unit circuit in the N cascaded storage unit circuits is electrically connected to the data valid signal input terminal of the m+1th storage unit circuit, and the data output terminal of the mth storage unit circuit is electrically connected to the data input terminal of the m+1th storage unit circuit, wherein m is an integer and 1≤m <N。

[0020] According to a third aspect of the present disclosure, an electronic device is provided, comprising the shift sorting circuit according to the second aspect of the present disclosure.

[0021] The shift sorting circuit formed by the storage unit circuit disclosed in the present invention can sort data based on the aging degree of the data with fewer resources and simpler logic, and the signal flipping is very small, which can save chip area and reduce chip power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The specific embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings so that more details, features and advantages of the present disclosure can be more fully recognized and understood; in the accompanying drawings:

[0023] Figure 1 The structure of a memory cell circuit according to an exemplary embodiment of the present disclosure is schematically shown in the form of a block diagram;

[0024] Figure 2 According to an exemplary embodiment of the present disclosure, it is further schematically shown that Figure 1 Some details of the memory cell circuit shown;

[0025] Figure 3 According to an exemplary embodiment of the present disclosure, it is further schematically shown that Figure 1 Some details of the memory cell circuit shown;

[0026] Figure 4 According to an exemplary embodiment of the present disclosure, it is further schematically shown that Figure 3 Some details of the memory cell circuit are shown;

[0027] Figure 5 According to an exemplary embodiment of the present disclosure, it is further schematically shown that Figure 3 Some details of the memory cell circuit are shown;

[0028] Figure 6 The structure of a memory cell circuit according to another exemplary embodiment of the present disclosure is schematically shown in the form of a block diagram;

[0029] Figure 7 According to an exemplary embodiment of the present disclosure, it is further schematically shown that Figure 6 Some details of the memory cell circuit shown;

[0030] Figure 8 Schematically shows the structure of a memory cell circuit according to yet another exemplary embodiment of the present disclosure;

[0031] Fig. 9 Schematically illustrates the timing of some signals in a memory cell circuit according to various exemplary embodiments of the present disclosure;

[0032] Fig.10 The structure of a shift sorting circuit according to an exemplary embodiment of the present disclosure is schematically shown; and

[0033] Fig.11 The structure of an electronic device according to an exemplary embodiment of the present disclosure is schematically shown in the form of a block diagram.

[0034] It should be understood that the contents shown in the drawings are only schematic and therefore, they are not necessarily drawn to scale. In addition, in all the drawings, the same, similar or same type of features are indicated by the same or similar reference numerals. DETAILED DESCRIPTION

[0035] The following description provides specific details of each exemplary embodiment of the present disclosure, so that those skilled in the art can fully understand and implement the technical solutions described according to each exemplary embodiment of the present disclosure.

[0036] See also Figure 1 , which schematically shows the structure of a memory cell circuit according to an exemplary embodiment of the present disclosure in the form of a block diagram. Figure 1 As shown, the storage unit circuit 100 includes: a data valid signal input terminal Data-EN, a data input terminal Data-IN, a shift signal output terminal Shift-EN, a data output terminal Data-OUT, a clear signal input terminal Clear, a data strobe circuit 110, a first storage module 120, a control circuit 130 and a second storage module 140. The data valid signal input terminal Data-EN is configured to receive a data valid signal. The data input terminal Data-IN is configured to receive input data. The data valid signal is used to indicate whether the received input data can be stored in the storage unit circuit 100. Specifically, when the data valid signal is valid, it indicates that the received input data can be stored in the storage unit circuit 100. When the data valid signal is invalid, it indicates that the received input data cannot be stored in the storage unit circuit 100.

[0037] In each exemplary embodiment of the present disclosure, a signal is valid means that the signal is at a high potential, or in a logical "1" state, and a signal is invalid means that the signal is at a low potential, or in a logical "0" state. However, it should be understood that, according to actual needs, a signal is valid and can also mean that the signal is at a low potential, or in a logical "0" state, and a signal is invalid and means that the signal is at a high potential, or in a logical "1" state, and this situation does not conflict with the technical principle of the present invention. Therefore, the technical solutions in each exemplary embodiment of the present disclosure can be applied to the situation where the signal is valid and the signal is at a low potential (or logical "0") and the signal is invalid and the signal is at a high potential (or logical "1") after adaptive modification. That is to say, in the present disclosure, the validity and invalidity of a signal essentially refer to two different states of the signal, which can be embodied by the value of the corresponding physical parameter, such as the high and low potential. Therefore, any suitable physical parameter can be used to realize the validity and invalidity of the signal described in the present disclosure, as long as it has different parameter values, and the present disclosure is not limited to this. In addition, it should be understood that in the present disclosure, the terms "input end", "output end" and similar terms should be understood in a broad sense, that is, they may include not only situations where corresponding port features exist, but also situations where there are no port features but only leads or pins for realizing input, output or specific functions.

[0038] Continue to see Figure 1, wherein the shift signal output terminal Shift-EN is configured to output a shift signal, the data output terminal Data-OUT is configured to output storage data, and the clear signal input terminal Clear is configured to receive a clear signal. The shift signal is used to indicate whether the storage data output by the data output terminal Data-OUT can be stored in the connected next-level storage unit circuit, that is, when the shift signal is valid, the storage data of the storage unit circuit 100 is allowed to be stored in the connected next-level storage unit circuit, otherwise, the storage data is not allowed to be stored in the connected next-level storage unit circuit. The shift signal enables the data to be sorted based on the degree of aging (ie, age) in the shift sorting circuit composed of the storage unit circuit 100, which will be described in detail below. The storage data is the data stored in the storage unit circuit 100, which can be read or can be output to the next-level storage unit as described above to realize the shift of the storage data. The clear signal is used to clear the storage unit circuit 100, in other words, the clear signal is used to indicate whether the storage data stored in the storage unit circuit 100 is invalid. Specifically, when the clear signal is valid, it indicates that the storage data of the storage unit circuit 100 is invalid, and the storage data does not need to be shifted to the next level storage unit circuit, and can therefore be overwritten by new storage data. Therefore, when the clear signal is valid, the shift signal can be made invalid, and when the clear signal is valid and the data valid signal is invalid, the storage unit occupancy information can also be made invalid. The data selection circuit 110 is configured to: in response to the data valid signal being valid, the input data received from the data input terminal Data-IN is output as the data to be stored to the first storage module 120. The first storage module 120 is configured to: update the storage data stored in the first storage module 120 with the data to be stored, and output the storage data to the data output terminal Data-OUT. The second storage module 140 is configured to: receive the storage unit occupancy update information U-TMP, update the storage unit occupancy information U-VALID stored in the second storage module 140 with the storage unit occupancy update information U-TMP, and output the storage unit occupancy information U-VALID to the control circuit 130, wherein the storage unit occupancy information U-VALID indicates that the first storage module 120 has been occupied when it is valid. The control circuit 130 is configured to: generate a shift signal and the storage unit occupancy update information U-TMP based on the data valid signal, the clear signal and the storage unit occupancy information U-VALID.Specifically, the control circuit 130 is configured to: in response to a valid data valid signal, valid storage unit occupancy information and invalid clear signal, enable the shift signal; in response to at least one of the following situations, disable the shift signal, the situation including: the data valid signal is invalid, the storage unit occupancy information is invalid, and the clear signal is valid; in response to at least one of the following situations, enable the storage unit occupancy update information, the situation including: the data valid signal is valid, the storage unit occupancy information is valid and the clear signal is invalid; in response to the data valid signal being invalid, the storage unit occupancy information being invalid and / or the clear signal being valid, disable the storage unit occupancy update information.

[0039] The storage unit occupancy information U-VALID stored in the second storage module 140 indicates whether the first storage module 120 in the storage unit circuit 100 is currently occupied. In the case where the storage unit occupancy information U-VALID is valid, thereby indicating that the first storage module 120 is occupied, when receiving input data, the control circuit 130 will make the shift signal of the storage unit circuit 100 valid, so that the data stored in the first storage module 120 in the storage unit circuit 100 is shifted and output to another storage unit circuit connected to the data output terminal Data-OUT, and the input data is stored in the first storage module 120. In the case where the storage unit occupancy information U-VALID is invalid, thereby indicating that the first storage module 120 is not occupied, when receiving input data, the control circuit 130 will make the shift signal of the storage unit circuit 100 invalid, so that the input data only needs to be stored in the first storage module 120, and there is no need to perform a data shift operation. By using the storage unit occupancy information U-VALID stored in the second storage module 140, and combining the control circuit 130 to update the storage unit occupancy information U-VALID using the storage unit occupancy update information U-TMP, the storage unit circuit in the shift sorting circuit can be more fully utilized. For example, when the data in the individual storage unit circuit in the shift sorting circuit is cleared, the shift sorting circuit can mark the unoccupied storage unit circuit, so that when the shift sorting circuit subsequently receives input data, only the data of each storage unit circuit before (or upstream) the unoccupied storage unit circuit needs to be shifted. It should be noted that in some exemplary embodiments of the present disclosure, the first storage module 120 and / or the second storage module 140 may include a memory composed of a D flip-flop, or may include a register. It should be understood that any suitable memory with a cache can be used as the memory included in the first storage module 120 and / or the second storage module 140, and the present disclosure does not impose any restrictions on this.

[0040] It should be understood that in some embodiments of the present disclosure, the storage unit circuit may not include the second storage module. In this case, the control circuit can determine whether the shift signal is valid based only on the state of the data valid signal and the clear signal. Specifically, the control circuit can be configured to: invalidate the shift signal in response to at least one of the following situations, including: the data valid signal is invalid, and the clear signal is valid. In addition, the control circuit can also be configured to: validate the shift signal in response to the data valid signal being valid and the clear signal being invalid. In these embodiments, by removing the second storage module, the number of components of the storage unit circuit can be reduced, and the complexity of the circuit can also be reduced.

[0041] The memory cell circuit 100 according to the present disclosure can generate a shift signal based on a data valid signal, a clear signal and memory cell occupancy information, thereby realizing a shift sorting circuit with fewer resources, thereby realizing data sorting based on aging degree.

[0042] See also Figure 2 , which schematically shows Figure 1 Detail of the data strobe circuit 110 in the memory cell circuit 100 is shown. Figure 2 As shown, in this exemplary embodiment, the data strobe circuit 110 includes a controlled switch element 111, which includes an input terminal 111-1, an output terminal 111-2 and a control terminal 111-3. The input terminal 111-1 is electrically connected to the data input terminal Data-IN, the output terminal 111-2 is electrically connected to the input terminal of the first storage module 120, and the control terminal 111-3 is electrically connected to the data valid signal input terminal Data-EN. The controlled switch element 111 is configured to: in response to the valid data valid signal applied to the control terminal 111-3, the input terminal 111-1 and the output terminal 111-2 of the controlled switch element 111 are connected; and in response to the invalid data valid signal applied to the control terminal 111-3, the conduction between the input terminal 111-1 and the output terminal 111-3 of the controlled switch element 111 is disconnected. Thus, when the data valid signal applied to the data valid signal input terminal Data-EN is valid, the data input from the data input terminal Data-IN can be transmitted to the input terminal of the first storage module 120 and stored in the first storage module 120. It should be understood that the controlled switch element 111 can be any suitable controlled switch element, including but not limited to a transistor or a switch circuit composed of a transistor, etc., and the present disclosure does not impose any limitation on the type of the controlled switch element. Figure 2 The rest of the memory cell circuit 100 is shown in FIG. Figure 1 The corresponding parts of the memory cell circuit 100 are the same, and therefore, they are not described again here.

[0043] See also Figure 3 , which schematically shows Figure 1 Details of the control circuit 130 in the memory cell circuit 100 are shown. Figure 3 As shown, in this exemplary embodiment, the control circuit 130 includes a storage unit occupancy information update circuit 131 and a shift signal generation circuit 132. The storage unit occupancy information update circuit 131 is configured to: in response to the data valid signal being valid, or in response to the storage unit occupancy information U-VALID being valid and the clear signal being invalid, enable the generated storage unit occupancy update information U-TMP to be valid, and transmit the storage unit occupancy update information U-TMP to the input terminal of the second storage unit 140. The shift signal generation circuit 132 is configured to: in response to both the data valid signal and the storage unit occupancy information U-VALID being valid, and in response to the clear signal being invalid, enable the generated shift signal to be valid, and output the shift signal to the shift signal output terminal Shift-EN. Figure 3 The rest of the memory cell circuit 100 is shown in FIG. Figure 1 The corresponding parts of the memory cell circuit 100 are the same, and therefore, they are not described again here.

[0044] See also Figure 4 , which schematically shows according to an exemplary embodiment of the present disclosure Figure 3 Details of the memory cell occupancy information updating circuit 131 and the shift signal generating circuit 132 in the memory cell circuit 100 are shown. Figure 4As shown, in this exemplary embodiment, the storage unit occupancy information update circuit 131 includes: an inverting circuit 131a, an AND circuit 131b and an OR circuit 131c. The input end of the inverting circuit 131a is electrically connected to the clear signal input end Clear. The first input end 1 of the AND circuit 131b is electrically connected to the output end of the second storage module 140 to receive the storage unit occupancy information U-VALID, and the second input end 2 is electrically connected to the output end of the inverting circuit 131a. The first input end 1 of the OR circuit 131c is electrically connected to the data valid signal input end Data-EN, and the second input end 2 is electrically connected to the output end out of the AND circuit 131b. The output end out of the OR circuit 131c is electrically connected to the input end of the second storage module 140 to transmit the storage unit occupancy update information U-TMP to the second storage unit 140. The shift signal generation circuit 132 includes: an inverting circuit 132a and an AND circuit 132b. The input end of the inverting circuit 132a is electrically connected to the clear signal input end Clear. The first input end 1 of the AND gate circuit 132b is electrically connected to the data valid signal input end Data-EN, the second input end 2 is electrically connected to the output end of the second storage module 140 to receive the storage unit occupancy information U-VALID, the third input end 3 is electrically connected to the output end of the inverting circuit 132a, and the output end out of the AND gate circuit 132b is electrically connected to the shift signal output end Shift-EN.

[0045] See also Figure 5 , which schematically shows according to another exemplary embodiment of the present disclosure Figure 1 Details of the control circuit 130 in the memory cell circuit 100 are shown. Figure 5 As shown, in this exemplary embodiment, the control circuit 130 includes: an inversion gate circuit 133, a storage unit occupancy information update circuit 131' and a shift signal generation circuit 132'. The input end of the inversion gate circuit 133 is electrically connected to the clear signal input end Clear, and is configured to: invert the clear signal applied to the clear signal input end Clear to generate an inverted signal of the clear signal. The storage unit occupancy information update circuit 131' is configured to: in response to the data valid signal being valid, or in response to the storage unit occupancy information U-VALID being valid and the inverted signal being valid, make the generated storage unit occupancy update information U-TMP valid, and deliver the storage unit occupancy update information U-TMP to the input end of the second storage unit 140. The shift signal generation circuit 132' is configured to: in response to both the data valid signal and the storage unit occupancy information U-TMP being valid, and in response to the inverted signal being valid, generate a shift signal, and deliver the shift signal to the shift signal output end Shift-EN. As shown Figure 5As shown, the storage unit occupancy information update circuit 131' includes: an AND gate circuit 131'a and an OR gate circuit 131'b. The first input terminal 1 of the AND gate circuit 131'a is electrically connected to the output terminal of the second storage module 140 to receive the storage unit occupancy information U-VALID, and the second input terminal 2 thereof is electrically connected to the output terminal of the inverting circuit 133. The first input terminal 1 of the OR gate circuit 131'b is electrically connected to the data valid signal input terminal Data-EN, and the second input terminal 2 thereof is electrically connected to the output terminal out of the AND gate circuit 131'a. The output terminal out of the OR gate circuit 131'b is electrically connected to the input terminal of the second storage module 140, so as to transmit the storage unit occupancy update information U-TMP to the second storage unit 140. The shift signal generating circuit 132' comprises an AND gate circuit 132'a, whose first input terminal 1 is electrically connected to the data valid signal input terminal Data-EN, whose second input terminal 2 is electrically connected to the output terminal of the second storage module 140 to receive the storage unit occupancy information U-VALID, whose third input terminal 3 is electrically connected to the output terminal of the inverting circuit 133, and whose output terminal out of the AND gate circuit 132'a is electrically connected to the shift signal output terminal Shift-EN. Figure 3 and Figure 4 Compared with the control circuit 130 shown, Figure 5 The control circuit 130 shown can save one inverter circuit, thereby reducing the cost.

[0046] See also Figure 6 , which schematically shows the structure of a memory cell circuit according to another exemplary embodiment of the present disclosure in the form of a block diagram. Figure 6 As shown, the storage unit circuit 200 also includes: a data valid signal input terminal Data-EN, a data input terminal Data-IN, a shift signal output terminal Shift-EN, a data output terminal Data-OUT, a clear signal input terminal Clear, a data strobe circuit 210, a first storage module 220, a control circuit 230 and a second storage module 240. The first storage module 220, the control circuit 230 and the second storage module 240 are connected to the storage module 210. Figures 1 to 5 The first storage module 120, the control circuit 130 and the second storage module 140 shown in FIG. 1 are respectively the same, except that the data strobe circuit 210 is different from the first storage module 120, the control circuit 130 and the second storage module 140. Figures 1 to 5 The data strobe circuit 110 in is different. Figure 6In the exemplary embodiment shown, the data strobe circuit 210 is configured to: in response to the data valid signal being valid, select the input data input from the data input terminal Data-IN as the data to be stored and output; and in response to the data valid signal being invalid, output the storage data output from the data output terminal Data-OUT as the data to be stored. In this way, the memory cell circuit 200 can maintain the stability of the storage data output from the data output terminal Data-OUT when the data valid signal is invalid.

[0047] See also Figure 7 , which schematically shows according to an exemplary embodiment of the present disclosure Figure 6 Detail of the data strobe circuit 210 in the memory cell circuit 200 is shown. Figure 7 As shown, in this exemplary embodiment, the data strobe circuit 210 includes a selector 211, wherein the selector 211 includes a first input terminal 1, a second input terminal 2, a control terminal c, and an output terminal out, and the first input terminal 1 of the selector 211 is electrically connected to the data input terminal Data-IN, the second input terminal 2 is electrically connected to the data output terminal Data-OUT, the control terminal c is electrically connected to the data valid signal input terminal Data-EN, and the output terminal out is electrically connected to the input terminal of the first storage module 220. Therefore, the selector 211 is configured to: in response to the valid data valid signal applied to its control terminal c being valid, the first input terminal 1 and the output terminal out are connected; and in response to the invalid data valid signal applied to its control terminal c, the second input terminal 2 and the output terminal out are connected.

[0048] See also Figure 8 , which schematically shows the structure of a memory cell circuit according to another exemplary embodiment of the present disclosure. Figure 8As shown, in this exemplary embodiment, the storage unit circuit 300 includes: a data valid signal input terminal Data-EN, a data input terminal Data-IN, a shift signal output terminal Shift-EN, a data output terminal Data-OUT, a clear signal input terminal Clear, a data strobe circuit 310, a first storage module 320, a control circuit 330 and a second storage module 340. The first storage module 320 and the second storage module 340 include a memory composed of a D flip-flop. The data strobe circuit 310 includes a selector 311, wherein the selector 311 includes a selector first input terminal 1, a selector second input terminal 2, a selector control terminal c and a selector output terminal out, and the selector first input terminal 1 is electrically connected to the data input terminal Data-IN, the selector second input terminal 2 is electrically connected to the data output terminal Data-OUT, the selector control terminal c is electrically connected to the data valid signal input terminal Data-EN, and the selector output terminal out is electrically connected to the input terminal of the first storage module 320. Therefore, the selector 311 is configured to: in response to the valid data valid signal applied to the selector control terminal c being valid, the selector first input terminal 1 is connected to the selector output terminal out; and in response to the invalid data valid signal applied to the selector control terminal c, the selector second input terminal 2 is connected to the selector output terminal out. The control circuit 330 includes a storage unit occupancy information update circuit 331 and a shift signal generation circuit 332. The storage unit occupancy information update circuit 311 includes: a first inversion gate circuit 331a, a first AND gate circuit 331b and an OR gate circuit 331c. The input end of the first inversion gate circuit 331a is electrically connected to the clear signal input terminal Clear. The first input end 1 of the first AND gate circuit 331b is electrically connected to the output end of the second storage module 340 to receive the storage unit occupancy information U-VALID, and its second input end 2 is electrically connected to the output end of the first inversion gate circuit 331a. The first input terminal 1 of the OR gate circuit 331c is electrically connected to the data valid signal input terminal Data-EN, the second input terminal 2 is electrically connected to the output terminal out of the first AND gate circuit 331a, and the output terminal out of the OR gate circuit 331c is electrically connected to the input terminal of the second storage module. The shift signal generating circuit 332 includes: a second inversion gate circuit 332a and a second AND gate circuit 332b. The input terminal of the second inversion gate circuit 332a is electrically connected to the clear signal input terminal Clear. The first input terminal 1 of the second AND gate circuit 332b is electrically connected to the data valid signal input terminal Data-EN, the second input terminal 2 is electrically connected to the output terminal of the second storage module 340, the third input terminal 3 is electrically connected to the output terminal of the second inversion gate circuit 332a, and the output terminal out of the second AND gate circuit 332b is electrically connected to the shift signal output terminal Shift-EN.

[0049] See also Fig. 9 , which schematically shows Figures 6 to 8 The timing of some signals in the exemplary memory cell circuit shown in FIG. Fig. 9As shown, during the first beat of the clock, the data valid signal applied to the data valid signal input terminal Data-EN is invalid (or, at a low potential), there is no data input at the data input terminal Data-IN, and the clear signal applied to the clear signal input terminal Clear also remains invalid, while the storage unit occupancy information U-VALID received from the output terminal of the second storage module remains valid (or, at a high potential; this indicates that the storage unit circuit currently has data stored). At this time, the shift signal output by the shift signal output terminal Shift-EN is invalid, the data to be stored applied to the input terminal of the first storage module is the data Data currently stored in the storage unit circuit, and the data output at the data output terminal Data-OUT is also the data Data currently stored. In the second beat of the clock, the data valid signal applied to the data valid signal input terminal Data-EN becomes valid (or, becomes a high voltage), new data New Data is input at the data input terminal Data-IN, the clear signal applied to the clear signal input terminal Clear remains invalid, and the storage unit occupancy information U-VALID received from the output terminal of the second storage module remains valid. At this time, the shift signal output by the shift signal output terminal Shift-EN becomes valid, and the data to be stored applied to the input terminal of the first storage module becomes the input new data New Data, but the data output at the data output terminal Data-OUT is still the currently stored data Data. At the third beat of the clock, the data valid signal applied to the data valid signal input terminal Data-EN remains valid, the new data New Data is maintained at the data input terminal Data-IN, the clear signal applied to the clear signal input terminal Clear remains invalid, and the storage unit occupancy information U-VALID received from the output terminal of the second storage module remains valid. At this time, the shift signal output by the shift signal output terminal Shift-EN remains valid, the data to be stored applied to the input terminal of the first storage module remains the new data NewData, and the data output at the data output terminal Data-OUT now becomes the new data NewData. At the fourth beat of the clock, the data valid signal applied to the data valid signal input terminal Data-EN becomes invalid again, there is no data input at the data input terminal Data-IN, the clear signal applied to the clear signal input terminal Clear remains invalid, and the storage unit occupancy information U-VALID received from the output terminal of the second storage module remains valid. At this time, the shift signal output by the shift signal output terminal Shift-EN becomes invalid, the data to be stored applied to the input terminal of the first storage module remains as the new data NewData, and the data output at the data output terminal Data-OUT also remains as the new data NewData.

[0050] As can be seen, in the second clock cycle, the shift signal output from the shift signal output terminal Shift-EN becomes valid. However, the data output at the data output terminal Data-OUT is still the currently stored data Data. Thus, this memory cell circuit can write (or shift) the currently stored data Data into the next connected memory cell circuit. Then, in the third clock cycle, the new data New Data is written into the first memory module, overwriting the previously stored data Data. In this way, the memory cell circuit according to various exemplary embodiments of the present disclosure can implement a shift sorting circuit with fewer resources, in which sorting based on the degree of aging of the data can be achieved.

[0051] See Fig.10 , which schematically shows the structure of a shift sorting circuit according to an exemplary embodiment of the present disclosure. As Fig.10 shown, in this exemplary embodiment, the shift sorting circuit 400 includes N cascaded memory cell circuits SU[1], SU[2],..., SU[N-1], SU[N], where N is an integer greater than 1. Each of the memory cell circuits SU[1], SU[2],..., SU[N-1], SU[N] can be implemented as each of the exemplary memory cell circuits as Figures 1 to 8 shown. Thus, each memory cell circuit includes: a data valid signal input terminal Data-EN, a data input terminal Data-IN, a shift signal output terminal Shift-EN, a data output terminal Data-OUT, and a clear signal input terminal Clear. The shift signal output terminal Shift-EN of the m-th memory cell circuit among the N cascaded memory cell circuits SU[1], SU[2],..., SU[N-1], SU[N] is electrically connected to the data valid signal input terminal Data-EN of the (m + 1)-th memory cell circuit, and the data output terminal Data-OUT of the m-th memory cell circuit is electrically connected to the data input terminal Data-IN of the (m + 1)-th memory cell circuit, where m is an integer and 1 ≤ m < N. The data input terminal Data-IN of the memory cell circuit SU[1] is electrically connected to the corresponding data signal terminal D-IN, and its data valid signal input terminal Data-EN is electrically connected to the corresponding data valid signal terminal D-EN. In Fig.10In the shift sorting circuit 400 shown, the clear signal input terminal Clear of each storage unit circuit is respectively connected to the corresponding clear signal terminal CLEAR[1], CLEAR[2], ..., CLEAR[N-1], CLEAR[N]. When the data stored in the corresponding storage unit circuit has been scheduled for use and the data no longer needs to be saved, the clear signal applied by the corresponding clear signal terminal will become valid, making the shift signal and storage unit occupancy information in the storage unit circuit invalid. Therefore, when new data is stored in the storage unit circuit next time, the previously stored data will not be shifted to the next level storage unit circuit, but will be overwritten by the new data. In addition, in other exemplary embodiments of the present disclosure, because there is no need to clear the storage unit circuit, the clear signal input terminal Clear of each storage unit circuit can be kept at a low potential, for example, electrically connected to the ground.

[0052] It can be seen from this that Fig.10 The shift sorting circuit 400 shown can implement data sorting based on aging degree. In addition, not all data need to be shifted each time, only the data that must be shifted need to be moved, so data sorting based on aging degree can be implemented with better power consumption.

[0053] Specifically, when the shift sorting circuit 400 starts to work, the storage unit circuits SU[1], SU[2], ..., SU[N-1], and SU[N] do not store data; when the first new data is stored, it will be stored in the storage unit circuit SU[1]; when the second new data is stored, the first new data is moved to the storage unit circuit SU[2], and the second new data is stored in the storage unit circuit SU[1]; the same can be said for the remaining newly stored data. Since the time when each stored data is scheduled for use is different, the time when each storage unit circuit is cleared is also different. Once a storage unit circuit is cleared, it means that the storage unit circuit becomes an idle storage unit circuit. Therefore, for the entire shift sorting circuit 400, when there are idle storage unit circuits in the storage unit circuits SU[1], SU[2], ..., SU[N-1], SU[N], if new data needs to be stored, then only the data in the storage unit circuits whose sorting numbers are smaller than the sorting numbers of the idle storage unit circuits need to be shifted, and the data in the remaining storage unit circuits do not need to be shifted. For example, if the storage unit circuit SU[i] is an idle storage unit circuit, then only the data in the storage unit circuits SU[1] to SU[i-1] need to be shifted accordingly, and the storage unit circuit SU[i] stores the data from the storage unit circuit SU[i-1], but the data is no longer shifted to the storage unit circuit SU[i+1]. Of course, if the storage unit circuit SU[i] is performing a clear operation (i.e., the clear signal at its clear signal input terminal Clear is valid) when the data of the storage unit circuit SU[i-1] is stored in the storage unit circuit SU[i], then the data from the storage unit circuit SU[i-1] is stored in the storage unit circuit SU[i], but the data is no longer shifted to the storage unit circuit SU[i+1]. It can be seen that in the shift sorting circuit 400, the aging degree of the data stored in the storage unit circuit with a larger sorting sequence number is greater. Therefore, when processing data, the data stored in the storage unit circuit with a larger sorting sequence number can be preferentially scheduled.

[0054] The shift sorting circuit 400 is particularly advantageous for application scenarios involving ray tracing (i.e., ray tracing). In the application of ray tracing, it is hoped that the old ray data can be traversed as quickly as possible so that the cache space can be released after the traversal is completed, so that the cache space can be allocated to the new ray data. In the existing related art, a specific storage location is allocated for each new ray data, and during the entire traversal process, the aging degree of each ray data and the corresponding storage location need to be recorded, resulting in the situation where a large number of ray data (for example, more than 64) need to be sorted and managed based on the aging degree, and the conventional technical solution cannot be implemented or the resource cost is too high. According to the above analysis of the present disclosure, the shift sorting circuit 400 does not need to move all the ray data each time it shifts, but only needs to move the ray data that must be shifted, and the sorting sequence number of each storage unit circuit itself reflects the aging degree of the ray data (for example, the aging degree of the data stored in the storage unit circuit with a larger sorting sequence number is greater), so it is possible to achieve sorting management of the ray data based on the aging degree at a lower resource cost.

[0055] See also Fig.11 , which schematically shows the structure of an electronic device according to an exemplary embodiment of the present disclosure in the form of a block diagram. Fig.11 As shown, the electronic device 500 includes a shift sorting circuit 510, wherein the shift sorting circuit 510 can be implemented as follows Fig.10 The shift sorting circuit 400 is shown. It should be understood that the electronic device 500 can be implemented as any suitable electronic device, including but not limited to a motherboard, a graphics card, an image processing device, a GPU chip, a CPU chip, etc. The present disclosure does not impose any limitation on the specific type of the electronic device 500.

[0056] The terms used in this disclosure are only used to describe the embodiments in the present disclosure and are not intended to limit the present disclosure. As used herein, the singular forms "one", "an" and "the" are intended to also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include" and "comprise" when used in the present disclosure refer to the existence of the features described, but do not exclude the existence of one, one or more other features or add one or more other features. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. It will be understood that although the terms "first", "second", "third", etc. can be used to describe various features in this article, these features should not be limited by these terms. These terms are only used to distinguish one feature from another feature.

[0057] Unless otherwise defined, all terms (including technical and scientific terms) used in the present disclosure have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It is also understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the relevant art and / or the context of this specification, and will not be interpreted in an idealized or overly formal sense unless explicitly defined in the present disclosure.

[0058] In the description of this specification, the description of the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradicting each other and without violating technical principles, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, or may omit some technical features from the different embodiments or examples described in this specification, and the embodiments or examples obtained based on such combination, combination or omission are also considered to fall within the scope of the present disclosure.

[0059] Although the present disclosure has been described in detail in conjunction with some exemplary embodiments, it is not intended to be limited to the specific forms set forth herein. Rather, the scope of the present disclosure is limited only by the appended claims.

Claims

1. A memory cell circuit, characterized in that: include: A data input terminal configured to: receive input data; A data output terminal, which is configured to: output storage data; A data valid signal input terminal, configured to: receive a data valid signal, wherein when the data valid signal is valid, it indicates that the input data can be stored in the storage unit circuit; A shift signal output terminal, which is configured to: output a shift signal, wherein when the shift signal is valid, it indicates that the stored data can be output to the next level storage unit circuit through the data output terminal; a clear signal input terminal, configured to receive a clear signal, wherein the clear signal indicates that the stored data is invalid when it is valid; a first storage module, configured to store input data, or update the stored data stored in the first storage module with the input data when the data valid signal is valid, or output the stored data to the next level storage unit circuit through the data output terminal when the shift signal is valid; The control circuit is configured to: in response to at least one of the following situations, invalidate the shift signal, including: the data valid signal is invalid, and the clear signal is valid.

2. The memory cell circuit according to claim 1, wherein: The control circuit is further configured to assert the shift signal in response to the data valid signal being asserted and the clear signal being deasserted.

3. The memory cell circuit according to claim 1, wherein: The memory cell circuit further includes a data strobe circuit configured to: in response to the data valid signal being valid, output the input data as data to be stored to the first memory module.

4. The memory cell circuit according to claim 3, characterized in that: The data gating circuit comprises a controlled switch element, wherein the controlled switch element comprises an input terminal, an output terminal and a control terminal, wherein the input terminal is electrically connected to the data input terminal, the control terminal is electrically connected to the data valid signal input terminal, and the output terminal is electrically connected to the input terminal of the first storage module; Wherein, the controlled switch element is configured as follows: In response to the data valid signal applied to the control terminal being valid, the input terminal and the output terminal of the controlled switch element are turned on; In response to the data valid signal applied to the control terminal being invalid, disconnecting the conduction between the input terminal and the output terminal of the controlled switch element.

5. The memory cell circuit according to claim 1, wherein: The memory cell circuit further includes a data strobe circuit configured to: In response to the data valid signal being valid, outputting the input data as data to be stored to the first storage module; In response to the data valid signal being invalid, the storage data outputted from the data output terminal is transmitted to the first storage module as the data to be stored.

6. The memory cell circuit according to claim 5, characterized in that: The data strobe circuit includes a selector, the selector includes a first input terminal, a second input terminal, a control terminal and an output terminal, wherein the first input terminal is electrically connected to the data input terminal, the second input terminal is electrically connected to the data output terminal, the control terminal is electrically connected to the data valid signal input terminal, and the output terminal is electrically connected to the input terminal of the first storage module; Wherein, the selector is configured as: In response to the data valid signal applied to the control terminal being valid, the first input terminal and the output terminal are connected; In response to the data valid signal applied to the control terminal being invalid, the second input terminal and the output terminal are connected.

7. The memory cell circuit according to claim 1, wherein: The storage unit circuit also includes a second storage module, which is configured to: receive storage unit occupancy update information, update the storage unit occupancy information stored in the second storage module with the storage unit occupancy update information, and output the storage unit occupancy information to the control circuit, wherein the storage unit occupancy information indicates that the first storage module has been occupied when it is valid.

8. The memory cell circuit according to claim 7, characterized in that: The control circuit is further configured to: in response to the storage unit occupancy information being invalid, invalidate the shift signal.

9. The memory cell circuit according to claim 7, characterized in that: The control circuit is further configured to: In response to at least one of the following situations, the storage unit occupancy update information is enabled, including: the data valid signal is enabled, the storage unit occupancy information is enabled, and the clear signal is disabled; In response to the data valid signal being invalid and the memory cell occupancy information being invalid or the clear signal being valid, the memory cell occupancy update information is invalidated.

10. The memory cell circuit according to claim 7, characterized in that: The first storage module and / or the second storage module includes a memory formed by a D flip-flop.

11. The memory cell circuit according to claim 7, characterized in that: The first storage module and / or the second storage module includes a register.

12. The memory cell circuit according to claim 7, wherein: The control circuit further includes a shift signal generating circuit, wherein the shift signal generating circuit includes: an inverter circuit, whose input terminal is electrically connected to the clear signal input terminal; An AND gate circuit, whose first input terminal is electrically connected to the data valid signal input terminal, whose second input terminal is electrically connected to the output terminal of the second storage module, whose third input terminal is electrically connected to the output terminal of the inversion gate circuit, and whose output terminal is electrically connected to the shift signal output terminal.

13. The memory cell circuit according to claim 7, wherein: The control circuit includes a storage unit occupancy information updating circuit, wherein the storage unit occupancy information updating circuit includes: an inverter circuit, whose input terminal is electrically connected to the clear signal input terminal; an AND gate circuit, a first input end of which is electrically connected to the output end of the second storage module, and a second input end of which is electrically connected to the output end of the inverter circuit; An OR gate circuit has a first input terminal electrically connected to the data valid signal input terminal, a second input terminal electrically connected to the output terminal of the AND gate circuit, and an output terminal electrically connected to the input terminal of the second storage module.

14. The memory cell circuit according to claim 7, wherein: The control circuit comprises: an inversion gate circuit, whose input terminal is electrically connected to the clear signal input terminal to generate an inversion signal of the clear signal; an AND gate circuit, wherein a first input terminal thereof is electrically connected to the data valid signal input terminal, a second input terminal thereof is electrically connected to the output terminal of the second storage module, a third input terminal thereof is electrically connected to the output terminal of the inverter circuit, and an output terminal thereof is electrically connected to the shift signal output terminal; A first AND gate circuit, wherein a first input terminal is electrically connected to the data valid signal input terminal, a second input terminal is electrically connected to the output terminal of the second storage module, a third input terminal is electrically connected to the output terminal of the inverter circuit, and an output terminal is electrically connected to the shift signal output terminal; A second AND gate circuit, a first input end of which is electrically connected to the output end of the second storage module, and a second input end of which is electrically connected to the output end of the inverter circuit; An OR gate circuit has a first input terminal electrically connected to the data valid signal input terminal, a second input terminal electrically connected to the output terminal of the AND gate circuit, and an output terminal electrically connected to the input terminal of the second storage module.

15. The memory cell circuit according to claim 7, characterized in that: The device further comprises a data strobe circuit, the data strobe circuit comprising a selector, the selector comprising a first selector input terminal, a second selector input terminal, a selector control terminal and a selector output terminal, wherein the first selector input terminal is electrically connected to the data input terminal, the second selector input terminal is electrically connected to the data output terminal, the selector control terminal is electrically connected to the data valid signal input terminal, the selector output terminal is electrically connected to the input terminal of the first storage module, and wherein the selector is configured to: in response to the data valid signal applied to the selector control terminal being valid, the first selector input terminal is connected to the selector output terminal, and in response to the data valid signal applied to the selector control terminal being invalid, the second selector input terminal is connected to the selector output terminal; The control circuit comprises: A first inverter circuit, whose input terminal is electrically connected to the clear signal input terminal; A second inverter circuit, whose input terminal is electrically connected to the clear signal input terminal; A first AND gate circuit, wherein a first input terminal is electrically connected to the data valid signal input terminal, a second input terminal is electrically connected to the output terminal of the second storage module, a third input terminal is electrically connected to the output terminal of the second inverter circuit, and an output terminal is electrically connected to the shift signal output terminal; A second AND gate circuit, a first input end of which is electrically connected to the output end of the second storage module, and a second input end of which is electrically connected to the output end of the first inverter circuit; An OR gate circuit has a first input terminal electrically connected to the data valid signal input terminal, a second input terminal electrically connected to the output terminal of the first AND gate circuit, and an output terminal electrically connected to the input terminal of the second storage module.

16. A shift sorting circuit, characterized in that: A memory cell circuit according to any one of claims 1 to 15 comprising N cascaded memory cell circuits, wherein N is an integer greater than 1, characterized in that the shift signal output terminal of the mth memory cell circuit in the N cascaded memory cell circuits is electrically connected to the data valid signal input terminal of the m+1th memory cell circuit, the data output terminal of the mth memory cell circuit is electrically connected to the data input terminal of the m+1th memory cell circuit, m is an integer, and 1≤m <N。 17. An electronic device, characterized in that: Comprising the shift sequencing circuit according to claim 16.

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