Epitaxial wafer and its preparation method

Abstract

The present application discloses an epitaxial wafer and a preparation method thereof, belonging to the technical field of semiconductor manufacturing. An epitaxial wafer includes: a substrate; a silicon carbide lattice matching layer located on one side of the substrate; a nucleation layer located on the side of the lattice matching layer away from the substrate; wherein, the substrate has a first in-plane lattice constant d1, the silicon carbide lattice matching layer has a second in-plane lattice constant d2, and the nucleation layer has a third in-plane lattice constant d3, satisfying: |d3 - d2| < |d3 - d1|. By arranging a silicon carbide lattice matching layer between the substrate and the nucleation layer and controlling the first in-plane lattice constant d1, the second in-plane lattice constant d2, and the third in-plane lattice constant d3 to satisfy: |d3 - d2| < |d3 - d1|, the present application can improve the lattice mismatch between the nucleation layer and the substrate, thereby reducing the defect density of the nucleation layer and improving the crystal quality of the epitaxial wafer.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and particularly to an epitaxial wafer and a method for preparing the same. Background Art

[0002] The main raw material of gallium nitride power devices is silicon-based gallium nitride (GaN) epitaxial wafers, that is, GaN epitaxial films are grown on silicon (Si) substrates, and the main preparation method is metalorganic chemical vapor deposition. Structurally, the gallium nitride epitaxial film includes a nucleation layer, a buffer layer, a graded buffer layer or a superlattice buffer layer, a channel layer, an insertion layer, a barrier layer, and a surface layer. Among them, the nucleation layer plays a crucial role in the crystal quality of the entire epitaxial wafer and is the basis for the multi-layer structure of the entire epitaxial wafer. The huge lattice mismatch between the nucleation layer and the silicon substrate makes the nucleation layer exhibit a polycrystalline structure with a high defect density, resulting in a relatively high defect density in the crystals of other epitaxial layers. Summary of the Invention

[0003] The purpose of this application is to provide an epitaxial wafer and a method for preparing the same, which can reduce the lattice mismatch between the nucleation layer and the substrate, thereby reducing the defect density of the nucleation layer and improving the crystal quality of the epitaxial wafer.

[0004] The first aspect of this application provides an epitaxial wafer, including:

[0005] A substrate;

[0006] A silicon carbide lattice adaptation layer located on one side of the substrate;

[0007] A nucleation layer located on the side of the silicon carbide lattice adaptation layer away from the substrate;

[0008] Wherein, the substrate has a first in-plane lattice constant d 1 , the silicon carbide lattice adaptation layer has a second in-plane lattice constant d 2 , the nucleation layer has a third in-plane lattice constant d 3 , satisfying: |d 3 - d 2 | < |d 3 - d 1 |.

[0009] In some embodiments, the thickness of the silicon carbide lattice adaptation layer is 2 - 10 nm.

[0010] In some embodiments, the nucleation layer includes a first nucleation layer and a second nucleation layer, the first nucleation layer is located between the silicon carbide lattice adaptation layer and the second nucleation layer, and the formation temperature of the second nucleation layer is greater than that of the first nucleation layer.

[0011] In some embodiments, the epitaxial wafer further includes a first buffer layer, a second buffer layer, a channel layer, an insertion layer, a barrier layer, and a surface layer that are stacked on a side of the nucleation layer away from the silicon carbide lattice adaptation layer.

[0012] The second aspect of the present application provides a method for preparing an epitaxial wafer, including:

[0013] Placing a substrate in a reaction chamber;

[0014] Forming a silicon carbide lattice adaptation layer on one side of the substrate;

[0015] Forming a nucleation layer on a side of the silicon carbide lattice adaptation layer away from the substrate;

[0016] Wherein, the substrate has a first in-plane lattice constant d 1 , the silicon carbide lattice adaptation layer has a second in-plane lattice constant d 2 , the nucleation layer has a third in-plane lattice constant d 3 , satisfying: |d 3 -d 2 |<|d 3 -d 1 |.

[0017] In some embodiments, the step of forming a silicon carbide lattice adaptation layer on one side of the substrate includes:

[0018] Introducing a first silicon source into the reaction chamber;

[0019] Closing the first silicon source and introducing a carbon source into the reaction chamber;

[0020] Closing the carbon source and continuing to introduce a second silicon source into the reaction chamber, and alternately introducing the carbon source and the second silicon source to form a silicon carbide lattice adaptation layer on one side of the substrate.

[0021] In some embodiments, the nucleation layer includes a first nucleation layer and a second nucleation layer, the first nucleation layer is located between the silicon carbide lattice adaptation layer and the second nucleation layer, and the formation temperature of the second nucleation layer is higher than that of the first nucleation layer.

[0022] In some embodiments, the formation temperature of the first nucleation layer is 900 - 1000 °C.

[0023] In some embodiments, the formation temperature of the second nucleation layer is 1050 - 1150 °C.

[0024] In some embodiments, the time for introducing the first silicon source is t 1 , the time for introducing the carbon source is t 2, the time for introducing the second silicon source is t 3 , satisfying: t 3 ≤t 2 ≤t 1 .

[0025] In some embodiments, the total amount of the carbon source introduced is q 1 , the total amount of the second silicon source introduced is q 2 , satisfying: q 2 <q 1

[0026] In some embodiments, the time for introducing the first silicon source is t 1 , satisfying: 4 min ≤ t 1 ≤ 5 min, and the flow rate of the first silicon source introduced is Q 1 , satisfying: 5 sccm ≤ Q 1 ≤ 10 sccm.

[0027] In some embodiments, the time for introducing the carbon source is t 2 , satisfying: 1 min ≤ t 2 ≤ 2 min, and the flow rate of the carbon source introduced is Q 2 , satisfying: 5 sccm ≤ Q 2 ≤ 20 sccm.

[0028] In some embodiments, the time for introducing the second silicon source is t 3 , satisfying: 1 min ≤ t 3 ≤ 2 min, and the flow rate of the second silicon source introduced is Q 3 , satisfying: 5 sccm ≤ Q 3 ≤ 10 sccm.

[0029] In some embodiments, the first silicon source is selected from at least one of silane, dichlorosilane, trichlorosilane, and silicon tetrachloride.

[0030] In some embodiments, the carbon source is selected from at least one of ethylene, methane, and ethane.

[0031] In some embodiments, the second silicon source is selected from at least one of silane, dichlorosilane, trichlorosilane, and silicon tetrachloride.

[0032] In some embodiments, the number of times the carbon source and the second silicon source are introduced separately is M, satisfying: 8 times ≤ M ≤ 40 times.

[0033] In some embodiments, the thickness of the silicon carbide lattice matching layer is 2 - 10 nm.

[0034] In some embodiments, after forming a nucleation layer on a side of the silicon carbide layer lattice adaptation layer away from the substrate, the following steps are further included:

[0035] Forming a first buffer layer on a side of the nucleation layer away from the silicon carbide lattice adaptation layer;

[0036] Forming a second buffer layer on a side of the first buffer layer away from the nucleation layer;

[0037] Forming a channel layer on a side of the second buffer layer away from the first buffer layer;

[0038] Forming an insertion layer on a side of the channel layer away from the second buffer layer;

[0039] Forming a barrier layer on a side of the insertion layer away from the channel layer;

[0040] Forming a surface layer on a side of the barrier layer away from the insertion layer.

[0041] In some embodiments, the first buffer layer includes K stacked AlGaN layers, where 3 ≤ K ≤ 5.

[0042] In some embodiments, the material of the first buffer layer is selected from AlGaN; the chemical formula of AlGaN is Al x Ga 1- x N, where 0.05 ≤ x ≤ 0.95, and along the direction away from the nucleation layer, the molar content of aluminum in the first buffer layer gradually decreases.

[0043] In some embodiments, the material of the barrier layer is selected from AlGaN; the chemical formula of AlGaN is Al y Ga 1-y N, where 0.75 ≤ y ≤ 0.85.

[0044] In some embodiments, the thickness of the nucleation layer is 200 - 300 nm.

[0045] In some embodiments, the thickness of the first buffer layer is 1500 - 2000 nm.

[0046] In some embodiments, the thickness of the second buffer layer is 1800 - 2000 nm.

[0047] In some embodiments, the thickness of the channel layer is 150 - 300 nm.

[0048] In some embodiments, the thickness of the insertion layer is 0.5 - 2 nm.

[0049] In some embodiments, the thickness of the barrier layer is 15 - 25 nm.

[0050] In some embodiments, the thickness of the surface layer is 0.5 - 2 nm.

[0051] In some embodiments, the material of the substrate is selected from any one of silicon and sapphire.

[0052] In some embodiments, the material of the nucleation layer is selected from AlN.

[0053] In some embodiments, the material of the first buffer layer is selected from AlGaN.

[0054] In some embodiments, the material of the second buffer layer is selected from GaN.

[0055] In some embodiments, the material of the channel layer is selected from GaN.

[0056] In some embodiments, the material of the insertion layer is selected from any one of AlN, AlGaN or SiN x among them.

[0057] In some embodiments, the material of the barrier layer is selected from AlGaN.

[0058] In some embodiments, the material of the surface layer is selected from any one of GaN, P - GaN or SiN x among them.

[0059] In some embodiments, after placing the substrate in the reaction chamber, it further includes:

[0060] Introducing an etching gas into the reaction chamber to etch the substrate.

[0061] In some embodiments, the etching gas is selected from hydrogen or hydrogen chloride.

[0062] In some embodiments, the etching time is 5 - 15 min; the etching temperature is 1000 - 1100 °C; the flow rate of the etching gas is 150 - 200 slm.

[0063] The beneficial effect of this application lies in:

[0064] This application sets a silicon carbide lattice matching layer between the substrate and the nucleation layer, and controls the first in - plane lattice constant d 1 , the second in - plane lattice constant d 2 and the third in - plane lattice constant d 3 , satisfying: |d 3 - d 2 | < |d 3 - d1 | can reduce the lattice mismatch between the nucleation layer and the substrate, thereby reducing the defect density of the nucleation layer and improving the crystal quality of the epitaxial wafer. Description of the Drawings

[0065] Figure 1 FIG. is a schematic structural diagram of an epitaxial wafer provided by the present application;

[0066] Figure 2 FIG. is another schematic structural diagram of an epitaxial wafer provided by the present application;

[0067] Figure 3 FIG. is the crystal plane diffraction curve of GaN(002) of the epitaxial wafers prepared in Example 1 and Comparative Examples 1-3 of the present application;

[0068] Figure 4 FIG. is the crystal plane diffraction curve of GaN(102) of the epitaxial wafers prepared in Example 1 and Comparative Examples 1-3 of the present application;

[0069] Figure 5 FIG. is the atomic force microscope image of the nucleation layer prepared in Example 1 of the present application;

[0070] Figure 6 FIG. is the atomic force microscope image of the nucleation layer prepared in Comparative Example 4 of the present application;

[0071] Figure 7 FIG. is the atomic force microscope image of the nucleation layer prepared in Comparative Example 5 of the present application;

[0072] Figure 8 FIG. is the atomic force microscope image of the nucleation layer prepared in Comparative Example 6 of the present application.

[0073] In the drawings, the components represented by the reference numerals are as follows:

[0074] 1. Substrate; 2. Silicon carbide lattice adaptation layer; 3. Nucleation layer; 301. First nucleation layer; 302. Second nucleation layer; 4. First buffer layer; 5. Second buffer layer; 6. Channel layer; 7. Insertion layer; 8. Barrier layer; 9. Surface layer. Detailed Embodiments

[0075] The technical solution of the present application will be clearly and completely described below in conjunction with the embodiments and the accompanying drawings of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present application. The various embodiments of the present application may exist in the form of a range; it should be understood that the description in the form of a range is only for convenience and brevity, and should not be construed as a rigid limitation on the scope of the present application; therefore, it should be considered that the described range description has specifically disclosed all possible sub-ranges and single values within that range. For example, it should be considered that the range description from 1 to 6 has specifically disclosed sub-ranges such as from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6, etc., as well as single numbers within the range, such as 1, 2, 3, 4, 5, and 6, regardless of the range. Additionally, whenever a numerical range is indicated herein, it means including any cited number (fraction or integer) within the indicated range.

[0076] As Figure 1 and Figure 2 shown, a first aspect of the present application provides an epitaxial wafer, including:

[0077] Substrate 1;

[0078] A silicon carbide lattice matching layer 2, located on one side of the substrate 1;

[0079] A nucleation layer 3, located on the side of the silicon carbide lattice matching layer 2 away from the substrate 1;

[0080] Wherein, the substrate 1 has a first in-plane lattice constant d 1 , the silicon carbide lattice matching layer 2 has a second in-plane lattice constant d 2 , and the nucleation layer 3 has a third in-plane lattice constant d 3 , satisfying: |d 3 - d 2 | < |d 3 - d 1 |.

[0081] It can be understood that, by providing the silicon carbide lattice matching layer 2 between the substrate 1 and the nucleation layer 3 and controlling the first in-plane lattice constant d 1 , the second in-plane lattice constant d 2 , and the third in-plane lattice constant d 3 , satisfying: |d 3 - d 2 | < |d 3 - d 1 |, the lattice mismatch between the nucleation layer 3 and the substrate 1 can be reduced, thereby reducing the defect density of the nucleation layer 3 and improving the crystal quality of the epitaxial wafer.

[0082] In some embodiments, the lattice constant d in the first plane 1 is

[0083] In some embodiments, the lattice constant d in the second plane 2 is

[0084] In some embodiments, the lattice constant d in the third plane 3 is

[0085] The lattice constant refers to the edge length of the unit cell, that is, the edge length of each parallelepiped unit, and it is an important basic parameter of the crystal structure. In this application, X-ray Diffraction is used to measure the lattice constant. By measuring the angle and intensity of X-ray diffraction, the lattice constant and the crystal structure information can be obtained.

[0086] In some embodiments, the thickness of the silicon carbide lattice matching layer 2 is 2 - 10 nm. Specifically, the thickness of the silicon carbide lattice matching layer 2 can be any value among 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm or a range composed of any two values.

[0087] It can be understood that too high a thickness of the silicon carbide lattice matching layer 2 will affect the crystal quality of the nucleation layer 3, that is, the defect density of the crystal in the nucleation layer 3 will be too large. Too low a thickness of the silicon carbide lattice matching layer 2 will affect the coverage rate of the silicon carbide lattice matching layer 2 on the substrate 1, resulting in the silicon carbide lattice matching layer 2 being unable to completely cover the substrate 1. By controlling the thickness of the silicon carbide lattice matching layer 2 to be 2 - 10 nm in this application, the lattice mismatch between the nucleation layer 3 and the substrate 1 can be reduced, thereby reducing the defect density of the nucleation layer 3 and improving the crystal quality of the epitaxial wafer.

[0088] As Figure 2 shown, in some embodiments, the nucleation layer 3 includes a first nucleation layer 301 and a second nucleation layer 302. The first nucleation layer 301 is located between the silicon carbide lattice matching layer 2 and the second nucleation layer 302, and the formation temperature of the second nucleation layer is higher than that of the first nucleation layer.

[0089] It can be understood that the first nucleation layer 301 is a low-temperature nucleation layer, and the second nucleation layer 302 is a high-temperature nucleation layer. In this application, by providing a silicon carbide lattice matching layer 2 between the substrate 1 and the nucleation layer 3, and controlling the lattice constant d in the first plane 1 and the lattice constant d in the second plane 2 as well as the lattice constant d in the third plane 3 , to satisfy: |d 3 - d2 |<|d 3 -d 1 | can reduce the lattice mismatch between the low-temperature nucleation layer and the substrate 1, thereby reducing the defect density of the low-temperature nucleation layer and improving the crystal quality of the epitaxial wafer.

[0090] In some embodiments, the epitaxial wafer further includes a first buffer layer 4, a second buffer layer 5, a channel layer 6, an insertion layer 7, a barrier layer 8, and a surface layer 9 that are stacked on a side of the nucleation layer 3 away from the silicon carbide lattice adaptation layer 2.

[0091] It can be understood that the silicon carbide lattice adaptation layer 2, the nucleation layer 3, the first buffer layer 4, the second buffer layer 5, the channel layer 6, the insertion layer 7, the barrier layer 8, and the surface layer 9 constitute the epitaxial layer of the epitaxial wafer, that is, the epitaxial structure.

[0092] The second aspect of the present application provides a method for manufacturing an epitaxial wafer, including:

[0093] Placing the substrate 1 in a reaction chamber;

[0094] Forming a silicon carbide (SiC) lattice adaptation layer 2 on one side of the substrate 1;

[0095] Forming a nucleation layer 3 on a side of the silicon carbide lattice adaptation layer 2 away from the substrate 1;

[0096] Wherein, the substrate 1 has a first in-plane lattice constant d 1 , the silicon carbide lattice adaptation layer 2 has a second in-plane lattice constant d 2 , the nucleation layer 3 has a third in-plane lattice constant d 3 , satisfying: |d 3 -d 2 |<|d 3 -d 1 |.

[0097] It can be understood that in the present application, by forming a silicon carbide lattice adaptation layer 2 between the substrate 1 and the nucleation layer 3 and controlling the first in-plane lattice constant d 1 , the second in-plane lattice constant d 2 , and the third in-plane lattice constant d 3 , satisfying: |d 3 -d 2 |<|d 3 -d 1 |, the lattice mismatch between the nucleation layer 3 and the substrate 1 can be reduced, thereby reducing the defect density of the nucleation layer 3 and improving the crystal quality of the epitaxial wafer.

[0098] In some embodiments, the step of forming a silicon carbide lattice adaptation layer 2 on one side of the substrate 1 includes:

[0099] Introduce a first silicon source into the reaction chamber;

[0100] Close the first silicon source and introduce a carbon source into the reaction chamber;

[0101] Close the carbon source and continue to introduce a second silicon source into the reaction chamber. By alternately introducing the carbon source and the second silicon source, a silicon carbide lattice adaptation layer 2 is formed on one side of the substrate 1.

[0102] It can be understood that when the substrate 1 is a silicon substrate, by introducing the first silicon source, silicon (Si) layer growth is carried out on the surface of the silicon (Si) substrate. On the one hand, it can repair the defects on the surface of the Si substrate, make the Si substrate smoother, and ensure the two-dimensional growth of the SiC lattice adaptation layer 2. On the other hand, Si atoms with dangling bonds are formed on the surface of the Si substrate; then, by introducing the carbon source, carbon (C) is pre-laid on it, and the cracked C combines with the Si with dangling bonds to generate an extremely thin SiC lattice adaptation layer 2; then, Si pre-laying and C pre-laying are alternately carried out multiple times to obtain the SiC lattice adaptation layer 2 with a near two-dimensional surface; and then, based on this, a nucleation layer 3 is grown, which can reduce the lattice mismatch between the nucleation layer 3 and the silicon substrate 1, thereby reducing the defect density of the nucleation layer 3 and improving the crystal quality of the epitaxial wafer.

[0103] In some embodiments, the nucleation layer 3 includes a first nucleation layer 301 and a second nucleation layer 302. The first nucleation layer 301 is located between the silicon carbide lattice adaptation layer 2 and the second nucleation layer 302, and the formation temperature of the second nucleation layer is higher than that of the first nucleation layer.

[0104] In some embodiments, the formation temperature of the first nucleation layer 301 is 900 - 1000 °C. Specifically, the formation temperature of the first nucleation layer 301 can be any value among 900 °C, 910 °C, 920 °C, 930 °C, 940 °C, 950 °C, 960 °C, 970 °C, 980 °C, 990 °C, 1000 °C or any range composed of any two values.

[0105] In some embodiments, the formation temperature of the second nucleation layer 302 is 1050 - 1150 °C. Specifically, the formation temperature of the second nucleation layer 302 can be any value among 1050 °C, 1060 °C, 1070 °C, 1080 °C, 1090 °C, 1100 °C, 1110 °C, 1120 °C, 1130 °C, 1140 °C, 1150 °C or any range composed of any two values.

[0106] In some embodiments, the total amount of the carbon source introduced is q 1 , and the total amount of the second silicon source introduced is q 2 , satisfying: q 2 < q 1 . Specifically, the flow rate Q 2 of the carbon source introduced and the time t2 The product of is the total amount of carbon source introduced, with the unit of milliliter (mL), and the flow rate Q of the second silicon source introduced 3 and the time t for introducing the second silicon source 3 The product of is the total amount of the second silicon source introduced, with the unit of milliliter (mL).

[0107] It can be understood that by controlling the total amount of carbon source introduced to be q 1 , and the total amount of the second silicon source introduced to be q 2 , satisfying: q 2 < q 1 , on the one hand, it can repair the defects on the surface of the Si substrate, make the Si substrate smoother, and ensure the two-dimensional growth of the SiC lattice adaptation layer 2. On the other hand, Si atoms with dangling bonds are formed on the surface of the Si substrate; then pre-carbonize (C) it by introducing a carbon source. On the one hand, the cracked C combines with the Si with dangling bonds to generate an extremely thin SiC lattice adaptation layer 2; then pre-Si and pre-C are alternately carried out multiple times to obtain the SiC lattice adaptation layer 2 with a near two-dimensional surface. On the other hand, the total amount of the carbon source is higher than that of the silicon source, which can avoid the formation of silicon droplets and prevent the silicon droplets from damaging the crystal structure of the SiC lattice adaptation layer 2.

[0108] In some embodiments, the time for introducing the first silicon source is t 1 , the time for introducing the carbon source is t 2 , and the time for introducing the second silicon source is t 3 , satisfying: t 3 ≤ t 2 ≤ t 1 .

[0109] It can be understood that by controlling the time t for introducing the first silicon source 1 , the time t for introducing the carbon source 2 , and the time t for introducing the second silicon source 3 , satisfying: t 3 ≤ t 2 ≤ t 1 ; the thickness of the formed silicon layer can be controlled. On the one hand, it can repair the defects on the surface of the Si substrate, make the Si substrate smoother, and ensure the two-dimensional growth of the SiC lattice adaptation layer 2. On the other hand, Si atoms with dangling bonds are formed on the surface of the Si substrate; pre-carbonize (C) it by introducing a carbon source. On the one hand, the cracked C combines with the Si with dangling bonds to generate an extremely thin SiC lattice adaptation layer 2; then pre-Si and pre-C are alternately carried out multiple times to obtain the SiC lattice adaptation layer 2 with a near two-dimensional surface. On the other hand, the total amount of the carbon source is higher than that of the silicon source, which can avoid the formation of silicon droplets and prevent the silicon droplets from damaging the crystal structure of the SiC lattice adaptation layer 2.

[0110] In some embodiments, the time for introducing the first silicon source is t1 which satisfies: 4 min ≤ t 1 ≤ 5 min, and the flow rate of the first silicon source introduced is Q 1 which satisfies: 5 sccm ≤ Q 1 ≤ 10 sccm. Specifically, the value of the time t 1 (unit: min) for introducing the first silicon source can be any value among 4 min, 4.5 min, and 5 min or any range composed of any two of these values; the value of the flow rate Q 1 (unit: sccm) for introducing the first silicon source can be any value among 5 sccm, 6 sccm, 7 sccm, 8 sccm, 9 sccm, and 10 sccm or any range composed of any two of these values.

[0111] It can be understood that by controlling the time for introducing the first silicon source to be t 1 which satisfies: 4 min ≤ t 1 ≤ 5 min, and the flow rate of the first silicon source introduced is Q 1 which satisfies: 5 sccm ≤ Q 1 ≤ 10 sccm, the thickness of the formed silicon layer can be controlled. On the one hand, the defects on the surface of the Si substrate can be repaired, making the Si substrate smoother and ensuring the two-dimensional growth of the SiC lattice adaptation layer 2. On the other hand, Si atoms with dangling bonds are formed on the surface of the Si substrate.

[0112] In some embodiments, the time for introducing the carbon source is t 2 which satisfies: 1 min ≤ t 2 ≤ 2 min, and the flow rate of the carbon source introduced is Q 2 which satisfies: 5 sccm ≤ Q 2 ≤ 20 sccm. Specifically, the value of the time t 2 (unit: min) for introducing the carbon source can be any value among 1 min, 1.5 min, and 2 min or any range composed of any two of these values; the value of the flow rate Q 2 (unit: sccm) for introducing the carbon source can be any value among 5 sccm, 6 sccm, 7 sccm, 8 sccm, 9 sccm, 10 sccm, 11 sccm, 12 sccm, 13 sccm, 14 sccm, 15 sccm, 16 sccm, 17 sccm, 18 sccm, 19 sccm, and 20 sccm or any range composed of any two of these values.

[0113] In some embodiments, the time for introducing the second silicon source is t 3 which satisfies: 1 min ≤ t 3 ≤ 2 min, and the flow rate of the second silicon source introduced is Q 3 which satisfies: 5 sccm ≤ Q 3≤10 sccm. Specifically, the time t 3 for introducing the second silicon source (unit: min) can be any value among 1 min, 1.5 min, and 2 min or any range composed of any two of these values; the flow rate Q 3 for introducing the second silicon source (unit: sccm) can be any value among 5 sccm, 6 sccm, 7 sccm, 8 sccm, 9 sccm, and 10 sccm or any range composed of any two of these values.

[0114] It can be understood that by controlling the time for introducing the carbon source to be t 2 , the following is satisfied: 1 min ≤ t 2 ≤ 2 min, and the flow rate of the carbon source is Q 2 , satisfying: 5 sccm ≤ Q 2 ≤ 20 sccm. The time for introducing the second silicon source is t 3 , satisfying: 1 min ≤ t 3 ≤ 2 min, and the flow rate of the second silicon source is Q 3 , satisfying: 5 sccm ≤ Q 3 ≤ 10 sccm. First, the carbon source is introduced to pre - deposit carbon (C). On the one hand, the cracked C combines with Si with dangling bonds to form an extremely thin SiC lattice adaptation layer 2; then, Si pre - deposition and C pre - deposition are alternately carried out multiple times to obtain the SiC lattice adaptation layer 2 with a near - two - dimensional surface. On the other hand, the total amount of the carbon source is higher than that of the silicon source, which can avoid the formation of silicon droplets and prevent the silicon droplets from damaging the crystal structure of the SiC lattice adaptation layer 2.

[0115] In some embodiments, the first silicon source is selected from at least one of silane, dichlorosilane, trichlorosilane, and silicon tetrachloride.

[0116] In some embodiments, the carbon source is selected from at least one of ethylene, methane, and ethane.

[0117] In some embodiments, the second silicon source is selected from at least one of silane, dichlorosilane, trichlorosilane, and silicon tetrachloride.

[0118] In some embodiments, the first silicon source and the second silicon source can be the same or different.

[0119] In some embodiments, the number of times for separately introducing the carbon source and the second silicon source is M, satisfying: 8 times ≤ M ≤ 40 times. Specifically, the value of the number of times M for separately introducing the carbon source and the second silicon source (unit: times) can be any value among 8, 10, 15, 20, 25, 30, 35, and 40 or any range composed of any two of these values.

[0120] It can be understood that by controlling the number of times M of separately introducing the carbon source and the second silicon source, the thickness of the formed silicon layer can be controlled. On the one hand, the defects on the surface of the Si substrate can be repaired, making the Si substrate smoother and ensuring the two-dimensional growth of the SiC lattice adaptation layer 2. On the other hand, Si atoms with dangling bonds are formed on the surface of the Si substrate; by introducing the carbon source to pre-deposit carbon (C), the cracked C combines with the Si with dangling bonds to generate an extremely thin SiC lattice adaptation layer 2; then, Si pre-deposition and C pre-deposition are alternately carried out multiple times. On the one hand, a nearly two-dimensional surface SiC lattice adaptation layer 2 is obtained to fully cover the surface of the substrate 1. On the other hand, the thickness of the SiC lattice adaptation layer 2 is prevented from being too high, resulting in too high a defect density in the crystal of the nucleation layer 3.

[0121] In some embodiments, the thickness of the silicon carbide lattice adaptation layer 2 is 2 to 10 nm. Specifically, the thickness of the silicon carbide lattice adaptation layer 2 can be any value among 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm or a range composed of any two values.

[0122] In some embodiments, after forming the nucleation layer 3 on the side of the silicon carbide layer lattice adaptation layer 2 away from the substrate 1, it further includes:

[0123] Forming a first buffer layer 4 on the side of the nucleation layer 3 away from the silicon carbide lattice adaptation layer 2;

[0124] Forming a second buffer layer 5 on the side of the first buffer layer 4 away from the nucleation layer 3;

[0125] Forming a channel layer 6 on the side of the second buffer layer 5 away from the first buffer layer 4;

[0126] Forming an insertion layer 7 on the side of the channel layer 6 away from the second buffer layer 5;

[0127] Forming a barrier layer 8 on the side of the insertion layer 7 away from the channel layer 6;

[0128] Forming a surface layer 9 on the side of the barrier layer 8 away from the insertion layer 7.

[0129] It can be understood that forming a nucleation layer 3 on the side of the silicon carbide layer lattice adaptation layer 2 away from the substrate 1 can introduce compressive stress to compensate for the tensile stress of the epitaxial wafer, thereby improving the stress and warping during the epitaxial growth process, avoiding the occurrence of surface microcracks, and improving the quality and uniformity of the epitaxial wafer; forming a first buffer layer 4 on the side of the nucleation layer 3 away from the substrate 1 can filter the penetrating dislocations formed by the growth of the nucleation layer 3 and reduce the crystal defect density; forming a second buffer layer 5 on the side of the first buffer layer 4 away from the nucleation layer 3, and the second buffer layer 5 can be a superlattice stacking structure, which can increase the impedance of the epitaxial wafer in the vertical direction, thereby increasing the vertical breakdown voltage of the epitaxial wafer and the device; forming a channel layer 6 on the side of the second buffer layer 5 away from the first buffer layer 4, and the spontaneous polarization of GaN in the channel layer 6 generates a large number of conductive electrons in the channel layer 6, and the electron density is higher on the side close to the insertion layer 7, making the channel layer 6 conductive; forming an insertion layer 7 and a barrier layer 8 in sequence on the side of the channel layer 6 away from the second buffer layer 5. On the one hand, the piezoelectric polarization between the channel layer 6 and the barrier layer 8 will increase the electron density in the channel layer 6 and improve the conductivity of the channel layer 6. On the other hand, the insertion layer 7 will reduce the carrier scattering between the channel layer 6 and the barrier layer 8 and improve the conductivity of the channel layer 6; forming a surface layer 9, that is, a cap layer, on the side of the barrier layer 8 away from the insertion layer 7 can protect the barrier layer 8 from being oxidized, thereby improving the quality of the epitaxial wafer.

[0130] In some embodiments, the first buffer layer 4 includes K stacked AlGaN layers, satisfying: 3 ≤ K ≤ 5. Specifically, the value of K can be any one value among 3, 4, 5 or a range composed of any two values.

[0131] It can be understood that by controlling the first buffer layer 4 to include K stacked AlGaN layers, satisfying: 3 ≤ K ≤ 5, the first buffer layer 4 can gradually filter the penetrating dislocations formed by the growth of the nucleation layer 3, and can achieve layer-by-layer filtering, greatly reducing crystal defects.

[0132] In some embodiments, the material of the first buffer layer 4 is selected from AlGaN; the chemical formula of AlGaN is Al x Ga 1-x N, where 0.05 ≤ x ≤ 0.95, and along the direction away from the nucleation layer 3, the molar content of aluminum in the first buffer layer 4 gradually decreases. Specifically, the value of x can be any one value among 0.05, 0.15, 0.20, 0.25, 0.30, 0.35, 0.40, 0.45, 0.50, 0.55, 0.60, 0.65, 0.70, 0.75, 0.80, 0.85, 0.90, 0.95 or a range composed of any two values.

[0133] It can be understood that when the value of x, that is, the molar content of Al in the first buffer layer 4, satisfies the above value range, the defect density can be rapidly reduced while reducing the lattice mismatch of the epitaxial growth.

[0134] In some embodiments, the material of the barrier layer 8 is selected from AlGaN; the chemical formula of AlGaN is Al y Ga 1-y N, where 0.15 ≤ y ≤ 0.25. Specifically, the value of y can be any value in 0.15, 0.20, 0.21, 0.22, 0.23, 0.24, 0.25 or the range composed of any two values.

[0135] It can be understood that when the value of y, that is, the molar content of Al in the barrier layer 8, satisfies the above value range, the Al component can both generate sufficient two-dimensional electron gas and not increase scattering to affect the mobility, achieving an epitaxial wafer sheet resistance range of 350 - 650 Ω / sq, meeting the requirements of device fabrication.

[0136] In some embodiments, the thickness of the nucleation layer 3 is 200 - 300 nm. Specifically, the thickness of the nucleation layer 3 can be any value in 200 nm, 210 nm, 220 nm, 230 nm, 240 nm, 250 nm, 260 nm, 270 nm, 280 nm, 290 nm, 300 nm or the range composed of any two values.

[0137] In some embodiments, the thickness of the first buffer layer 4 is 1500 - 2000 nm. Specifically, the thickness of the first buffer layer 4 can be any value in 1500 nm, 1600 nm, 1700 nm, 1800 nm, 1900 nm, 2000 nm or the range composed of any two values.

[0138] In some embodiments, the thickness of the second buffer layer 5 is 1800 - 2000 nm. Specifically, the thickness of the second buffer layer 5 can be any value in 1800 nm, 1850 nm, 1900 nm, 1950 nm, 2000 nm or the range composed of any two values.

[0139] In some embodiments, the thickness of the channel layer 6 is 150 - 300 nm. Specifically, the thickness of the channel layer 6 can be any value in 150 nm, 160 nm, 170 nm, 180 nm, 190 nm, 200 nm, 210 nm, 220 nm, 230 nm, 240 nm, 250 nm, 260 nm, 270 nm, 280 nm, 290 nm, 300 nm or the range composed of any two values.

[0140] In some embodiments, the thickness of the insertion layer 7 is 0.5 - 2 nm. Specifically, the thickness of the insertion layer 7 can be any value among 0.5 nm, 1 nm, 1.5 nm, 2 nm or a range composed of any two values.

[0141] In some embodiments, the thickness of the barrier layer 8 is 15 - 25 nm. Specifically, the thickness of the barrier layer 8 can be any value among 15 nm, 16 nm, 17 nm, 18 nm, 19 nm, 20 nm, 21 nm, 22 nm, 23 nm, 24 nm, 25 nm or a range composed of any two values.

[0142] In some embodiments, the thickness of the surface layer 9 is 0.5 - 2 nm. Specifically, the thickness of the surface layer 9 can be any value among 0.5 nm, 1 nm, 1.5 nm, 2 nm or a range composed of any two values.

[0143] It can be understood that due to the lattice mismatch and thermal mismatch between the substrate 1 and the nucleation layer 3, cracks are likely to occur on the surface of the epitaxial layer, and the thicker the epitaxial layer, the more difficult it is to avoid surface cracks. Therefore, the nucleation layer 3, the first buffer layer 4, the second buffer layer 5, the channel layer 6, the insertion layer 7, the barrier layer 8 and the surface layer 9 should not only have a certain thickness to achieve their functions, but also have an upper limit on their thickness to avoid excessive thickness of the epitaxial layer and cracks on the surface of the epitaxial wafer. By controlling the thickness of the nucleation layer 3 to be 200 - 300 nm, the pinholes on the surface of the nucleation layer 3 can be reduced and surface cracks can be avoided, while providing appropriate tensile stress to balance the compressive stress and improving the crystal quality of the epitaxial wafer; by controlling the thickness of the first buffer layer 4 to be 1500 - 2000 nm and the thickness of the second buffer layer 5 to be 1200 - 1800 nm, the impedance of the epitaxial wafer in the vertical direction can be increased; by controlling the thickness of the channel layer 6 to be 150 - 300 nm, the channel layer 6 has a certain thickness to improve the horizontal breakdown voltage. At the same time, an overly thick channel layer 6 will lead to a decrease in the crystal quality of its surface and an increase in the defect density, which will reduce the conductivity of the channel layer 6 and deteriorate the core performance of the epitaxial wafer; by controlling the thickness of the insertion layer 7 to be 0.5 - 2 nm, it can be ensured that the insertion layer 7 completely covers the surface of the channel layer 6, suppress the carrier scattering in the channel layer 6, and at the same time avoid the weakening of the piezoelectric polarization due to the excessive thickness of the insertion layer 7, resulting in a decrease in the conductivity of the channel layer 6; by controlling the thickness of the barrier layer 8 to be 15 - 25 nm, combined with controlling 0.15 ≤ y ≤ 0.25 in the barrier layer 8 with the chemical formula Al y Ga 1-y N, the sheet resistance range of the epitaxial wafer is 350 - 650 Ω / sq, meeting the requirements for device fabrication; by controlling the thickness of the surface layer 9 to be 0.5 - 2 nm, it can be ensured that the surface layer 9 covers the surface of the barrier layer 8, protecting the barrier layer 8 and preventing its oxidation.

[0144] In some embodiments, the material of the substrate 1 is selected from any one of silicon and sapphire.

[0145] In some embodiments, the material of the nucleation layer 3 is selected from AlN.

[0146] In some embodiments, the material of the second buffer layer 5 is selected from GaN.

[0147] In some embodiments, the material of the channel layer 6 is selected from GaN.

[0148] In some embodiments, the material of the insertion layer 7 is selected from any one of AlN, AlGaN or SiN x among them.

[0149] In some embodiments, the material of the surface layer 9 is selected from any one of GaN, P-GaN or SiN x among them.

[0150] It can be understood that by using an Si substrate, the cost can be greatly reduced; by using AlN to prepare the nucleation layer 3, the formation of a silicon-gallium alloy can be avoided, thereby avoiding back-melting etching, and moreover, the lattice constant of AlN is more matched with that of GaN, which can improve the crystal quality of GaN; by using the AlN, AlGaN or SiNx insertion layer 7, carrier scattering can be reduced and the mobility of carriers in the channel layer 6 can be increased; by using the GaN, P-GaN or SiN x surface layer 9, the barrier layer 8 can be prevented from being oxidized, thereby improving the quality of the epitaxial wafer.

[0151] In some embodiments, after the substrate 1 is placed in the reaction chamber, it further includes:

[0152] Introducing an etching gas into the reaction chamber to etch the substrate 1.

[0153] It can be understood that by introducing hydrogen into the reaction chamber to etch the substrate 1, the strain damage layer on the surface of the substrate 1 can be removed, which is beneficial to the growth of the epitaxial layer, thereby improving the crystal quality of the epitaxial wafer.

[0154] In some embodiments, the etching gas is selected from hydrogen or hydrogen chloride.

[0155] In some embodiments, the etching time is 5 to 15 minutes; the etching temperature is 1000 to 1100 °C; the flow rate of hydrogen is 150 to 200 slm. Specifically, the etching time can be any value among 5 minutes, 8 minutes, 10 minutes, 13 minutes, 15 minutes or a range composed of any two of these values; the etching temperature can be any value among 1000 °C, 1020 °C, 1040 °C, 1060 °C, 1080 °C, 1100 °C or a range composed of any two of these values; the flow rate of the etching gas can be any value among 150 slm, 160 slm, 170 slm, 180 slm, 190 slm, 200 slm or a range composed of any two of these values.

[0156] The present application will be described below in conjunction with specific embodiments.

[0157] Example 1

[0158] Step S1: Provide a 6-inch silicon (111) substrate, place the silicon substrate in the reaction chamber, with a thickness of 1000 μm;

[0159] Step S2: Introduce hydrogen into the reaction chamber to etch the silicon substrate, with the flow rate of hydrogen being 180 slm and the etching time being 10 minutes; the etching temperature is 1050 °C.

[0160] Step S3: After cooling the temperature of the reaction chamber from 1050 °C to 1030 °C, introduce a first silicon source into the reaction chamber. The first silicon source is selected as silane, and the flow rate Q 1 of the first silicon source is 8 sccm, and the introduction time t 1 of the first silicon source is 5 minutes;

[0161] Step S4: Turn off the first silicon source, introduce a carbon source into the reaction chamber. The carbon source is selected as ethane, and the flow rate Q 2 of the carbon source is 10 sccm, and the introduction time t 2 of the carbon source is 2 minutes;

[0162] Step S5: Turn off the carbon source, continue to introduce a second silicon source into the reaction chamber. The second silicon source is selected as silane, and the flow rate Q 3 of the first silicon source is 8 sccm, and the introduction time t 3 of the second silicon source is 2 minutes;

[0163] Step S6: By alternately introducing the carbon source 10 times and the second silicon source 10 times, a silicon carbide lattice adaptation layer 2 with a thickness of 3.5 nm is formed on one side of the silicon substrate 1;

[0164] Step S7: In-situ grow a first nucleation layer (AlN low-temperature nucleation layer) 301 and a second nucleation layer (AlN high-temperature nucleation layer) 302 on the silicon carbide lattice adaptation layer 2 in sequence. The formation temperature of the AlN low-temperature nucleation layer is 950 °C, and the thickness is 30 nm. The formation temperature of the AlN high-temperature nucleation layer is 1100 °C, and the thickness is 220 nm;

[0165] Step S8: In-situ grow 4 AlGaN buffer layers 4 with gradually decreasing molar content of aluminum on the second nucleation layer (AlN high-temperature nucleation layer) 302. The molar contents of aluminum in the 4 AlGaN buffer layers are 78%, 50%, 30%, and 20% respectively, and the thicknesses of the 4 AlGaN buffer layers are 250 nm, 500 nm, 500 nm, and 500 nm respectively;

[0166] Step S9: Grow a GaN buffer layer 5 on the AlGaN buffer layer, with a thickness of 2000 nm;

[0167] Step S10: Grow a GaN channel layer 6 on the GaN buffer layer 5, with a thickness of 250 nm;

[0168] Step S11: Grow an AlN insertion layer 7 on the grown GaN channel layer 6, with a thickness of 1 nm;

[0169] Step S12: Grow an AlGaN barrier layer 8 on the AlN insertion layer 7, with a thickness of 22 nm;

[0170] Step S13: Grow a GaN surface layer 9 on the AlGaN barrier layer 8, with a thickness of 1 nm;

[0171] Step S14: In-situ cool to room temperature to end the growth of the gallium nitride epitaxial wafer.

[0172] Comparative Example 1

[0173] The preparation method of Comparative Example 1 is the same as that of Example 1, except that step S3 is omitted.

[0174] Comparative Example 2

[0175] The preparation method of Comparative Example 2 is the same as that of Example 1, except that steps S4, S5, and S6 are omitted.

[0176] Comparative Example 3

[0177] The preparation method of Comparative Example 3 is the same as that of Example 1, except that steps S3, S4, S5, and S6 are omitted.

[0178] Example 2

[0179] S1: Provide a 6-inch silicon (111) substrate, place the silicon substrate in the reaction chamber, with a thickness of 1000 μm;

[0180] S2: Introduce hydrogen into the reaction chamber to etch the silicon substrate. The flow rate of hydrogen is 180 slm, the etching time is 10 min, and the etching temperature is 1050 °C.

[0181] S3: After cooling the temperature of the reaction chamber from 1050 °C to 1030 °C, introduce a first silicon source into the reaction chamber. The first silicon source is selected as silane, and the flow rate Q 1 of the first silicon source is 8 sccm, and the introduction time t 1 of the first silicon source is 5 min.

[0182] S4: Turn off the first silicon source, and introduce a carbon source into the reaction chamber. The carbon source is selected as ethane, and the flow rate Q 2 of the carbon source is 10 sccm, and the introduction time t 2 of the carbon source is 2 min.

[0183] S5: Turn off the carbon source, and continue to introduce a second silicon source into the reaction chamber. The second silicon source is selected as silane, and the flow rate Q 3 of the first silicon source is 8 sccm, and the introduction time t 3 of the second silicon source is 2 min.

[0184] S6: By alternately introducing the carbon source 10 times and the second silicon source 10 times, a silicon carbide lattice matching layer 2 with a thickness of 3.5 nm is formed on one side of the silicon substrate 1.

[0185] S7: In-situ grow a first nucleation layer (AlN low-temperature nucleation layer) 301 and a second nucleation layer (AlN high-temperature nucleation layer) 302 on the silicon carbide lattice matching layer 2 in sequence. The formation temperature of the AlN low-temperature nucleation layer is 950 °C, and the thickness is 30 nm. The formation temperature of the AlN high-temperature nucleation layer is 1100 °C, and the thickness is 220 nm.

[0186] Comparative Example 4

[0187] The preparation method of Comparative Example 4 is the same as that of Example 2, except that step S3 is omitted.

[0188] Comparative Example 5

[0189] The preparation method of Comparative Example 5 is the same as that of Example 2, except that steps S4, S5, and S6 are omitted.

[0190] Comparative Example 6

[0191] The preparation method of Comparative Example 6 is the same as that of Example 2, except that steps S3, S4, S5, and S6 are omitted.

[0192] Examples 3 - 4

[0193] Examples 3 to 6 are the same as Example 1, except that the process parameters for growing the silicon carbide lattice matching layer are adjusted.

[0194] Comparative Examples 7 to 8

[0195] Comparative Examples 7 to 8 are the same as Example 1, except that the process parameters for growing the silicon carbide lattice matching layer are adjusted.

[0196] Testing method:

[0197] (1) Use a high-resolution X-ray diffractometer (XRD) to detect the crystal quality (GaN(002) FWHM & GaN(102) FWHM) of the epitaxial wafers prepared in Example 1, Examples 3 to 4, and Comparative Examples 1 to 3, Comparative Examples 7 to 8. The test results of Example 1 and Comparative Examples 1 to 3 are shown in Table 1 and Figures 3 - 4 as shown; the test results of Example 1, Examples 3 to 4, and Comparative Examples 7 to 8 are shown in Table 3.

[0198] (2) Use an atomic force microscope (AFM) to detect the average arithmetic deviation Ra of the surface profile of the nucleation layer prepared in Example 2 and Comparative Examples 4 to 6 to characterize the surface roughness. The test results are shown in Table 2 and Figures 5 - 8 as shown.

[0199] Table 1 shows the process step settings and test results of Example 1 and Comparative Examples 1 to 3.

[0200]

[0201] Table 2 shows the process step settings and test results of Example 2 and Comparative Examples 4 to 6.

[0202]

[0203] Table 3 shows the process settings and test results of Example 1, Examples 3 to 6, and Comparative Examples 7 to 8.

[0204]

[0205]

[0206] Result analysis:

[0207] From the test results of Example 1 and Comparative Examples 1 to 3, it can be seen that the gallium nitride epitaxial wafer prepared in Example 1 has the smallest GaN(002) FWHM and GaN(102) FWHM, that is, the lowest defect density. By setting a silicon carbide lattice matching layer between the substrate and the nucleation layer in this application, the crystal quality of the GaN epitaxial wafer is improved.

[0208] From the test results of Example 2 and Comparative Examples 4 to 6, it can be seen that the AlN low-temperature nucleation layer prepared in Example 2 has the smallest arithmetic mean deviation of surface profile (Ra). The surface of its AlN low-temperature nucleation layer presents obvious step stripes. That is, by setting a silicon carbide lattice matching layer between the substrate and the nucleation layer in this application, the quality of the AlN low-temperature nucleation layer is improved, and thus the crystal quality of the GaN epitaxial wafer is improved.

[0209] From the test results of Example 1, Examples 3 to 4 and Comparative Examples 7 to 8, it can be seen that too high a thickness of the silicon carbide lattice matching layer 2 will affect the crystal quality of the GaN epitaxial wafer, and too low a thickness of the silicon carbide lattice matching layer 2 will also affect the crystal quality of the GaN epitaxial wafer. By controlling the thickness of the silicon carbide lattice matching layer 2 to be 2 - 10 nm in this application, the lattice mismatch between the nucleation layer 3 and the substrate 1 can be reduced, thereby reducing the defect density of the nucleation layer 3 and improving the crystal quality of the GaN epitaxial wafer.

[0210] From the test results of Example 1, Examples 3 to 6, at flow rates Q 2 and Q 3 , as well as inlet times t 2 and t 3 , when the number of cycles is within the range provided in this application, adjusting these parameters has almost no effect on the crystal quality of the GaN epitaxial wafer, that is, the crystal quality of the GaN epitaxial wafer can be improved in all cases.

[0211] The above has introduced this application in detail. Specific examples are used in this article to elaborate on the principle and implementation manner of this application. The description of the above examples is only used to help understand the method and its core idea of this application; at the same time, for those skilled in the art, based on the idea of this application, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to this application.

Claims

1. A method for preparing an epitaxial wafer, characterized in that: include: Placing a substrate (1) in a reaction chamber, wherein the substrate (1) is made of silicon; Forming a silicon carbide lattice adaptation layer (2) on one side of the substrate (1); forming a nucleation layer (3) on a side of the silicon carbide lattice adaptation layer (2) away from the substrate (1); The substrate (1) has a first in-plane lattice constant d1, the silicon carbide lattice adaptation layer (2) has a second in-plane lattice constant d2, and the nucleation layer (3) has a third in-plane lattice constant d3, satisfying: |d3-d2|<|d3-d1|; The step of forming a silicon carbide lattice adaptation layer (2) on one side of the substrate (1) comprises: introducing a first silicon source into the reaction chamber; Turning off the first silicon source and introducing a carbon source into the reaction chamber; The carbon source is turned off, and the second silicon source continues to be introduced into the reaction chamber, and the carbon source and the second silicon source are introduced alternately to form a silicon carbide lattice adaptation layer (2) on one side of the substrate (1).

2. The method for preparing an epitaxial wafer according to claim 1, characterized in that: The nucleation layer (3) comprises a first nucleation layer (301) and a second nucleation layer (302), the first nucleation layer (301) being located between the silicon carbide lattice adaptation layer (2) and the second nucleation layer (302), and the formation temperature of the second nucleation layer being greater than the formation temperature of the first nucleation layer.

3. The method for preparing an epitaxial wafer according to claim 2, characterized in that: The formation temperature of the first nucleation layer (301) is 900-1000°C; and / or, The formation temperature of the second nucleation layer (302) is 1050-1150°C.

4. The method for preparing an epitaxial wafer according to claim 1, characterized in that: The time for introducing the first silicon source is t1, the time for introducing the carbon source is t2, and the time for introducing the second silicon source is t3, satisfying: t3≤t2≤t1; and / or, The total amount of the carbon source introduced is q1, and the total amount of the second silicon source introduced is q2, satisfying: q2 <q1。 5. The method for preparing an epitaxial wafer according to claim 1, characterized in that: The time for the first silicon source to be introduced is t1, which satisfies: 4min≤t1≤5min, the flow rate of the first silicon source to be introduced is Q1, which satisfies: 5sccm≤Q1≤10sccm; and / or, The time for the carbon source to be introduced is t2, which satisfies: 1min≤t2≤2min, and the flow rate of the carbon source to be introduced is Q2, which satisfies: 5sccm≤Q2≤20sccm; and / or, The time for the second silicon source to be introduced is t3, which satisfies: 1min≤t3≤2min, and the flow rate of the second silicon source to be introduced is Q3, which satisfies: 5sccm≤Q3≤10sccm.

6. The method for preparing an epitaxial wafer according to claim 1, characterized in that: The first silicon source is selected from at least one of silane, dichlorosilane, trichlorosilane and silicon tetrachloride; and / or, The carbon source is selected from at least one of ethylene, methane and ethane; and / or, The second silicon source is selected from at least one of silane, dichlorosilane, trichlorosilane and silicon tetrachloride.

7. The method for preparing an epitaxial wafer according to claim 1, characterized in that: The number of times the carbon source and the second silicon source are alternately introduced is M, which satisfies: 8 times≤M≤40 times.

8. The method for preparing an epitaxial wafer according to claim 1, characterized in that: The thickness of the silicon carbide lattice adaptation layer (2) is 2-10 nm.

9. The method for preparing an epitaxial wafer according to claim 1, characterized in that: After a nucleation layer (3) is formed on a side of the silicon carbide lattice adaptation layer (2) away from the substrate (1), the method further comprises: forming a first buffer layer (4) on a side of the nucleation layer (3) away from the silicon carbide lattice adaptation layer (2); forming a second buffer layer (5) on a side of the first buffer layer (4) away from the nucleation layer (3); forming a channel layer (6) on a side of the second buffer layer (5) away from the first buffer layer (4); forming an insertion layer (7) on a side of the channel layer (6) away from the second buffer layer (5); forming a barrier layer (8) on a side of the insertion layer (7) away from the channel layer (6); A surface layer (9) is formed on a side of the barrier layer (8) away from the insertion layer (7).

10. The method for preparing an epitaxial wafer according to claim 9, characterized in that: The first buffer layer (4) comprises an AlGaN layer stacked with a K layer, satisfying: 3≤K≤5; The material of the first buffer layer (4) is selected from AlGaN; the chemical formula of AlGaN is Al x Ga 1-x N, wherein 0.05≤x≤0.95, and the molar content of aluminum in the first buffer layer (4) gradually decreases in a direction away from the nucleation layer (3).

11. The method for preparing an epitaxial wafer according to claim 9, characterized in that: The material of the barrier layer (8) is selected from AlGaN; the chemical formula of AlGaN is Al y Ga 1-y N, where 0.15≤y≤0.

25.

12. The method for preparing an epitaxial wafer according to claim 9, characterized in that: The thickness of the nucleation layer (3) is 200-300 nm; and / or, The thickness of the first buffer layer (4) is 1500-2000 nm; and / or, The thickness of the second buffer layer (5) is 1800-2000 nm; and / or, The thickness of the channel layer (6) is 150-300 nm; and / or, The thickness of the insertion layer (7) is 0.5-2 nm; and / or, The barrier layer (8) has a thickness of 15 to 25 nm; and / or, The thickness of the surface layer (9) is 0.5-2 nm.

13. The method for preparing an epitaxial wafer according to claim 9, characterized in that: The material of the nucleation layer (3) is selected from AlN; and / or, The material of the second buffer layer (5) is selected from GaN; and / or, The material of the channel layer (6) is selected from GaN; and / or, The material of the insertion layer (7) is selected from AlN, AlGaN or SiN x Any of; and / or, The material of the surface layer (9) is selected from GaN, SiN x Any one of .

14. The method for preparing an epitaxial wafer according to claim 1, characterized in that: After placing the substrate (1) in the reaction chamber, the method further comprises: An etching gas is introduced into the reaction chamber to etch the substrate (1).

15. The method for preparing an epitaxial wafer according to claim 14, characterized in that: The etching gas is selected from hydrogen or hydrogen chloride; and / or, the etching time is 5-15 minutes; the etching temperature is 1000-1100° C.; the flow rate of the etching gas is 150-200 slm.

16. An epitaxial wafer, characterized in that: The epitaxial wafer is prepared by the method for preparing an epitaxial wafer according to any one of claims 1 to 15, and the epitaxial wafer comprises: Substrate (1); A silicon carbide lattice adaptation layer (2), located on one side of the substrate (1); A nucleation layer (3) located on a side of the silicon carbide lattice adaptation layer (2) away from the substrate (1); The substrate (1) has a first in-plane lattice constant d1, the silicon carbide lattice adaptation layer (2) has a second in-plane lattice constant d2, and the nucleation layer (3) has a third in-plane lattice constant d3, satisfying: |d3-d2|<|d3-d1|.

17. The epitaxial wafer according to claim 16, characterized in that: The thickness of the silicon carbide lattice adaptation layer (2) is 2-10 nm.

18. The epitaxial wafer according to claim 16, characterized in that: The nucleation layer (3) comprises a first nucleation layer (301) and a second nucleation layer (302), the first nucleation layer (301) being located between the silicon carbide lattice adaptation layer (2) and the second nucleation layer (302), and the formation temperature of the second nucleation layer being greater than the formation temperature of the first nucleation layer.

19. The epitaxial wafer according to claim 16, characterized in that: The epitaxial wafer further comprises a first buffer layer (4), a second buffer layer (5), a channel layer (6), an insertion layer (7), a barrier layer (8) and a surface layer (9) which are stacked and arranged on a side of the nucleation layer (3) away from the silicon carbide lattice adaptation layer (2).

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