Power device and manufacturing method thereof, power module, power conversion circuit, and vehicle

Abstract

The application discloses a power device and a preparation method thereof, a power module, a power conversion circuit and a vehicle. The power device comprises a substrate and an epitaxial layer which are sequentially stacked; a surface of the epitaxial layer away from the substrate comprises a gate trench; a first gate oxide layer, a polysilicon layer and a second gate oxide layer are arranged in the gate trench; the first gate oxide layer comprises a first subpart and a second subpart, the first subpart covers a sidewall of the gate trench, and the second subpart covers a bottom surface of the gate trench; the second gate oxide layer is arranged on a surface of the second subpart away from the substrate; the polysilicon layer is arranged on a side of the first gate oxide layer and the second gate oxide layer away from the epitaxial layer, the polysilicon layer covers the second gate oxide layer, and the polysilicon layer covers a first surface of the first subpart, and the first surface of the first subpart is a surface of the first subpart away from the sidewall of the gate trench. The application can avoid the gate oxide layer at the bottom of the gate trench from being broken down, and improve the reliability of the power device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a power device, a preparation method thereof, a power module, a power conversion circuit and a vehicle. BACKGROUND

[0002] The trench type silicon carbide power device has the advantages of large current density and small cell pitch, and is widely used. The electric field at the bottom of the gate trench of the existing trench type silicon carbide power device is high. Due to the slow oxidation rate at the bottom of the gate trench and the fast oxidation rate at the sidewall of the gate trench, the conventional gate oxide technical solution has a thick oxide layer at the sidewall of the gate trench and a thin oxide layer at the bottom of the gate trench, which causes the oxide layer at the bottom of the trench to be easily broken down, affecting the reliability of the device. SUMMARY

[0003] The present application provides a power device, a preparation method thereof, a power module, a power conversion circuit and a vehicle to avoid the gate oxide layer at the bottom of the gate trench from being broken down and improve the reliability of the power device.

[0004] According to an aspect of the present application, a power device is provided, comprising:

[0005] a substrate and an epitaxial layer which are sequentially stacked;

[0006] a surface of the epitaxial layer away from the substrate comprises a gate trench; the gate trench is provided with a first gate oxide layer, a polysilicon layer and a second gate oxide layer;

[0007] the first gate oxide layer comprises a first subpart and a second subpart, the first subpart covers the sidewall of the gate trench, and the second subpart covers the bottom surface of the gate trench;

[0008] the second gate oxide layer is arranged at a surface of the second subpart away from the substrate; the polysilicon layer is arranged at a side of the first gate oxide layer and the second gate oxide layer away from the epitaxial layer, the polysilicon layer covers the second gate oxide layer, and the polysilicon layer covers a first surface of the first subpart, the first surface of the first subpart being a surface of the first subpart away from the sidewall of the gate trench.

[0009] Optionally, the polysilicon layer comprises a first polysilicon layer and a second polysilicon layer, the first polysilicon layer is arranged at the first surface of the first subpart, the second gate oxide layer covers the surface of the second subpart away from the substrate, and the second gate oxide layer covers part of the second surface of the first polysilicon layer, wherein the second surface of the first polysilicon layer is a surface of the first polysilicon layer away from the sidewall of the gate trench.

[0010] The second polysilicon layer covers the second gate oxide layer, and the second polysilicon layer covers the second surface which is not covered by the second gate oxide layer.

[0011] Optionally, the second gate oxide layer extends from the surface of the second sub-portion to the second surface of the first polysilicon layer, and the second gate oxide layer covers a partial area of the second surface adjacent to the substrate.

[0012] Optionally, in a direction of the substrate pointing to the epitaxial layer, a size of an area of the second surface of the first polysilicon layer which is not covered by the second gate oxide layer is less than or equal to 0.5 microns.

[0013] Optionally, the second gate oxide layer at the bottom of the gate trench and the thickness of the second sub-portion are a first thickness, and the thickness of the first sub-portion is a second thickness.

[0014] A ratio of the first thickness to the second thickness is greater than or equal to 2 and less than or equal to 5.

[0015] Optionally, a thickness of the first gate oxide layer is greater than or equal to 50 nanometers and less than or equal to 60 nanometers.

[0016] A thickness of the second gate oxide layer is greater than or equal to 50 nanometers and less than or equal to 100 nanometers.

[0017] Optionally, a thickness of the first polysilicon layer is greater than or equal to 50 nanometers and less than or equal to 100 nanometers.

[0018] Optionally, the first gate oxide layer and the second gate oxide layer adopt the same material.

[0019] Optionally, the surface of the epitaxial layer away from the substrate further comprises a source trench, and the first gate oxide layer and the first polysilicon layer are arranged in the source trench.

[0020] In the source trench, the first gate oxide layer is arranged between the first polysilicon layer and the epitaxial layer.

[0021] Optionally, the surface of the epitaxial layer away from the substrate further comprises a first conductive type region and a second conductive type region; the second conductive type region is located on a side of the first conductive type region away from the substrate, and the first conductive type region and the second conductive type region are located between the source trench and the gate trench.

[0022] An epitaxial layer surface in the source trench is provided with an electric field shielding region.

[0023] The power device further comprises an insulating layer, a source metal, and a drain metal.

[0024] The insulating layer is disposed on a side of the epitaxial layer away from the substrate, and covers the gate trench; the source metal is disposed on a side of the insulating layer away from the substrate, and contacts the second-conductivity-type region between the source trench and the gate trench; and the electric field shielding region contacts the source metal.

[0025] The drain metal is disposed on a side of the substrate away from the epitaxial layer.

[0026] According to another aspect of the present application, there is provided a power module comprising a substrate and the power device according to any of the embodiments of the present application, wherein the substrate is configured to support the power device.

[0027] According to another aspect of the present application, there is provided a power conversion circuit configured to perform one or more of current conversion, voltage conversion, and power factor correction.

[0028] The power conversion circuit comprises a circuit board and at least one power device according to any of the embodiments of the present application, wherein the power device is electrically connected to the circuit board.

[0029] According to another aspect of the present application, there is provided a vehicle comprising a load and a power conversion circuit according to any of the embodiments of the present application, wherein the power conversion circuit is configured to convert alternating current into direct current, convert alternating current into alternating current, convert direct current into direct current, or convert direct current into alternating current, and input the converted current to the load.

[0030] According to another aspect of the present application, there is provided a method for manufacturing a power device, comprising:

[0031] forming an epitaxial layer on a side of a substrate;

[0032] forming a gate trench on a surface of the epitaxial layer away from the substrate;

[0033] forming a first gate oxide layer, a polysilicon layer, and a second gate oxide layer in the gate trench; wherein the first gate oxide layer comprises a first sub-portion and a second sub-portion, the first sub-portion covers a sidewall of the gate trench, and the second sub-portion covers a bottom surface of the gate trench; the second gate oxide layer is disposed on a surface of the second sub-portion away from the substrate; and the polysilicon layer is disposed on a side of the first gate oxide layer and the second gate oxide layer away from the epitaxial layer, and covers the second gate oxide layer and a first surface of the first sub-portion, the first surface being a surface of the first sub-portion away from the sidewall of the gate trench.

[0034] Optionally, forming a first gate oxide layer, a polysilicon layer, and a second gate oxide layer in the gate trench comprises:

[0035] forming a first gate oxide layer in the gate trench;

[0036] forming a first polysilicon layer in the gate trench; wherein the first polysilicon layer is disposed on a first surface of the first sub-portion;

[0037] forming a second gate oxide layer in the gate trench; wherein the second gate oxide layer covers a surface of the second sub-portion distal to the substrate, and the second gate oxide layer covers a partial area of a second surface of the first polysilicon layer, the second surface of the first polysilicon layer being a surface of the first polysilicon layer distal to a sidewall of the gate trench;

[0038] forming a second polysilicon layer in the gate trench; wherein the second polysilicon layer covers the second gate oxide layer, and the second polysilicon layer covers the second surface not covered by the second gate oxide layer.

[0039] Optionally, forming a second gate oxide layer in the gate trench comprises:

[0040] forming a second gate oxide material layer using chemical vapor deposition or high-temperature oxidation process;

[0041] patterning the second gate oxide material layer to form the second gate oxide layer.

[0042] Optionally, before forming a gate trench on a surface of the epitaxial layer distal to the substrate, further comprising:

[0043] forming a source trench on a surface of the epitaxial layer distal to the substrate;

[0044] simultaneously with forming a first gate oxide layer in the gate trench, further comprising:

[0045] forming a first gate oxide layer in the source trench; wherein the first gate oxide layer covers the epitaxial layer in the source trench;

[0046] simultaneously with forming a first polysilicon layer in the gate trench, further comprising:

[0047] forming the first polysilicon layer in the source trench.

[0048] The power device of the embodiment of the present application is provided with a first gate oxide layer, a polysilicon layer and a second gate oxide layer in the gate trench of the power device; the first gate oxide layer comprises a first sub-portion and a second sub-portion, the first sub-portion covers the sidewall of the gate trench, and the second sub-portion covers the bottom surface of the gate trench; the second gate oxide layer is arranged on the surface of the second sub-portion away from the substrate, so that the bottom of the gate trench comprises two layers of gate oxide layers, i.e., the first gate oxide layer and the second gate oxide layer, the total thickness of the gate oxide layer at the bottom of the gate trench is relatively thick, the gate oxide layer at the bottom of the gate trench can be prevented from being broken down, and the reliability of the power device is improved.

[0049] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present application, nor is it used to limit the scope of the present application. Other features of the present application will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0050] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0051] Figure 1 is a schematic diagram of a power device provided by an embodiment of the present application;

[0052] Figure 2 is a schematic diagram of another power device provided by an embodiment of the present application;

[0053] Figure 3 is a flowchart of a preparation method of a power device provided by an embodiment of the present application;

[0054] Figure 4 is a schematic diagram after forming a first conductive type layer and a second conductive type layer provided by an embodiment of the present application;

[0055] Figure 5 is a schematic diagram after forming a source trench provided by an embodiment of the present application;

[0056] Figure 6 is a schematic diagram after forming an electric field shielding layer provided by an embodiment of the present application;

[0057] Figure 7 is a schematic diagram after forming a gate trench provided by an embodiment of the present application;

[0058] Figure 8 is a schematic diagram after forming a first gate oxide layer provided by an embodiment of the present application;

[0059] Figure 9is a schematic view after forming a first polysilicon layer provided by the embodiment of the present application;

[0060] Figure 10 is a schematic view after forming a second gate oxide layer provided by the embodiment of the present application;

[0061] Figure 11 is a schematic view after forming a second polysilicon layer provided by the embodiment of the present application;

[0062] Figure 12 is a schematic view after forming an insulating layer provided by the embodiment of the present application. DETAILED DESCRIPTION

[0063] In order to make the personnel in the art better understand the present application scheme, the technical scheme in the embodiment of the present application will be described clearly and completely below by combining the drawings in the embodiment of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, not all. Based on the embodiments in the present application, all other embodiments obtained by the person skilled in the art without creative labor should belong to the scope of protection of the present application.

[0064] It should be noted that the terms "first", "second" and the like in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units does not have to be limited to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0065] The embodiment of the present application provides a power device, Figure 1 is a schematic view of a power device provided by the embodiment of the present application, referring to Figure 1 , the power device comprises:

[0066] The substrate 10 and the epitaxial layer 20 are sequentially laminated and arranged;

[0067] The surface of the epitaxial layer 20 away from the substrate 10 comprises a gate trench 30; the gate trench 30 is provided with a first gate oxide layer 40, a polysilicon layer 50 and a second gate oxide layer 60;

[0068] The first gate oxide layer 40 comprises a first sub-portion 41 and a second sub-portion 42, the first sub-portion 41 covers the sidewall of the gate trench 30, and the second sub-portion 42 covers the bottom surface of the gate trench 30;

[0069] The second gate oxide layer 60 is arranged on the surface of the second sub-portion 42 away from the substrate 10; the polysilicon layer 50 is arranged on the side of the first gate oxide layer 40 and the second gate oxide layer 60 away from the epitaxial layer 20, the polysilicon layer 50 covers the second gate oxide layer 60, and the polysilicon layer 50 covers the first surface of the first sub-portion 41, which is the surface of the first sub-portion 41 away from the sidewall of the gate trench 30.

[0070] The power device can be a silicon carbide trench metal oxide semiconductor field effect transistor (MOSFET). The substrate 10 is a second-conductivity-type substrate, and the epitaxial layer 20 is a second-conductivity-type epitaxial layer. The second conductivity type is P-type, or the second conductivity type is N-type. For example, if the device is an N-type device, the substrate 10 is an N+ substrate, which can be an N+ silicon carbide substrate; the epitaxial layer 20 is an N- epitaxial layer, which can be an N- silicon carbide epitaxial layer; if the device is a P-type device, the substrate 10 is a P+ substrate, and the epitaxial layer 20 is a P- epitaxial layer.

[0071] The materials of the first gate oxide layer 40 and the second gate oxide layer 60 can be the same, for example, the materials of the first gate oxide layer 40 and the second gate oxide layer 60 can be silicon dioxide. By arranging the second gate oxide layer 60 on the surface of the second sub-portion 42, the total thickness of the gate oxide layer at the bottom of the gate trench 30 is relatively thick, which can avoid the breakdown of the gate oxide layer at the bottom of the gate trench 30, and improve the reliability of the power device.

[0072] Specifically, the first gate oxide layer 40 can be formed on the surface of the gate trench 30 first, then a first polysilicon layer 51 is formed on the first surface of the first sub-portion 41, then the second gate oxide layer 60 is formed on the surface of the second sub-portion 42, and then a second polysilicon layer 52 is formed, which covers the second gate oxide layer 60 and is connected to the first polysilicon layer 51.

[0073] The power device of the embodiment of the present application is provided with the first gate oxide layer 40, the polysilicon layer 50 and the second gate oxide layer 60 in the gate trench 30; the first gate oxide layer 40 includes the first sub-portion 41 and the second sub-portion 42, the first sub-portion 41 covers the sidewall of the gate trench 30, and the second sub-portion 42 covers the bottom surface of the gate trench 30; the second gate oxide layer 60 is arranged on the surface of the second sub-portion 42 away from the substrate 10, so that the bottom of the gate trench 30 includes two layers of gate oxide layers, i.e., the first gate oxide layer 40 and the second gate oxide layer 60, and the total thickness of the gate oxide layer at the bottom of the gate trench 30 is relatively thick, which can avoid the breakdown of the gate oxide layer at the bottom of the gate trench 30, and improve the reliability of the power device.

[0074] On the basis of the above-mentioned embodiment, optionally,Figure 1 The polysilicon layer 50 includes a first polysilicon layer 51 and a second polysilicon layer 52. The first polysilicon layer 51 is arranged on the first surface of the first sub-portion 41. The second gate oxide layer 60 covers the surface of the second sub-portion 42 away from the substrate 10, and covers part of the second surface 5 of the first polysilicon layer 51. The second surface 5 of the first polysilicon layer 51 is the surface of the first polysilicon layer 51 away from the sidewall of the gate trench 30. The second polysilicon layer 52 covers the second gate oxide layer 60, and covers the second surface 5 not covered by the second gate oxide layer 60.

[0075] The material of the first polysilicon layer 51 and the second polysilicon layer 52 can be the same. After the first gate oxide layer 40 is formed, a polysilicon material layer is deposited on the surface of the first gate oxide layer 40, and then the polysilicon material layer is etched to retain the polysilicon material layer on the first surface of the first sub-portion 41, thereby forming the first polysilicon layer 51. For example, the polysilicon material layer can be etched by dry etching or wet etching. After the first polysilicon layer 51 is formed, an oxide material layer is deposited, and then the oxide material layer is etched to retain the oxide material layer on the surface of the second sub-portion 42 and part of the oxide material layer on the second surface 5 of the first polysilicon layer 51, thereby forming the second gate oxide layer 60. After the second gate oxide layer 60 is formed, a polysilicon material layer is deposited, and then the polysilicon material layer outside the gate trench 30 is etched away, thereby forming the second polysilicon layer 52.

[0076] The embodiment sets the first polysilicon layer 51 on the surface of the first sub-portion 41 of the first gate oxide layer 40, so that the second gate oxide layer 60 is formed on the surface of the second sub-portion 42 and the first polysilicon layer 51. Thus, the total thickness of the gate oxide layer at the bottom of the gate trench 30 is thick without affecting the thickness of the first gate oxide layer 40 on the sidewall of the gate trench 30, which can avoid the gate oxide layer at the bottom of the gate trench 30 from being broken down, and improve the reliability of the power device. Moreover, the second gate oxide layer 60 covers part of the second surface of the first polysilicon layer 51, so that the first polysilicon layer 51 and the second polysilicon layer 52 are connected to each other, thereby ensuring the normal transmission of the gate signal.

[0077] It should be noted that, Figure 1 It should be noted that, In the embodiment, only the case that part of the surface of the second gate oxide layer 60 extending into the polysilicon layer 50 is shown, which is not a limitation to the present application. In other embodiments, part of the surface of the second gate oxide layer 60 extending into the polysilicon layer 50 can not be shown. For example, the surface of the second gate oxide layer 60 away from the substrate 10 is a plane or an approximately plane, or the surface of part of the second gate oxide layer 60 extending into the polysilicon layer 50 away from the substrate 10 is lower than the surface of other regions of the second gate oxide layer 60 away from the substrate 10.

[0078] On the basis of the above-mentioned embodiments, optionally, with reference to the above-mentioned embodiments Figure 1 The second gate oxide layer 60 extends from the surface of the second sub-portion 42 to the second surface 5 of the first polysilicon layer 51, and covers a partial region of the second surface adjacent to the substrate 10.

[0079] The second gate oxide layer 60 covers a partial region of the second surface 5 adjacent to the substrate 10, that is, a region of the second surface 5 of the first polysilicon layer 50 away from the substrate 10 is not covered by the second gate oxide layer 60. In this way, the difficulty of the manufacturing process of the second gate oxide layer 60 can be reduced.

[0080] Specifically, when the second gate oxide layer 60 is formed, an oxide material layer is first formed, then a photoresist layer is arranged on the surface of the oxide material layer, the photoresist layer is patterned to expose the oxide material layer that needs to be etched, and then the oxide material layer is etched to form the second gate oxide layer 60. When the oxide material layer is etched, the oxide material layer in a region of the second surface 5 of the first polysilicon layer 50 away from the substrate 10 needs to be etched and removed. The difficulty of patterning the photoresist layer in this region and the difficulty of etching the oxide material layer are relatively low, thereby reducing the difficulty of the manufacturing process of the second gate oxide layer 60.

[0081] On the basis of the above-mentioned embodiments, optionally, in a direction along the substrate 10 pointing to the epitaxial layer 20, the size D of the region of the second surface 5 of the first polysilicon layer 51 not covered by the second gate oxide layer 60 is less than or equal to 0.5 microns.

[0082] That is, the width of the region of the surface of the first polysilicon layer 51 away from the sidewall of the gate trench 30 is less than or equal to 0.5 microns. In this way, the difficulty of patterning the photoresist layer and the difficulty of etching the oxide material layer in the process of forming the second gate oxide layer 60 can be further reduced, and the difficulty of the manufacturing process of the second gate oxide layer 60 can be further reduced.

[0083] On the basis of the above-mentioned embodiments, optionally, the thickness of the second gate oxide layer 60 at the bottom of the gate trench 30 and the thickness of the second sub-portion 42 are a first thickness, and the thickness of the first sub-portion 41 is a second thickness.

[0084] The ratio of the first thickness to the second thickness is greater than or equal to 2 and less than or equal to 5.

[0085] In this way, the gate oxide layer at the bottom of the gate trench 30 has a relatively large thickness, which can avoid being broken down by an electric field, and the thickness of the gate oxide layer at the bottom of the gate trench 30 will not be too large to occupy too much space, thereby not affecting the volume of the polysilicon layer.

[0086] On the basis of the above embodiment, optionally, the thickness S1 of the first gate oxide layer 50 is greater than or equal to 50 nanometers and less than or equal to 60 nanometers.

[0087] The thickness S2 of the second gate oxide layer 60 is greater than or equal to 50 nanometers and less than or equal to 100 nanometers.

[0088] Specifically, when the thickness S1 of the first gate oxide layer 50 is too small, the insulation effect between the polysilicon layer 50 and the epitaxial layer 20 is weak, which may affect the performance of the device. When the thickness S1 of the first gate oxide layer 50 is too large, the space occupied is too large. By setting the thickness S1 of the first gate oxide layer 50 to be greater than or equal to 50 nanometers and less than or equal to 60 nanometers, the insulation effect can be ensured, and at the same time, the volume occupied can be smaller, which is beneficial to the manufacture of the polysilicon layer 50 and the second gate oxide layer 60.

[0089] When the thickness S2 of the second gate oxide layer 60 is too small, the total thickness of the gate oxide layer at the bottom of the gate trench 30 is small, which cannot avoid breakdown well. When the thickness S2 of the second gate oxide layer 60 is too large, the space occupied in the gate trench 30 is too large. By setting the thickness S2 of the second gate oxide layer 60 to be greater than or equal to 50 nanometers and less than or equal to 100 nanometers, the total thickness of the gate oxide layer at the bottom of the gate trench 30 can be ensured to be large, which can avoid breakdown well, and at the same time, the space occupied by the second gate oxide layer 60 can be small, so that the polysilicon layer 50 has a larger volume, and the polysilicon layer 50 can transmit the gate signal well.

[0090] On the basis of the above embodiment, optionally, the thickness S3 of the first polysilicon layer 51 is greater than or equal to 50 nanometers and less than or equal to 100 nanometers.

[0091] Specifically, when the thickness S3 of the first polysilicon layer 51 is too small, the manufacturing process is difficult. When the thickness S3 of the first polysilicon layer 51 is too large, the first polysilicon layer 51 will cover part of the second sub 42, so that the area of the second gate oxide layer 60 covering the second sub 42 is small, which affects the thickness of the gate oxide layer at the bottom of the gate trench 30. By setting the thickness S3 of the first polysilicon layer 51 to be greater than or equal to 50 nanometers and less than or equal to 100 nanometers, the manufacturing process can be reduced, and at the same time, the first polysilicon layer 51 can avoid affecting the coverage area of the second gate oxide layer 60 at the bottom of the gate trench 30, so as to avoid affecting the thickness of the gate oxide layer at the bottom of the gate trench 30, and ensure that the gate oxide layer at the bottom of the gate trench 30 has a larger thickness, which can avoid breakdown well.

[0092] On the basis of the above embodiment, optionally, the first gate oxide layer 50 and the second gate oxide layer 60 adopt the same material.

[0093] In this way, the first gate oxide layer 50 and the second gate oxide layer 60 can be prepared by the same process, thereby reducing the process cost.

[0094] Based on the above embodiment, optionally, continuing to refer to Figure 1 The epitaxial layer 20 away from the surface of the substrate 10 further comprises a source trench 70, and the first gate oxide layer 40 and the first polysilicon layer 51 are arranged in the source trench 70.

[0095] In the source trench 70, the first gate oxide layer 40 is arranged between the first polysilicon layer 51 and the epitaxial layer 20.

[0096] Specifically, the first polysilicon layer 51 in the gate trench 30 and the source trench 70 is prepared by the same material in the same process, thereby reducing the process steps and reducing the process cost. The first gate oxide layer 40 in the gate trench 30 and the source trench 70 is prepared by the same material in the same process, thereby reducing the process steps and reducing the process cost.

[0097] Figure 2 is another schematic diagram of a power device provided by the embodiment of the present application, and optionally, referring to Figure 2 The epitaxial layer 20 away from the surface of the substrate 10 further comprises a first conductive type region 80 and a second conductive type region 90; the second conductive type region 90 is located on the side of the first conductive type region 80 away from the substrate 10, and the first conductive type region 80 and the second conductive type region 90 are located between the source trench 70 and the gate trench 30.

[0098] The surface of the epitaxial layer 20 in the source trench 70 is provided with an electric field shielding region 100.

[0099] The power device further comprises an insulating layer 110, a source metal 120 and a drain metal 130.

[0100] The insulating layer 110 is arranged on the side of the epitaxial layer 20 away from the substrate 10, and the insulating layer 110 covers the gate trench 30; the source metal 120 is arranged on the side of the insulating layer 110 away from the substrate 10, the second conductive type region 90 between the source trench 70 and the gate trench 30 and the source metal 120 are in contact, and the electric field shielding region 100 is in contact with the source metal 120.

[0101] The drain metal 130 is arranged on the side of the substrate 10 away from the epitaxial layer 20.

[0102] Specifically, the first conductive type is N type and the second conductive type is P type, or the first conductive type is P type and the second conductive type is N type. After the epitaxial layer 20 is grown on the substrate 10, ion implantation can be performed on the epitaxial layer 20 to form the first conductive type region 80 and the second conductive type region 90, respectively. The electric field shielding region 100 can be formed by performing ion implantation on the epitaxial layer 20 at the bottom of the source trench 70. The electric field shielding region 100 has the same conductive type as the first conductive type region 80. For example, P+ ion implantation can be performed on the epitaxial layer 20 at the bottom of the source trench 70 to form the electric field shielding region 100.

[0103] The source trench 70 can be located on one side of the gate trench 30, and the source trench 70 surrounds the gate trench 30. The power device can also include two source trenches 70, and the gate trench 30 is located between the two source trenches 70. The two source trenches 70 can be symmetrically arranged relative to the gate trench 30, or can be asymmetrically arranged. The electric field shielding region 100 is used to shield the electric field of the gate trench 30, further avoiding breakdown of the gate oxide layer at the bottom of the gate trench 30. By arranging the source trench 70 and the electric field shielding region 100 at the bottom and sidewall of the source trench 70, the electric field of the gate trench 30 can be better shielded, and the breakdown of the gate oxide layer at the bottom of the gate trench 30 can be better avoided.

[0104] Specifically, during operation of the power device, by applying a gate voltage to the polysilicon layer 50 in the gate trench 30, applying a source voltage to the source metal 120, and applying a drain voltage to the drain metal 130, the gate voltage and the source voltage satisfy the conduction condition, the channel between the source metal 120 and the drain metal 130 is turned on, and the power device operates normally. The source metal 120, the electric field shielding region 100, the epitaxial layer 20, and the drain metal 130 form a diode structure. When the voltages on the source metal 120 and the drain metal 130 are reversed, the diode structure is turned on, and the channel between the source metal 120 and the drain metal 130 is not conductive, thereby avoiding damage to the power device caused by the reverse voltage.

[0105] In addition, with reference to Figure 2 , the power device further includes a passivation layer 140 and a PI layer 150. The passivation layer 130 is arranged on the side of the source metal 120 away from the substrate 10. The PI layer 150 is arranged on the side of the passivation layer 130 away from the substrate 10. The passivation layer 140 can be made of silicon nitride material. The passivation layer 140 includes an opening, and the source metal 100 is exposed at the opening.

[0106] The embodiment of the present application further provides a power module, which includes a substrate and the power device according to any of the embodiments of the present application. The substrate is used to carry the power device.

[0107] The power module provided by the technical solution of the present invention has the same beneficial effects as the power device described in any embodiment of the present invention.

[0108] Based on the above embodiments, this invention also provides a power conversion circuit, which is used for one or more of current conversion, voltage conversion, and power factor correction. The power conversion circuit includes a circuit board and the power device described in any embodiment of this invention, and the power device is electrically connected to the circuit board.

[0109] The power conversion circuit provided by the technical solution of this invention has the same beneficial effects as the power device described in any embodiment of this invention.

[0110] Based on the above embodiments, this invention also provides a vehicle, including a load and the power conversion circuit described in any embodiment of this invention. The power conversion circuit is used to convert AC power to DC power, convert AC power to AC power, convert DC power to DC power, or convert DC power to AC power and then input it to the load.

[0111] The vehicle provided by the technical solution of this invention has the same beneficial effects as the power device described in any embodiment of this invention.

[0112] This invention also provides a method for fabricating a power device. Figure 3 This is a flowchart of a method for fabricating a power device according to an embodiment of the present invention, see reference. Figure 3 The fabrication methods for power devices include:

[0113] S210. An epitaxial layer is formed on one side of the substrate;

[0114] S220, A gate trench is formed on the surface of the epitaxial layer away from the substrate;

[0115] S230. A first gate oxide layer, a polysilicon layer, and a second gate oxide layer are formed within the gate trench. The first gate oxide layer includes a first sub-part and a second sub-part, the first sub-part covering the sidewall of the gate trench, and the second sub-part covering the bottom surface of the gate trench. The second gate oxide layer is disposed on the surface of the second sub-part away from the substrate. The polysilicon layer is disposed on the side of the first and second gate oxide layers away from the epitaxial layer, the polysilicon layer covering the second gate oxide layer, and the polysilicon layer covering the first surface of the first sub-part, which is the surface of the first sub-part away from the sidewall of the gate trench.

[0116] The gate trench of the power device is provided with a first gate oxide layer, a polysilicon layer and a second gate oxide layer; the first gate oxide layer comprises a first subpart and a second subpart, the first subpart covers the sidewall of the gate trench, and the second subpart covers the bottom surface of the gate trench; the second gate oxide layer is arranged on the surface of the second subpart away from the substrate, so that the bottom of the gate trench comprises two layers of gate oxide layers, i.e., the first gate oxide layer and the second gate oxide layer, the total thickness of the gate oxide layer at the bottom of the gate trench is relatively large, the gate oxide layer at the bottom of the gate trench can be prevented from being broken down, and the reliability of the power device is improved.

[0117] Optionally, the first gate oxide layer, the polysilicon layer and the second gate oxide layer are formed in the gate trench, comprising:

[0118] The first gate oxide layer is formed in the gate trench;

[0119] The first polysilicon layer is formed in the gate trench; wherein the first polysilicon layer is arranged on the first surface of the first subpart;

[0120] The second gate oxide layer is formed in the gate trench; wherein the second gate oxide layer covers the surface of the second subpart away from the substrate, and the second gate oxide layer covers part of the second surface of the first polysilicon layer, the second surface of the first polysilicon layer being the surface of the first polysilicon layer away from the sidewall of the gate trench;

[0121] The second polysilicon layer is formed in the gate trench; wherein the second polysilicon layer covers the second gate oxide layer, and the second polysilicon layer covers the second surface which is not covered by the second gate oxide layer.

[0122] Optionally, before the gate trench is formed on the surface of the epitaxial layer away from the substrate, further comprising:

[0123] The source trench is formed on the surface of the epitaxial layer away from the substrate;

[0124] The first gate oxide layer is formed in the gate trench at the same time, further comprising:

[0125] The first gate oxide layer is formed in the source trench; wherein the first gate oxide layer covers the epitaxial layer in the source trench;

[0126] The first polysilicon layer is formed in the gate trench at the same time, further comprising:

[0127] The first polysilicon layer is formed in the source trench.

[0128] Optionally, the second gate oxide layer is formed in the gate trench, comprising:

[0129] forming a second gate oxide material layer by a chemical vapor deposition or a high temperature oxidation process;

[0130] forming the second gate oxide layer by patterning the second gate oxide material layer.

[0131] The forming process of the power device will be described below in combination with specific drawings:

[0132] Figure 4 is a schematic diagram of the first conductive type layer and the second conductive type layer provided by the embodiment of the present application, referring to Figure 4 After forming the epitaxial layer 20, the epitaxial layer 20 can be doped to form the first conductive type layer 801 and the second conductive type layer 901, or the first conductive type layer 801 and the second conductive type layer 901 can be grown outside the epitaxial layer 20. For example, the epitaxial layer 20 can be implanted with PW and N+ ions to form the first conductive type layer 801 and the second conductive type layer 901. Figure 5 is a schematic diagram of the source trench provided by the embodiment of the present application, referring to Figure 5 The first conductive type layer 801 and the second conductive type layer 901 and the epitaxial layer 20 can be etched by using dry etching and wet etching processes to form the source trench 70. Figure 6 is a schematic diagram of the electric field shielding layer provided by the embodiment of the present application, referring to Figure 6 The source trench bottom and sidewall are implanted with P+ ions to form the electric field shielding region 100. Figure 7 is a schematic diagram of the gate trench provided by the embodiment of the present application, referring to Figure 7 The first conductive type layer 801 and the second conductive type layer 901 and the epitaxial layer 20 between the source trenches 70 can be etched by using dry etching and wet etching processes to form the gate trench 30, the first conductive type region 80 and the second conductive type region 90.

[0133] Figure 8 is a schematic diagram of the first gate oxide layer provided by the embodiment of the present application, referring to Figure 8 The first gate oxide layer 40 can be formed by using thermal oxidation, chemical vapor deposition and HTO (high temperature oxidation) processes. Figure 9 is a schematic diagram of the first polysilicon layer provided by the embodiment of the present application, referring to Figure 9 After depositing the doped polysilicon material, the polysilicon material at the bottom surface of the gate trench 30, the polysilicon material outside the gate trench 30 and the polysilicon material outside the source trench 70 are removed, and finally the first polysilicon layer 51 covering the sidewall of the gate trench 30 and covering the source trench 70 is formed. Since the source trench 70 has a small width, the first polysilicon layer 51 will fill the source trench 70. Figure 10is a schematic diagram provided by the embodiment of the present application after forming the second gate oxide layer, referring to Figure 10 SiO2 can be deposited by HTO (high temperature oxidation) or chemical vapor deposition process to form a silicon dioxide material layer, and then etching back to remove the silicon dioxide material layer outside the gate trench 30 and the part of the silicon dioxide material layer on the surface of the first polysilicon layer 51, forming the second gate oxide layer 60. Figure 11 is a schematic diagram provided by the embodiment of the present application after forming the second polysilicon layer, referring to Figure 11 , depositing doped polysilicon material, and then etching back to remove the polysilicon material outside the gate trench 30, forming the second polysilicon layer 52. Figure 12 is a schematic diagram provided by the embodiment of the present application after forming the insulating layer, referring to Figure 12 The silicon dioxide can be deposited on the surface of the epitaxial layer 20, and then etched to expose the source trench 70 and part of the second conductive type region 90, forming the insulating layer 110. Referring to Figure 1 and Figure 2 After forming the insulating layer 110, the source metal 120 is formed on the side of the insulating layer 110 away from the substrate 10, the drain metal 130 is formed on the surface of the substrate 10 away from the epitaxial layer 20, and the passivation layer 140 and the PI layer 150 are formed on the surface of the source metal 100.

[0134] The preparation method of the power device described in the embodiment of the present application belongs to the same inventive concept as the power device described in any embodiment of the present application, and has corresponding beneficial effects. The detailed technical details of the embodiment of the present application are described in detail in the power device described in any embodiment of the present application.

[0135] It should be understood that the various forms of flow shown above can be reordered, added or deleted steps. For example, the steps described in the present application can be executed in parallel, sequentially or in different order, as long as the desired results of the technical solutions of the present application can be achieved, which is not limited herein.

[0136] The above specific embodiments do not constitute a limitation on the scope of protection of the present application. Those skilled in the art should understand that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A power device, characterized in that, include: A substrate and an epitaxial layer are stacked sequentially. The surface of the epitaxial layer away from the substrate includes a gate trench; a first gate oxide layer, a polysilicon layer, and a second gate oxide layer are disposed within the gate trench; The first gate oxide layer includes a first sub-part and a second sub-part, the first sub-part covering the sidewall of the gate trench and the second sub-part covering the bottom surface of the gate trench; The second gate oxide layer is disposed on the surface of the second sub-part away from the substrate; the polysilicon layer is disposed on the side of the first gate oxide layer and the second gate oxide layer away from the epitaxial layer, the polysilicon layer covers the second gate oxide layer, and the polysilicon layer covers the first surface of the first sub-part, the first surface of the first sub-part being the surface of the first sub-part away from the sidewall of the gate trench; The polysilicon layer includes a first polysilicon layer and a second polysilicon layer. The first polysilicon layer is disposed on a first surface of the first sub-part. The second gate oxide layer covers the surface of the second sub-part away from the substrate, and the second gate oxide layer covers a portion of the second surface of the first polysilicon layer. The second surface of the first polysilicon layer is the surface of the first polysilicon layer away from the sidewall of the gate trench. The second polysilicon layer covers the second gate oxide layer, and the second polysilicon layer covers the second surface that is not covered by the second gate oxide layer; The second polysilicon layer includes a main body and a protrusion, the protrusion protruding toward the substrate relative to the main body; the second gate oxide layer is located on the surface of the first polysilicon layer, between the protrusion and the main body of the first polysilicon layer and the second polysilicon layer.

2. The power device according to claim 1, characterized in that: The second gate oxide layer extends from the surface of the second sub-section to the second surface of the first polysilicon layer, and the second gate oxide layer covers a portion of the second surface adjacent to the substrate.

3. The power device according to claim 2, characterized in that: Along the direction from the substrate to the epitaxial layer, the size of the region on the second surface of the first polysilicon layer that is not covered by the second gate oxide layer is less than or equal to 0.5 micrometers.

4. The power device according to claim 1, characterized in that: The sum of the thicknesses of the second gate oxide layer and the second sub-part located at the bottom of the gate trench is the first thickness, and the thickness of the first sub-part is the second thickness; The ratio of the first thickness to the second thickness is greater than or equal to 2 and less than or equal to 5.

5. The power device according to claim 4, characterized in that: The thickness of the first gate oxide layer is greater than or equal to 50 nanometers and less than or equal to 60 nanometers; The thickness of the second gate oxide layer is greater than or equal to 50 nanometers and less than or equal to 100 nanometers.

6. The power device according to claim 1, characterized in that: The thickness of the first polycrystalline silicon layer is greater than or equal to 50 nanometers and less than or equal to 100 nanometers.

7. The power device according to claim 1, characterized in that: The first gate oxide layer and the second gate oxide layer are made of the same material.

8. The power device according to claim 1, characterized in that: The surface of the epitaxial layer away from the substrate also includes a source trench, and the first gate oxide layer and the first polysilicon layer are disposed in the source trench; Within the source trench, the first gate oxide layer is disposed between the first polysilicon layer and the epitaxial layer; The surface of the epitaxial layer away from the substrate further includes a first conductivity type region and a second conductivity type region; the second conductivity type region is located on the side of the first conductivity type region away from the substrate, and the first conductivity type region and the second conductivity type region are located between the source trench and the gate trench; An electric field shielding area is provided on the surface of the epitaxial layer within the source trench; The power device also includes an insulating layer, a source metal, and a drain metal; The insulating layer is disposed on the side of the epitaxial layer away from the substrate, and the insulating layer covers the gate trench; the source metal is disposed on the side of the insulating layer away from the substrate, and the second conductivity type region between the source trench and the gate trench is in contact with the source metal; the electric field shielding region is in contact with the source metal; The drain metal is disposed on the side of the substrate away from the epitaxial layer.

9. A power module, characterized in that, It includes a substrate and at least one power device as described in any one of claims 1-8, wherein the substrate is used to carry the power device.

10. A power conversion circuit, characterized in that, The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one power device as described in any one of claims 1-8, wherein the power device is electrically connected to the circuit board.

11. A vehicle, characterized in that, The device includes a load and a power conversion circuit as described in claim 10, the power conversion circuit being used to convert AC power to DC power, convert AC power to AC power, convert DC power to DC power, or convert DC power to AC power and then input it to the load.

12. A method for fabricating a power device, characterized in that, include: An epitaxial layer is formed on one side of the substrate; A gate trench is formed on the surface of the epitaxial layer away from the substrate; A first gate oxide layer, a polysilicon layer, and a second gate oxide layer are formed within the gate trench. The first gate oxide layer includes a first sub-part and a second sub-part, the first sub-part covering the sidewall of the gate trench, and the second sub-part covering the bottom surface of the gate trench. The second gate oxide layer is disposed on the surface of the second sub-part away from the substrate. The polysilicon layer is disposed on the side of the first and second gate oxide layers away from the epitaxial layer, covering the second gate oxide layer, and covering the first surface of the first sub-part, which is the surface of the first sub-part away from the sidewall of the gate trench. A first gate oxide layer, a polysilicon layer, and a second gate oxide layer are formed within the gate trench, including: The first gate oxide layer is formed within the gate trench; A first polysilicon layer is formed within the gate trench; wherein the first polysilicon layer is disposed on the first surface of the first sub-part; A second gate oxide layer is formed within the gate trench; wherein the second gate oxide layer covers the surface of the second sub-part away from the substrate, and the second gate oxide layer covers a portion of the second surface of the first polysilicon layer, the second surface of the first polysilicon layer being the surface of the first polysilicon layer away from the sidewall of the gate trench; A second polysilicon layer is formed within the gate trench; wherein the second polysilicon layer covers the second gate oxide layer, and the second polysilicon layer covers the second surface not covered by the second gate oxide layer; the second polysilicon layer includes a main body portion and a protrusion portion, the protrusion portion protruding relative to the main body portion toward the substrate; the portion of the second gate oxide layer located on the surface of the first polysilicon layer is located between the first polysilicon layer, the protrusion portion of the second polysilicon layer, and the main body portion.

13. The method for fabricating a power device according to claim 12, characterized in that, A second gate oxide layer is formed within the gate trench, comprising: The second gate oxide material layer is formed by chemical vapor deposition or high-temperature oxidation process; The second gate oxide material layer is patterned to form the second gate oxide layer.

14. The method for fabricating a power device according to claim 12, characterized in that, Before forming the gate trench on the surface of the epitaxial layer away from the substrate, the method further includes: A source trench is formed on the surface of the epitaxial layer away from the substrate; While forming the first gate oxide layer in the gate trench, the method also includes: A first gate oxide layer is formed within the source trench; wherein the first gate oxide layer covers the epitaxial layer within the source trench; While forming the first polysilicon layer within the gate trench, the method also includes: The first polysilicon layer is formed within the source trench.

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