An Adaptive Superjunction LDMOS Structure

Abstract

The present invention discloses an adaptive super junction LDMOS structure, comprising: a first conductive type substrate, a second conductive type epitaxial layer is arranged above the first conductive type substrate, a first conductive type body region with a preset junction depth is arranged on the surface of the second conductive type epitaxial layer, and a tangent first conductive type back gate injection region and a second conductive type source injection region are arranged on the surface of the first conductive type body region; a super junction region is arranged in the upper surface of the second conductive type epitaxial layer, and is located on the right side of the first conductive type body region; in the super junction region, m columns of first conductive type super junction regions and second conductive type super junction regions are arranged, which are alternately distributed one by one along the longitudinal direction of the super junction region. The present invention can adaptively modify the state of the super junction structure as the external voltage changes, and can not only improve the performance of the LDMOS device through the auxiliary depletion function of the super junction structure, but also can realize a lower specific on-resistance of the LDMOS by utilizing the inversion of the gate to the super junction region while ensuring the withstand voltage of the device.

Description

Technical Field

[0001] The invention belongs to the fields of electronic components, semiconductors and integrated circuits, and particularly relates to an adaptive super junction LDMOS structure. Background Art

[0002] LDMOS, or Lateral Diffused Metal-Oxide-Semiconductor Field-Effect Transistor, is a semiconductor device widely used in motor drives, switching power supplies, and various power conversions, and is particularly suitable for high-power, high-efficiency applications. Figure 1 The LDMOS device shown controls the switch passing through the device by controlling the gate-source potential difference of the semiconductor device, and uses the built-in drift region to withstand high voltage. However, high voltage requires a low-concentration drift region, and too low impurity concentration in the drift region will lead to an increase in the specific on-resistance and thus increase the conduction loss of the LDMOS. Therefore, a superjunction structure is proposed as an effective technical solution to the above-mentioned problems, which is a milestone invention of power semiconductor devices. Although the superjunction structure works well for vertical devices, for lateral devices, the superjunction structure is restricted by the shape of the voltage-resistant layer and it is difficult to exert its maximum capacity. Moreover, whether the traditional superjunction LDMOS is in the on state or the off state, the superjunction structure is fixed and cannot change with the change of the external voltage. Therefore, there is a limit value and it cannot adapt to the change of the external voltage, which limits its application. Summary of the invention

[0003] In order to solve the above technical problems, the present invention proposes an adaptive super junction LDMOS structure, which can adaptively modify the state of the super junction structure as the external voltage changes. It can not only improve the performance of the LDMOS device through the auxiliary depletion function of the super junction structure, but also achieve a lower specific on-resistance of the LDMOS by utilizing the inversion of the gate to the super junction region while ensuring the withstand voltage of the device.

[0004] The main technical solutions adopted in the present invention are:

[0005] An adaptive super junction LDMOS structure, comprising: a first conductive type substrate, a second conductive type epitaxial layer is arranged above the first conductive type substrate, a first conductive type body region with a preset junction depth is arranged on the surface of the second conductive type epitaxial layer, and a tangent first conductive type back gate injection region and a second conductive type source injection region are arranged on the surface of the first conductive type body region;

[0006] A super junction region is provided in the upper surface of the second conductive type epitaxial layer and is located on the right side of the first conductive type body region;

[0007] In the super junction region, m columns of first conductivity type super junction regions and second conductivity type super junction regions are arranged alternately distributed one by one along the longitudinal direction of the super junction region.

[0008] Preferably, a longitudinal cross-sectional width of the first conductive type super junction region is the same as a longitudinal cross-sectional width of the second conductive type super junction region.

[0009] Preferably, a field oxide layer is provided on the upper surface of the second conductive type epitaxial layer, a gate oxide layer I is provided above the surface between the right side of the second conductive type source injection region and the right side of the first conductive type body region, and a gate oxide layer II is provided above the surface in the area above the first conductive type super junction region in the super junction region.

[0010] Preferably, a longitudinal cross-sectional width of the first conductive type super junction region is greater than a longitudinal cross-sectional width of the second conductive type super junction region.

[0011] Preferably, a field oxide layer is provided on the upper surface of the second conductive type epitaxial layer, a gate oxide layer I is provided above the surface between the right side of the second conductive type source injection region and the right side of the first conductive type body region, and a gate oxide layer II is provided above the surface in the area above the super junction region.

[0012] Preferably, gate polysilicon is formed on both the gate oxide layer I and the gate oxide layer II, and the gate polysilicon on the gate oxide layer II is extended laterally to connect with the gate polysilicon on the gate oxide layer I.

[0013] Preferably, the junction depths of the first conductivity type super junction region and the second conductivity type super junction region in the same layer are the same.

[0014] Preferably, a second conductivity type drain implantation region is provided on the surface of the second conductivity type epitaxial layer at the right side of the super junction region.

[0015] Preferably, it also includes source metal and drain metal, the source metal passes through the field oxide layer to contact the first conductivity type back gate injection region and the second conductivity type source injection region, and the drain metal passes through the field oxide layer to contact the second conductivity type drain injection region.

[0016] Preferably, the first conductivity type is P type, and the second conductivity type is N type; or, the first conductivity type is N type, and the second conductivity type is P type.

[0017] Beneficial effects: The present invention provides an adaptive super junction LDMOS structure, which has the following advantages compared with the prior art:

[0018] (1) The present invention arranges the superjunction structure in two dimensions in the drift region, so that the voltage-resistant layer of the device produces a superjunction effect in the lateral direction, and utilizes the superjunction structure NPNP to deplete two by two, thereby enhancing the depletion degree of the region, thereby greatly improving the voltage-resistant performance of the device;

[0019] (2) The present invention arranges a gate oxide layer of a certain thickness on the super junction structure and connects it to the gate polysilicon, so that when the device is turned on, inversion occurs in the first conductive type region of the super junction to form multiple channels, thereby converting the original super junction structure into a semiconductor structure, thereby obtaining a lower specific on-resistance and achieving lower conduction loss. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 This is a diagram of the traditional super junction LDMOS structure;

[0021] Figure 2 The structure diagram of the adaptive super junction LDMOS of Example 1;

[0022] Figure 3 is a schematic diagram of the current path of the device of Example 1 when in the on state;

[0023] Figure 4 The structure diagram of the adaptive super junction LDMOS of Example 2;

[0024] In the figure: P-type substrate 100, N-type epitaxial layer 200, P-type body region 300, P+ back gate injection region 310, N+ source injection region 320, super junction region 400, P-type super junction region 410, N-type super junction region 420, N+ drain injection region 500, field oxide layer 600, gate oxide layer I 610, gate oxide layer II 620, source metal 710, drain metal 720, gate polysilicon 800. DETAILED DESCRIPTION

[0025] In order to enable those skilled in the art to better understand the technical solutions in this application, the technical solutions in the embodiments of this application are clearly and completely described below. Obviously, the described embodiments are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of this application.

[0026] Embodiment 1, an adaptive super junction LDMOS structure, such as Figure 2 As shown, in this embodiment 1, the first conductivity type is P type, the second conductivity type is N type, and the specific structure includes:

[0027] P-type substrate 100;

[0028] An N-type epitaxial layer 200 is disposed above the P-type substrate 100;

[0029] A P-type body region 300 with a preset junction depth is disposed on the surface of the N-type epitaxial layer 200;

[0030] A tangent P+ back gate injection region 310 and an N+ source injection region 320 are arranged on the surface of the P-type body region 300, and the P+ back gate injection region 310 is located on the left side of the N+ source injection region 320;

[0031] A super junction region 400 is provided on the surface of the N-type epitaxial layer 200 and is located on the right side of the P-type body region 300;

[0032] In the super junction region 400 , m columns of P-type super junction regions 410 and columns of N-type super junction regions 420 are arranged alternately distributed along the longitudinal direction of the super junction region 400 , and the longitudinal cross-sectional width of the P-type super junction region 410 is equal to the longitudinal cross-sectional width of the N-type super junction region 420 .

[0033] In the present invention, the number of columns m is determined according to the actual size of the device.

[0034] In the first embodiment, the junction depths of the P-type super junction region and the N-type super junction region in the same layer are the same.

[0035] An N+ drain implantation region 500 is disposed on the surface of the N-type epitaxial layer 200 at the right side of the super junction region.

[0036] A field oxide layer 600 is arranged above the upper surface of the N-type epitaxial layer 200, the field oxide layer above the surface between the right side of the N+ source injection region 320 and the right side of the P-type body region 300 is set as gate oxide layer I 610, and the field oxide layer in the area above the P-type super junction region in the super junction region is gate oxide layer II 620. At this time, the area above the N-type super junction region in the super junction region 400 is still the field oxide layer 600.

[0037] The source metal 710 passes through the field oxide layer 600 and contacts the P+ back gate implantation region 310 and the N+ source implantation region 320 , and the drain metal 720 passes through the field oxide layer 600 and contacts the N+ drain implantation region 500 ;

[0038] Gate polysilicon 800 is formed on both gate oxide layer I 610 and gate oxide layer II 620 , and gate polysilicon 800 on gate oxide layer II 620 is extended laterally to connect with gate polysilicon 800 on gate oxide layer I 610 .

[0039] The working principle of this embodiment 1 is as follows:

[0040] When the gate potential of the LDMOS device is 0, the device is in the off state, and the high voltage of the drain will be borne entirely by the N-type drift region (i.e., the N-type epitaxial layer). When the voltage comes, the super junction regions set by the device will be depleted PNPN in pairs, thereby enhancing the degree of depletion in the region. Since the gate at 0 potential has an accumulation effect, it can also be depleted when the concentration of the P-type super junction region 410 is lower, so the same voltage resistance level as the traditional super junction LDMOS can be obtained, and at the same time, the concentration of the P-type super junction region 410 of the structure can be reduced. The reduction in the concentration of the P-type super junction region 410 can increase the channel concentration of the device in the on state, thereby reducing the value of the on-resistance.

[0041] When the gate potential of the LDMOS device is high, the device is in the on state. Due to the change of external voltage, the P-type super junction region will undergo surface inversion to form several N-type channels, such as Figure 3 As shown, the N-type channel on the surface of the P-type super junction region will be connected to the N-type super junction region, thereby increasing several electron current paths. Compared with the traditional super junction LDMOS, the super junction structure at this time becomes a semiconductor, which can further reduce the device's specific on-resistance and conduction loss, and greatly improve the device's conductive performance.

[0042] An adaptive superjunction LDMOS structure, such as Figure 4 As shown, in this embodiment 2, the first conductivity type is P type, and the second conductivity type is N type. The specific structure is different from the embodiment in that: the longitudinal cross-sectional width of the P type super junction region 410 is greater than the longitudinal cross-sectional width of the N type super junction region 420. A field oxide layer 600 is arranged above the upper surface of the N type epitaxial layer 200, and the field oxide layer above the surface between the right side of the N+ source injection region 320 and the right side of the P type body region 300 is a gate oxide layer I 610. The field oxide layers in the region above the super junction region are all gate oxide layers II 620. Gate polysilicon 800 is fabricated above both gate oxide layers I 610 and gate oxide layers II 620, and the gate polysilicon 800 above the gate oxide layer II 620 is extended laterally and connected to the gate polysilicon 800 above the gate oxide layer I 610. The rest of the structure is the same as that of embodiment 1.

[0043] The working principle of this embodiment 2 is roughly the same as that of embodiment 1, except that: when the device is in the off state, the super junction regions PNPN are mutually depleted, and since the N-type super junction region 420 accounts for a smaller proportion, an N-type super junction region with a higher concentration than that of embodiment 1 can be used. In this way, when the voltage is in the off state, the N-type super junction region 420 can be completely depleted, and the device can still maintain the same voltage resistance level as the traditional super junction, and the resistance of the N-type super junction region can be lower. Although the increase in the proportion of the P-type super junction region may not be completely depleted, the full depletion of the P-type super junction region 410 can be achieved by further reducing the concentration of the P-type super junction region. When the device is in the on state, since the P-type super junction region has a lower concentration and a larger proportion than that of embodiment 1, under the same gate voltage, the P-type super junction region 410 will be more severely inverted, thereby generating a lower resistance and wider N-type channel in the on state, thereby further reducing the specific on-resistance while maintaining the same voltage resistance.

[0044] The structure proposed by the present invention can be realized by various other processes or substrates in addition to the embodiments. In addition, when the first conductivity type is N type, the second conductivity type is P type.

[0045] In the present invention, the doping concentration of each doping region can be selectively designed by those skilled in the art according to actual needs based on the technical inspiration of this application.

[0046] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. An adaptive super junction LDMOS structure, characterized in that: include: A first conductive type substrate, a second conductive type epitaxial layer is arranged above the first conductive type substrate, a first conductive type body region with a preset junction depth is arranged on the surface of the second conductive type epitaxial layer, and a tangent first conductive type back gate injection region and a second conductive type source injection region are arranged on the surface of the first conductive type body region; A super junction region (400) is provided in the upper surface of the second conductive type epitaxial layer and is located on the right side of the first conductive type body region; In the super junction region (400), m columns of first conductivity type super junction regions and second conductivity type super junction regions are arranged alternately distributed one by one along the longitudinal direction of the super junction region (400); A field oxide layer (600) is arranged on the upper surface of the second conductive type epitaxial layer, a gate oxide layer I (610) is arranged above the surface between the right side of the second conductive type source injection region and the right side of the first conductive type body region, and a gate oxide layer II (620) is arranged above the surface in the region above the first conductive type super junction region in the super junction region (400), or both surfaces in the region above the super junction region (400) are arranged above the gate oxide layer II (620); Gate polysilicon (800) is fabricated on both the gate oxide layer I and the gate oxide layer II, and the gate polysilicon on the gate oxide layer II is extended laterally to connect with the gate polysilicon (800) on the gate oxide layer I.

2. The adaptive super junction LDMOS structure according to claim 1, characterized in that: When a gate oxide layer II (620) is provided above the surface in the region above the first conductive type super junction region in the super junction region (400), the longitudinal cross-sectional width of the first conductive type super junction region is the same as the longitudinal cross-sectional width of the second conductive type super junction region.

3. The adaptive super junction LDMOS structure according to claim 1, characterized in that: When the surface above the area above the super junction region (400) is provided with gate oxide layer II (620), the longitudinal cross-sectional width of the first conductive type super junction region is greater than the longitudinal cross-sectional width of the second conductive type super junction region.

4. The adaptive superjunction LDMOS structure according to any one of claims 1 to 3, characterized in that: The junction depths of the first conductivity type super junction region and the second conductivity type super junction region in the same layer are the same.

5. The adaptive superjunction LDMOS structure according to any one of claims 1 to 3, characterized in that: A second conductivity type drain injection region is arranged on the surface of the second conductivity type epitaxial layer on the right side of the super junction region (400).

6. The adaptive super junction LDMOS structure according to any one of claims 1 to 3, characterized in that: It also includes a source metal (710) and a drain metal (720), wherein the source metal (710) passes through the field oxide layer (600) to contact the first conductive type back gate injection region and the second conductive type source injection region, and the drain metal (720) passes through the field oxide layer (600) to contact the second conductive type drain injection region.

7. The adaptive superjunction LDMOS structure according to any one of claims 1 to 3, characterized in that: The first conductivity type is P type, and the second conductivity type is N type; or, the first conductivity type is N type, and the second conductivity type is P type.

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