A low leakage sample and hold circuit

Abstract

The present invention belongs to the field of analog integrated circuits, specifically a low-leakage sample-and-hold circuit. The present invention includes a low-leakage switch S1, a sampling capacitor C1, an output-stage operational amplifier, and a feedback switch S2. By reusing the output-stage operational amplifier, the present invention clamps the source and drain of the MOS transistor in the low-leakage switch S1 to the same voltage, thereby reducing leakage between the source and drain of the MOS transistor due to subthreshold conduction of the transistor. Furthermore, a low-leakage switch structure is constructed using isolated MOS transistors, where the substrate potential is no longer connected to ground, eliminating the leakage path from the sampling capacitor to ground, and further reducing leakage caused by the parasitic diode between the source and drain in the low-leakage switch S1 structure.

Description

Technical Field

[0001] The present invention belongs to the field of analog integrated circuits, and in particular relates to a low leakage sampling and holding circuit. Background Art

[0002] The sample-and-hold circuit is an important module in the field of analog integrated circuits. The sample-and-hold circuit samples the voltage information output by the previous circuit and holds it on a capacitor. A typical sample-and-hold circuit (see attached) Figure 1 The CMOS (Figure 2) includes a sampling switch and a sampling capacitor. The sampling switch is typically implemented using a MOS transistor. Due to the inherent characteristics of MOS transistors, leakage occurs when the switch is turned off, causing charge to leak from the holding capacitor and change the voltage information.

[0003] There are two main ways for the capacitor to leak charge during the hold phase of the sample-and-hold circuit: one is the subthreshold conductivity of the switch MOS tube in the off state, which causes the source and drain of the MOS tube to form a charge discharge path; the other is the reverse conduction current in the parasitic diode between the source, drain and substrate of the switch MOS tube, which causes the charge to be discharged through the substrate. Commonly used non-isolated MOS tubes of the same type can only be made on the same substrate (such as the attached Figure 2 As shown in the figure, the substrates of the same type of MOS transistors are all connected to the same potential. Taking the NMOS transistor as an example, the NMOS transistors are made on the same P-sub substrate, and the P-sub substrate is usually connected to the ground potential. At this time, a parasitic diode is generated between the NMOS source and drain and the substrate end. Since the NMOS source and drain potential is greater than or equal to the ground potential, the parasitic diode will not conduct in the forward direction. However, since the diode has a reverse conduction characteristic (as shown in the figure), the NMOS transistors are made on the same P-sub substrate, and the P-sub substrate is usually connected to the ground potential. Figure 3 As shown in FIG, as the reverse voltage of the diode increases, there will be a small reverse conduction current, which will cause the charge of the sampling capacitor to leak, resulting in a decrease in the holding time of the sample-and-hold circuit.

[0004] To reduce leakage in the sample-and-hold circuit during the hold phase, the above two issues need to be addressed. For sample-and-hold circuits requiring a longer hold time, this leakage phenomenon causes the voltage held on the capacitor to drop, shortening the hold time. In a typical sample-and-hold circuit structure, the solution is to use a larger capacitor. However, charging a large capacitor requires a stronger driving capability from the preceding circuitry, resulting in increased circuit current consumption. Furthermore, a large capacitor increases the circuit area. Summary of the Invention

[0005] In response to the above-mentioned problems and to solve the charge leakage problem of existing sample-and-hold circuits, the present invention provides a low-leakage sample-and-hold circuit, proposes a low-leakage switch, and reuses the output-stage operational amplifier as a voltage-clamping operational amplifier to reduce charge leakage on the capacitor.

[0006] A low leakage sampling and holding circuit, comprising: a low leakage switch S1, a sampling capacitor C1, an output stage operational amplifier and a feedback switch S2 (as shown in the attached Figure 4 shown).

[0007] The first end of the low leakage switch S1 is used as the input end (connected to V in ), the second end is connected to the upper plate of the sampling capacitor C1 and the positive input terminal of the output stage operational amplifier; the lower plate of the sampling capacitor C1 is connected to the ground; the output terminal of the output stage operational amplifier is connected to the output terminal of the sampling and holding circuit (V out ), and the output terminal of the output stage operational amplifier is connected to its own negative input terminal, forming a unity gain negative feedback loop; the second terminal of the feedback switch S2 is connected to the output terminal and the negative input terminal of the output stage operational amplifier; the first terminal of the feedback switch S2 is connected to the low leakage switch S1, and the gate of the feedback switch S2 is connected to the control signal K2.

[0008] The low leakage switch S1 is composed of N MOS tubes M1...M N The MOS tube M1 substrate is connected to the source end of M1, and the MOS tube M2 substrate is connected to the drain end of M2. (2m+1) The substrate is connected to its own source terminal, and the even-numbered MOS tube M (2m) The substrate is connected to its own drain terminal (m = 0, 1, 2 ...) to achieve the opposite direction of the substrate connection between two adjacent switch MOS tubes; as N increases, the holding time of the sample and hold circuit becomes longer. MOS tubes M1 ... M N The gates of the feedback switches S2 are connected to the control signal K1. The first end of the feedback switch S2 is connected to the middle node Y of the series connection of adjacent MOS transistors in the low leakage switch S1. The N MOS transistors have a total of N-1 middle nodes Y.

[0009] Furthermore, the N MOS transistors of the low leakage switch S1 are all PMOS transistors, or are all NMOS transistors.

[0010] Furthermore, the MOS transistor in the low leakage switch S1 is an isolated MOS transistor. The substrates of the isolated MOS transistors are isolated from each other, and the substrates can be connected to different potentials (such as the attached Figure 5 In the low-leakage switch S1, the two adjacent MOS tube substrates are connected in opposite directions. At this time, the charge on the capacitor needs to leak through the parasitic diodes connected in opposite directions. This connection method can prevent leakage current from occurring at both ends of the switch due to the forward conduction of the diodes.

[0011] The control logic of the above low leakage sampling and holding circuit (see attached Figure 6 shown):

[0012] In the capacitor sampling stage, the control signal K1 controls the low leakage switch S1 to turn on; the control signal K2 controls the feedback switch S2 to turn off, and the sampling capacitor C1 is connected to the input end through the low leakage switch S1 to sample the input end voltage and store the voltage on the capacitor.

[0013] In the capacitor holding stage, the control signal K1 controls the low-leakage switch S1 to be turned off; the control signal K2 controls the feedback switch S2 to be turned on, and the output-stage operational amplifier outputs the voltage on the sampling capacitor C1 to the output end in the form of unity-gain feedback; at the same time, the feedback switch S2 is turned on to feed the sampled voltage back to the low-leakage switch S1.

[0014] By multiplexing the output-stage operational amplifier, the present invention clamps the source and drain voltages of switch S1 to the same voltage, reducing leakage caused by subthreshold conduction between the source and drain of the MOS transistor. This also further reduces leakage caused by the parasitic diode between the source and drain in the aforementioned low-leakage switch structure.

[0015] The key to increasing the hold time in the sample-and-hold circuit structure proposed in the present invention is to reduce the leakage path of node X on the upper plate of capacitor C1. Node X is connected to the positive input of an operational amplifier, a high-impedance node that has no effect on node X leakage. The main leakage paths are subthreshold conduction between the source and drain of the MOS transistor in switch S1 and reverse leakage of the parasitic diode. Furthermore, the present invention proposes a switch voltage clamping technique based on an output-stage operational amplifier. During the hold phase, the operational amplifier outputs the voltage held on capacitor C1 through unity-gain negative feedback. Furthermore, because the output-stage operational amplifier is designed to have drive capability, it can meet the requirement for fast voltage clamping across the switch. This operational amplifier can be reused as a voltage-clamping operational amplifier, eliminating one operational amplifier compared to existing designs. The operational amplifier clamps node X and the output terminal to the same voltage; at this time, S2 is turned on, making the voltage at node Y equal to the voltage at the output terminal. Therefore, the output stage operational amplifier can be used as a clamping operational amplifier for node X and node Y, that is, the voltage at node Y is equal to that at node X. Therefore, the voltage difference between the source and drain of the MOS tube in the low leakage switch S1 is 0, reducing the subthreshold conduction between the source and drain of the MOS tube in the low leakage switch S1. At the same time, based on the above-mentioned switch voltage clamping technology, the voltage difference between the source and drain of the MOS tube is 0, that is, the voltage difference between the two ends of the parasitic diode of the MOS tube is zero, as shown in the attached figure. Figure 3 As shown, the parasitic diode current is 0 at this time, further reducing the leakage current caused by the parasitic diode.

[0016] In summary, the present invention proposes a low leakage switch and reuses the output stage operational amplifier as a voltage clamping operational amplifier to reduce charge leakage on the capacitor; ultimately, the problems of the existing sample-and-hold circuit are effectively solved. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 This is a typical sample-and-hold circuit schematic.

[0018] Figure 2 It is a cross-sectional view of a non-isolated NMOS tube.

[0019] Figure 3 It is a schematic diagram of the IV characteristic curve of the parasitic diode of the MOS tube.

[0020] Figure 4 It is a circuit diagram of the present invention.

[0021] Figure 5 FIG. 4 is a cross-sectional view of an isolated NMOS used in the embodiment.

[0022] Figure 6 This is a control logic timing diagram of the low leakage sampling and holding circuit of the present invention.

[0023] Figure 7 2 is a schematic diagram of a sample-and-hold circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0024] The working principle of the present invention will be further described in detail below with reference to the accompanying drawings.

[0025] Attachment Figure 7 This is a low-leakage sample-and-hold circuit according to an embodiment of the present invention. The low-leakage switch S1 consists of isolated NMOS transistors M1 and M2. The feedback switch S2 consists of an NMOS transistor M3. The substrate of M1 is connected to the source of M1, and the substrate of M2 is connected to the drain of M2. The source of M3 is connected to the drain of M1 and the source of M2 (node Y). The gates of M1 and M2 are connected to the control signal K1, and the gate of M3 is connected to the control signal K2.

[0026] The control logic is:

[0027] During the capacitor sampling phase, when control signal K1 is high, low-leakage switch S1 is turned on; when control signal K2 is low, M3 is turned off. The sampling capacitor is connected to the input terminal via C1 through low-leakage switch S1, sampling the input terminal voltage and storing it on the capacitor.

[0028] In the capacitor holding stage, the control signal K1 is low, and the low leakage switch S1 is turned off; the control signal K2 is high, and M3 is turned on.

[0029] The above embodiments demonstrate that the present invention, by multiplexing the output-stage operational amplifier, clamps the source and drain voltages of switch M2 to the same voltage, thereby reducing leakage caused by subthreshold conduction between the source and drain of the MOS transistor. Furthermore, the low-leakage switch structure constructed using isolated MOS transistors eliminates the leakage path from the sampling capacitor to ground, reducing the parasitic diode leakage of the MOS transistor, and further reducing the leakage caused by the parasitic diode between the source and drain in the above-mentioned low-leakage switch structure.

Claims

1. A low leakage sample-and-hold circuit, characterized in that: It includes a low leakage switch S1, a sampling capacitor C1, an output stage operational amplifier and a feedback switch S2; The first end of the low leakage switch S1 serves as an input end, and the second end is connected to the upper plate of the sampling capacitor C1 and the positive input end of the output stage operational amplifier; the lower plate of the sampling capacitor C1 is connected to the ground; the output end of the output stage operational amplifier is connected to the output end of the sample and hold circuit, and the output end of the output stage operational amplifier is connected to its own negative input end, forming a unity gain negative feedback loop; the second end of the feedback switch S2 is connected to the output end and the negative input end of the output stage operational amplifier; the first end of the feedback switch S2 is connected to the low leakage switch S1, and the gate of the feedback switch S2 is connected to the control signal K2; The low leakage switch S1 is composed of N MOS tubes M1...M N The MOS tube M1 substrate is connected to the source end of M1, and the MOS tube M2 substrate is connected to the drain end of M2. (2m+1) The substrate is connected to its own source terminal, and the even-numbered MOS tube M (2m) The substrate is connected to its own drain end to achieve opposite substrate connection directions between two adjacent switch MOS tubes, m = 0, 1, 2..., M1...M N The gates are all connected to the control signal K1; the first end of the feedback switch S2 is connected to the middle node Y of the adjacent MOS transistors in series in the low leakage switch S1, and the N MOS transistors have a total of N-1 middle nodes Y.

2. The low leakage sample-and-hold circuit according to claim 1, wherein: The N MOS transistors of the low leakage switch S1 are all PMOS transistors, or are all NMOS transistors.

3. The low leakage sample-and-hold circuit according to claim 1, wherein: The MOS transistor in the low leakage switch S1 is an isolation MOS transistor.

4. The low leakage sample and hold circuit according to claim 1, wherein: The control logic is: In the capacitor sampling stage: at this time, the control signal K1 controls the low leakage switch S1 to turn on; the control signal K2 controls the feedback switch S2 to turn off, and the sampling capacitor C1 is connected to the input end through the low leakage switch S1, sampling the input end voltage and storing the voltage on the capacitor; In the capacitor holding stage: at this time, the control signal K1 controls the low leakage switch S1 to be turned off; the control signal K2 controls the feedback switch S2 to be turned on, and the output stage operational amplifier outputs the voltage on the sampling capacitor C1 to the output end in the form of unity gain feedback; at the same time, the feedback switch S2 is turned on to feed the sampled voltage back to the low leakage switch S1.

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