A method and apparatus for providing a clock signal in a data link

Abstract

The embodiment of the present application provides a method and device for providing a clock signal in a data link, the method comprising: in each clock domain of a plurality of clock domains of the data link, generating a reset pulse signal based on an input synchronization reference signal and an input clock signal, generating an output synchronization reference signal based on the input synchronization reference signal and the input clock signal, and generating an output clock signal based on the input clock signal; resetting the output synchronization reference signal and the output clock signal through the reset pulse signal, and synchronously generating the reset output synchronization reference signal and the reset output clock signal at a next rising edge of the input clock signal after the reset pulse signal ends, which are transmitted into a next clock domain through the same time delay as input synchronization reference signals and input clock signals of the next clock domain, so that the load of the synchronization reference signal is reduced, the uncertainty of time delay between different clock domains is reduced, and the problems of misfire and metastability are avoided.

Description

Technical Field

[0001] This application relates to the field of communications, and more specifically, to a method and apparatus for providing clock signals in a data link. Background Technology

[0002] In recent years, 5G communication has developed rapidly. Technologies such as massive MIMO and GPS Pulse Per Second (GPS PPS) timing have improved system capacity and clock accuracy. However, this has also placed higher demands on the accuracy of data link latency in baseband and radio frequency transceiver systems.

[0003] Traditional methods for clock phase initialization in multi-clock domains employ asynchronous reset and synchronous release to ensure a clear release sequence for the reset signal. This reduces metastability issues caused by the reset signal release and effectively captures the reset signal, ensuring the reset function is not lost even with a narrow reset pulse. However, this approach has the following drawbacks: First, in large circuits with significant distances between different clock domains, the reset signal becomes heavily loaded, requiring extensive buffering to maintain signal quality. This causes the delay in the reset signal reaching different clock domains to vary considerably with process voltage temperature (PVT), affecting the accuracy of the reset signal's arrival at each clock domain. Second, there is uncertainty in the reset signal delay between different clock domains. Third, metastability still exists during reset release, severely impacting the reset signal's delay accuracy.

[0004] No solution has yet been proposed to address the uncertainty of latency between different clock domains in related technologies. Summary of the Invention

[0005] This application provides a method and apparatus for providing a clock signal in a data link, so as to at least solve the problem in the related art that the uncertainty of the time delay between different clock domains leads to a large load and mis-clocking of the reset signal, and that metastability still exists when the reset is released.

[0006] According to one embodiment of this application, a method for providing a clock signal in a data link is provided, the method comprising:

[0007] In each of the multiple clock domains of the data link, a reset pulse signal is generated based on the input synchronization reference signal and the input clock signal; an output synchronization reference signal is generated based on the input synchronization reference signal and the input clock signal; and an output clock signal is generated based on the input clock signal.

[0008] The output synchronization reference signal and the output clock signal are reset by the reset pulse signal. After the reset pulse signal ends, the next rising edge of the input clock signal synchronously generates the reset output synchronization reference signal and the reset output clock signal. The reset output synchronization reference signal and the reset output clock signal are transmitted to the next clock domain of the data link after the same time delay, and serve as the input synchronization reference signal and the input clock signal of the next clock domain.

[0009] According to another embodiment of this application, an apparatus for providing a clock signal in a data link is also provided. The apparatus includes: a reset pulse signal generation circuit, an output synchronization reference signal generation circuit, and an output clock signal generation circuit, wherein...

[0010] The reset pulse signal generation circuit is used to generate a reset pulse signal based on an input synchronization reference signal and an input clock signal in each of the multiple clock domains of the data link, generate an output synchronization reference signal based on the input synchronization reference signal and the input clock signal, and generate an output clock signal based on the input clock signal; and input the reset pulse signal to the output synchronization reference signal generation circuit and the output clock signal generation circuit to reset the output synchronization reference signal and the output clock signal.

[0011] The output synchronization reference signal generation circuit is used to synchronously generate the reset output synchronization reference signal at the next rising edge of the input clock signal after the reset pulse signal ends.

[0012] The output clock signal generation circuit is used to synchronously generate a reset output clock signal at the next rising edge of the input clock signal after the reset pulse signal ends. The reset output synchronization reference signal and the reset output clock signal are transmitted to the next clock domain of the data link after the same second time delay, serving as the input synchronization reference signal and input clock signal of the next clock domain.

[0013] According to yet another embodiment of this application, a computer-readable storage medium is also provided, wherein a computer program is stored therein, wherein the computer program is configured to perform the steps in any of the above method embodiments when it is run.

[0014] According to yet another embodiment of this application, an electronic device is also provided, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.

[0015] In this embodiment, in each of the multiple clock domains of the data link, a reset pulse signal is generated based on the input synchronization reference signal and the input clock signal; an output synchronization reference signal is generated based on the input synchronization reference signal and the input clock signal; and an output clock signal is generated based on the input clock signal. The output synchronization reference signal and the output clock signal are reset by the reset pulse signal. The reset output synchronization reference signal and the reset output clock signal are synchronously generated on the next rising edge of the input clock signal after the reset pulse signal ends. The reset output synchronization reference signal and the reset output clock signal are transmitted to the next clock domain after the same time delay, serving as the input synchronization reference signal and the input clock signal for the next clock domain. This solves the problems of high load on the reset signal and inconsistency in the transmission path, which lead to uncertainty in the time delay between different clock domains and cause timing errors and metastability in related technologies. Because each clock domain uses sequential synchronization, each clock domain has clear phase information, reducing the load on the synchronization reference signal and thus reducing the uncertainty in the time delay between different clock domains. The method of transmitting the clock signal and the synchronization reference signal together avoids timing errors and reduces the probability of metastability. Attached Figure Description

[0016] Figure 1 This is a system block diagram of a digital-to-analog converter in related technologies;

[0017] Figure 2 This is a flowchart of a method for providing a clock signal in a data link according to an embodiment of this application;

[0018] Figure 3 This is a timing diagram of high-precision time delay according to this embodiment;

[0019] Figure 4 The circuit structure of high-precision time delay according to this embodiment. Figure 1 ;

[0020] Figure 5 This is a schematic diagram of clock frequency deviation compensation according to this embodiment. Figure 1 ;

[0021] Figure 6 This is a circuit diagram of the buffer according to this embodiment;

[0022] Figure 7 The circuit structure for generating a multi-phase clock according to this embodiment. Figure 1 ;

[0023] Figure 8 The circuit structure for generating a multi-phase clock according to this embodiment. Figure 2 ;

[0024] Figure 9The circuit structure for generating the reset pulse according to this embodiment. Figure 1 ;

[0025] Figure 10 The circuit structure for generating the reset pulse according to this embodiment. Figure 2 , ;

[0026] Figure 11 This is a schematic diagram of clock frequency deviation compensation according to this embodiment. Figure 2 ;

[0027] Figure 12 The circuit structure of high-precision time delay according to this embodiment. Figure 2 ;

[0028] Figure 13 The circuit structure of high-precision time delay according to this embodiment. Figure 3 ;

[0029] Figure 14 This is a block diagram of an apparatus for providing a clock signal in a data link according to an embodiment of this application. Detailed Implementation

[0030] The embodiments of this application will be described in detail below with reference to the accompanying drawings and examples.

[0031] It should be noted that the terms "first," "second," etc., in the specification, claims, and drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0032] Figure 1 This is a system block diagram of a digital-to-analog converter in related technologies, such as... Figure 1As shown, a digital-to-analog converter (DAC) includes a data path, a clock path, and a DAC core. The data path includes an interface circuit, a digital data path, a decoder, a serializer, and a switch driver. The clock path includes a clock receiver, a clock divider, and a driver. The DAC core includes multiple DAC core slices. In the interface circuit, 16 low-speed data streams operate at a frequency of Fs / 16 and are transmitted in parallel to the digital data link. The digital data link mainly consists of four random access memories (RAMs). The 16 data streams are divided into four groups and written into the four RAMs at an Fs / 16 clock frequency. A four-phase Fs / 4 clock frequency reads the four data streams from the four RAMs and inputs them into the decoder. The decoder performs code conversion, and the serializer uses double-edge sampling to merge the four-phase data into two-phase data. Then, the switch starter merges the two-phase data into one-phase data. Throughout the parallel-to-serial conversion process, modules in different data links operate at different clock frequencies, and the clock phases of multiple data streams within the same module are also different. Ultimately, data transmission and delivery are completed under the control of multiple clock frequency domains. Therefore, the accuracy of the clock frequency and clock phase in different clock domains determines the latency accuracy of the data link.

[0033] This embodiment provides a method for providing clock signals in a data link. Figure 2 This is a flowchart of a method for providing a clock signal in a data link according to an embodiment of this application, such as... Figure 2 As shown, the process includes the following steps:

[0034] Step S202: In each of the multiple clock domains of the data link, a reset pulse signal is generated based on the input synchronization reference signal and the input clock signal; an output synchronization reference signal is generated based on the input synchronization reference signal and the input clock signal; and an output clock signal is generated based on the input clock signal.

[0035] In this embodiment, the reset pulse signal is a pulse signal with a preset width, which can be flexibly set according to actual needs.

[0036] Step S204: The output synchronization reference signal and the output clock signal are reset by a reset pulse signal. After the reset pulse signal ends, the next rising edge of the input clock signal synchronously generates the reset output synchronization reference signal and the reset output clock signal. The reset output synchronization reference signal and the reset output clock signal are transmitted to the next clock domain of the data link after the same time delay, and serve as the input synchronization reference signal and the input clock signal of the next clock domain.

[0037] Through steps S202 to S204 above, the problems of time delay uncertainty between different clock domains caused by the large load of the reset signal and the inconsistency of the transmission path in related technologies can be solved, thus preventing mis-synchronization and metastability. Since each clock domain is synchronized sequentially, each clock domain has clear phase information, reducing the load of the synchronization reference signal and thereby reducing the time delay uncertainty between different clock domains. Because the clock signal and synchronization reference signal are transmitted together, the problem of mis-synchronization is avoided, and the probability of metastability is reduced.

[0038] In this embodiment, step S202 may specifically include: generating a reset pulse signal when a rising edge of the input synchronization reference signal is detected at the rising edge of the input clock signal.

[0039] In one embodiment, step S204 may specifically include: changing the output synchronization reference signal from high level to low level based on the reset pulse signal, and changing the output clock signal from high level to low level based on the reset pulse signal to reset the output synchronization reference signal and the output clock signal; when the next rising edge of the input clock signal arrives, the reset output synchronization reference signal and the reset output clock signal are generated synchronously. This embodiment is only a preferred embodiment, and it may also be a reset from low level to high level.

[0040] In another embodiment, step S204 above, generating the reset output clock signal may specifically include: generating a single-phase reset output clock signal based on the reset pulse signal and the input clock signal; or generating a multi-phase reset output clock signal based on the reset pulse signal and the input clock signal.

[0041] The above step S204 can be specifically executed by the output synchronization reference signal generation circuit and the output clock signal generation circuit. When the output synchronization reference signal generation circuit includes a first flip-flop (D-type Flip Flop, abbreviated as DFF), the first DFF generates the reset output synchronization reference signal synchronously according to the reset pulse signal, the input synchronization reference signal and the input clock signal at the next rising edge of the input clock signal after the reset pulse signal ends. When the rising edge of the clock signal in the first DFF arrives, the output synchronization reference signal becomes the input synchronization reference signal, and when the low level of the clock signal arrives, the output synchronization reference signal remains unchanged.

[0042] The aforementioned output clock signal generation circuit can be a single-phase clock generation circuit or a multi-phase clock generation circuit. If the output clock signal is a single-phase clock generation circuit, the single-phase clock generation circuit generates a single-phase reset output clock signal synchronously with the reset pulse signal and the input clock signal at the next rising edge of the input clock signal after the reset pulse signal ends. Furthermore, if the single-phase clock generation circuit includes a third DFF, the third DFF generates a single-phase reset output clock signal synchronously with the reset pulse signal and the input clock signal at the next rising edge of the input clock signal after the reset pulse signal ends.

[0043] If the output clock signal is a multi-phase clock generation circuit, the multi-phase output clock signal after reset is generated synchronously based on the reset pulse signal and the input clock signal at the next rising edge of the input clock signal after the reset pulse signal ends. Further, if the multi-phase clock generation circuit includes a divider and a shift register, the divider generates a single-phase divided clock based on the input clock signal and the reset pulse signal at the next rising edge of the input clock signal after the reset pulse signal ends; the shift register, under the control of the input clock signal, generates a multi-phase output clock signal after reset based on the single-phase divided clock generated by the divider. If the multi-phase clock generation circuit includes a state machine and a synchronization circuit, the state machine generates a multi-phase divided clock based on the input clock signal and the reset pulse signal at the next rising edge of the input clock signal after the reset pulse signal ends; the synchronization circuit synchronizes the multi-phase divided clock and outputs the multi-phase output clock signal after reset.

[0044] In an optional embodiment, after step S204 above, the method further includes: synchronizing the reset output synchronization reference signal according to the reset output clock signal to obtain a new reset output synchronization reference signal. At this time, the output synchronization reference signal generation circuit further includes a second DFF, which is connected to the first DFF. Through the second DFF, the reset output synchronization reference signal is synchronized according to the reset output clock signal to obtain a new reset output synchronization reference signal.

[0045] In this embodiment of the application, step S202 may specifically include: generating a reset pulse signal based on an input synchronization reference signal and an input clock signal using a reset pulse generation method with a delayed signal; or generating a reset pulse signal based on an input synchronization reference signal and an input clock signal using a reset pulse generation method with two non-overlapping two-phase signals.

[0046] In another optional embodiment, the method further includes: generating the reset pulse signal based on the input synchronization reference signal and the input clock signal when the reset pulse enable signal is enabled and the new air interface signal is enabled; synchronously resetting the output synchronization reference signal and the output clock signal using the reset pulse signal when the reset pulse enable signal is enabled and the new air interface signal is enabled; furthermore, not resetting the output synchronization reference signal and the output clock signal when the reset pulse enable signal is enabled and the new air interface signal is not enabled; not resetting the output synchronization reference signal and the output clock signal when the reset pulse enable signal is not enabled and the new air interface signal is enabled; and generating the output synchronization reference signal and the output clock signal at the rising edge of the input clock signal.

[0047] In this embodiment, the input synchronization reference signal enters the reset pulse signal generation circuit and the output synchronization reference signal generation circuit through the first buffer, respectively. The input clock signal enters the reset pulse signal generation circuit, the output synchronization reference signal generation circuit and the output clock signal generation circuit through the second buffer, respectively. The first buffer and the second buffer are inverter chain structures, or the first buffer and the second buffer are integrated with a delay adjustment circuit, or the first buffer and the second buffer are integrated with a duty cycle adjustment circuit.

[0048] The embodiments of this application can also compensate for the time delay of the data link in the following two ways: Method 1: Count the input clock signal within the period of the input synchronization reference signal in multiple clock domains to obtain the counting result; compare the counting result with the preset counting result to obtain the first comparison result; determine the first clock frequency deviation of the target time delay based on the first comparison result; adjust the time delay of the data link by adjusting the address of the read data to compensate for the first clock frequency deviation of the target time delay, thereby realizing the compensation for the time delay of the data link. Method 2: Obtain the current address when the rising edge of the input synchronization reference signal arrives; compare the current address with the initial address to obtain a second comparison result; determine the second clock frequency error of the target time delay based on the second comparison result; adjust the time delay of the data link by adjusting the position of the read address in the random access memory to compensate for the second clock frequency deviation of the target time delay. The storage depth of the random access memory is the product of the ratio of the period of the input synchronization reference signal to the period of the read signal and the reciprocal of N, to compensate for the first clock frequency deviation of the target time delay. The time delay of the data link is compensated by adjusting the position of the read address in the random access memory. The aforementioned target time delay is the time from the start of resetting the output synchronization reference signal and the output clock signal to the synchronous generation of the reset output synchronization reference signal and the reset output clock signal.

[0049] This application embodiment introduces an input synchronization reference signal, which can be a periodic signal or a step signal. A reset pulse signal is generated using synchronous timing logic based on the input synchronization reference signal and the input clock signal, giving the reset pulse signal a clear time delay characteristic. Then, the multi-phase output clock signal generation cable and the output synchronization reference signal generation cable are reset and synchronized, ensuring the phase information of the multi-phase output clock signal is clear. Both are then transmitted together to the next clock domain, repeating the above operation. By using a sequential synchronization method for each clock domain, the load on the synchronization reference signal is reduced, thereby reducing the uncertainty of time delay between different clock domains. The method of transmitting the clock signal and synchronization reference signal together avoids mis-beat problems and reduces the probability of metastability. In this way, each clock domain has clear phase information. When the synchronization reference signal is a periodic signal, its period is an integer multiple of the ideal clock frequency. Within the period of the synchronization reference signal, the clock signal is counted, and the count result is compared with the ideal count result to determine the clock frequency deviation. The data link delay is adjusted by adjusting the read data address to compensate for the time delay deviation. The above methods ensure that the entire data transmission link has stable clock phase information, and by timely compensating for the delay error caused by the clock frequency, accurate delay characteristics are obtained.

[0050] Figure 3This is a timing diagram based on the high-precision time delay of this embodiment, such as... Figure 3 As shown, the top five signals are in clock domain 1 (clk domain1), and the bottom five signals are in clock domain 2 (clk domain2). This diagram illustrates the process of generating reset pulses (sync pulses 1 / 2), multi-phase divided clocks (Clk out 1 / 2), and output synchronization reference signals (Sync out 1 / 2) locally from the synchronization reference signals (syncin1 / 2) and the local clocks (Clk in 1 / 2), as well as the transmission process of synchronization reference signals and clock signals between different clock domains (Clk out 1 becomes Clk in 2 after a delay, and Sync out 1 becomes sync in 2 after a delay). The reset pulse signal, multi-phase divided clock, and output synchronization reference signal are all generated synchronously under the control of the local clock signal, possessing clear and stable timing and accurate delay information. Figure 3 As shown, after clk1 acquires sync in1, a rising edge of sync pulse1 is generated. Then, sync out1 and clk out1 are reset. After two clk1 cycles, a falling edge of sync pulse1 is generated. On the next rising edge of clk1, the reset clk out1 and sync out1 are generated. Thus, after three clk1 cycles (Td1) following the acquisition of sync in1, a new clock signal and synchronization signals clk out1 and sync out1 are generated. Since the synchronization reference signal (sync out1) is transmitted to the next clock domain together with the output clock (clk out1), by matching the same transmission path for both, it is ensured that when the synchronization reference signal and the clock signal are transmitted to the next clock domain (clk domain2), they (sync in2 and clk in2) still have a clear phase relationship and delay information Td2. In clock domain 2, the multi-phase clock (Clk out2) reset and the clock and synchronization reference signal (Sync out2) transmission are also performed, in the same way as in clock domain 1. When Clk in2 samples three Clk in2 cycles of sync in2, Td3, the reset Clk out2 and Sync out2 are generated. After the synchronization reference signal is transmitted to all clock domains, the entire clock reset is completed, thus ensuring that the clock signal in each clock domain has a definite delay information relative to the synchronization reference signal, and therefore, there is also a definite delay information between the clock signals. Figure 3As shown, if we consider two clock domains, then clk1 out has a delay of 3 clk in1 cycles relative to sync in1, and clk2 out has a delay of 3 clk in2 cycles plus the signal propagation delay Td2 between clock domains 1 and 2. Since the signal delay Td2 in the wiring is relatively stable, it can be considered a relatively fixed delay. Therefore, clk out2 also has a fixed delay relative to sync in1.

[0051] Figure 4 The circuit structure of high-precision time delay according to this embodiment. Figure 1 ,like Figure 4 As shown, the input synchronization reference signal (Sync in) and the local input clock signal (Clk in) pass through a buffer circuit to reach the local clock domain, generating a reset pulse signal (sync pulse) and an output synchronization reference signal (Sync out). <x:0>) and output clock signal (Clk out) <x:0>The circuit consists of the following components. All of these signals are generated under the synchronous timing logic of the local clock signal (Clk in). The reset pulse signal (sync pulse) is generated using the synchronous reference signal (Sync out) and the input clock signal (Clk in), and includes pulse width adjustment functionality. The output pulse width is an integer multiple of the period of the input clock signal (Clk in). The reset pulse signal acts on the output synchronous reference signal generation circuit and the output clock signal generation circuit. The output clock signal generation circuit specifically includes DFF41 (corresponding to the first DFF mentioned above) and DFF42 (corresponding to the second DFF mentioned above) to reset the output synchronous reference signal and the output pulse signal, obtaining the reset output synchronous reference signal and the reset output pulse signal. When the reset pulse signal ends and the next rising edge of the local clock arrives, a new output clock signal and output synchronous reference signal with a defined phase relationship are generated. Multi-phase output clock signals can be generated in various ways. Figure 4 The method first generates a single-phase clock using a divider, and then generates a multi-phase clock using a shift register. <x:0>The scheme involves synchronizing the output multi-phase clock signal and the output synchronization reference signal with the output multi-phase clock (DFF). To ensure the phase relationship between the output multi-phase clock signal and the output synchronization reference signal, the output synchronization reference signal is synchronized with the output multi-phase clock (DFF). <x:0>Output multi-phase synchronization reference signal (Sync out) <x:0>In addition, this circuit integrates a reset pulse enable signal (sync pulse en, abbreviated as Spen) and a new radio enable signal (new radio en, abbreviated as Nren). When the reset pulse signal is enabled, the reset pulse signal is generated normally, resetting the output synchronization reference signal and the output clock signal; when the reset pulse enable signal is disabled and the new radio enable signal is enabled, the output synchronization reference signal and the output clock signal are not reset, and the synchronization reference signal is synchronously transmitted to the next clock domain through the local clock.

[0052] The synchronization reference signal can be a single rising edge step signal or a periodic signal. When the synchronization reference signal is a step signal, it is often used for clock phase reset and address initialization in random access memory. When the synchronization reference signal is a periodic signal, in addition to reset and initialization, it can also be used to correct the time delay error caused by the frequency error of the frequency division clock signal. When the synchronization reference signal is a periodic signal, the period of the synchronization reference signal must be an integer multiple of the frequency of the ideal clock. Figure 5 This is a schematic diagram of clock frequency deviation compensation according to this embodiment. Figure 1 ,like Figure 5 As shown, a data buffer is introduced into the digital data link to correct delay deviations. The accuracy of the divided clock frequency is determined by periodically counting the divided clock signal and comparing the count result with the ideal count result. The clock frequency deviation is corrected by adjusting the data delay. To avoid frequent updates to the read address position, a threshold is configured. When the deviation is within the threshold range, no read address update is performed; when the deviation exceeds the threshold, the read address is updated to the expected position, thus ensuring that the delay deviation remains within the required range.

[0053] In this embodiment, the buffers for the synchronization reference signal and the local clock signal have various variations. Figure 6 The circuit diagram of the buffer according to this embodiment is as follows: Figure 6 As shown, a buffer can be a simple inverter chain ( Figure 6 a) to increase driving capability, the buffer can also integrate delay adjustment function ( Figure 6 b. By using a multiplexer to select different delay paths and adjust the input-to-output delay, a relatively stable timing relationship between data and clock is obtained, along with integrated duty cycle adjustment functionality. Figure 6 c. Inserting bidirectional inverters between differential signal transmission paths to form positive feedback and optimize the duty cycle, so that the signal has accurate duty cycle information, etc.

[0054] Various variations of multi-phase clock generation circuits can be employed. Figure 4 The frequency divider and shift register configuration is shown. Figure 7 The circuit structure for generating a multi-phase clock according to this embodiment. Figure 1 ,like Figure 7 As shown, when rst_n is low, DFF71-72 is reset, and clk_div outputs a low level. After rest_n is released, on the rising edge of the first clk, the output of DFF1 changes from low to high, and the output of DFF72 remains low. On the rising edge of the second clk, the output of DFF1 remains high, and the output of DFF72, i.e., clk_div, changes from low to high. Following this pattern, a 4-division signal clk_div is generated. Then, clk_div generates a 4-phase 4-division signal clk_div<3:0> through DFF73-DFF76. Figure 8 The circuit structure for generating a multi-phase clock according to this embodiment. Figure 2 ,like Figure 8 As shown, the output is generated using a state machine and output synchronization. When rest_n is low, DFF81-82 is reset, and div<3:0> outputs a low level. After rest_n is released, DFF1 outputs div on the rising edge of the first clk. <3> The inverted signal div changes from low to high. <1> When the signal changes from high to low, the DFF82 output remains low. On the second rising edge of Clk, the DFF1 output remains high, and the DFF82 output (div) continues to rise. <2> The inverted signal div changes from low to high. <1> The output clk_div<3:0> is generated by the multi-phase frequency division signal div<3:0> after being synchronized with clk by DFF83-86 after changing from high level to low level.

[0055] The circuit for generating the reset pulse signal can have various variations. In this application, to shield the falling edge of the synchronization reference signal, a rising edge triggering circuit is integrated into the design. Figure 9 The circuit structure for generating the reset pulse according to this embodiment. Figure 1 , Figure 10 The circuit structure for generating the reset pulse according to this embodiment. Figure 2 ,like Figure 9 and Figure 10 The DFF91 is a rising-edge triggered IC, meaning its output only changes when the rising edge of the Sync-in signal arrives. If dual-edge triggering is required, the rising-edge triggering circuit can be removed. Figure 9 The output signal of DFF91, under the control of clk, is processed by DFF92-94 to generate signals with different delays (each DFF delays clk by one clock cycle). When s1 is high and s1n is low, the outputs of DFF92 and DFF93 generate a pulse signal of one clk cycle through an XOR gate. When s1 is low and s1n is high, a pulse signal of two clk cycles is generated. Increasing the number of DFFs can also generate signals with larger pulse widths. Figure 10 In this circuit, the principle of generating two-phase non-overlapping signals is utilized. By adjusting the non-overlapping time of the DFF, signals with different pulse widths are generated. When s1 is high and s1n is low, DFF102 and DFF103 are connected to the input of an XOR gate. Since the DFF103 signal is generated by the DFF102 signal through one NOR gate and one DFF, a pulse signal delayed by one DFF and one NOR gate is generated. When s1 is high and s1n is low, DFF104 and DFF105 are connected to the input of an XOR gate. Since the DFF105 signal is generated by the DFF104 signal through one NOR gate and two DFFs, a pulse signal delayed by two DFFs and one NOR gate is generated. When the number of DFFs increases, signals with larger pulse widths can also be generated.

[0056] like Figure 3 As shown, after the system is powered on, a synchronization reference signal (Sync in1) is generated. When the synchronization reference signal passes through different clock domains (Clk domain1 / 2), it sequentially triggers the generation of local reset pulse signals (Sync pulse1 / 2), which synchronously reset the clock signals (Clk out1 / 2) of each clock domain and the output synchronization reference signal (Sync out1 / 2), so that each clock signal (Clk out1 / 2) has clear phase information. Figure 11 This is a schematic diagram of clock frequency deviation compensation according to this embodiment. Figure 2 ,like Figure 11 As shown, after the clock domain of the random access memory (RAM) generates a clock signal (data_rd_clk) and a synchronization reset signal (Sync pulse), the read address (data_rd_addr) of the RAM is initialized, and the read address is periodically checked. If the deviation of the read address exceeds a set threshold, the read address is reset to the initialized address (rd_addr_init); otherwise, the read address remains unchanged. Through the above process, the precise time delay of the data link is obtained.

[0057] Clock frequency error correction methods can have various variations, such as Figure 11 As shown, to simplify the clock frequency detection method, the memory depth must be guaranteed so that the number of data reads within the synchronization reference period is an integer multiple of the memory depth. Ideally, when the rising edge of the synchronization reference signal (Sync pulse) arrives, the address of the read data (data_rd_addr) should always be the initialized address (rd_addr_init). The clock frequency error is determined by comparing the current address at the rising edge of the synchronization reference signal with the initialized address. Then, the impact of the clock frequency error on delay accuracy is compensated by adjusting the position of the read address in the data buffer.

[0058] The synchronization method for the output clock signal and the output synchronization reference signals (Sync out and Clk out) can be as follows: Figure 4 The output synchronization reference signal shown is synchronized by the output multi-phase clock to generate a multi-phase synchronization reference signal; Figure 12 The circuit structure of high-precision time delay according to this embodiment. Figure 2 ,like Figure 12 As shown, the output synchronization reference signal generation circuit is DFF121 (corresponding to DFF41 mentioned above), and the output clock signal generation circuit includes a divider and a shift register (as described above). Figure 4 (Similar to), asynchronous direct output; Figure 13 The circuit structure of high-precision time delay according to this embodiment. Figure 3 ,like Figure 13 As shown, the output synchronization reference signal generation circuit is DFF131 (corresponding to DFF41 mentioned above). If the output clock frequency is consistent with the input clock frequency, the multi-phase clock generation circuit is replaced with a single-phase clock generation circuit, which includes DFF132 (corresponding to the third DFF mentioned above).

[0059] This application introduces a synchronization reference signal and employs synchronous timing logic to sequentially transmit it and the clock signal to different clock domains. A reset pulse is generated locally in the clock domain to reset the clock, reducing the uncertainty of the reset signal delay. By using synchronous timing logic, each synchronized signal has clear delay information, avoiding mis-beat or metastability problems. Through the above methods, the stability and accuracy of the clock phase are achieved.

[0060] The accuracy of the clock frequency is detected by using the period of the synchronization reference signal as a reference. The delay is adjusted by changing the location of the random access memory read address to compensate for the delay deviation introduced by the clock frequency deviation. This method is not found in traditional solutions.

[0061] According to another embodiment of this application, an apparatus for providing a clock signal in a data link is also provided. Figure 14 This is a block diagram of an apparatus for providing a clock signal in a data link according to an embodiment of this application, such as... Figure 14 As shown, the device includes: a reset pulse signal generation circuit 142, an output synchronization reference signal generation circuit 144, and an output clock signal generation circuit 146, wherein,

[0062] The reset pulse signal generation circuit 142 is used to generate a reset pulse signal based on an input synchronization reference signal and an input clock signal in each of the multiple clock domains of the data link, generate an output synchronization reference signal based on the input synchronization reference signal and the input clock signal, and generate an output clock signal based on the input clock signal; and input the reset pulse signal to the output synchronization reference signal generation circuit 144 and the output clock signal generation circuit 146 to reset the output synchronization reference signal and the output clock signal.

[0063] The output synchronization reference signal generation circuit 144 is used to synchronously generate the reset output synchronization reference signal at the next rising edge of the input clock signal after the reset pulse signal ends.

[0064] The output clock signal generation circuit 146 is used to synchronously generate a reset output clock signal at the next rising edge of the input clock signal after the reset pulse signal ends. The reset output synchronization reference signal and the reset output clock signal are transmitted to the next clock domain of the data link after the same second time delay, serving as the input synchronization reference signal and the input clock signal of the next clock domain.

[0065] In one embodiment, the reset pulse signal generating circuit 142 is further configured to generate the reset pulse signal when the rising edge of the input synchronization reference signal is detected at the rising edge of the input clock signal.

[0066] In one embodiment, the output synchronization reference signal generation circuit 144 is further configured to convert the output synchronization reference signal from a high level to a low level based on the reset pulse signal, and to convert the output clock signal from a high level to a low level based on the reset pulse signal, so as to reset the output synchronization reference signal and the output clock signal.

[0067] In one embodiment, the output synchronization reference signal generation circuit 144 includes a first flip-flop (DFF), the output clock signal generation circuit 146 is a single-phase clock generation circuit or a multi-phase clock generation circuit, and the reset pulse signal generation circuit 142 is connected to the first DFF. Alternatively, the reset pulse signal generation circuit 142 may be connected to the single-phase clock generation circuit or the multi-phase clock generation circuit.

[0068] The reset pulse signal generation circuit 142 is used to generate the reset pulse signal based on the input synchronization reference signal and the input clock signal, and input the reset pulse signal to the first DFF and the single-phase clock generation circuit, or input the reset pulse signal to the first DFF and the multi-phase clock generation circuit.

[0069] The first DFF is used to generate the reset output synchronization reference signal synchronously based on the reset pulse signal, the input synchronization reference signal, and the input clock signal on the next rising edge of the input clock signal after the reset pulse signal ends.

[0070] The single-phase clock generation circuit is used to generate a single-phase reset output clock signal synchronously with the input clock signal based on the next rising edge of the input clock signal after the reset pulse signal ends; or

[0071] The multi-phase clock generation circuit is used to generate a multi-phase output clock signal after the reset based on the reset pulse signal and the input clock signal synchronously at the next rising edge of the input clock signal after the reset pulse signal ends.

[0072] In one embodiment, the output synchronization reference signal generation circuit 144 includes a first flip-flop (DFF) and a second DFF, the first DFF and the second DFF being connected. The output clock signal generation circuit 146 is a multi-phase clock generation circuit or a single-phase clock generation circuit. The reset pulse signal generation circuit 142 is connected to the first DFF, the reset pulse signal generation circuit 142 is connected to the single-phase clock generation circuit, or the reset pulse signal generation circuit 142 is connected to the multi-phase clock generation circuit.

[0073] The reset pulse signal generation circuit 142 is used to generate the reset pulse signal based on the input synchronization reference signal and the input clock signal, and input the reset pulse signal to the first DFF and the single-phase clock generation circuit, or input the reset pulse signal to the first DFF and the multi-phase clock generation circuit.

[0074] The first DFF is used to generate the reset output synchronization reference signal based on the reset pulse signal, the input synchronization reference signal and the input clock signal on the next rising edge of the input clock signal after the reset pulse signal ends, and input the reset output synchronization reference signal to the second DFF.

[0075] The second DFF is used to synchronize the reset output synchronization reference signal according to the reset output clock signal to obtain a new reset output synchronization reference signal;

[0076] The single-phase clock generation circuit is used to synchronously generate a single-phase output clock signal after the reset based on the reset pulse signal and the input clock signal at the next rising edge of the input clock signal after the reset pulse signal ends; or

[0077] The multi-phase clock generation circuit is used to synchronously generate the multi-phase output clock signal after the reset based on the reset pulse signal and the input clock signal at the next rising edge of the input clock signal after the reset pulse signal ends.

[0078] In one embodiment, the single-phase clock generation circuit includes a third DFF, wherein the third DFF is used to generate a single-phase reset output clock signal synchronously with the input clock signal based on the reset pulse signal and the input clock signal at the next rising edge of the input clock signal after the reset pulse signal ends.

[0079] The multi-phase clock generation circuit includes a divider (Divider) and a shift register (Shift register). A reset pulse signal generation circuit 142 is connected to the divider, and the divider is connected to the shift register.

[0080] The Divider is used to generate a single-phase frequency-divided clock based on the reset pulse signal and the input clock signal on the next rising edge of the input clock signal after the reset pulse signal ends.

[0081] The Shift register is used to generate a multi-phase output clock signal after reset, based on the input clock signal, under the control of the single-phase frequency divider clock.

[0082] In one embodiment, the single-phase clock generation circuit includes a third DFF, wherein the third DFF is used to synchronously generate a single-phase reset output clock signal based on the reset pulse signal and the input clock signal at the next rising edge of the input clock signal after the reset pulse signal ends.

[0083] The multi-phase clock generation circuit includes a state machine and a synchronization circuit. A reset pulse signal generation circuit 142 is connected to the state machine, and the state machine is connected to the synchronization circuit.

[0084] The state machine is used to generate a multi-phase frequency-divided clock based on the reset pulse signal and the input clock signal at the next rising edge of the input clock signal after the reset pulse signal ends.

[0085] The synchronization circuit is used to synchronize the multi-phase frequency-divided clock and output the multi-phase reset output clock signal.

[0086] In one embodiment, the device further includes a first buffer and a second buffer. The first buffer is connected to the reset pulse signal generation circuit 142 and the output synchronization reference signal generation circuit 144, respectively. The second buffer is connected to the reset pulse signal generation circuit 142, the output synchronization reference signal generation circuit 144, and the output clock signal generation circuit 146, respectively.

[0087] The input synchronization reference signal enters the reset pulse signal generation circuit 142 and the output synchronization reference signal generation circuit 144 respectively through the first buffer;

[0088] The input clock signal passes through the second buffer and enters the reset pulse signal generation circuit 142, the output synchronization reference signal generation circuit 144, and the output clock signal generation circuit 146, respectively.

[0089] In one embodiment, the first buffer and the second buffer are an inverter chain structure, or the first buffer and the second buffer integrate a delay adjustment circuit, or the first buffer and the second buffer integrate a duty cycle adjustment circuit.

[0090] In one embodiment, the reset pulse generation circuit is further configured to generate the reset pulse signal based on the input synchronization reference signal and the input clock signal when the reset pulse enable signal is enabled and the new air interface signal is enabled; to reset the output synchronization reference signal and the output clock signal through the reset pulse signal when the reset pulse enable signal is enabled and the new air interface signal is enabled; and to synchronously generate the reset output synchronization reference signal and the reset output clock signal on the next rising edge of the input clock signal after the reset pulse signal ends.

[0091] In one embodiment, the reset pulse generating circuit is further configured to not reset the output synchronization reference signal and the output clock signal when the reset pulse enable signal is enabled and the new air interface signal is disabled; and not reset the output synchronization reference signal and the output clock signal when the reset pulse enable signal is disabled and the new air interface signal is enabled.

[0092] In one embodiment, the reset pulse signal generating circuit 142 is further configured to generate the reset pulse signal based on the input synchronization reference signal and the input clock signal using a delayed signal reset pulse generation method; or to generate the reset pulse signal based on the input synchronization reference signal and the input clock signal using a two-phase non-overlapping signal reset pulse generation method.

[0093] In one embodiment, the device further includes: a compensation circuit, wherein,

[0094] The compensation circuit is configured to: count the input clock signal within the period of the input synchronization reference signal in the plurality of clock domains to obtain a counting result; compare the counting result with a preset counting result to obtain a first comparison result; determine a first clock frequency deviation of the target time delay based on the first comparison result; adjust the time delay of the data link by adjusting the address of the read data to compensate for the first clock frequency deviation of the target time delay; or obtain the current address when the rising edge of the input synchronization reference signal arrives; compare the current address with the initialization address to obtain a second comparison result; determine a second clock frequency error of the target time delay based on the second comparison result; adjust the time delay of the data link by adjusting the position of the read address in the random access memory to compensate for the second clock frequency deviation of the target time delay, wherein the target time delay is the time from the start of resetting the output synchronization reference signal and the output clock signal to the synchronous generation of the reset output synchronization reference signal and the reset output clock signal, and the storage depth of the random access memory is the product of the ratio of the period of the input synchronization reference signal to the period of the read signal and the reciprocal of N.

[0095] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above method embodiments when run.

[0096] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0097] Embodiments of this application also provide an electronic device including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.

[0098] In one exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor and the input / output device is connected to the processor.

[0099] Specific examples in this embodiment can be found in the examples described in the above embodiments and exemplary implementations, and will not be repeated here.

[0100] Obviously, those skilled in the art should understand that the modules or steps of this application described above can be implemented using general-purpose computing devices. They can be centralized on a single computing device or distributed across a network of multiple computing devices. They can be implemented using computer-executable program code, and thus can be stored in a storage device for execution by a computing device. In some cases, the steps shown or described can be performed in a different order than those presented here, or they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, this application is not limited to any particular combination of hardware and software.

[0101] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the principles of this application should be included within the protection scope of this application.

Claims

1. A method of providing a clock signal in a data link, characterized by, The method comprises: in each clock domain of a plurality of clock domains of a data link, generating a reset pulse signal based on an input synchronization reference signal and an input clock signal, generating an output synchronization reference signal based on the input synchronization reference signal and the input clock signal, and generating an output clock signal based on the input clock signal; resetting the output synchronization reference signal and the output clock signal by the reset pulse signal, and synchronously generating the reset output synchronization reference signal and the reset output clock signal at a next rising edge of the input clock signal after the reset pulse signal ends, wherein the reset output synchronization reference signal and the reset output clock signal are transmitted into a next clock domain of the data link as an input synchronization reference signal and an input clock signal of the next clock domain after passing through the same time delay.

2. The method of claim 1, wherein, Generating the reset pulse signal based on the input synchronization reference signal and the input clock signal comprises: generating the reset pulse signal when a rising edge of the input synchronization reference signal is detected at a rising edge of the input clock signal.

3. The method of claim 1, wherein, Resetting the output synchronization reference signal and the output clock signal by the reset pulse signal, and synchronously generating the reset output synchronization reference signal and the reset output clock signal at a next rising edge of the input clock signal after the reset pulse signal ends comprises: converting the output synchronization reference signal from high level to low level based on the reset pulse signal, and converting the output clock signal from high level to low level based on the reset pulse signal to reset the output synchronization reference signal and the output clock signal; synchronously generating the reset output synchronization reference signal and the reset output clock signal when a next rising edge of the input clock signal comes after the reset pulse signal ends.

4. The method of claim 1, wherein, Generating the reset output clock signal comprises: generating the reset output clock signal in single phase according to the reset pulse signal and the input clock signal; or generating the reset output clock signal in multiple phases according to the reset pulse signal and the input clock signal.

5. The method of claim 4, wherein, After generating the reset output synchronization reference signal and the reset output clock signal, the method further comprises: synchronizing the reset output synchronization reference signal according to the reset output clock signal to obtain a new reset output synchronization reference signal.

6. The method of claim 4, wherein, Generating the reset output clock signal in multiple phases according to the reset pulse signal and the input clock signal comprises: generating a single-phase divided clock according to the input clock signal and the reset pulse signal, and generating the reset output clock signal in multiple phases according to the single-phase divided clock under the control of the input clock signal; generating a multiple-phase divided clock according to the input clock signal and the reset pulse signal, synchronizing the multiple-phase divided clock, and outputting the reset output clock signal in multiple phases.

7. The method of claim 1, wherein, The generating the reset pulse signal based on the input synchronous reference signal and the input clock signal comprises: The generating the reset pulse signal based on the input synchronous reference signal and the input clock signal comprises: The generating the reset pulse signal based on the input synchronous reference signal and the input clock signal comprises:

8. The method of any one of claims 1-7, wherein The generating the reset pulse signal based on the input synchronous reference signal and the input clock signal comprises: generating the reset pulse signal based on the input synchronous reference signal and the input clock signal in a case that a reset pulse enable signal is enabled and a new radio signal is enabled. The resetting the output synchronous reference signal and the output clock signal by the reset pulse signal and synchronously generating the reset output synchronous reference signal and the reset output clock signal after a next rising edge of the input clock signal comprises: resetting the output synchronous reference signal and the output clock signal by the reset pulse signal and synchronously generating the reset output synchronous reference signal and the reset output clock signal after a next rising edge of the input clock signal in a case that the reset pulse enable signal is enabled and the new radio enable signal is enabled.

9. The method of claim 8, wherein, The method further comprises: In a case that the reset pulse enable signal is not enabled and the new radio signal is enabled, not resetting the reset output synchronous reference signal and the reset output clock signal. The method further comprises:

10. The method according to any one of claims 1 to 7, 9, characterized in that, In a period of the input synchronous reference signal of the plurality of clock domains, counting the input clock signal to obtain a count result; Comparing the count result with a pre-designed count result to obtain a first comparison result; According to the first comparison result, determining a first clock frequency deviation of a target time delay, wherein the target time delay is a time from a start of resetting the output synchronous reference signal and the output clock signal to a synchronous generation of the reset output synchronous reference signal and the reset output clock signal; Adjusting a time delay of the data link by adjusting an address of reading data to compensate for the first clock frequency deviation of the target time delay. The method further comprises:

11. The method according to any one of claims 1 to 7, 9, characterized in that, Obtaining a current address when a rising edge of the input synchronous reference signal arrives; Comparing the current address with an initial address to obtain a second comparison result; According to the second comparison result, determining a second clock frequency deviation of a target time delay, wherein the target time delay is a time from a start of resetting the output synchronous reference signal and the output clock signal to a synchronous generation of the reset output synchronous reference signal and the reset output clock signal; and ​ adjusting a time delay of the data link by adjusting a position of a read address in a random memory, to compensate for a second clock frequency deviation of the target time delay, wherein a storage depth of the random memory is a product of a ratio of a period of the input synchronous reference signal to a period of a read signal and an inverse of N.

12. An apparatus for providing a clock signal in a data link, the apparatus comprising: The device comprises a reset pulse signal generation circuit, an output synchronous reference signal generation circuit and an output clock signal generation circuit, wherein the reset pulse signal generation circuit is configured to generate a reset pulse signal based on an input synchronous reference signal and an input clock signal in each clock domain of a plurality of clock domains of a data link, generate an output synchronous reference signal based on the input synchronous reference signal and the input clock signal, generate an output clock signal based on the input clock signal, and input the reset pulse signal to the output synchronous reference signal generation circuit and the output clock signal generation circuit to reset the output synchronous reference signal and the output clock signal; the output synchronous reference signal generation circuit is configured to generate a reset output synchronous reference signal synchronously with a next rising edge of the input clock signal after the reset pulse signal ends; the output clock signal generation circuit is configured to generate a reset output clock signal synchronously with the next rising edge of the input clock signal after the reset pulse signal ends, wherein the reset output synchronous reference signal and the reset output clock signal are transmitted to a next clock domain of the data link as an input synchronous reference signal and an input clock signal of the next clock domain after passing through a same second time delay.

13. The device of claim 12, wherein the reset pulse signal generation circuit is further configured to generate the reset pulse signal when a rising edge of the input clock signal detects a rising edge of the input synchronous reference signal.

14. The device of claim 12, wherein the output synchronous reference signal generation circuit is further configured to reset the output synchronous reference signal from a high level to a low level based on the reset pulse signal, and reset the output clock signal from a high level to a low level based on the reset pulse signal.

15. The apparatus of claim 12, wherein, the output synchronous reference signal generation circuit comprises a first flip-flop (DFF), the output clock signal generation circuit is a single-phase clock generation circuit or a multi-phase clock generation circuit, the reset pulse signal generation circuit is connected to the first DFF, the reset pulse signal generation circuit is connected to the single-phase clock generation circuit, or the reset pulse signal generation circuit is connected to the multi-phase clock generation circuit, and the reset pulse signal generation circuit is configured to generate the reset pulse signal based on the input synchronous reference signal and the input clock signal, and input the reset pulse signal to the first DFF and the single-phase clock generation circuit, or input the reset pulse signal to the first DFF and the multi-phase clock generation circuit. the first DFF is configured to generate the reset output synchronous reference signal based on the reset pulse signal, the input synchronous reference signal and the input clock signal at a next rising edge of the input clock signal after the reset pulse signal ends, and input the reset output synchronous reference signal to the second DFF; the single-phase clock generation circuit is configured to generate the single-phase reset output clock signal based on the reset pulse signal and the input clock signal at a next rising edge of the input clock signal after the reset pulse signal ends; or the multi-phase clock generation circuit is configured to generate the multi-phase reset output clock signal based on the reset pulse signal and the input clock signal at a next rising edge of the input clock signal after the reset pulse signal ends.

16. The apparatus of claim 12, wherein, the output synchronous reference signal generation circuit comprises a first DFF and a second DFF, the first DFF is connected to the second DFF, the output clock signal generation circuit is a multi-phase clock generation circuit or a single-phase clock generation circuit, the reset pulse signal generation circuit is connected to the first DFF, the reset pulse signal generation circuit is connected to the single-phase clock generation circuit, or the reset pulse signal generation circuit is connected to the multi-phase clock generation circuit, wherein the reset pulse signal generation circuit is configured to generate the reset pulse signal based on the input synchronous reference signal and the input clock signal, and input the reset pulse signal to the first DFF and the single-phase clock generation circuit, or input the reset pulse signal to the first DFF and the multi-phase clock generation circuit; the first DFF is configured to generate the reset output synchronous reference signal based on the reset pulse signal, the input synchronous reference signal and the input clock signal at a next rising edge of the input clock signal after the reset pulse signal ends, and input the reset output synchronous reference signal to the second DFF; the second DFF is configured to synchronize the reset output synchronous reference signal according to the reset output clock signal to obtain a new reset output synchronous reference signal; the single-phase clock generation circuit is configured to generate the single-phase reset output clock signal based on the reset pulse signal and the input clock signal at a next rising edge of the input clock signal after the reset pulse signal ends; or the multi-phase clock generation circuit is configured to generate the multi-phase reset output clock signal based on the reset pulse signal and the input clock signal at a next rising edge of the input clock signal after the reset pulse signal ends.

17. The apparatus of claim 15 or 16, wherein The single-phase clock generation circuit comprises a third DFF, wherein the third DFF is configured to generate the single-phase reset output clock signal based on the reset pulse signal and the input clock signal at a next rising edge of the input clock signal after the reset pulse signal ends. The multi-phase clock generation circuit comprises a frequency divider Divider and a shift register Shift register, the reset pulse signal generation circuit is connected with the Divider, and the Divider is connected with the Shift register, wherein The Divider is configured to generate a single-phase frequency-divided clock based on the reset pulse signal and the input clock signal at a next rising edge of the input clock signal after the reset pulse signal ends. The Shift register is configured to generate a multi-phase reset output clock signal based on the input clock signal under control of the single-phase frequency-divided clock.

18. The apparatus according to claim 15 or 16, wherein The single-phase clock generation circuit comprises a third DFF, wherein the third DFF is configured to generate the single-phase reset output clock signal based on the reset pulse signal and the input clock signal at a next rising edge of the input clock signal after the reset pulse signal ends. The multi-phase clock generation circuit comprises a state machine and a synchronization circuit, the reset pulse signal generation circuit is connected with the state machine, and the state machine is connected with the synchronization circuit, wherein The state machine is configured to generate a multi-phase frequency-divided clock based on the reset pulse signal and the input clock signal at a next rising edge of the input clock signal after the reset pulse signal ends. The synchronization circuit is configured to synchronize the multi-phase frequency-divided clock and output a multi-phase reset output clock signal.

19. The apparatus of any one of claims 12-16, wherein, The apparatus further comprises a first buffer and a second buffer, the first buffer is connected with the reset pulse signal generation circuit and the output synchronization reference signal generation circuit respectively, and the second buffer is connected with the reset pulse signal generation circuit, the output synchronization reference signal generation circuit and the output clock signal generation circuit respectively, wherein The input synchronization reference signal enters the reset pulse signal generation circuit and the output synchronization reference signal generation circuit through the first buffer respectively. The input clock signal enters the reset pulse signal generation circuit, the output synchronization reference signal generation circuit and the output clock signal generation circuit through the second buffer respectively.

20. The apparatus according to claim 19, wherein The first buffer and the second buffer are inverter chain structures, or the first buffer and the second buffer are integrated with delay adjustment circuits, or the first buffer and the second buffer are integrated with duty cycle adjustment circuits.

21. The apparatus according to any one of claims 12 to 16, wherein The reset pulse generation circuit is further configured to generate the reset pulse signal based on the input synchronization reference signal and the input clock signal when the reset pulse enable signal is enabled and the new radio signal is enabled, reset the output synchronization reference signal and the output clock signal by the reset pulse signal when the reset pulse enable signal is enabled and the new radio enable signal is enabled, and generate the reset output synchronization reference signal and the reset output clock signal synchronously at a next rising edge of the input clock signal after the reset pulse signal ends.

22. The apparatus of claim 21, wherein The reset pulse generation circuit is further configured to not reset the output synchronization reference signal and the output clock signal when the reset pulse enable signal is enabled and the new radio signal is not enabled, and not reset the output synchronization reference signal and the output clock signal when the reset pulse enable signal is not enabled and the new radio signal is enabled.

23. The apparatus of any one of claims 12 to 16, wherein The reset pulse signal generation circuit is further configured to generate the reset pulse signal based on the input synchronization reference signal and the input clock signal in a reset pulse generation mode of a delay signal, or generate the reset pulse signal based on the input synchronization reference signal and the input clock signal in a reset pulse generation mode of two-phase non-overlapping signals. The apparatus further comprises a compensation circuit, wherein 24. The apparatus of any one of claims 12-16, wherein, The compensation circuit is configured to count the input clock signal in a period of the input synchronization reference signal of the plurality of clock domains to obtain a count result, compare the count result with a pre-designed count result to obtain a first comparison result, determine a first clock frequency deviation of a target time delay according to the first comparison result, adjust the time delay of the data link by adjusting an address of reading data to compensate for the first clock frequency deviation of the target time delay, or obtain a current address when a rising edge of the input synchronization reference signal arrives, compare the current address with an initial address to obtain a second comparison result, determine a second clock frequency deviation of the target time delay according to the second comparison result, and adjust the time delay of the data link by adjusting a position of a reading address in a random memory to compensate for the second clock frequency deviation of the target time delay, wherein the target time delay is a time from a start of resetting the output synchronization reference signal and the output clock signal to synchronous generation of the reset output synchronization reference signal and the reset output clock signal, and a storage depth of the random memory is a product of a ratio of a period of the input synchronization reference signal to a reading signal period and an inverse of N. The computer program is arranged to perform the method of any one of claims 1 to 11 when the computer program is run.

25. A computer readable storage medium having stored therein a computer program, wherein, ​ 26. An electronic device comprising a memory and a processor, the memory storing a computer program, the processor being configured to run the computer program to perform the method of any one of claims 1 to 11.

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