Window detection method, system, electronic device and storage medium for differential link

Abstract

The present application provides a window detection method, system, electronic device and storage medium for a differential link, and relates to the field of data processing. The method includes: splitting the differential signal in the differential link into a positive polarity signal and a negative polarity signal; collecting signal data of the positive polarity signal and the negative polarity signal under different delay times, respectively as the first data sequence and the second data sequence; performing inversion processing on the signal data in the second data sequence to obtain a third data sequence; selecting the delay time interval with the same data in the first data sequence and the third data sequence as the latch window of the differential signal. Based on the above processing, the present application compares the first data sequence and the third data sequence to screen out the stable intervals of the positive polarity signal and the negative polarity signal, thereby realizing rapid detection of the latch window position and size. Moreover, the present application belongs to a delay detection method for a data channel that does not require a training data set, and has great universality.

Description

Technical Field

[0001] The present invention belongs to the field of data processing, and in particular relates to a window detection method, system, electronic equipment and storage medium for a differential link. Background Art

[0002] Differential links are commonly found in various systems such as data acquisition and transmission. For example, in the field of machine vision, image sensors use differential links to collect image data and transmit it over long distances. In addition, as the resolution and output frame rate of image sensors continue to increase, the number of data channels in differential links also increases. For example, the data interface of an image sensor usually consists of a single clock and many data channels (for example, 144 data channels).

[0003] In differential links, due to the influence of routing delays and chip packaging parasitic parameters, there are always various delay differences between clock signals and differential signals, as well as between different differential signals, which eventually leads to the failure of the existing fixed data acquisition method of delaying the clock signal by 90 degrees. Especially when there are a large number of data channels, the effective latch window formed between different differential signals becomes smaller, affecting the data transmission efficiency of the differential link. Among them, the latch window refers to the time window that can stably acquire the logic level based on the effective clock edge of the clock signal.

[0004] Therefore, there is an urgent need for a window detection method for detecting the latch window of each differential signal in a differential link, so as to facilitate subsequent alignment processing of the latch windows of differential signals in different data channels. Summary of the invention

[0005] The present application proposes a differential link window detection method, system, electronic device and storage medium, which are used to detect the latch window of a differential signal in a differential link.

[0006] To achieve the above objectives, this application proposes the following technical solutions:

[0007] In a first aspect of the present application, a window detection method for a differential link is provided, comprising:

[0008] Splitting the differential signal in the differential link into a positive polarity signal and a negative polarity signal;

[0009] Collecting signal data of the positive polarity signal and the negative polarity signal at different delay times as a first data sequence and a second data sequence respectively;

[0010] The signal data in the second data sequence is inverted to obtain a third data sequence

[0011] A delay time interval having the same data in the first data sequence and the third data sequence is selected as a latch window for the differential signal.

[0012] Optionally, the signal receiving end of the differential link is configured as a fully differential circuit.

[0013] Optionally, the differential link includes a clock signal for collecting the signal data.

[0014] Optionally, the clock signal is used to collect the signal data after each of multiple consecutive delays.

[0015] Optionally, the delay is a fixed step size.

[0016] Optionally, the method further includes:

[0017] Obtaining a latch window of each data channel in the differential link; wherein each data channel is used to transmit a differential signal;

[0018] Determine the number of delay steps for each data channel based on the time value of the center of the latch window;

[0019] Based on the delay step number and delay chain of each data channel, delay compensation is performed on each data channel so that the time value of the center of the latch window in each data channel is the same.

[0020] Optionally, the method further includes:

[0021] Selecting a positive polarity signal or a negative polarity signal as a reference signal, and the remaining signal as a working signal for transmitting data in the differential link;

[0022] Delaying or advancing the reference signal by a preset time period as a signal to be compared;

[0023] Determine whether the signal data of the signal to be compared and the opposite value of the signal data of the working signal are the same, if so, keep the time position of the positive polarity signal and the negative polarity signal unchanged; if not, advance or delay the preset time period of the positive polarity signal and the negative polarity signal;

[0024] Among them, the opposite values ​​of the signal data of the signal to be compared and the signal data of the working signal are extracted from the same acquisition time; and the acquisition time is determined based on the clock signal in the differential link.

[0025] Optionally, the preset time period is within half of the latch window time length.

[0026] In a second aspect of the present application, a window detection system for a differential link is provided, comprising:

[0027] A signal splitting module, used for splitting the differential signal in the differential link into a positive polarity signal and a negative polarity signal;

[0028] A signal acquisition module, used for acquiring signal data of the positive polarity signal and the negative polarity signal at different delay times as a first data sequence and a second data sequence respectively;

[0029] A data inversion module is used to invert the signal data in the second data sequence to obtain a third data sequence.

[0030] The interval selection module is used to select a delay time interval with the same data in the first data sequence and the third data sequence as a latch window for the differential signal.

[0031] In a third aspect of the present application, an electronic device is provided, comprising a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other via the communication bus;

[0032] Memory, used to store computer programs;

[0033] The processor is used to implement the steps of any window detection method when executing the program stored in the memory.

[0034] In a fourth aspect of the present application, a computer-readable storage medium is provided, in which a computer program is stored. When the computer program is executed by a processor, the steps of any window detection method are implemented.

[0035] The beneficial effects of this application are as follows:

[0036] The present application provides a window detection method for a differential link, comprising: splitting a differential signal in the differential link into a positive polarity signal and a negative polarity signal; collecting signal data of the positive polarity signal and the negative polarity signal at different delay times as a first data sequence and a second data sequence, respectively; performing inversion processing on the signal data in the second data sequence to obtain a third data sequence; and selecting a delay time interval with the same data in the first data sequence and the third data sequence as a latch window for the differential signal.

[0037] Based on the above processing, the present application screens out the stable intervals of the positive polarity signal and the negative polarity signal by comparing the first data sequence and the third data sequence, and then uses the interval with the same data as the latch window, effectively realizing the rapid detection of the latch window position and size. In addition, the technical solution provided by the present application can directly detect the latch window position and size by processing the differential signal that continuously works in the differential link. It is a delay detection method for a data channel that does not require a training data set, has great universality, and can effectively improve the stability of data acquisition and transmission in high-speed differential links. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of this application. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0039] Figure 1 It is a flow chart of improving the effective latch window provided by the present application;

[0040] Figure 2 is a flow chart of a window detection method provided by the present application;

[0041] Figure 3 It is a flowchart of a window detection provided by this application;

[0042] Figure 4 It is a flow chart of a signal acquisition process provided by this application;

[0043] Figure 5 It is a schematic diagram of a latch window movement provided by the present application;

[0044] Figure 6 It is a schematic diagram of a latch window calibration process provided by the present application;

[0045] Figure 7 It is a flowchart of another latch window calibration provided by the present application;

[0046] Figure 8 It is a schematic diagram of a differential link workflow provided by this application;

[0047] Fig. 9 is a structural diagram of a window detection system provided by the present application;

[0048] Fig.10 It is a structural diagram of an electronic device provided by this application. DETAILED DESCRIPTION

[0049] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments.

[0050] Sending a digital signal can be understood as sending a sequence of 0s or 1s. When communicating with different devices, the timing information needs to be associated with the transmitted bits, so a clock signal is needed to provide timing signals for each part of the digital circuit system so that each signal data transmission process can be triggered at a precise time point. The clock signal is used to synchronize the digital signal transmitter and signal receiver during the data transmission process. Among them, the determined edge of the clock is also called the effective clock edge. The digital signal transmitter triggers new data transmission at each effective clock edge, and the signal receiver samples data at each effective clock edge.

[0051] In order to improve the anti-interference ability of signal transmission and suppress electromagnetic interference, the prior art usually uses differential signals to transmit the required digital signals. In the actual transmission process, the voltage change process on the two lines transmitting the differential signal takes a certain amount of time, resulting in a voltage change region for a period of time at both ends and a voltage constant region in the middle within a cycle of the differential signal. Correspondingly, at the effective clock edge of the clock signal, the signal receiving end can stably collect the logic "1" and logic "0" states from the voltage constant region. Among them, the voltage constant region in the above differential signal is defined as the latch window of the differential signal in this application. Alternatively, the latch window can also be understood as: when the signal receiving end samples the data on the digital line, the setup time and hold time form a stable window near the effective clock edge of the signal receiving end, so that the signal receiving end can reliably collect data.

[0052] Taking the field of machine vision as an example, image sensor data acquisition, long-distance transmission of image data and most other occasions use differential links. The level standards range from LVDS to sub-LVDS to SLVS, and the interface types range from CameraLink interface commonly used in industrial cameras, MIPI interface commonly used in mobile phones, and PCIE interface commonly used in computers. Almost all data acquisition systems are composed of front-end image sensors and back-end processors. Considering the complexity and cost of implementation, most image sensor data outputs currently use LVDS-like differential interfaces, and use no protocol (pure data mode) or MIPI protocol to output data. In order to be compatible with the driver design (generally FPGA or other embedded processors), the interface rate is usually below 1.6Gbps, and the double-edge (DDR) data latch mode is used.

[0053] With the continuous improvement of image sensor resolution and output frame rate, the image sensor data interface is usually composed of a single clock and many data channels (such as 144 data channels). Due to the influence of routing delays and chip packaging parasitic parameters, there are always various delay differences between the clock signal and data (that is, the differential signal in this application) and between the data and the data channel, which eventually leads to the original fixed data acquisition method of delaying the clock signal by 90 degrees gradually becoming invalid. Especially when the number of data channels is large, it usually leads to a smaller effective latch window of the differential signal. Among them, in the technical solution provided by the present application, the data channel represents a channel for transmitting a differential signal, and the effective latch window represents a common interval of different latch windows in multiple data channels.

[0054] See also Figure 1 , Figure 1 A schematic diagram of a process for improving the effective latch window provided by the present application. Figure 1 As shown in the figure, before the differential signals in each data channel are delayed and aligned, each data channel has a delay time relative to the reference time. The difference in this delay time is the result of factors such as the output delay of the data transmitter (for example, the image sensor), the wiring delay, the device package, and the parasitic parameters in the device. This results in a very small effective latch window under a unified latch signal, which is very likely to cause bit errors. By calculating the delay amount of each data channel, as shown in Figure 1 By using the delay chain to compensate for the delay, the data channels can be aligned. At this time, the effective latch window in the differential link can be greatly improved, thereby ensuring data integrity and avoiding bit errors.

[0055] In order to solve the problem of the effective latch window becoming smaller in the existing differential link, it is necessary to first detect the latch window position and size of each data channel. Based on this, the present application provides a window detection method for a differential link, such as Figure 2 As shown, the window detection method includes the following steps:

[0056] S201 . Split a differential signal in a differential link into a positive polarity signal and a negative polarity signal.

[0057] S202 : Collect signal data of the positive polarity signal and the negative polarity signal at different delay times as a first data sequence and a second data sequence, respectively.

[0058] S203: Perform inversion processing on the signal data in the second data sequence to obtain a third data sequence.

[0059] S204: Select a delay time interval with the same data in the first data sequence and the third data sequence as a latch window for a differential signal.

[0060] Based on the above processing, the present application screens out the stable intervals of the positive polarity signal and the negative polarity signal by comparing the first data sequence and the third data sequence, and then uses the interval with the same data as the latch window, effectively realizing the rapid detection of the latch window position and size. In addition, the technical solution provided by the present application can directly detect the latch window position and size by processing the differential signal that continuously works in the differential link. It is a delay detection method for a data channel that does not require a training data set, has great universality, and can effectively improve the stability of data acquisition and transmission in the differential link.

[0061] For step S201, a fully differential circuit is set at the signal receiving end of the differential link, and then the differential signal in the differential link is split into a positive polarity signal and a negative polarity signal based on the fully differential circuit. In view of the characteristics of the existence of positive and negative end signals in the differential signal, the signal receiving end adopts a circuit with differential input and differential output (for example, a fully differential amplifier) ​​to receive the differential signal and still convert it to differential processing. Each data channel is actually divided into two sub-data channels at the signal receiving end according to the differential positive and negative end signals, including a positive sub-data channel and a negative sub-data channel. Among them, the positive sub-data channel is used to transmit the positive end signal (that is, the positive polarity signal), and the negative sub-data channel is used to transmit the negative end signal (that is, the negative polarity signal). The above scheme is effectively different from the traditional method in which the signal receiving end adopts differential input, and the single-ended output amplifier converts the differential signal to a single-ended post-processing process.

[0062] Due to the asymmetry of the circuit parameters on the signal transmitting end, the slight difference in the routing delay (differential signal routing is generally required to be equal in length, but there will still be a delay difference), the load difference on the signal receiving end, etc., there will be a slight delay difference between the two sub-data channels. However, this delay difference is generally within 100ps, which can be basically ignored for a bit width of 10ns. The adverse effects brought by this solution can actually be understood as only losing part of the latch window.

[0063] In some embodiments, the differential link includes a clock signal. Accordingly, step S202 may include the following steps:

[0064] S20201. Based on a fixed delay step, delay the clock signal in the differential link multiple times.

[0065] S20202. After each delay, collect signal data of the positive polarity signal and the negative polarity signal based on the delayed clock signal.

[0066] In actual work, the clock signal can be delayed by a delay chain to scan the data channel to collect multiple signal data of positive polarity signals and negative polarity signals. That is, each time the clock signal moves a fixed value step, data of positive polarity signals and negative polarity signals are collected. Specifically, step S202 includes the following steps:

[0067] S20203. Use a delay chain to continuously delay the clock signal in the differential link for multiple times, wherein the step lengths between different delays are the same.

[0068] S20204. After each delay, collect signal data of the positive polarity signal and the negative polarity signal based on the clock signal.

[0069] With respect to step S20203, in the process of delaying the clock signal of the delay chain to scan the data channel, the clock signal can be moved by one step each time, and data of the positive polarity signal and the negative polarity signal can be collected. The signal data of the positive polarity signal collected after the first delay is set as D1, and the signal data of the negative polarity signal is set as B1. If it is assumed that the clock signal is delayed and moved n times, the data sequence D1-Dn of the positive polarity signal data and the data sequence B1-Bn of the negative polarity signal data can be obtained.

[0070] Based on the above processing, the data sequence D1-Dn of the positive polarity signal data is used as the first data sequence, and the data sequence B1-Bn of the negative polarity signal data is used as the second data sequence. Then, each sampled data in the second data sequence is inverted to obtain the inverted data sequence C1-Cn as the third data sequence.

[0071] Then, D1-Dn and C1-Cn are compared. When the acquisition interval is in the unstable interval (such as Figure 3 The interval where D1 or C1 is located). At this time, since the differential signal has not yet stabilized and the slight delay difference of the positive and negative signals and the delay difference of the sampling clock routing are superimposed, D1 is not always equal to C1 (that is, the unstable interval in the differential signal). Under a certain clock step, by detecting the data changes over a period of time, the comparison result of Dx! = Cx can always be obtained for the unstable area. For the stable interval, the comparison result of Dx=Cx can always be obtained. Among them, Dx represents the signal data of the positive polarity signal collected after the xth delay, and Cx represents the signal data of the negative polarity signal collected after the xth delay. Therefore, the effective latch window of the data channel can be obtained by comparing the data sequence results, such as Figure 3 The Dj-Dk or Cj-Ck interval is shown in .

[0072] In the actual working process, the signal data (such as D1, C1, etc.) sampled after each delay can be a 1-bit or multi-bit binary value. Among them, the total number of bits in the signal data is related to the number of samplings after each delay. Specifically, after each delay of the clock signal, based on the effective clock edge of the clock signal, the above-mentioned positive polarity signal and negative polarity signal can be sampled once or multiple times for logic level, thereby obtaining a 1-bit or multi-bit binary value as the signal data. For example, if the number of samplings is 5, the corresponding sampling data D1 is "01110", B1 is "10001", and C1 after inverting B1 is "01110". At this time, the data in D1 and C1 are exactly the same, indicating that D1 matches C1, that is, D1=C1.

[0073] In addition, in actual operation, the window detection method provided by the present application does not require storing the complete data sequence (for example, D1-Dn and C1-Cn) before performing data comparison. Instead, data comparison can be performed simultaneously during the sampling process of the signal data to improve the efficiency of latch window detection.

[0074] This application uses a fully differential circuit at the signal receiving end to split the original data channel into two positive and negative sub-channels (i.e., split the differential signal into a positive polarity signal and a negative polarity signal), and simultaneously scans and collects data on the two sub-channels, and then compares the data collected by the two sub-channels to obtain the latch window position and size in the data channel (i.e., the differential signal in this application). It is worth noting that the above processing process eliminates the requirement that the data channel must output a training data set, and can be applied to the collection of all data signals based on differential links.

[0075] It is worth noting that the signal data of the positive polarity signal and the negative polarity signal are collected in different signal cycles under different delay times. Among them, signal data is usually collected only once in each signal cycle. In the technical solution provided in the present application, the position of the latch window of the differential signal is basically fixed in different signal cycles. The window detection method provided in the present application can be understood as: in multiple signal cycles, the data sequences of the positive polarity signal and the negative polarity signal under different delay times are collected respectively, and the data in the above two data sequences are compared (before comparison, the data sequence of the negative polarity signal has been inverted), and the delay time interval corresponding to the same comparison result is used as the latch window of the differential signal.

[0076] In addition, the present application proposes that the additional cost of a fully differential (i.e., differential input and differential output) receiving circuit relative to a differential to single-ended (i.e., differential input and single-ended output) circuit is basically negligible, and most existing FPGAs support fully differential input circuits. Therefore, the above-mentioned window detection method for the differential link can be implemented based on FPGA.

[0077] In some embodiments, the latch window can also be detected by link training data set and delay chain scanning. That is, the signal output end (such as an image sensor) is set to output fixed pattern data as a training data set (Training Pattern), and the signal receiving end (usually an FPGA) calculates the delay of each data channel by detecting the training data.

[0078] The delay of each channel can be calculated by scanning the delay chain and outputting a fixed training data set from the image sensor, such as Figure 1 Specifically, the clock channel is delayed by a delay chain (the data channel is not delayed at this time, or another operation mode is: the clock channel is not delayed, and the data channel is moved one step each time, the principle is the same) to scan the data channel, move one step each time and collect data, let the data collected for the first time be D1, then after moving n times, the data sequence from D1 to Dn can be obtained. Because the data channel output is a fixed-mode training data set at this time, it is only necessary to find the data sequence that meets the training data set from D1-Dn, and its corresponding interval (such as Figure 4 The interval Dj-Dk in the figure is the latch window position and size of the data channel. Figure 4 The effective latch window position of the data channel shown in the figure is j, and the window size is kj, and the unit is the number of delay chain steps. According to this method, the window position and size of all data channels can be obtained, which can prepare for the next step of aligning all data channels through delay compensation.

[0079] Based on the above processing, the window position and size of all data channels can be obtained, thereby increasing the size of the effective latch window. However, this method depends on the training data set of the data channel. If the signal sending end (such as the image sensor or the data sending module) does not support the training data set output mode, this method will fail directly.

[0080] After completing the latch window detection in the differential link, each data channel can be delayed and supplemented through a delay chain to maximize the data latch window, including the following steps:

[0081] Step a: obtaining a latch window of each data channel in the differential link, wherein each data channel is used to transmit a differential signal.

[0082] Step b: Determine the delay step value of each data channel based on the time value of the center of the latch window.

[0083] Step c: Based on the delay step value and delay chain of each data channel, delay compensation is performed on each data channel in the differential link to make the time value of the center of the latch window in each data channel the same.

[0084] Among them, the above steps ac can be completed by the delay chain integrated inside the FPGA. Specifically, after the differential signal is scanned by the delay chain delay clock signal, the delay step interval corresponding to the latch window interval of different differential signals is obtained. For example, the delay step numbers contained in a certain delay step number interval are "3, 4, 5, 6, 7" respectively. Among them, the latch window of the differential signal can be obtained using the above delay step interval, and the delay step number 5 is used as the center point of the latch window. Then, the delay chain is used to delay compensate the differential signal so that the sampling point of the differential signal is set at the center of the latch window, that is, the effective clock edge of the clock signal corresponds to the center point of the latch window.

[0085] For differential links that have completed delay alignment or for differential links that do not require delay alignment, delay alignment is often only performed once when the signal output end (such as the image sensor) is powered on and initialized, and no adjustment is made during subsequent normal operations. When the working environment of the image sensor and the signal receiving end (FPGA) undergoes significant changes, such as temperature changes, changes in certain working voltages may cause the original latch window to shift when the link rate is high, causing the previously set sampling points to no longer be valid, thereby causing bit errors.

[0086] Specifically, the latch window detection and calibration process is usually completed when the sensor is powered on and initialized. Once the sensor enters the normal working state, the image sensor continuously outputs data streams and usually does not re-perform window detection and calibration during operation. Figure 5 As shown in the figure, if the operating temperature of the image sensor changes significantly (such as rising from about 25 degrees during cold start to 60-70 degrees under full speed operation), and the differential link rate is high (above 1Gbps), and the power supply ripple of the data interface on the image sensor side is not well controlled, the offset relationship between the clock signal and the data channel may change significantly compared to the detection at power-on initialization. If the original latch window interval is too small, it is likely to cause the original sampling point position to fail and lead to data acquisition errors. At this time, many noise-like pixels will appear in the image data.

[0087] In view of the above situation, the present application also provides a differential link calibration method for solving the latch window transfer problem caused by changes in the working environment, so as to avoid the bit error problem that may be caused by the latch window transfer. After completing the splitting of the differential signal in the differential link into a positive polarity signal and a negative polarity signal, the method includes the following steps:

[0088] S301. Select a positive polarity signal or a negative polarity signal as a reference signal, and the remaining signal as a working signal for transmitting data in a differential link.

[0089] S302, determine whether the signal data of the working signal and the signal opposite value of the first signal to be compared are the same. If so, keep the original time position of the positive polarity signal and the negative polarity signal unchanged; if not, move the positive polarity signal and the negative polarity signal in the opposite direction to a preset time period relative to the original time position.

[0090] The first signal to be compared is a signal after a preset time period of the forward moving reference signal. The forward moving is represented by a time delay or a time advance, and the reverse moving is the opposite time operation relative to the forward moving. Specifically, if the forward moving is a time delay, the reverse moving is a time advance.

[0091] The signal data of the working signal and the signal opposite value of the first signal to be compared are collected at the same time. The signal opposite value of the signal to be compared is obtained by inverting the collected signal data of the signal to be compared.

[0092] Based on the above processing, the present application transmits the data in the differential link through the working signal to ensure the normal operation of the differential link. At the same time, by adjusting the reference signal and comparing it with the working signal, it can predict the sampling point failure problem that may occur in the differential link, and perform latch window calibration in advance by moving the positive polarity signal and the negative polarity signal in reverse, thereby avoiding the bit error problem that may be caused by the latch window transfer.

[0093] For step S302, the working signal is used to transmit valid data of the differential signal in the differential link. Specifically, the working signal is used as a carrier for data transmission and signal acquisition is performed, and the acquired signal data is always within the latch window of the working signal, thereby ensuring normal data transmission.

[0094] In one implementation, the differential link includes a clock signal for collecting the signal data, wherein the signal data is collected based on the effective clock edge of the clock signal, ensuring that the signal data collected from different signals are at the same collection time.

[0095] In some embodiments, the present application also provides a dynamic calibration method for a latch link, such as Figure 7 As shown, after step S301, the dynamic calibration method includes the following steps:

[0096] S401, execute the data judgment step, if not, go to S402; if yes, go to S403. The data judgment step includes judging whether the signal data of the working signal and the signal opposite value of the first signal to be compared are the same.

[0097] S402, reversely move the positive polarity signal and the negative polarity signal to a preset time period relative to the original time position, and go to S401.

[0098] S403, determine whether the signal data of the working signal and the signal opposite value of the second signal to be compared are the same; if so, go to S404, if not, go to S405. The second signal to be compared is obtained by moving the reference signal in the reverse direction for a preset time period.

[0099] S404: Keep the original time positions of the positive polarity signal and the negative polarity signal unchanged, and go to S401.

[0100] S405 , positively move the positive polarity signal and the negative polarity signal to a preset time period relative to the original time position, and go to S401 .

[0101] Based on the above processing, dynamic calibration of the differential link is achieved, thereby ensuring the accuracy of data collection during the overall data transmission process.

[0102] After the positive polarity signal and the negative polarity signal are moved forward or reversely to a preset time period relative to the original time position, the moved signal needs to be checked to confirm whether a calibration is completed. That is, in the aforementioned steps S402 and S405, the above-mentioned checking process is performed before going to step S401.

[0103] Specifically, in step S402 or S405, the following contents are included:

[0104] Step A, determine whether the positive polarity signal and the negative polarity signal after the movement match. If so, complete a calibration and go to S401; if not, go to step B. Wherein, the movement includes forward movement and reverse movement. The matching determination method is: determine whether the signal data of the positive polarity signal after the movement and the signal opposite value of the negative polarity signal after the movement are the same.

[0105] Step B: cancel the operation of moving the positive polarity signal and the negative polarity signal to the preset time period relative to the original time position, and reduce the length of the preset time period, and go to S401.

[0106] Based on the above processing, after canceling the operation of moving the positive polarity signal and the negative polarity signal to the preset time period relative to the original time position, the time length of the preset time period is shortened, and the differential signal is dynamically calibrated again. It is worth noting that by shortening the length of the preset time period, the time length of the reference time delay or advance can be reduced, which not only improves the detection accuracy of the latch window movement, but also can realize dynamic calibration when the latch window interval becomes smaller.

[0107] In actual work, after step S301, the calibration method further includes the following steps:

[0108] S303. Compare whether the signal data of the left-shifted signal to be compared and the opposite value of the signal of the working signal are the same at the same acquisition time; if not, go to step S304. Here, the left-shifted signal to be compared refers to the signal obtained by advancing the reference signal by a preset time period.

[0109] S304. Delay the positive-polarity signal and the negative-polarity signal by a preset time period.

[0110] Based on the above processing, when advancing the reference signal by a preset time period, by comparing the left-shifted signal to be compared and the working signal, if the comparison results are the same, it can be known that the original latch window has a certain margin in the time-advancing direction, so there is no need to delay or advance the differential signal. If the comparison results are different, it can be known that the margin of the latch window in the time-advancing direction is low. Therefore, subsequently, both the positive-polarity signal and the negative-polarity signal are delayed by a preset time period relative to their original positions to increase the margin of the latch window in the time-advancing direction. As Figure 5 shown, based on the above processing, the problem of low margin in the leftward movement direction (i.e., the time-advancing direction) of the latch window is solved.

[0111] In one implementation, after step S304, the dynamic calibration method further includes the following steps:

[0112] S305. If so, compare whether the signal data of the right-shifted signal to be compared and the opposite value of the signal of the working signal are the same at the same acquisition time. If not, go to S306. If so, go to S303. Here, the right-shifted signal to be compared refers to the signal obtained by delaying the reference signal by a preset time period.

[0113] S306. Advance the positive-polarity signal and the negative-polarity signal by a preset time period.

[0114] Based on the above processing, if the comparison results of the right-shifted signal to be compared and the working signal are different, it can be known that the margin of the latch window in the time-delay direction is low. Therefore, subsequently, both the positive-polarity signal and the negative-polarity signal are advanced by a preset time period relative to their original positions to increase the margin of the latch window in the time-delay direction, thereby solving the problem of low margin in the rightward movement direction (i.e., the time-delay direction) of the latch window.

[0115] In addition, the length of the preset time period can be determined by the latch window interval of the differential signal. Specifically, the preset time period is within half of the latch window time length. That is, the range of the preset time period is: 0 < T < S / 2. Here, T represents the preset time period, and S represents the time length of the latch interval of the differential signal.

[0116] After completing the power-on initialization window detection and calibration, the sampling points of the positive-polarity signal and the negative-polarity signal obtained by splitting each differential signal are all at the optimal positions (i.e., the center of the effective window), that is Figure 6The corresponding relationship between the clock signal and the data positive subchannel and the data negative subchannel at the original position is shown in . Therefore, the length of the preset time period is set to not more than half of the latch window size. Usually, the window is cut into N equal parts according to the effective window size, and the delay time represented by each equal part is TN. Figure 6 As shown, by performing a 90-degree periodic phase shift on the negative polarity signal in the data negative sub-channel relative to the effective window, that is, N is set to 4, and the preset time period TN is set to one quarter of the latch window size.

[0117] In actual work, Figure 6 As shown, after the power-on calibration is completed, the positive polarity signal in the data positive sub-channel is set as the working signal, and the negative polarity signal in the data negative sub-channel is operated as follows:

[0118] Step 1: Shift the data to the left by TN (i.e., the positive shift in this application) relative to the original position as the first signal to be compared. Detect the data matching of the positive and negative sub-channels within the time t0. If the data matches completely, it means that the latch window margin on the right side of the sampling point is sufficient, and jump to step 2, otherwise jump to step 3.

[0119] The detection of data matching of the positive and negative sub-channels within the time t0 indicates that the data sampling of the positive polarity signal and the negative polarity signal is completed within the time range of the time period length t0, and the sampled signal data are compared to see whether they are the same. The data sampling process is also as follows: the acquisition of the positive polarity signal and the negative polarity signal is completed through the effective clock edge of the clock signal.

[0120] Step 2: Shift right TN relative to the original position (i.e., reverse shift in this application) as the second signal to be compared. Measure the data matching of the positive and negative sub-channels within time t0. If the data matches completely, it means that the latch window margin on the left side of the sampling point is sufficient, and jump to step 1, otherwise jump to step 4.

[0121] Step 3: Entering this step means that due to environmental changes, the latch window margin on the right side of the current sampling point is insufficient, and the entire data channel needs to be moved to the right by TN. Note that the positive and negative sub-channels of the data need to be moved to the right by TN at the same time, and jump to step 5.

[0122] Step 4: Entering this step means that due to environmental changes, the latch window margin on the left side of the current sampling point is insufficient, and the entire data channel needs to be moved to the left by TN. Note that the positive and negative sub-channels of the data need to be moved to the left by TN at the same time, and jump to step 5.

[0123] Step 5. Entering this step means that the position of the original latch window has just been adjusted, and the validity of the adjusted position needs to be tested. The data matching of the positive and negative sub-channels is tested within the t0 time. If the data matches completely, it means that there is no problem with the adjusted window position; if not, cancel the latch window movement in steps 3 and 4 and re-enter step 1.

[0124] In step 5, if there is still data mismatch (bit error) after dynamic adjustment and calibration of the latch window, the current strategy is to cancel the previous adjustment operation and re-perform window detection. Before re-performing window detection, the time length of TN can be shortened to reduce the time length of reference time delay or advance, which not only improves the detection accuracy of latch window movement, but also enables dynamic calibration when the latch window interval becomes smaller.

[0125] In addition, there is an extreme case where there is a data mismatch in the adjustment window, that is, the original latch window is small, and after being affected by changes in environmental factors such as temperature, the effective latch window is further compressed to the point where there is no effective latch window. Otherwise, dynamic adjustment and calibration of the latch window will improve the sampling accuracy of the sampling point.

[0126] It is worth noting that in the above-mentioned movement process (i.e., delay or advance), the original position of the positive polarity signal or the negative polarity signal is used as the reference point. Among them, the original position represents the time position before the calibration method is executed. Specifically, if the latch window is only calibrated once during the differential signal transmission process, the original position can be understood as the time position after the delay compensation of the differential signal is completed. If the latch window is dynamically calibrated multiple times during the differential signal transmission process, the original position corresponds to the time position after the last calibration is completed.

[0127] The process of simultaneously moving the data positive and negative sub-channels to the right by TN in the above step 3 may be: after step 1 is completed, the negative polarity signal in the data negative sub-channel is restored to the original position, and both the positive polarity signal and the negative polarity signal are moved to the right by TN in step 3. Alternatively, the process may also be: after step 1 is completed, the negative polarity signal in the data negative sub-channel is not restored to the original position, but in step 3, the positive polarity signal is moved to the right by TN, and the negative polarity signal is moved to the right by 2 times TN.

[0128] Note that the above dynamic window detection and calibration method does not sacrifice data integrity, that is, by dynamically adjusting the data negative sub-channel, the possible sampling point failure problem is predicted in advance and the window calibration is performed in advance. At this time, the data is always collected using the data positive sub-channel as the sample and the collected data is always within the valid window, that is, the data collection process is always accurate.

[0129] In addition, the granularity and step size of the window calibration can be adjusted by setting the TN size, and the frequency of the window calibration can be set by t0. Among them, the calibration frequency in the dynamic calibration can be increased by reducing the value of t0. According to the time when the delay amount setting inside the existing FPGA takes effect, the technical solution provided by the present application can support a calibration frequency of milliseconds, and can cope with all factors of changes in external environmental conditions that can affect the change of the effective data latch window, such as the most important temperature change.

[0130] In addition, the above-mentioned window detection method and dynamic calibration method can be applied separately or simultaneously in FPGA. Among them, the window detection method can be combined with the internal delay chain of FPGA to obtain the effective latch window position and size of each data channel and perform delay compensation, which can maximize the data latch window and ensure data integrity. At the same time, the calibration method of the latch window can be used to solve the bit error problem that may be caused by the transfer of the data latch window. The above method does not rely on the training data set, has great universality, can greatly increase the stability of differential signal data acquisition and transmission, and provide a strong guarantee for many image acquisition and transmission occasions in the field of machine vision.

[0131] See also Figure 8 , the window detection and calibration method provided in this application can be applied to FPGA. The specific workflow is as follows Figure 8 As shown, at the initial moment, the transmission system of the differential link performs power-on processing and completes internal initialization of the signal transmitter and the signal receiver. Among them, the dynamic detection and calibration of the link (i.e., latch window) can be used as a configuration option. When enabled, after completing the power-on initialization window detection and calibration, the dynamic detection and calibration module will perform real-time calibration of the latch window during the working process. If it is not enabled, it will end after completing the power-on initialization window detection and calibration, that is, the position of the sampling point is always fixed in the subsequent work. When the differential link rate is not high or the window is large, and the link is relatively stable, a single power-on detection and calibration can be used.

[0132] In some embodiments, the present application also provides a differential link window detection system, such as Fig. 9 As shown, the window detection system includes:

[0133] The signal splitting module 901 is used to split the differential signal in the differential link into a positive polarity signal and a negative polarity signal.

[0134] The signal acquisition module 902 is used to acquire signal data of positive polarity signals and negative polarity signals at different delay times as a first data sequence and a second data sequence, respectively.

[0135] The data inversion module 903 is used to perform inversion processing on the signal data in the second data sequence to obtain a third data sequence.

[0136] The interval selection module 904 is used to select a delay time interval with the same data in the first data sequence and the third data sequence as a latch window for the differential signal.

[0137] The present application also provides an electronic device, such as Fig.10 As shown, it includes a processor 1001, a communication interface 1002, a memory 1003 and a communication bus 1004, wherein the processor 1001, the communication interface 1002, and the memory 1003 communicate with each other through the communication bus 1004.

[0138] Memory 1003, used for storing computer programs;

[0139] The processor 1001 is configured to implement any of the above-mentioned window detection methods for differential links when executing the program stored in the memory 1003 .

[0140] The communication bus mentioned in the above electronic device can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The communication bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, only one thick line is used in the figure, but it does not mean that there is only one bus or one type of bus.

[0141] The communication interface is used for communication between the above electronic device and other devices.

[0142] The memory may include a random access memory (RAM) or a non-volatile memory (NVM), such as at least one disk memory. Optionally, the memory may also be at least one storage device located away from the aforementioned processor.

[0143] The above-mentioned processor can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0144] In another embodiment provided in the present application, a computer-readable storage medium is provided, in which a computer program is stored. When the computer program is executed by a processor, the steps of the window detection method of any differential link described above are implemented.

[0145] In another embodiment provided by the present application, a computer program product including instructions is also provided. When the computer program product is run on a computer, the computer executes the steps of the window detection method for a differential link in any of the above embodiments.

[0146] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A window detection method for a differential link, characterized in that: include: Splitting the differential signal in the differential link into a positive polarity signal and a negative polarity signal; Collecting signal data of the positive polarity signal and the negative polarity signal at different delay times as a first data sequence and a second data sequence respectively; performing inversion processing on the signal data in the second data sequence to obtain a third data sequence; Selecting a delay time interval in which data in the first data sequence and the third data sequence are the same as each other as a latch window for the differential signal; The differential link includes a clock signal; The collecting of signal data of the positive polarity signal and the negative polarity signal at different delay times includes: Based on a fixed delay step, the clock signal in the differential link is delayed multiple times; After each delay, signal data of the positive polarity signal and the negative polarity signal are collected based on the delayed clock signal.

2. The method according to claim 1, characterized in that The signal receiving end of the differential link is configured as a fully differential circuit.

3. The method according to any one of claims 1 to 2, characterized in that: The method further comprises: Obtaining a latch window of each data channel in the differential link; wherein each data channel is used to transmit a differential signal; Determine the number of delay steps for each data channel based on the time value of the center of the latch window; Based on the delay step number and delay chain of each data channel, delay compensation is performed on each data channel so that the time value of the center of the latch window in each data channel is the same.

4. The method according to claim 3, characterized in that The method further comprises: Selecting a positive polarity signal or a negative polarity signal as a reference signal, and the remaining signal as a working signal for transmitting data in the differential link; Determine whether the signal data of the working signal and the signal opposite value of the first signal to be compared are the same, if so, keep the original time positions of the positive polarity signal and the negative polarity signal unchanged; if not, move the positive polarity signal and the negative polarity signal in the opposite direction to a preset time period relative to the original time position; Among them, the first signal to be compared is a signal after the reference signal is moved forward for a preset time period; the forward movement is represented by time delay or time advance, and the reverse movement represents the opposite time operation relative to the forward movement; the signal data of the working signal and the opposite signal value of the first signal to be compared are collected at the same time; the opposite signal value of the signal to be compared represents the value obtained after inverting the collected signal data of the signal to be compared.

5. The method according to claim 4, characterized in that The preset time period is within half of the latch window time length.

6. A window detection system for a differential link, characterized in that: include: A signal splitting module, used for splitting the differential signal in the differential link into a positive polarity signal and a negative polarity signal; A signal acquisition module, used for acquiring signal data of the positive polarity signal and the negative polarity signal at different delay times as a first data sequence and a second data sequence respectively; A data inversion module is used to invert the signal data in the second data sequence to obtain a third data sequence. An interval selection module, used for selecting a delay time interval with the same data in the first data sequence and the third data sequence as a latch window for the differential signal; The differential link includes a clock signal; The collecting of signal data of the positive polarity signal and the negative polarity signal at different delay times includes: Based on a fixed delay step, the clock signal in the differential link is delayed multiple times; After each delay, signal data of the positive polarity signal and the negative polarity signal are collected based on the delayed clock signal.

7. An electronic device, characterized in that: It includes a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other through the communication bus; Memory, used to store computer programs; A processor, for implementing the window detection method according to any one of claims 1 to 5 when executing a program stored in a memory.

8. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the window detection method according to any one of claims 1 to 5 is implemented.

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