Multi-objective optimization design method for DC bus capacitor of motor drive

Abstract

The present invention discloses a multi-objective optimization design method for a DC bus capacitor of a motor driver, which belongs to the field of power electronics technology and includes the following steps: S1 setting design objectives and constraints; S2 constructing various models of the DC bus capacitor, calculating various performance parameters of the DC bus capacitor, and obtaining performance indicators of the DC bus capacitor; S3 comprehensively analyzing various design parameters, evaluating the performance of multiple design schemes, and using a genetic algorithm to select and output the optimal design scheme to ensure that it meets the preset design objectives and constraints. The multi-objective optimization design method provided by the present invention can select a suitable capacitor group to achieve multi-objective optimization without relying on much engineering experience and comprehensively considering limiting factors such as volume and cost.

Description

Technical Field

[0001] The present invention belongs to the technical field of power electronics and relates to a multi-objective optimization design method for a DC bus capacitor of a motor driver. Background Art

[0002] With the widespread application of permanent magnet synchronous motors (PMSMs) in industrial and commercial applications such as electric vehicles, aerospace, and robotics, the demand for the design and optimization of DC link capacitors in drive systems is increasing. DC link capacitors play a vital role in regulating instantaneous power differences in the power supply, reducing power supply voltage fluctuations, and lowering harmonic currents, especially in applications with high dynamic load changes. Effective capacitor design can not only significantly improve the overall efficiency and reliability of the system, but also effectively reduce cost and space. Traditionally, the selection and design of DC link capacitors mainly rely on empirical rules and manufacturer's standard recommendations. Although this method is simple, it often fails to meet the optimal performance requirements of specific applications.

[0003] Currently, many researchers have begun to explore more systematic and scientific methods to optimize the performance and cost of capacitors, including using series and parallel configurations of capacitors to achieve the required capacitance value and voltage level while minimizing size and weight. There are also studies focusing on optimizing the electrical performance of capacitors, such as improving the equivalent series resistance (ESR) and equivalent series inductance (ESL) of capacitors. These parameters directly affect the efficiency and thermal management of motor drive systems. At the same time, the development of life prediction models has also become a key area in DC bus capacitor research. Researchers attempt to use physical models to predict the aging and failure modes of capacitors under different operating conditions, thereby improving system reliability and reducing maintenance costs.

[0004] CN116915079A discloses a method for minimizing the DC bus capacitance of a hybrid multi-level converter. The method includes: obtaining system parameters of the hybrid multi-level converter during operation; determining a modulation wave; determining the duty cycle of each switch based on the modulation wave; determining the total neutral point current of the system; determining the fundamental component of the voltage of the upper and lower DC bus capacitors of the system; determining the maximum voltage fluctuation of the upper and lower DC bus capacitors; and determining the minimum DC bus capacitance value that meets the system capacitance voltage fluctuation requirement by traversing the capacitance values.

[0005] CN117614255A discloses a method for reducing the ripple current of a DC bus capacitor. An energy storage inductor is arranged between the positive electrode of a battery and the positive electrode of a DC bus capacitor. A control circuit controls the energy storage inductor to charge or discharge to a motor according to the direction and magnitude of the current flowing through the DC bus capacitor, thereby reducing the charging or discharging current of the DC bus capacitor, and further reducing the ripple current of the DC bus capacitor, thereby reducing the temperature rise of the DC bus capacitor during operation, and thus extending the service life of the DC bus capacitor.

[0006] CN213342023U discloses an inverter power supply for estimating the life of a DC bus capacitor. The power supply comprises a power supply unit, a rectifier unit, a bus capacitor unit, an inverter unit, a load unit, a main control system, and a human-machine interface. The main control system collects the voltage of the bus capacitor unit and calculates the relationship between the bus capacitor value and time based on the discharge time when the bus is powered off. The DSP chip calculates the service life of the capacitor and transmits the calculated value to the human-machine interface via communication. The human-machine interface can monitor the capacitor life in real time.

[0007] CN110460295A discloses a method for suppressing harmonics in DC bus capacitor current using phase shifting. The method employs a carrier phase shifting method to phase-shift the four PWM signals of a four-unit permanent magnet synchronous motor. The specific processing method is as follows: If the initial phase of the PWM signal controlling the first voltage source inverter is 0°, the initial phase of the PWM signal for the second inverter is 90°, the initial phase of the PWM signal for the third inverter is 180°, and the initial phase of the PWM signal for the fourth inverter is 270°. This method, applied to a four-unit permanent magnet synchronous motor control system, can improve the current harmonics of the DC bus filter capacitor in the system, extend the service life of the DC bus capacitor and motor driver, and improve the reliability of the motor system.

[0008] CN110086369A discloses a method for selecting and evaluating a DC bus capacitor and an application device thereof. After determining the output voltage and output current of a three-phase DC / AC converter for a candidate DC bus capacitor, the total arm trunk current of the three-phase DC / AC converter is determined based on the output voltage and output current and the modulation strategy of the three-phase DC / AC converter. Then, based on the total arm trunk current, the half-bus ripple current of the three-phase DC / AC converter is extracted. Finally, based on the half-bus ripple current and the DC bus capacitor voltage fluctuation amplitude requirement of the three-phase DC / AC converter, the DC bus capacitor capacity of the three-phase DC / AC converter is calculated.

[0009] However, while these studies have achieved improvements in a single aspect of capacitor performance, they often fail to fully consider the multiple key factors that influence design. For example, focusing on cost reduction may sacrifice capacitor reliability; or, to reduce capacitor design requirements, robust bus voltage control may be introduced, increasing the complexity of drive control and the risk of loss of control. Single-variable optimization often ignores how to balance the diverse requirements of these capacitors. Its limitations result in failure to achieve optimal global performance, making it difficult to implement in practical applications. Summary of the Invention

[0010] The purpose of this invention is to provide a multi-objective optimization design method for DC bus capacitors in motor drives, aiming to improve their performance and economic efficiency. By comprehensively considering multiple capacitor design factors, the optimal design of DC bus capacitors for permanent magnet synchronous motor drives is achieved. This objective is achieved through the following specific technical solutions.

[0011] The multi-objective optimization design method for the DC bus capacitor of the motor drive includes the following steps:

[0012] S1 sets design goals and constraints based on system parameters, system indicators, design variables and capacitance database;

[0013] S2 constructs various models of DC bus capacitors, calculates various performance parameters of DC bus capacitors, and obtains performance indicators of DC bus capacitors;

[0014] S3 comprehensively analyzes various design parameters, evaluates the performance of multiple design options, and uses genetic algorithms to select and output the optimal design solution that comprehensively considers lifespan, cost, and volume to ensure that it meets the preset design goals and constraints.

[0015] Furthermore, the design goal in step S1 is that the service life reaches a specified value; the constraint condition is that both the cost and the volume do not exceed the specified values.

[0016] Furthermore, the various models of the DC bus capacitor in step S2 include an equivalent series resistance (ESR) model, a loss model, a heat dissipation area model, a heat dissipation model, a life model, a cost model, and a volume model.

[0017] Furthermore, the equivalent series resistance model is shown as follows:

[0018] ,

[0019] Where ESR stands for equivalent series resistance, ESR ( C, f i , T h ) is the frequency f i and temperature T h The equivalent series resistance, ESR rated ( C ) is the ESR at rated frequency, which is a function of capacitance. ESR ( fi,T h ) is related to the frequency f i and temperature T h The relevant ESR coefficient, k 1,ESR and k 2,ESR They are the coefficients describing the dielectric resistance and package resistance related to the capacitor ESR, C is the DC bus capacitance.

[0020] Furthermore, the ESR calculated according to the equivalent series resistance model is rated ( C ), the power loss is calculated using a loss model, which is shown in the following formula:

[0021] ,

[0022] Where, P loss is the power loss, I rms ( f i ) is the current flowing through the capacitor at frequency f i The effective value of m Representative m Subharmonic current.

[0023] Furthermore, the heat dissipation model is shown as follows:

[0024] ,

[0025] Where, A is the heat dissipation area, k 1,A 、 k 2,A is the fitting coefficient of the surface area model, R th is the thermal resistance, k 1,Rth 、 k 2,Rth is the fitting coefficient of the heat dissipation model.

[0026] Furthermore, the loss model data is imported into the heat dissipation model to calculate the operating temperature of the capacitor. The life model is shown as follows:

[0027] ,

[0028] Where, L Indicates the expected life of the capacitor under actual working conditions; L 0 means the life of the capacitor under rated conditions; T 0 represents the rated temperature of the capacitor; T Indicates the operating temperature of the capacitor, unit: °C; V 0 represents the rated voltage of the capacitor; V Indicates the actual working voltage of the capacitor; n is the voltage acceleration factor, usually between 2 and 3.

[0029] Furthermore, the cost model is shown as follows:

[0030] ,

[0031] Where, Cost Indicates cost, k 1,cost represents the cost coefficient per unit capacity, C is the DC bus capacitance, k 2,cost Indicates a fee that does not vary with capacity.

[0032] Furthermore, the volume model is shown as follows:

[0033] ,

[0034] Where, Volume Indicates volume, k 1,volume The volume coefficient per unit capacity, C is the DC bus capacitance, k 2,volume Represents a fixed volume that does not change with capacity.

[0035] Furthermore, step S2 also considers the impact of voltage pumping caused by motor emergency stop on the capacitor, as shown in the following formula:

[0036] ,

[0037] Where, V 0 is the rated voltage, V is the actual working voltage of the capacitor, P is the rated power of the motor driver, Δu For voltage pump appreciation, ESR ( C i ) is the equivalent series resistance of the corresponding capacitor ，t The time it takes for the motor to stop completely after receiving the emergency stop command. C th,i is the thermal capacity of the corresponding capacitor, L1, L2 and L3 are the lifespan under normal operation, emergency stop and parking conditions respectively. t 1、 t 2 and t 3 are the actual total working time under normal operation, emergency stop and parking conditions respectively, T equal is the equivalent working time, k L is the equivalent life factor, L To ignore the life of the voltage pump, L' To consider the life of the voltage pump.

[0038] Compared with the prior art, the present invention has the following beneficial technical effects: without relying on much engineering experience and taking into account limiting factors such as volume and cost, it is possible to select a suitable capacitor group to achieve multi-objective optimization. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 It is a flow chart of the multi-objective optimization design method for the DC bus capacitor of the motor driver provided by the present invention.

[0040] Figure 2 This is the relationship diagram between the equivalent series resistance of a capacitor and the capacitance.

[0041] Figure 3 This is a graph showing the relationship between the equivalent series resistance of a capacitor and frequency and temperature.

[0042] Figure 4 It is the three-phase voltage modulation waveform.

[0043] Figure 5 It is a diagram of parameter changes within a single carrier cycle.

[0044] Figure 6 This is a graph showing the relationship between capacitor surface area and capacitance.

[0045] Figure 7 This is a graph showing the relationship between capacitor thermal resistance and surface area.

[0046] Figure 8 This is a cost model diagram for capacitors.

[0047] Figure 9 This is the volume model diagram of the capacitor.

[0048] Figure 10 It is to select different capacitor combinations to optimize the scatter plot.

[0049] Figure 11 This is a relationship diagram between life, cost and volume of different capacitor combinations.

[0050] Figure 12 This is the temperature rise diagram of the three capacitor group experiments. DETAILED DESCRIPTION

[0051] The following is a clear and complete description of the technical solution of the present invention in conjunction with the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present invention.

[0052] The multi-objective optimization design method for the DC bus capacitor of the motor drive is as follows: Figure 1 As shown, it specifically includes the following contents.

[0053] 1. Set design goals and constraints

[0054] Design goal: lifespan exceeds 21,900 hours;

[0055] Constraints: Cost no more than 10 yuan and volume no more than 14000mm 3 .

[0056] 2 Capacitor model analysis and construction

[0057] In power electronics systems, capacitors behave not only as ideal capacitive elements but also exhibit parasitic parameters, such as equivalent series resistance (ESR) and equivalent series inductance (ESL). While ideal capacitance reflects the capacitor's primary function—energy storage and release—ESR represents resistive losses, and ESL accounts for the inductance caused by the capacitor's internal wiring and structure. These parasitic parameters affect the capacitor's performance at various frequencies, thereby impacting the efficiency and stability of the entire power electronics system. Therefore, establishing an equivalent capacitor model that incorporates these parasitic parameters is crucial.

[0058] 2.1 Equivalent Series Resistance Model

[0059] ESR stands for equivalent series resistance. The ESR of a capacitor includes the resistance of the dielectric material, the resistance of the terminal leads, the resistance of the dielectric connection, and the resistance of the capacitor plates. Since ESR is frequency and temperature dependent, it can be modeled as:

[0060] ,

[0061] ESR rated ( C ) is the ESR at rated frequency (100 Hz / 120 Hz for electrolytic capacitors) and is a function of capacitance. The loss factor of a capacitor is a material-based coefficient defined as ESR rated ( C ) to capacitive reactance:

[0062]

[0063] From formula (2), it can be seen that for the same capacitor packaging technology, the capacitance value and ESR are rated ( C ) have an inverse relationship:

[0064]

[0065] in k 1,ESR and k 2,ESR They are the coefficients describing the dielectric resistance and package resistance related to the capacitor ESR, respectively, and are given by Figure 2 The fitted curve shown is available.

[0066] Since the ESR of the capacitor is related to temperature and frequency, the frequency-dependent ESR is introduced into formula (1). f i and temperature T h Related ESR coefficient α ESR ( f i , T h ). ESR rated ( C ) is usually affected by changes in dielectric viscosity and shows a trend of decreasing with increasing temperature. In addition, ESR decreases monotonically with increasing frequency until it reaches a frequency of 100 kHz or higher. By measuring ESR over a certain frequency and temperature range, the frequency temperature coefficient of ESR for electrolytic capacitors can be obtained. α ESR ( f i , T h ),like Figure 3 shown.

[0067] 2.2 Equivalent Series Inductance Model

[0068] The equivalent series inductance (ESL) of the capacitor is introduced by the winding layer and the connected power terminal. For direct-insert electrolytic capacitors, the typical value of its ESL ranges from 20 to 40 nH. Since the ESL of capacitors of the same type is mainly proportional to the capacitance, it acts on the harmonic current distribution at high frequencies. The present invention only studies one type of electrolytic capacitor. Therefore, the harmonic current distribution of the parallel capacitor group can be approximated as the capacitance ratio. At the same time, in practical applications, electrolytic capacitors are usually directly connected to the DC power supply input terminal through a large area of ​​copper plating. This connection method can significantly reduce the additional inductance caused by wiring. Therefore, the influence of the capacitor's own ESL and the additional ESL generated by the wiring on the capacitor performance is considered to be negligible in the present invention.

[0069] 2.3 Loss Model

[0070] To build a capacitor loss model, it is necessary to analyze the ripple current on the DC bus of the motor drive side. This section derives the ripple current on the DC side based on the SVPWM (space vector pulse width modulation) modulation method. Figure 4 The waveform of the three-phase modulation signal is shown in Figure 1. Compared with the modulation signal, the frequency of the carrier signal is much higher, so within a carrier cycle, the value of the modulation signal can be considered constant. Only segment A is analyzed as an example. Figure 5 shown.

[0071] Assuming that the inverter motor load is linear and the output current is an ideal sinusoidal waveform, the three-phase current can be expressed as:

[0072]

[0073] in: I N is the amplitude of the phase current, φ is the power factor angle, ω is the output frequency of the inverter.

[0074] In one carrier cycle (A), the average current of the inverter input is:

[0075]

[0076] The square of the effective value of the inverter input current is:

[0077]

[0078] in, M is the modulation coefficient.

[0079] Then within the range, the square of the effective value of the inverter input current is:

[0080]

[0081] The analysis of section BF is the same as that of section A, so the square of the effective value of the input current of the inverter during one modulation cycle is:

[0082]

[0083] Due to the characteristic of capacitors that “pass AC and block DC”, it is assumed that the average current of the inverter input is all used as a DC source for power conversion. Then the capacitor ripple current (effective value) is:

[0084]

[0085] Power loss P loss Estimated from the ESR and the ripple current flowing through the capacitor, it can be expressed as:

[0086]

[0087] in I rms ( f i ) is the current flowing through the capacitor at frequency f i The effective value (RMS) under m Representative m Regarding subharmonic current, the present invention mainly considers the high-frequency harmonic current caused by the switching process of the switch tube.

[0088] In practical applications, in addition to high-frequency harmonic currents, low-frequency harmonic currents (usually expressed as mf 1± nf 2 frequency components, where m and n is an integer, f 1 is the motor frequency, f 2 is the reducer frequency). To simplify the model and focus on the main factors, the present invention ignores the influence of these low-frequency harmonic currents.

[0089] 2.4 Heat Dissipation Model

[0090] Thermal stress is one of the key stresses of capacitors. Current ripple and ambient temperature are the causes of thermal stress inside the capacitor, which leads to a higher operating temperature inside the capacitor. T h It can be expressed as:

[0091]

[0092] in T ais the ambient temperature, R ha It is the equivalent thermal resistance from the heating point to the environment.

[0093] The thermal resistance of the capacitor considered in this invention ignores the heat dissipation of the pins and PCB, and therefore only considers the heat convection and heat radiation on the capacitor surface.

[0094] Whether considering convection or radiation heat transfer, it can be seen that the thermal resistance from the hot spot to the surface of the capacitor is inversely proportional to the surface area of ​​the capacitor. According to the parallel plate capacitor equation, the capacitance is proportional to the capacitor area, such as Figure 6 Therefore, for capacitors of the same voltage level, their surface area A It is linearly related to the capacitance value. Therefore, the heat dissipation surface area of ​​the capacitor A Thermal resistance R th The mathematical model can be expressed as:

[0095]

[0096] in, k 1,Rth 、 k 2,Rth is the fitting coefficient of the heat dissipation model, k 1,A 、 k 2,A is the fitting coefficient of the surface area model, given by Figure 7 The fitting curve is shown.

[0097] 2.5 Lifespan Model

[0098] Capacitor life is a key factor affecting system reliability and stability. It is affected by factors such as temperature, voltage, and operating frequency. The life of plug-in aluminum electrolytic capacitors can be estimated based on their operating conditions and rated parameters. A common lifespan model is based on the accelerated aging test results of the Arrhenius equation. Generally speaking, the relationship between capacitor life and temperature and operating voltage is as follows:

[0099]

[0100] in: L Indicates the expected life of the capacitor under actual working conditions; L 0 means the life of the capacitor under rated conditions; T 0 represents the rated temperature of the capacitor (usually 105°C); T Indicates the operating temperature of the capacitor (unit: degrees Celsius); V 0 represents the rated voltage of the capacitor; V Indicates the actual working voltage of the capacitor;n is the voltage acceleration factor, usually between 2 and 3.

[0101] 2.6 Cost and Volume Model

[0102] During the design process, the cost and size of a through-hole aluminum electrolytic capacitor can usually be expressed as a linear function of the capacitance. Cost ,volume Volume and capacitance C The relationship between them can be expressed as:

[0103]

[0104] in, k 1,cost 、k 1,volume denote the cost coefficient and volume coefficient per unit capacity, respectively. k 2,cost and k 2,volume They represent the cost and fixed volume that do not change with capacity, respectively, which can be obtained by Figure 8 and Figure 9 Available.

[0105] 3 Consider the impact of voltage pumping caused by motor emergency stop on capacitor

[0106] 3.1 Effect of pump-up voltage on capacitor temperature

[0107] In modern industrial applications such as automated guided vehicles (AGVs), emergency motor stops are a common occurrence, especially in critical situations. During these situations, the voltage in the drive system experiences a phenomenon known as "voltage pumping." This voltage pumping not only challenges the stability and safety of the motor control system but, more importantly, has a direct impact on the stable operation and lifespan of capacitors.

[0108] During the full load and full speed emergency stop process, the capacitor voltage changes from the rated working voltage to V 0 Rising to the highest voltage V The energy absorbed during the process is:

[0109]

[0110] The time it takes for the voltage to rise is:

[0111]

[0112] The total charging current of the capacitor bank during the voltage pump-up phase is:

[0113]

[0114] The heat generation power of a single capacitor is:

[0115]

[0116] The temperature rise of a single capacitor during the emergency stop phase is:

[0117]

[0118] in, P is the rated power of the motor driver, Δu For voltage pump appreciation, ESR( C i ) is the equivalent series resistance of the corresponding capacitor ，t The time it takes for the motor to stop completely after receiving the emergency stop command. C th,i is the thermal capacitance of the corresponding capacitor.

[0119] 3.2 Effect of pump voltage on capacitor life

[0120] If the motor works for n hours a day, it works in a cyclical working system and operates normally ( T 1)—Emergency Stop( T 2)—Parking T 3) During the parking phase, the capacitor temperature drops to the highest temperature during normal operation. T The capacitor then goes through the following three working states:

[0121] (1) Normal working state: the capacitor temperature is T， The operating voltage is V 0 , the total working time is t 1 (unit: h);

[0122] (2) Emergency stop state: Capacitor temperature is T+ΔT, The operating voltage is V , the total working time is t 2 (unit: h);

[0123] (3) Parking state: Capacitor temperature is T+ΔT / 2, The operating voltage is V 0 , the total working time is t 3 (unit: h).

[0124] The lifespan L1, L2 and L3 under each working state are calculated in sequence according to the aforementioned lifespan model.

[0125] Taking the normal working state as the standard, the equivalent working time factors of the three working states are:

[0126]

[0127] The equivalent working time of the whole process is:

[0128]

[0129] The equivalent life factor is:

[0130]

[0131] Therefore, considering the temperature rise caused by the pump voltage, the capacitor life is:

[0132]

[0133] 4 Multi-objective optimization

[0134] like Figure 1 As shown in the figure, the multi-objective optimization design of the DC-Link capacitor module employed in this invention considers the following design variables: the individual capacitances of the parallel capacitors. Due to considerations for the driver board PCB design, the number of parallel modules is limited to two. During the design process, comprehensive considerations were made of capacitor lifespan, capacitance, ESR, surface area, thermal resistance, cost, and volume to determine the optimal capacitor configuration.

[0135] First, design goals and constraints are set, specifically the minimum lifespan requirement for the capacitors, as well as their cost and size. Next, various performance parameters of the capacitor module are calculated, including capacitance loss, lifespan estimation, and cost and size assessments. These performance metrics are then derived to serve as the basis for evaluating design solutions. Finally, a comprehensive analysis of all design parameters is performed to evaluate the performance of all possible design solutions. A genetic algorithm is then used to select and output the optimal design, ensuring it meets the pre-defined performance, cost, and size requirements.

[0136] The entire design comprehensively considers multiple design parameters, including lifespan, cost, and volume, and employs a multi-objective optimization approach to achieve comprehensive optimization of the capacitor module's overall performance. This systematic design process effectively improves design efficiency and quality, providing reliable support for DC-Link capacitor module applications.

[0137] 5 Simulation optimization and experimental results analysis

[0138] 5.1 Experimental subjects and parameter design

[0139] The present invention designs a DC bus capacitor for a three-phase inverter. Table 1 lists the parameters of the permanent magnet synchronous motor and driver targeted by the present invention.

[0140] Table 1 Motor driver board related parameters

[0141]

[0142] Since the rated power of the driver board in the present invention is relatively large, the capacitor cannot withstand all the feedback energy. Therefore, a discharge resistor is added in actual motor applications to absorb the feedback energy caused by emergency stop. At the same time, the bus voltage is limited to a certain range (60V). Therefore, for the motor driver in the present invention, according to calculations, the shutdown temperature rise and corresponding lifespan of the capacitor caused by the pump-up voltage (60V) are extremely small and can be ignored.

[0143] Table 2 shows the specific optimization index requirements for the capacitor module design in the present invention.

[0144] Table 2 Optimization index requirements

[0145]

[0146] 5.2 Optimization results and experimental verification

[0147] By selecting different capacitor combinations for multi-objective optimization, we can obtain Figure 10 and Figure 11 Results shown.

[0148] Figure 10 and Figure 11 This optimization scatter plot is generated by importing actual capacitor-related data, and the specific capacitor model of the optimal design is output. By comparison, the optimal choice achieves a small size and low cost while also having a long lifespan. Partial performance verification on a test bench further demonstrates the effectiveness and practicality of the optimization model.

[0149] By selecting different capacitor groups including those selected by experience and the best value, and running them at full speed and full load for 60 minutes, we can get the following results: Figure 12 The temperature rise curve is shown.

[0150] As shown in Table 3, the relevant model calculation indicators of the three different capacitor groups, Group 1, Group 2 and Group 3 in the above experiment are shown. Through comparison, it can be clearly seen that the optimal group, Group 3, has more superior performance in terms of comprehensive considerations of cost, volume and life.

[0151] Table 3 Related indicators of three capacitor groups

[0152]

[0153] Depend on Figure 12It can be seen that through the multi-objective optimization process, a more appropriate capacitor bank selection can be obtained. Compared with the current subjective experience of capacitor selection Group 1 and Group 2, while meeting the constraints of volume and cost, the maximum temperature of the capacitor module after 60 minutes of operation decreased by 10.4°C and 8°C, respectively. According to the relevant model calculation, the service life increased by 13.05 times and 1.828 times, respectively, achieving the goal of optimized design.

[0154] In summary, the present invention successfully achieves a balance between volume, cost, and life of the capacitor module by establishing a capacitor model and performing multi-objective optimization, thereby significantly improving the reliability of the capacitor module.

[0155] Although the embodiments of the present invention have been shown and described above, it should be understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art may make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present invention without departing from the principles and intent of the present invention. The scope of protection of the present invention is defined by the claims and their equivalents.

Claims

1. A multi-objective optimization design method for DC bus capacitor of a motor drive, characterized in that: The following steps are involved: S1 Set design goals and constraints based on system parameters, system indicators, design variables and capacitance database; S2 constructs the equivalent series resistance model, loss model, heat dissipation area model, heat dissipation model, life model, cost model and volume model of the DC bus capacitor, calculates various performance parameters of the DC bus capacitor, and obtains the performance index of the DC bus capacitor; The equivalent series resistance model is shown as follows: ， Where ESR stands for equivalent series resistance, ESR ( C, f i , T h ) is the frequency f i and temperature T h The equivalent series resistance, ESR rated ( C ) is the ESR at rated frequency, which is a function of capacitance. ESR ( fi,T h ) is related to the frequency f i and temperature T h The relevant ESR coefficient, k 1,ESR and k 2,ESR They are the coefficients describing the dielectric resistance and package resistance related to the capacitor ESR, C is the DC bus capacitance; ESR calculated using the equivalent series resistance model rated ( C ), the power loss is calculated using a loss model, which is shown in the following formula: ， In the formula, P loss is the power loss, I rms ( f i ) is the current flowing through the capacitor at frequency f i The effective value of m Representative m Subharmonic current; The heat dissipation area model and the heat dissipation model are respectively shown in the following formulas: ， In the formula, A is the heat dissipation area, k 1,A , k 2,A is the fitting coefficient of the surface area model, R th is the thermal resistance, k 1,Rth , k 2,Rth is the fitting coefficient of the heat dissipation model; The loss model data is imported into the heat dissipation model to calculate the operating temperature of the capacitor. The life model is shown in the following formula: ， In the formula, L Indicates the expected life of the capacitor under actual working conditions; L 0 means the life of the capacitor under rated conditions; T 0 represents the rated temperature of the capacitor; T Indicates the operating temperature of the capacitor, in °C; V 0 represents the rated voltage of the capacitor; V Indicates the actual working voltage of the capacitor; n is the voltage acceleration factor, which is between 2 and 3; The cost model is as follows: ， In the formula, Cost Indicates the cost, k 1,cost represents the cost coefficient per unit capacity, k 2,cost represents a cost that does not vary with capacity; The volume model is shown as follows: ， In the formula, Volume Indicates volume, k 1,volume The volume factor representing the unit capacity, k 2,volume Represents a fixed volume that does not change with capacity; S3 comprehensively analyzes various design parameters, evaluates the performance of multiple design schemes, and uses genetic algorithms to select and output the optimal design scheme that comprehensively considers life, cost, and volume to ensure that it meets the preset design goals and constraints.

2. The multi-objective optimization design method according to claim 1, characterized in that: The design goal described in step S1 is that the service life reaches a specified value, and the constraint condition is that both the cost and the volume do not exceed the specified values.

3. The multi-objective optimization design method according to claim 1, characterized in that: Step S2 also considers the impact of voltage pumping caused by motor emergency stop on the capacitor, as shown in the following formula: ， In the formula, P is the rated power of the motor driver, Δu For voltage pump appreciation, ESR ( C i ) is the equivalent series resistance of the corresponding capacitor ，t It is the time taken for the motor to stop completely after receiving the emergency stop command. C th,i is the thermal capacity of the corresponding capacitor, L1, L2 and L3 are the lifespans under normal operation, emergency stop and parking conditions respectively. t 1、 t 2 and t 3 are the actual total working time under normal operation, emergency stop and parking conditions, respectively. T equal is the equivalent working time, k L is the equivalent life factor, L To ignore the life of the voltage pump, L' To consider the life of the voltage pump.

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