A method for manufacturing a backside low resistance via structure of a vertical power device

Abstract

The application provides a manufacturing method of a back low-resistance via structure of a longitudinal power device. The back low-resistance via structure is formed by etching a groove in a substrate and depositing heavily doped polysilicon, so as to further reduce the substrate resistance of the device and lower the static power consumption of the device. The manufacturing method does not need to pay more expensive cost or use more advanced process technology to thin the substrate of the device, and is easier to realize the reduction of the substrate resistance of the device.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor power devices, and particularly relates to a manufacturing method of a back low-resistance via structure of a longitudinal power device. BACKGROUND

[0002] For power devices, a larger on-resistance means greater power consumption, so it is desirable to reduce the on-resistance as much as possible to reduce the power consumption of the device. Among them, the substrate resistance of the longitudinal transistor power device is one of the components of the on-resistance, and the proportion is particularly large at low voltage levels. The current substrate thinning technology can reduce the substrate resistance by thinning the substrate and optimize the heat dissipation problem, but it is subject to the level of thinning process technology, and thinning the substrate to a lower thickness requires more expensive costs and more advanced process technology. In addition, the wafer is subject to support and stress problems, and it must maintain a relatively thick substrate thickness, resulting in a large substrate resistance. In order to further reduce the substrate resistance, researchers have proposed a low-resistance via structure on the back of the power longitudinal device. By etching a groove in the back substrate and depositing heavily doped polysilicon to form a low-resistance via structure and shorting to the back drain as the back electrode of the longitudinal device, the substrate resistance of the device can be further reduced to improve the power consumption of the longitudinal device. SUMMARY

[0003] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a manufacturing method of a back low-resistance via structure of a longitudinal power device.

[0004] To achieve the above-mentioned purpose of the application, the technical solution of the present application is as follows:

[0005] A manufacturing method of a back low-resistance via structure of a longitudinal power device, comprising the following steps:

[0006] Step (1) manufacturing a longitudinal device until the device forms a first type of heavily doped region 106 and is annealed;

[0007] Step (2) depositing an isolation medium layer 107 on the upper surface of the device, and annealing the isolation medium layer;

[0008] Step (3) performing a substrate thinning process on the back of the substrate of the device to achieve substrate thinning;

[0009] Step (4) depositing an oxide layer as a barrier oxide layer 203 on the back of the substrate of the device;

[0010] Step (5) spin-coating photoresist on the oxide layer on the back of the substrate of the device; etching a pattern and etching the oxide layer to form an etching window through a photolithography process;

[0011] Step (6) etching the substrate silicon in the oxide layer window of the substrate of the device to form a trench 205;

[0012] Step (7) removing the photoresist, forming a layer of sacrificial oxide on the surface of the trench by thermal oxidation process, and removing the sacrificial oxide layer by wet etching 206;

[0013] Step (8) depositing the first type of heavily doped polysilicon in the trench and etching back to the lower surface of the device, and then introducing inert gas for high temperature annealing above 900℃;

[0014] Step (9) etching the isolation medium layer on the surface of the device, and spin-coating photoresist on the upper surface of the device; etching the pattern by photolithography process and etching the oxide layer to form a metal via hole, ion implanting the second type of doping material to form the second type of heavily doped region, and rapid thermal annealing to form the body terminal heavily doped region 109;

[0015] Step (10) depositing the barrier metal on the surface of the device and etching back, then depositing the interconnection metal and forming different electrodes, and annealing, and finally depositing the passivation layer 300 on the surface of the device;

[0016] Step (11) forming the back metal layer 208 on the lower surface of the substrate.

[0017] The application also provides a manufacturing method of the back low resistance via hole structure of the second longitudinal power device, comprising the following steps:

[0018] Step (1) manufacturing the longitudinal device until the isolation medium layer 107 is deposited on the upper surface of the device, and annealing treatment is performed on the isolation medium layer;

[0019] Step (2) spin-coating photoresist on the surface of the device; etching the pattern by photolithography process and etching the oxide layer to form a metal via hole, ion implanting the second type of doping material to form the second type of heavily doped region, and rapid thermal annealing to form the body terminal ohmic contact region 109, and depositing the barrier metal on the surface of the device and the via hole thereof;

[0020] Step (3) performing the thinning process on the back of the substrate of the device to achieve substrate thinning;

[0021] Step (4) depositing an oxide layer as a barrier oxide layer 203 on the back of the substrate of the device;

[0022] Step (5) spin-coating photoresist on the oxide layer on the back of the substrate of the device; etching the pattern by photolithography process and etching the oxide layer to form an etching window;

[0023] Step (6) etching the substrate silicon in the oxide layer window of the substrate of the device to form a trench 205;

[0024] Step (7) removes the photoresist, forms a sacrificial oxide layer on the trench surface by thermal oxidation process, and removes the sacrificial oxide layer by wet etching;

[0025] Step (8) deposits a first type of heavily doped polysilicon in the trench and etches back to the lower surface of the device, and then introduces an inert gas to perform high-temperature annealing at 900°C or above;

[0026] Step (9) etches back the barrier layer metal on the device surface and deposits an interconnection metal, forms different electrodes, and performs annealing, and finally deposits a passivation layer 300 on the device surface;

[0027] Step (10) forms a back metal layer 208 on the lower surface of the substrate.

[0028] As a preferred mode, in the above two manufacturing methods, step (1) uses a silicon substrate, a silicon epitaxial layer is formed on the surface of the silicon substrate, and the device unit cell is formed in the silicon epitaxial layer;

[0029] As a preferred mode, in the above two manufacturing methods, step (1) is a trench isolation gate device;

[0030] As a preferred mode, in the above two manufacturing methods, step (3) uses chemical mechanical polishing to thin the substrate of the device;

[0031] As a preferred mode, in the above two manufacturing methods, the photoetching pattern of step (5) is a regular polygon or a circle, as shown in Figures 5-A to 5-B ;

[0032] As a preferred mode, in the above two manufacturing methods, step (6) uses a dry etching process to vertically etch on the back of the device, so that the sidewall of the trench formed by etching is vertical up and down;

[0033] As a preferred mode, in the above two manufacturing methods, step (8) uses atomic layer deposition (ALD) process to deposit polysilicon, so as to realize low-temperature deposition and reduce the impact of thermal process on the device;

[0034] As a preferred mode, in the above two manufacturing methods, step (8) performs high-temperature annealing of polysilicon at a temperature of 900°C or above, so as to make the distribution of dopants in the heavily doped polysilicon more uniform;

[0035] As a preferred mode, in the above first manufacturing method, the isolation medium layer material deposited in step (2) is undoped silicon glass (USG), phosphorus-doped silicon (BSG), or boron-phosphorus-doped silicon (BPSG); and the thickness is greater than 0.8um;

[0036] As a preferred mode, in the above first manufacturing method, the second type of doping material in step (9) is boron fluoride (BF2) or boron (B).

[0037] As a preferred mode, in the first manufacturing method, the step (11) uses a sputtering deposition process to form the back metal layer;

[0038] As a preferred mode, in the second manufacturing method, the barrier metal material in the step (2) is a refractory metal selected from tungsten, titanium, titanium nitride;

[0039] As a preferred mode, in the second manufacturing method, the second type of doping material in the step (2) is boron fluoride (BF2) or boron (B);

[0040] As a preferred mode, in the second manufacturing method, the step (10) uses a sputtering deposition process to form the back metal layer;

[0041] The present application has the following advantages: by etching a groove in the substrate and depositing heavily doped polysilicon to form a back low-resistance via structure, the substrate resistance of the device is further reduced and the static power consumption of the device is lowered, without incurring higher cost and using more advanced process technology to thin the substrate to reduce the substrate resistance of the device. BRIEF DESCRIPTION OF DRAWINGS

[0042] Figure 1 is a cross-sectional view of a conventional trench-type separate gate transistor;

[0043] Figure 2 is a cross-sectional view of a trench-type separate gate transistor improved by using the embodiment of the present application;

[0044] Figures 3-A to 3-I is a device cross-sectional view in the preparation process step of Example 1;

[0045] Figures 4-A to 4-I is a device cross-sectional view in the preparation process step of Example 2;

[0046] Figures 5-A to 5-C is a photolithography pattern of the back etching groove in the embodiment;

[0047] BRIEF DESCRIPTION OF DRAWINGS DETAILED DESCRIPTION

[0048] The present application is herein described, by way of example only, with the comprehension that the advantages and utility thereof are not limited thereto. Changes in form and detail can be made by those skilled in the art without departing from the spirit and scope of the application as expressed in the appended claims.

[0049] Embodiment 1

[0050] The present embodiment provides a method for manufacturing a back low resistance via structure of a longitudinal power device, wherein

[0051] The process in step (1) starts after the device is finished with NSD ion implantation and annealing;

[0052] In step (2), a thick USG and BPSG is deposited on the upper surface of the device to form an isolation medium layer 107, and the isolation medium layer is annealed;

[0053] The formation of the back low resistance via structure on the device specifically includes:

[0054] Step (1) manufactures a longitudinal device until the device forms a first type of heavily doped region 106 and is annealed;

[0055] Step (2) deposits an isolation medium layer 107 on the upper surface of the device, and the isolation medium layer is annealed;

[0056] Step (3) performs a thinning process on the back of the substrate of the device to achieve substrate thinning;

[0057] Step (4) deposits an oxide layer on the back of the substrate of the device as a barrier oxide layer 203;

[0058] Step (5) spins photoresist on the oxide layer on the back of the substrate of the device; etches a pattern through a photolithography process and etches the oxide layer to form an etching window;

[0059] Step (6) etches the substrate silicon in the oxide layer window of the substrate of the device to form a trench 205;

[0060] Step (7) removes the photoresist, forms a sacrificial oxide layer on the surface of the trench through a thermal oxidation process, and removes the sacrificial oxide layer 206 through wet etching;

[0061] Step (8) deposits a first type of heavily doped polysilicon in the trench and etches back to the lower surface of the device, and then introduces an inert gas to perform high temperature annealing above 900°C;

[0062] Step (9) etching isolation medium layer on the device surface, spin coating photoresist on the device surface; etching pattern and etching oxide layer to form metal via hole by photoetching process, ion implanting second type of doping material to form second type of heavily doped region, and rapid thermal annealing to form body end heavily doped region 109;

[0063] Step (10) depositing barrier layer metal on the device surface and etching back, then depositing interconnection metal and forming different electrodes, and annealing, and finally depositing passivation layer 300 on the device surface;

[0064] Step (11) forming back metal layer 208 on the lower surface of the substrate.

[0065] Figure 3-A is a simplified cross-sectional view of the device after depositing thick USG and BPSG on the upper surface of the device to form an isolation medium layer in the trench type separation gate transistor process step, and annealing the isolation medium layer, which can meet the stress requirements of the device surface. As shown, at this time, the substrate 200 has not been thinned and the bottom trench has not been etched, the first type of doped epitaxial layer 100 is located on the substrate 200, and the trenches of the cells and the terminals of the device are located on the epitaxial layer 100. The source ohmic contact region of the device cell is the first type of heavily doped region 106, which is located on the upper surface of the epitaxial layer 100, and the body region is the second type of doped region 105, which is located below 106; the shielding gate 101 of the device cell is located at the bottom of the trench, and the control gate 104 is located above the shielding gate 101. The surface of the epitaxial layer 100 is completely wrapped and covered by the passivation 107;

[0066] As shown in Figure 3-B , the substrate 200 can be thinned by chemical mechanical polishing to form a substrate 201, and a layer of oxide layer is deposited on the lower surface of the thinned substrate 201 as an etching barrier;

[0067] As shown in Figure 3-C , photoresist is spin-coated on the bottom of the device; etching window is formed on the lower surface of the substrate by photoetching oxide layer;

[0068] As shown in Figure 3-D , the substrate silicon is etched in the bottom oxide layer window of the device to form a trench, and in this application, dry etching process is used to etch vertically on the back of the device, so that the sidewall of the etched trench is vertical up and down;

[0069] As shown in Figure 3-E , the photoresist is removed from the bottom of the device, and a layer of sacrificial oxide layer is grown on the surface of the trench 205 by thermal oxidation process to restore the interface damage caused by etching;

[0070] As shown in Figure 3-FAs shown, after removing the sacrificial oxide layer at the bottom of the device by wet etching, first-type heavily doped polysilicon 207 is deposited at the bottom of the device by chemical vapor deposition or atomic layer deposition, and the first-type heavily doped polysilicon is etched back onto the surface of the substrate 201 so that the bottom of the polysilicon is flush with the surface of the substrate silicon. Inert gas is then introduced for high-temperature annealing to make the impurities in the polysilicon uniformly distributed and form a low-resistivity ohmic contact region.

[0071] like Figure 3-G As shown, an isolation dielectric layer is etched on the surface of the device, and photoresist is spin-coated on the upper surface of the device; a pattern is etched and an oxide layer is etched to form a metal via, and then a second type of doping material is implanted by ion implantation. BF2 and B can be used, where BF2 has a smaller diffusion coefficient and can more easily form a second type of heavily doped region at the body end, and B has a larger diffusion coefficient and can form a buffer to mitigate the concentration difference of P+ / P junction and smooth the electric field at that location; then rapid thermal annealing is performed to form the second type of heavily doped region 109 at the body end;

[0072] like Figure 3-H As shown, a barrier metal layer is deposited on the surface of the device and etched back, interconnect metal is deposited and different electrodes are etched out and subjected to low-temperature annealing, and a passivation layer is further deposited on the surface of the device.

[0073] like Figure 3-I As shown, a barrier metal layer is deposited on the surface of the device and etched back, interconnect metal is deposited and different electrodes are etched and then subjected to low-temperature annealing, a passivation layer is further deposited on the surface of the device, and finally interconnect metal is sputtered on the lower surface of the substrate to form a back metal layer, thereby forming a basic structure of a low-resistance via on the back.

[0074] As a preferred embodiment, the device in step (1) uses a silicon substrate, and a silicon epitaxial layer is formed on the surface of the silicon substrate, and the device unit cell is formed in the silicon epitaxial layer;

[0075] As a preferred embodiment, the device in step (1) uses a silicon substrate, and a silicon epitaxial layer is formed on the surface of the silicon substrate, and the device unit cell is formed in the silicon epitaxial layer;

[0076] As a preferred embodiment, the device in step (1) is a trench-separated gate device;

[0077] As a preferred method, the isolation dielectric layer material deposited in step (2) is undoped silicon glass (USG), silicon phosphate (BSG), or silicon borophosphate (BPSG); its thickness is greater than 0.8 μm;

[0078] As a preferred method, step (3) uses chemical mechanical polishing to thin the substrate of the device;

[0079] As a preferred method, the photolithographic pattern in step (5) is a regular polygon or a circle. For example... Figures 5-A to 5-B As shown;

[0080] As a preferred method, step (6) employs a dry etching process to vertically etch the back of the device so that the sidewalls of the etched trench are vertical.

[0081] As a preferred method, atomic layer deposition (ALD) is used to deposit polysilicon in step (8) to achieve low-temperature deposition and reduce the impact of the thermal process on the device;

[0082] As a preferred method, the high-temperature annealing temperature of polycrystalline silicon in step (8) is above 900°C, so that the doping distribution in the heavily doped polycrystalline silicon is more uniform.

[0083] As a preferred embodiment, the second type of doping material in step (9) is boron fluoride (BF2) or boron (B);

[0084] As a preferred method, step (11) uses a sputtering deposition process to form the back metal;

[0085] Example 2:

[0086] The main difference between this embodiment and embodiment 1 is that in embodiment 1, the isolation dielectric layer on the upper surface of the device before thinning can meet the support and stress requirements of the subsequent back-side process, while in embodiment 2, the isolation dielectric layer and metal barrier layer on the upper surface of the device before thinning can meet the support and stress requirements of the subsequent back-side process.

[0087] Forming a low-resistivity via structure on the back of the device specifically includes:

[0088] Step (1) Fabricate a vertical device until an isolation dielectric layer 107 is deposited on the upper surface of the device, and anneal the isolation dielectric layer;

[0089] Step (2) spin-coating photoresist on the surface of the device; etching patterns and etching oxide layers through photolithography to form metal vias; ion implantation of second type doping material to form second type heavily doped regions; and rapid thermal annealing to form body end ohmic contact regions 109; and depositing metal on the surface of the device and its vias.

[0090] Step (3) involves performing a thinning process on the back side of the substrate of the device to achieve substrate thinning;

[0091] Step (4) Deposit an oxide layer as a barrier oxide layer 203 on the back of the substrate of the device;

[0092] Step (5) spin-coating photoresist onto the oxide layer on the back side of the substrate of the device; etching the pattern and etching the oxide layer to form an etching window by photolithography;

[0093] Step (6) involves etching the substrate silicon in the oxide layer window of the substrate of the device to form a trench 205;

[0094] Step (7) Remove the photoresist, form a sacrificial oxide layer on the surface of the trench by thermal oxidation, and remove the sacrificial oxide layer by wet etching;

[0095] Step (8) deposits first-type heavily doped polycrystalline silicon in the trench and etches it back to the lower surface of the device, and then introduces inert gas for high-temperature annealing at 900°C or higher;

[0096] Step (9) etch back the barrier layer metal on the surface of the device and deposit interconnect metal, form different electrodes, and perform annealing. Finally, deposit a passivation layer 300 on the surface of the device.

[0097] Step (10) forms a back metal layer 208 on the lower surface of the substrate.

[0098] Figure 4-A This is a simplified cross-sectional view of a trench-type split-gate transistor after the deposition of USG and BPSG on the upper surface of the device to form an isolation dielectric layer, followed by annealing of the isolation dielectric layer. The structure is similar to... Figure 3-A same;

[0099] like Figure 4-B As shown, photoresist is spin-coated onto the upper surface of the device; a pattern is etched and an oxide layer is etched to form metal vias using photolithography; a second type of doping material is implanted, which can be BF2 or B, where BF2 has a smaller diffusion coefficient and can more easily form a second type of heavily doped region at the body end, and B has a larger diffusion coefficient and can form a buffer to mitigate the concentration difference between the P+ and P junctions and smooth the electric field at that location; then rapid thermal annealing is performed to form the second type of heavily doped region at the body end, and finally a thick barrier metal layer is deposited on the surface of the device;

[0100] like Figure 4-C As shown, the substrate 200 can be thinned by chemical mechanical polishing to form the substrate 201, and an oxide layer is deposited on the lower surface of the thinned substrate 201 as an etching barrier layer.

[0101] like Figure 4-D As shown, photoresist is spin-coated onto the bottom of the device; an etching window is formed on the lower surface of the substrate by photolithography of the oxide layer;

[0102] like Figure 4-E As shown, a trench 205 is formed by etching the substrate silicon in the bottom oxide layer window of the device. In this application, a dry etching process is used to vertically etch the back of the device so that the sidewalls of the etched trench are vertical.

[0103] like Figure 4-FAs shown, the photoresist is removed from the bottom of the device, and a sacrificial oxide layer is grown on the surface of trench 205 by thermal oxidation process to restore the interface damage caused by etching.

[0104] like Figure 4-G As shown, after removing the sacrificial oxide layer at the bottom of the device by wet etching, first-type heavily doped polysilicon 207 is deposited at the bottom of the device by chemical vapor deposition or atomic layer deposition. The first-type heavily doped polysilicon is then etched back onto the surface of the substrate 201 so that the bottom of the polysilicon is flush with the surface of the substrate silicon. Inert gas is then introduced for high-temperature annealing to make the impurities in the polysilicon uniformly distributed and form a low-resistivity first-type heavily doped region.

[0105] like Figure 4-H As shown, a thick barrier metal layer is etched on the surface of the device, interconnect metal is deposited and different electrodes are etched and subjected to low-temperature annealing, and a passivation layer is further deposited on the surface of the device.

[0106] like Figure 4-I As shown, a barrier metal layer is deposited on the surface of the device and etched back, interconnect metal is deposited and different electrodes are etched and then subjected to low-temperature annealing. A passivation layer is further deposited on the surface of the device, and finally interconnect metal is sputtered on the lower surface of the substrate to form a back metal layer, thereby forming a basic structure of a low-resistance via on the back.

[0107] As a preferred embodiment, in the two manufacturing methods described above, a silicon substrate is used in the device in step (1), a silicon epitaxial layer is formed on the surface of the silicon substrate, and the device unit cell is formed in the silicon epitaxial layer;

[0108] As a preferred embodiment, the device in step (1) is a trench-separated gate device;

[0109] As a preferred method, the barrier layer metal material in step (2) is a refractory metal, selected from tungsten, titanium, and titanium nitride;

[0110] As a preferred embodiment, the second type of doping material in step (2) is boron fluoride (BF2) or boron (B);

[0111] As a preferred method, step (3) uses chemical mechanical polishing to thin the substrate of the device;

[0112] As a preferred method, the photolithographic pattern in step (5) is a regular polygon or a circle. For example... Figures 5-A to 5-B As shown;

[0113] As a preferred method, step (6) employs a dry etching process to vertically etch the back of the device so that the sidewalls of the etched trench are vertical.

[0114] As a preferred method, atomic layer deposition (ALD) is used to deposit polysilicon in step (8) to achieve low-temperature deposition and reduce the impact of the thermal process on the device;

[0115] As a preferred method, the high-temperature annealing temperature of polycrystalline silicon in step (8) is above 900°C, so that the doping distribution in the heavily doped polycrystalline silicon is more uniform.

[0116] As a preferred method, step (10) uses a sputtering deposition process to form the back metal layer;

[0117] The method for manufacturing a low-resistance via structure on the back side of a vertical power device provided by the present invention forms a low-resistance via structure on the back side by etching trenches on the back substrate and depositing heavily doped polysilicon, and shorting the back drain as the back electrode of the vertical device, which can further reduce the substrate resistance and power consumption of the device.

[0118] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for manufacturing a low-resistance via structure on the back of a vertical power device, characterized in that, Includes the following steps: Step (1) Fabricate the vertical device until the device forms a first type of heavily doped region (106) and anneal; Step (2) deposits an isolation dielectric layer (107) on the upper surface of the device and anneals the isolation dielectric layer; Step (3) involves performing a thinning process on the back side of the substrate of the device to achieve substrate thinning; Step (4) deposits an oxide layer as a barrier oxide layer (203) on the back of the substrate of the device; Step (5) spin-coating photoresist onto the oxide layer on the back side of the substrate of the device; etching the pattern and etching the oxide layer to form an etching window by photolithography; Step (6) involves etching the substrate silicon in the oxide window of the substrate of the device to form a trench (205); Step (7) Remove the photoresist, form a sacrificial oxide layer on the surface of the trench by thermal oxidation process, and remove the sacrificial oxide layer by wet etching (206); Step (8) deposits first-type heavily doped polycrystalline silicon in the trench and etches it back to the lower surface of the device, and then introduces inert gas for high-temperature annealing at 900°C or higher; Step (9) Etches an isolation dielectric layer on the surface of the device and spin-coats photoresist on the upper surface of the device; etches a pattern and an oxide layer through photolithography to form a metal via, implants a second type of doped material to form a second type of heavily doped region, and rapidly thermally anneals to form a body-end heavily doped region (109). Step (10) deposits a barrier metal layer on the surface of the device and etches it back, then deposits interconnect metal and forms different electrodes, and performs annealing, and finally deposits a passivation layer (300) on the surface of the device. Step (11) forms a back metal layer (208) on the lower surface of the substrate.

2. A method for manufacturing a low-resistance via structure on the back side of a vertical power device, characterized in that, Includes the following steps: Step (1) Fabricate a vertical device until an isolation dielectric layer (107) is deposited on the upper surface of the device, and anneal the isolation dielectric layer; Step (2) spin-coating photoresist on the surface of the device; etching patterns and etching oxide layers through photolithography to form metal vias; ion implantation of second type doping material to form second type heavily doped regions; and rapid thermal annealing to form body end ohmic contact regions (109); and depositing metal on the surface of the device and its vias. Step (3) involves performing a thinning process on the back side of the substrate of the device to achieve substrate thinning; Step (4) deposits an oxide layer as a barrier oxide layer (203) on the back of the substrate of the device; Step (5) spin-coating photoresist onto the oxide layer on the back side of the substrate of the device; etching the pattern and etching the oxide layer to form an etching window by photolithography; Step (6) involves etching the substrate silicon in the oxide window of the substrate of the device to form a trench (205); Step (7) Remove the photoresist, form a sacrificial oxide layer on the surface of the trench by thermal oxidation, and remove the sacrificial oxide layer by wet etching; Step (8) deposits first-type heavily doped polycrystalline silicon in the trench and etches it back to the lower surface of the device, and then introduces inert gas for high-temperature annealing at 900°C or higher; Step (9) involves etching back the barrier layer metal on the surface of the device and depositing interconnect metal, forming different electrodes, annealing, and finally depositing a passivation layer (300) on the surface of the device. Step (10) forms a back metal layer (208) on the lower surface of the substrate.

3. The method for manufacturing a low-resistance via structure on the back side of a vertical power device according to claim 1 or 2, characterized in that: In step (1), a silicon substrate is used in the device, and a silicon epitaxial layer is formed on the surface of the silicon substrate. The device unit cell is formed in the silicon epitaxial layer.

4. The method for manufacturing a low-resistance via structure on the back side of a vertical power device according to claim 1 or 2, characterized in that: The device in step (1) is a trench-separated gate device.

5. The method for manufacturing a low-resistance via structure on the back side of a vertical power device according to claim 1 or 2, characterized in that: The photolithographic pattern in step (5) is a regular polygon or a circle.

6. The method for manufacturing a low-resistance via structure on the back side of a vertical power device according to claim 1 or 2, characterized in that: In step (8), polycrystalline silicon is deposited using atomic layer deposition (ALD) process.

7. The method for manufacturing a low-resistance via structure on the back side of a vertical power device according to claim 1 or 2, characterized in that: Step (10) uses a sputtering deposition process to form a metal layer.

8. The method for manufacturing the back low-resistance via structure of the vertical power device according to claim 1, characterized in that: Step (2) uses a deposition process to form a thicker isolation medium layer with a thickness greater than 0.8 μm.

9. The method for manufacturing the back low-resistance via structure of the vertical power device according to claim 2, characterized in that: The metal material in step (2) is a refractory metal, selected from tungsten, titanium, and titanium nitride.

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