Shielded gate trench device with MGD structure and method of fabrication thereof

Abstract

The application provides a shielded gate trench device with an MGD structure and a manufacturing method thereof, which integrates an MGD structure in a common SGT device, wherein a substrate is divided into shielded gate trench transistor regions and MOS gate-controlled diode regions which are alternately arranged along a preset direction, first trenches and second trenches are arranged in the two regions respectively, the MGD structure comprises a second shielded gate oxide layer, a second shielded gate polysilicon layer, a second isolation layer, a third shielded gate oxide layer and a third shielded gate polysilicon layer which are arranged in the second trench, and the second shielded gate polysilicon layer and the third shielded gate polysilicon layer are connected to a source potential. The application can reduce a device source-drain voltage Vsd, reduce a reverse recovery charge Qrr and a reverse recovery time Trr, and help to improve circuit efficiency, wherein when the device is turned off, the circuit provides an extraction current to extract the reverse recovery charge Qrr from an epitaxial layer to an upper polysilicon layer of the MGD structure.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor, and relates to a shielded gate trench device with MGD structure and a manufacturing method thereof. BACKGROUND

[0002] The shielded gate trench (SGT) structure is an advanced MOSFET technology, which adds a shield electrode connected with the source electrode below the gate electrode by deep trench process, so as to realize the function of shielding the gate electrode and the drift region, thereby reducing the Miller capacitance and gate charge, accelerating the switching speed, and reducing the switching loss.

[0003] In a method for manufacturing the SGT structure, the preparation of the control gate includes the following processes: oxide layer etching, depositing polysilicon, and etching the polysilicon.

[0004] The source-drain voltage Vsd of the SGT structure manufactured by the current process is relatively high, generally 0.7-0.8V, and the reverse recovery time is long, which leads to low circuit efficiency.

[0005] Therefore, how to provide an SGT structure and a manufacturing method thereof to reduce the source-drain voltage Vsd and the reverse recovery charge Qrr and the reverse recovery time Trr, and improve the circuit efficiency, has become an important technical problem to be solved by those skilled in the art. SUMMARY

[0006] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a shielded gate trench device with MGD structure and a manufacturing method thereof, which is used to solve the problem of high source-drain voltage Vsd and long reverse recovery time of the existing shielded gate trench device, which leads to low circuit efficiency.

[0007] To achieve the above-mentioned purpose and other related purposes, the present application provides a manufacturing method of a shielded gate trench device with MGD structure, which comprises the following steps:

[0008] A substrate is provided, which comprises an N-type substrate and an N-type epitaxial layer located on the N-type substrate, and the substrate is divided into shielded gate trench type transistor regions and MOS gate-controlled diode regions which are alternately arranged along a predetermined direction;

[0009] First and second trenches are formed in the N-type epitaxial layer, the first trench is located in the shielded gate trench type transistor region, and the second trench is located in the MOS gate-controlled diode region;

[0010] A first shield gate oxide layer, a first shield gate polysilicon layer and a first isolation layer are formed in the first trench, and a second shield gate oxide layer, a second shield gate polysilicon layer and a second isolation layer are formed in the second trench.

[0011] forming a control gate oxide layer and a control gate polysilicon layer in the first trench, and forming a third shield gate oxide layer and a third shield gate polysilicon layer in the second trench;

[0012] forming a P-type body region, an N-type source region and a source metal layer, the P-type body region being located on an upper surface of the N-type epitaxial layer, the N-type source region being located on an upper surface of the P-type body region, and the source metal layer being electrically connected to the P-type body region and the N-type source region, wherein

[0013] the control gate polysilicon layer is located above the first shield gate oxide layer and is spaced from the first shield gate oxide layer by the first isolation layer, the first shield gate oxide layer is located between an outer wall of the first shield gate polysilicon layer and an inner wall of the first trench, and the control gate oxide layer is located between an outer wall of the control gate polysilicon layer and an inner wall of the first trench;

[0014] the third shield gate polysilicon layer is located above the second shield gate polysilicon layer and is spaced from the second shield gate polysilicon layer by the second isolation layer, the second shield gate oxide layer is located between an outer wall of the second shield gate polysilicon layer and an inner wall of the second trench, and the third shield gate oxide layer is located between an outer wall of the third shield gate polysilicon layer and an inner wall of the second trench;

[0015] the first shield gate polysilicon layer, the second shield gate polysilicon layer and the third shield gate polysilicon layer are all connected to a source potential.

[0016] Optionally, forming a first shield gate oxide layer, a first shield gate polysilicon layer and a first isolation layer in the first trench, and forming a second shield gate oxide layer, a second shield gate polysilicon layer and a second isolation layer in the second trench comprise the following steps:

[0017] depositing a first oxide layer, the first oxide layer covering inner walls of the first trench and the second trench;

[0018] depositing a first polysilicon layer, the first polysilicon layer filling into the first trench and the second trench;

[0019] dry-etching the first polysilicon layer to a first preset depth;

[0020] wet-etching the first oxide layer to expose part of a sidewall of the first polysilicon layer;

[0021] depositing a second oxide layer, the second oxide layer filling into the first trench and the second trench and covering an exposed surface of the first polysilicon layer;

[0022] etching the second oxide layer and the first oxide layer to a second preset depth, the second preset depth being higher than the first preset depth, at this time, the part of the first oxide layer in the first trench serves as the first shield gate oxide layer, the part of the first oxide layer in the second trench serves as the second shield gate oxide layer, the part of the first polysilicon layer in the first trench serves as the first shield gate polysilicon layer, the part of the first polysilicon layer in the second trench serves as the second shield gate polysilicon layer, the part of the second oxide layer in the first trench serves as the first isolation layer, and the part of the second oxide layer in the second trench serves as the second isolation layer.

[0023] Optionally, forming a control gate oxide layer and a control gate polysilicon layer in the first trench and forming a third shield gate oxide layer and a third shield gate polysilicon layer in the second trench include the following steps:

[0024] forming a third oxide layer, the third oxide layer covering the exposed sidewall of the first trench and the exposed sidewall of the second trench;

[0025] forming a photoresist layer, the photoresist layer covering the N-type epitaxial layer and filling into the first trench and the second trench;

[0026] patterning the photoresist layer to obtain an opening exposing the MOS gate-controlled diode region;

[0027] removing the part of the third oxide layer on the sidewall of the second trench, the part of the third oxide layer on the sidewall of the first trench serving as the control gate oxide layer;

[0028] removing the photoresist layer and forming a fourth oxide layer, the fourth oxide layer at least covering the exposed sidewall of the second trench, the part of the fourth oxide layer covering the sidewall of the second trench serving as the third shield gate oxide layer;

[0029] forming a second polysilicon layer, the second polysilicon layer covering the N-type epitaxial layer and filling into the first trench and the second trench;

[0030] patterning the second polysilicon layer to obtain the control gate polysilicon layer in the first trench and the third shield gate polysilicon layer in the second trench.

[0031] Optionally, the number of the first trenches in one shield gate trench transistor region is M, and the number of the second trenches in one adjacent MOS gate-controlled diode region is N, where N≥1 and M≥N.

[0032] Optionally, M / N≥5.

[0033] Optionally, the third shielding gate oxide layer has a thickness less than that of the control gate oxide layer.

[0034] Optionally, the third shielding gate oxide layer has a thickness ranging from 60 angstroms to 70 angstroms, and the control gate oxide layer has a thickness ranging from 250 angstroms to 350 angstroms.

[0035] The application further provides a shielding gate trench device with MGD structure, comprising:

[0036] a substrate comprising an N-type substrate and an N-type epitaxial layer on the N-type substrate, the substrate being divided into shielding gate trench transistor regions and MOS gate-controlled diode regions arranged alternately along a preset direction;

[0037] a first trench and a second trench in the N-type epitaxial layer, the first trench being in the shielding gate trench transistor region, and the second trench being in the MOS gate-controlled diode region;

[0038] a first shielding gate oxide layer, a first shielding gate polysilicon layer, a first isolation layer, a control gate oxide layer and a control gate polysilicon layer in the first trench, the control gate polysilicon layer being above and spaced from the first shielding gate oxide layer by the first isolation layer, the first shielding gate oxide layer being between the outer wall of the first shielding gate polysilicon layer and the inner wall of the first trench, the control gate oxide layer being between the outer wall of the control gate polysilicon layer and the inner wall of the first trench, and the first shielding gate polysilicon layer being connected to a source electrode;

[0039] a second shielding gate oxide layer, a second shielding gate polysilicon layer, a second isolation layer, a third shielding gate oxide layer and a third shielding gate polysilicon layer in the second trench, the third shielding gate polysilicon layer being above and spaced from the second shielding gate polysilicon layer by the second isolation layer, the second shielding gate oxide layer being between the outer wall of the second shielding gate polysilicon layer and the inner wall of the second trench, and the third shielding gate oxide layer being between the outer wall of the third shielding gate polysilicon layer and the inner wall of the second trench, the second shielding gate polysilicon layer and the third shielding gate polysilicon layer both being connected to the source electrode;

[0040] a P-type body region in the upper layer of the N-type epitaxial layer, an N-type source region in the upper layer of the P-type body region, and a source metal layer electrically connected to the P-type body region and the N-type source region.

[0041] Optionally, the number of the first trenches in one of the shielded gate trench transistor regions is M, and the number of the second trenches in one of the MOS gate-controlled diode regions adjacent to the shielded gate trench transistor region is N, wherein N≥1 and M≥N.

[0042] Optionally, M / N≥5.

[0043] Optionally, the thickness of the third shielded gate oxide layer is less than the thickness of the control gate oxide layer.

[0044] Optionally, the thickness of the third shielded gate oxide layer is in the range of 60-70 angstroms, and the thickness of the control gate oxide layer is in the range of 250-350 angstroms.

[0045] As described above, the shielded gate trench device with MGD structure and the manufacturing method thereof integrate the MGD structure in the common SGT device, wherein the substrate is divided into the shielded gate trench transistor region and the MOS gate-controlled diode region which are alternately arranged along a preset direction, the shielded gate trench transistor region and the MOS gate-controlled diode region are respectively provided with the first trench and the second trench, the MGD structure includes the second shielded gate oxide layer, the second shielded gate polysilicon layer, the second isolation layer, the third shielded gate oxide layer and the third shielded gate polysilicon layer which are located in the second trench, the third shielded gate polysilicon layer is located above the second shielded gate polysilicon layer and is separated from the second shielded gate polysilicon layer by the second isolation layer, and the second shielded gate polysilicon layer and the third shielded gate polysilicon layer are both connected to the source potential. The present application reduces the source-drain voltage Vsd of the device by adding the MGD structure in the device, and at the same time, reduces the reverse recovery charge Qrr and the reverse recovery time Trr, thereby improving the circuit efficiency. When the device is turned off, the circuit provides an extraction current to extract the reverse recovery charge Qrr from the epitaxial layer to the upper polysilicon layer of the MGD structure. BRIEF DESCRIPTION OF DRAWINGS

[0046] Figure 1 A process flow chart of the manufacturing method of the shielded gate trench device with MGD structure is shown.

[0047] Figure 2 A schematic diagram of the substrate provided by the manufacturing method of the shielded gate trench device with MGD structure is shown.

[0048] Figure 3 A planar layout diagram of the shielded gate trench transistor region and the MOS gate-controlled diode region is shown.

[0049] Figure 4 A structural schematic diagram of the shielded gate trench device with MGD structure after the first trench and the second trench are formed by the manufacturing method of the shielded gate trench device with MGD structure is shown.

[0050] Figure 5 A structure diagram shown after depositing a first oxide layer in a manufacturing method of a shield gate trench device with MGD structure of the present application.

[0051] Figure 6 A structure diagram shown after depositing a first polysilicon layer in a manufacturing method of a shield gate trench device with MGD structure of the present application.

[0052] Figure 7 A structure diagram shown after etching back the first polysilicon layer to a first preset depth in a manufacturing method of a shield gate trench device with MGD structure of the present application.

[0053] Figure 8 A structure diagram shown after wet etching the first oxide layer in a manufacturing method of a shield gate trench device with MGD structure of the present application.

[0054] Figure 9 A structure diagram shown after depositing a second oxide layer in a manufacturing method of a shield gate trench device with MGD structure of the present application.

[0055] Figure 10 A structure diagram shown after etching back the second oxide layer C and the first oxide layer A to a second preset depth in a manufacturing method of a shield gate trench device with MGD structure of the present application.

[0056] Figure 11 A structure diagram shown after forming a third oxide layer in a manufacturing method of a shield gate trench device with MGD structure of the present application.

[0057] Figure 12 A structure diagram shown after forming a photoresist layer in a manufacturing method of a shield gate trench device with MGD structure of the present application.

[0058] Figure 13 A structure diagram shown after patterning the photoresist layer in a manufacturing method of a shield gate trench device with MGD structure of the present application.

[0059] Figure 14 A structure diagram shown after removing the part of the third oxide layer located on the sidewall of the second trench in a manufacturing method of a shield gate trench device with MGD structure of the present application.

[0060] Figure 15 A structure diagram shown after removing the photoresist layer and forming a fourth oxide layer in a manufacturing method of a shield gate trench device with MGD structure of the present application.

[0061] Figure 16Figure 6 shows a schematic diagram of the structure of the shielded gate trench device with MGD structure according to the present application after the formation of the second polysilicon layer in the manufacturing method thereof.

[0062] Figure 17 Figure 7 shows a schematic diagram of the structure of the shielded gate trench device with MGD structure according to the present application after the patterning of the second polysilicon layer in the manufacturing method thereof.

[0063] Figure 18 Figure 8 shows a schematic diagram of the structure of the shielded gate trench device with MGD structure according to the present application after the formation of the P-type body region, N-type source region and source metal layer in the manufacturing method thereof.

[0064] BRIEF DESCRIPTION OF DRAWINGS

[0065] S1-S5 steps

[0066] 1 N-type substrate

[0067] 2 N-type epitaxial layer

[0068] 3 First trench

[0069] 4 Second trench

[0070] 5 Mask layer

[0071] 6 First shield gate oxide layer

[0072] 7 First shield gate polysilicon layer

[0073] 8 First isolation layer

[0074] 9 Second shield gate oxide layer

[0075] 10 Second shield gate polysilicon layer

[0076] 11 Second isolation layer

[0077] 12 Control gate oxide layer

[0078] 13 Control gate polysilicon layer

[0079] 14 Third shield gate oxide layer

[0080] 15 Third shield gate polysilicon layer

[0081] 16 Photoresist layer

[0082] 17 P-type body region

[0083] 18 N-type source region

[0084] 19 Source metal layer

[0085] 20 Dielectric layer

[0086] 21 via

[0087] I shielded gate trench transistor region

[0088] II MOS gate controlled diode region

[0089] A first oxide layer

[0090] B first polysilicon layer

[0091] C second oxide layer

[0092] D third oxide layer

[0093] E fourth oxide layer

[0094] F second polysilicon layer DETAILED DESCRIPTION

[0095] The present application is herein described, by way of example only, with the assistance of the accompanying drawings detailed description giving specific embodiments thereof. Other advantages and benefits will readily occur to those skilled in the art having the benefit of the present description. The present application can be practiced in alternative or equivalent manners than those specifically illustrated herein without departing from the spirit of the present application. The detailed description is therefore not to be considered in a limiting sense in any respect.

[0096] It is emphasized that the terms "comprises / comprising" when used in this specification are taken to specify the presence of stated features, integers, steps or components but do not preclude the presence or addition of one or more other features, integers, steps, components or groups thereof.

[0097] Features described and / or illustrated with respect to one embodiment can be used in the same or similar manner in one or more other embodiments in combination with or in place of features of other embodiments.

[0098] As will be realized, the application is capable of modifications in various obvious aspects, all without departing from the application. The application also is capable of other embodiments and of being practiced or being carried out in various ways. Examples of specific implementations are described in detail herein. These and other embodiments of the application are described in detail below.

[0099] In this document, relational terms such as "first," "second," and the like can be used solely to distinguish one entity or action from another entity or action, without necessarily requiring or implying any actual such relationship or order between such entities or actions. The terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element. The terms "a" and "an" are defined as taking the singular or plural as appropriate for the context. The terms "substantially," "essentially," "approximately," and the like are defined to include deviations that can exist in the real world situations such as variations in manufacturing or other processes that can result in small but not significant deviations.

[0100] In the context of the present application, a structure in which a first feature is described as being "on" a second feature can include embodiments in which the first and second features form direct contact, as well as embodiments in which additional features are formed between the first and second features, such that the first and second features can not be in direct contact.

[0101] It should be noted that the diagrams provided in the embodiments only schematically illustrate the basic concepts of the present application, and thus only the components related to the present application are shown in the diagrams, rather than being drawn according to the number, shape and size of the components in actual implementation. The shapes, number and proportions of the components in actual implementation can be arbitrarily changed, and the layout pattern of the components can be more complex.

[0102] Embodiment One

[0103] The present application provides a manufacturing method of a shield gate trench device with an MGD structure. Please refer to Figure 1 , which shows a process flow diagram of the method, including the following steps:

[0104] S1: providing a substrate, the substrate including an N-type substrate and an N-type epitaxial layer on the N-type substrate, the substrate being divided into shield gate trench transistor regions and MOS gate-controlled diode regions which are alternately arranged along a preset direction in a plane of the substrate;

[0105] S2: forming a first trench and a second trench in the N-type epitaxial layer, the first trench being located in the shield gate trench transistor region, and the second trench being located in the MOS gate-controlled diode region;

[0106] S3: forming a first shield gate oxide layer, a first shield gate polysilicon layer and a first isolation layer in the first trench, and forming a second shield gate oxide layer, a second shield gate polysilicon layer and a second isolation layer in the second trench;

[0107] S4: forming a control gate oxide layer and a control gate polysilicon layer in the first trench, and forming a third shield gate oxide layer and a third shield gate polysilicon layer in the second trench;

[0108] S5: forming a P-type body region, an N-type source region and a source metal layer, the P-type body region being located on an upper surface layer of the N-type epitaxial layer, the N-type source region being located on an upper surface layer of the P-type body region, and the source metal layer being electrically connected to the P-type body region and the N-type source region.

[0109] The manufacturing method of the present application divides the substrate plane into shield gate trench transistor regions and MOS gate-controlled diode regions which are arranged alternately along a preset direction, forms a first trench in the shield gate trench transistor region, and forms a second trench in the MOS gate-controlled diode region. The MGD structure includes a second shield gate oxide layer, a second shield gate polysilicon layer, a second isolation layer, a third shield gate oxide layer, and a third shield gate polysilicon layer in the second trench. The third shield gate polysilicon layer is above the second shield gate polysilicon layer and is separated from the second shield gate polysilicon layer by the second isolation layer. The first shield gate polysilicon layer, the second shield gate polysilicon layer, and the third shield gate polysilicon layer are all connected to the source potential. The presence of the MGD structure can reduce the device source-drain voltage Vsd, and can also reduce the reverse recovery charge Qrr and the reverse recovery time Trr, thereby improving the circuit efficiency.

[0110] The above steps are described in detail below in combination with the drawings.

[0111] First, refer to Figure 2 , the step S1 of providing a substrate is performed. The substrate includes an N-type substrate 1 and an N-type epitaxial layer 2 on the N-type substrate 1. The substrate plane is divided into shield gate trench transistor regions I and MOS gate-controlled diode regions II which are arranged alternately along a preset direction.

[0112] As an example, the doping concentration of the N-type substrate 1 is higher than that of the N-type epitaxial layer 2. The specific doping concentration can be adjusted according to actual needs, and is not specifically limited in the present application.

[0113] As an example, refer to Figure 3 , which shows a planar layout of the shield gate trench transistor regions I (SGT) and the MOS gate-controlled diode regions II (MGD). The number of the shield gate trench transistor regions I and the MOS gate-controlled diode regions II is both multiple and arranged alternately. The specific number of each region can be set according to actual needs, and is not specifically limited in the present application.

[0114] As an example, Figure 3 also shows the width W1 of the shield gate trench transistor region I and the width W2 of the MOS gate-controlled diode region II. The width W1 of the shield gate trench transistor region I is greater than the width W2 of the MOS gate-controlled diode region II. The specific value can be set according to actual needs, for example, in some examples, W1 is 10 times W2.

[0115] Again refer to Figure 4, the step S2 is performed: forming the first trench 3 and the second trench 4 in the N-type epitaxial layer 2 by dry etching and / or wet etching, the first trench 3 is located in the shield gate trench transistor region I, and the second trench 4 is located in the MOS gate-controlled diode region II.

[0116] As an example, a mask layer 5 is first formed on the N-type epitaxial layer 2, then the mask layer 5 is patterned, and the N-type epitaxial layer 2 is etched based on the patterned mask layer 5 to obtain the first trench 3 and the second trench 4, wherein the mask layer 5 can adopt a multi-layer structure, for example, a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer are sequentially included from bottom to top, and the specific depth of the first trench 3 and the second trench 4 can be set according to actual needs, which is not specifically limited in the present application.

[0117] As an example, the number of the first trench 3 in one of the shield gate trench transistor regions I is M, and the number of the second trench 4 in one of the adjacent MOS gate-controlled diode regions II is N, wherein N≥1 and M≥N.

[0118] Specifically, the ratio of M / N can be set according to actual needs, taking into account the required source-drain voltage and effective device area, for example, in some examples, M / N≥5, and in a specific example, M / N equals 10.

[0119] As an example, the pitch between the second trench 4 and the adjacent first trench 3 is equal to the pitch between two adjacent first trenches 3 (when M≥2), and the pitch between two adjacent second trenches 4 (when N≥2) is equal to the pitch between two adjacent first trenches 3.

[0120] Please also refer to Figures 5 to 9 , the step S3 is performed: forming the first shield gate oxide layer 6, the first shield gate polysilicon layer 7, and the first isolation layer 8 in the first trench 3, and forming the second shield gate oxide layer 9, the second shield gate polysilicon layer 10, and the second isolation layer 11 in the second trench 4.

[0121] As an example, forming the first shield gate oxide layer 6, the first shield gate polysilicon layer 7, and the first isolation layer 8 in the first trench 3, and forming the second shield gate oxide layer 9, the second shield gate polysilicon layer 10, and the second isolation layer 11 in the second trench 4 includes the following steps:

[0122] (1) As shown in Figure 5 , a first oxide layer A is deposited by a thermal oxidation method, a chemical vapor deposition method, or other suitable methods, covering the inner walls of the first trench 3 and the second trench 4, and in some examples, the first oxide layer A also covers the upper surface of the mask layer 5;

[0123] (2) As shown in FIG. 2B, a first polysilicon layer B is deposited, which fills into the first trench 3 and the second trench 4, and in some examples, covers the mask layer 5 as well. Figure 6

[0124] (3) As shown in FIG. 2C, the first polysilicon layer B is etched back to a first preset depth, and in some examples, the mask layer 5 is thinned in the process. Figure 7

[0125] (4) As shown in FIG. 2D, the first oxide layer A is etched by wet etching to expose part of the sidewall of the first polysilicon layer B, so that the subsequently deposited oxide layer can better cover the top end of the first polysilicon layer B. Figure 8

[0126] (5) As shown in FIG. 2E, a second oxide layer C is deposited by chemical vapor deposition or other suitable methods, which fills into the first trench 3 and the second trench 4 and covers the exposed surface of the first polysilicon layer B, and in some examples, covers the mask layer 5 as well. Figure 9

[0127] (6) As shown in FIG. 2F, the second oxide layer C and the first oxide layer A are etched back to a second preset depth, which is higher than the first preset depth. At this time, the part of the first oxide layer A in the first trench 3 serves as the first shield gate oxide layer 6, the part of the first oxide layer A in the second trench 4 serves as the second shield gate oxide layer 9, the part of the first polysilicon layer B in the first trench 3 serves as the first shield gate polysilicon layer 7, the part of the first polysilicon layer B in the second trench 4 serves as the second shield gate polysilicon layer 10, the part of the second oxide layer C in the first trench 3 serves as the first isolation layer 8, and the part of the second oxide layer C in the second trench 4 serves as the second isolation layer 11. Figure 10

[0128] As shown in FIG. 3B, the step S4 of forming the control gate oxide layer 12 and the control gate polysilicon layer 13 in the first trench 3, and forming the third shield gate oxide layer 14 and the third shield gate polysilicon layer 15 in the second trench 4 is performed. Figures 11 to 17 As an example, forming the control gate oxide layer 12 and the control gate polysilicon layer 13 in the first trench 3, and forming the third shield gate oxide layer 14 and the third shield gate polysilicon layer 15 in the second trench 4 includes the following steps:

[0129]

[0130] ​​​​​​(1) As Figure 11 As shown, a third oxide layer D is formed by thermal oxidation, chemical vapor deposition or other suitable methods. The third oxide layer D covers the exposed sidewalls of the first trench 3 and the second trench 4. In some examples, the third oxide layer D also covers the N-type epitaxial layer 2. The first isolation layer 8 and the second isolation layer 11 are also thickened.

[0131] (2) Figure 12 As shown, a photoresist layer 16 is formed, which covers the N-type epitaxial layer 2 and fills the first trench 3 and the second trench 4;

[0132] (3) Figure 13 As shown, the photoresist layer 16 is patterned using a photolithography process to obtain an opening that exposes the MOS gate-controlled diode region II;

[0133] (4) Figure 14 As shown, the portion of the third oxide layer D located on the sidewall of the second trench 4 is removed by wet etching or other suitable methods, and the portion of the third oxide layer D located on the sidewall of the first trench 3 serves as the control gate oxide layer 12.

[0134] (5) Figure 15 As shown, the photoresist layer 16 is removed, and a fourth oxide layer E is formed by thermal oxidation, chemical vapor deposition, or other suitable methods. The fourth oxide layer E at least covers the exposed sidewalls of the second trench 4. The portion of the fourth oxide layer E covering the sidewalls of the second trench 4 serves as the third shielding gate oxide layer 14. In some examples, the fourth oxide layer E also covers the N-type epitaxial layer 2, and the second isolation layer 11 is also thickened in the process.

[0135] It should be noted that during the formation of the fourth oxide layer E, the control gate oxide layer 12 may also thicken to a certain extent.

[0136] (6) Figure 16 As shown, a second polysilicon layer F is formed, which covers the N-type epitaxial layer 2 and fills the first trench 3 and the second trench 4;

[0137] (7) Figure 17 As shown, the second polysilicon layer F is graphically represented to obtain the control gate polysilicon layer 13 located in the first trench 3 and the third shielding gate polysilicon layer 15 located in the second trench 4.

[0138] Specifically, the control gate polysilicon layer 13 is located above the first shield gate polysilicon layer 7 and is spaced from the first shield gate polysilicon layer 7 by the first isolation layer 8, the first shield gate oxide layer 6 is located between the outer wall of the first shield gate polysilicon layer 7 and the inner wall of the first trench 2, and the control gate oxide layer 12 is located between the outer wall of the control gate polysilicon layer 13 and the inner wall of the first trench 3.

[0139] Specifically, the third shield gate polysilicon layer 15 is located above the second shield gate polysilicon layer 10 and is spaced from the second shield gate polysilicon layer 10 by the second isolation layer 11, the second shield gate oxide layer 9 is located between the outer wall of the second shield gate polysilicon layer 10 and the inner wall of the second trench 4, and the third shield gate oxide layer 14 is located between the outer wall of the third shield gate polysilicon layer 15 and the inner wall of the second trench 4.

[0140] As an example, the thickness of the third shield gate oxide layer 14 is less than the thickness of the control gate oxide layer 12, and in some examples, the thickness of the third shield gate oxide layer 14 ranges from 60 angstroms to 70 angstroms, for example 65 angstroms, and the thickness of the control gate oxide layer 12 ranges from 250 angstroms to 350 angstroms, for example 300 angstroms.

[0141] Please also refer to Figure 18 , the step S5 of forming a P-type body region 17, an N-type source region 18, and a source metal layer 19 is performed, the P-type body region 17 is located on the upper surface layer of the N-type epitaxial layer 2, the N-type source region 18 is located on the upper surface layer of the P-type body region 17, and the source metal layer 19 is electrically connected to the P-type body region 17 and the N-type source region 18.

[0142] As an example, the method of forming the P-type body region 17 and the N-type source region 18 includes ion implantation, and the desired doping concentration and doping depth can be achieved by controlling the implantation dose, energy, etc., and the method of forming the source metal layer 19 includes but is not limited to electroplating, physical vapor deposition, etc.

[0143] Specifically, an interlayer dielectric layer 20 is formed before the source metal layer 19 is formed, and a desired via hole 21 is formed in a predetermined position of the interlayer dielectric layer 20, the via hole extends downward into the N-type source region 18 and the P-type body region 17, the via hole 21 is filled with conductive material, and the source metal layer 19 is electrically connected to the P-type body region 17 and the N-type source region 18 through the via hole 21.

[0144] Specifically, the first shield gate polysilicon layer 7, the second shield gate polysilicon layer 10, and the third shield gate polysilicon layer 15 are all connected to the source potential.

[0145] Specifically, the reverse recovery charge Qrr refers to the amount of charge stored in the device when the device switches from the forward conducting state to the reverse blocking state, and this charge needs to be cleared when the device switches from the conducting state to the off state, and the reverse recovery time Trr refers to the time required for the device to completely switch from the forward conducting state to the reverse blocking state, which includes the time for the stored charge to decrease to zero, and the time for the device to reach a stable state, and a shorter Trr means that the device can switch from the conducting state to the off state faster. The manufacturing method of the shield gate trench device of the present application helps to reduce the source-drain voltage Vsd of the device, while reducing the reverse recovery charge Qrr and the reverse recovery time Trr, thereby improving the circuit efficiency, wherein when the device is off, the circuit provides an extraction current to extract the reverse recovery charge Qrr from the N-type epitaxial layer 2 to the upper polysilicon layer of the MGD structure (i.e. the third shield gate polysilicon layer 15) for discharge.

[0146] Example Two

[0147] In this embodiment, a shield gate trench device with MGD structure is provided, which can be manufactured by the manufacturing method described in Example One or other suitable methods. Please refer to Figure 18 , which shows the structure diagram of the shield gate trench device with MGD structure, including a substrate, a first trench 3, a second trench 4, a first shield gate oxide layer 6, a first shield gate polysilicon layer 7, a first isolation layer 8, a control gate oxide layer 12, a control gate polysilicon layer 13, a second shield gate oxide layer 9, a second shield gate polysilicon layer 10, a second isolation layer 11, a third shield gate oxide layer 14, a third shield gate polysilicon layer 15, a P-type body region 17, an N-type source region 18, and a source metal layer 19.

[0148] Specifically, the substrate includes an N-type substrate 1 and an N-type epitaxial layer 2 located on the N-type substrate 1, and the substrate is divided into a shield gate trench transistor region I and a MOS gate-controlled diode region II alternately arranged along a predetermined direction, the first trench 3 is located in the N-type epitaxial layer 2 of the shield gate trench transistor region I, and the second trench 4 is located in the N-type epitaxial layer 2 of the MOS gate-controlled diode region II.

[0149] Specifically, the first shield gate oxide layer 6, the first shield gate polysilicon layer 7, the first isolation layer 8, the control gate oxide layer 12 and the control gate polysilicon layer 13 are located in the first trench 3, the control gate polysilicon layer 12 is located above the first shield gate polysilicon layer 7 and is spaced from the first shield gate polysilicon layer 7 by the first isolation layer 8, the first shield gate oxide layer 6 is located between the outer wall of the first shield gate polysilicon layer 7 and the inner wall of the first trench 2, the control gate oxide layer 12 is located between the outer wall of the control gate polysilicon layer 13 and the inner wall of the first trench 3, and the first shield gate polysilicon layer 7 is connected to the source electrode.

[0150] Specifically, the second shield gate oxide layer 9, the second shield gate polysilicon layer 10, the second isolation layer 11, the third shield gate oxide layer 14 and the third shield gate polysilicon layer 15 are located in the second trench 4, the third shield gate polysilicon layer 15 is located above the second shield gate polysilicon layer 10 and is spaced from the second shield gate polysilicon layer 10 by the second isolation layer 11, the second shield gate oxide layer 9 is located between the outer wall of the second shield gate polysilicon layer 10 and the inner wall of the second trench 4, the third shield gate oxide layer 14 is located between the outer wall of the third shield gate polysilicon layer 15 and the inner wall of the second trench 4, and the second shield gate polysilicon layer 10 and the third shield gate polysilicon layer 14 are both connected to the source electrode.

[0151] Specifically, the P-type body region 17 is located on the upper surface layer of the N-type epitaxial layer 2, the N-type source region 18 is located on the upper surface layer of the P-type body region 17, and the source metal layer 19 is electrically connected to the P-type body region 17 and the N-type source region 18.

[0152] As an example, the number of the first trench 3 in one shield gate trench type transistor region I is M, and the number of the second trench 4 in one adjacent MOS gate-controlled diode region II is N, where N≥1 and M≥N.

[0153] Specifically, the ratio of M / N can be set according to actual needs, taking into account the required source-drain voltage and effective device area, for example, in some examples, M / N≥5, and in a specific example, M / N equals 10.

[0154] As an example, the spacing between the second trench 4 and the adjacent first trench 3 is equal to the spacing between two adjacent first trenches 3 (when M≥2), and the spacing between two adjacent second trenches 4 (when N≥2) is equal to the spacing between two adjacent first trenches 3.

[0155] As an example, the third shield gate oxide layer 14 has a thickness less than the thickness of the control gate oxide layer 12, in some examples the thickness of the third shield gate oxide layer 14 ranges from 60 angstroms to 70 angstroms, for example 65 angstroms, and the thickness of the control gate oxide layer 12 ranges from 250 angstroms to 350 angstroms, for example 300 angstroms.

[0156] The shield gate trench device with MGD structure has lower source-drain voltage Vsd, reverse recovery charge Qrr and reverse recovery time Trr, and higher circuit efficiency.

[0157] In summary, the shield gate trench device with MGD structure and the manufacturing method thereof integrate the MGD structure in the ordinary SGT device, wherein the substrate is divided into the shield gate trench transistor region and the MOS gate-controlled diode region which are alternately arranged along the preset direction, the shield gate trench transistor region and the MOS gate-controlled diode region are respectively provided with the first trench and the second trench, the MGD structure includes the second shield gate oxide layer, the second shield gate polysilicon layer, the second isolation layer, the third shield gate oxide layer and the third shield gate polysilicon layer which are located in the second trench, the third shield gate polysilicon layer is located above the second shield gate polysilicon layer and is separated therefrom by the second isolation layer, and the second shield gate polysilicon layer and the third shield gate polysilicon layer are both connected to the source potential. The MGD structure is added to the device to reduce the source-drain voltage Vsd, and at the same time, the reverse recovery charge Qrr and the reverse recovery time Trr are reduced, thereby improving the circuit efficiency. When the device is turned off, the circuit provides an extraction current to extract the reverse recovery charge Qrr from the epitaxial layer to the upper polysilicon layer of the MGD structure. Therefore, the present application effectively overcomes the shortcomings of the prior art and has high industrial utilization value.

[0158] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical thought of the present application should be covered by the claims of the present application.

Claims

1. A method for fabricating a shielding trench device with an MGD structure, characterized in that, The method comprises the following steps: providing a substrate, wherein the substrate comprises an N-type substrate and an N-type epitaxial layer on the N-type substrate, and the substrate is divided into shield gate trench transistor regions and MOS gate-controlled diode regions in a preset direction alternately; forming a first trench and a second trench in the N-type epitaxial layer, wherein the first trench is located in the shield gate trench transistor region, and the second trench is located in the MOS gate-controlled diode region; forming a first shield gate oxide layer, a first shield gate polysilicon layer and a first isolation layer in the first trench, and forming a second shield gate oxide layer, a second shield gate polysilicon layer and a second isolation layer in the second trench; forming a control gate oxide layer and a control gate polysilicon layer in the first trench, and forming a third shield gate oxide layer and a third shield gate polysilicon layer in the second trench; forming a P-type body region, an N-type source region and a source metal layer, wherein the P-type body region is located on the upper surface layer of the N-type epitaxial layer, the N-type source region is located on the upper surface layer of the P-type body region, and the source metal layer is electrically connected with the P-type body region and the N-type source region, the control gate polysilicon layer is located above the first shield gate polysilicon layer and is spaced from the first shield gate polysilicon layer by the first isolation layer, the first shield gate oxide layer is located between the outer wall of the first shield gate polysilicon layer and the inner wall of the first trench, and the control gate oxide layer is located between the outer wall of the control gate polysilicon layer and the inner wall of the first trench; the third shield gate polysilicon layer is located above the second shield gate polysilicon layer and is spaced from the second shield gate polysilicon layer by the second isolation layer, the second shield gate oxide layer is located between the outer wall of the second shield gate polysilicon layer and the inner wall of the second trench, and the third shield gate oxide layer is located between the outer wall of the third shield gate polysilicon layer and the inner wall of the second trench; the first shield gate polysilicon layer, the second shield gate polysilicon layer and the third shield gate polysilicon layer are all connected to a source potential.

2. The method of claim 1, wherein the MGD structure is formed by a process comprising: forming a first shield gate oxide layer, a first shield gate polysilicon layer and a first isolation layer in the first trench, and forming a second shield gate oxide layer, a second shield gate polysilicon layer and a second isolation layer in the second trench comprises the following steps: depositing a first oxide layer, wherein the first oxide layer covers the inner walls of the first trench and the second trench; depositing a first polysilicon layer, wherein the first polysilicon layer fills into the first trench and the second trench; dry etching the first polysilicon layer to a first preset depth; wet etching the first oxide layer to expose part of the sidewall of the first polysilicon layer; depositing a second oxide layer, wherein the second oxide layer fills into the first trench and the second trench and covers the exposed surface of the first polysilicon layer; etching the second oxide layer and the first oxide layer to a second preset depth, the second preset depth being higher than the first preset depth, at this time, the part of the first oxide layer in the first trench serving as the first shield gate oxide layer, the part of the first oxide layer in the second trench serving as the second shield gate oxide layer, the part of the first polysilicon layer in the first trench serving as the first shield gate polysilicon layer, the part of the first polysilicon layer in the second trench serving as the second shield gate polysilicon layer, the part of the second oxide layer in the first trench serving as the first isolation layer, and the part of the second oxide layer in the second trench serving as the second isolation layer.

3. The method of claim 1, wherein the MGD structure is formed by a process comprising: forming a control gate oxide layer and a control gate polysilicon layer in the first trench, and forming a third shield gate oxide layer and a third shield gate polysilicon layer in the second trench, comprising the following steps: forming a third oxide layer covering the exposed sidewalls of the first trench and the exposed sidewalls of the second trench; forming a photoresist layer covering the N-type epitaxial layer and filling into the first trench and the second trench; patterning the photoresist layer to obtain an opening exposing the MOS gate-controlled diode region; removing the part of the third oxide layer on the sidewall of the second trench, and the part of the third oxide layer on the sidewall of the first trench serving as the control gate oxide layer; removing the photoresist layer, and forming a fourth oxide layer covering at least the exposed sidewall of the second trench, the part of the fourth oxide layer covering the sidewall of the second trench serving as the third shield gate oxide layer; forming a second polysilicon layer covering the N-type epitaxial layer and filling into the first trench and the second trench; patterning the second polysilicon layer to obtain the control gate polysilicon layer in the first trench and the third shield gate polysilicon layer in the second trench.

4. The method of claim 1, wherein: The number of the first trenches in one shield gate trench transistor region is M, and the number of the second trenches in one MOS gate-controlled diode region adjacent to the shield gate trench transistor region is N, wherein N≥1 and M≥N.

5. The method of claim 4, wherein: M / N≥5.

6. The method of making a shielded gate trench device with MGD structure of claim 1, wherein: The thickness of the third shield gate oxide layer is less than the thickness of the control gate oxide layer.

7. The method of making a shielded gate trench device having a MGD structure of claim 6, wherein: The thickness of the third shield gate oxide layer ranges from 60 angstroms to 70 angstroms, and the thickness of the control gate oxide layer ranges from 250 angstroms to 350 angstroms.

8. A shielded gate trench device having an MGD structure, characterized by, comprising: a substrate comprising an N-type substrate and an N-type epitaxial layer on the N-type substrate, the substrate being divided by a preset direction into shield gate trench transistor regions and MOS gate-controlled diode regions arranged alternately; a first trench and a second trench in the N-type epitaxial layer, the first trench being in the shield gate trench transistor region, and the second trench being in the MOS gate-controlled diode region; The first shield gate oxide layer, the first shield gate polysilicon layer, the first isolation layer, the control gate oxide layer and the control gate polysilicon layer are located in the first trench, the control gate polysilicon layer is located above the first shield gate polysilicon layer and is spaced from the first shield gate polysilicon layer by the first isolation layer, the first shield gate oxide layer is located between the outer wall of the first shield gate polysilicon layer and the inner wall of the first trench, the control gate oxide layer is located between the outer wall of the control gate polysilicon layer and the inner wall of the first trench, and the first shield gate polysilicon layer is connected to the source electrode; The second shield gate oxide layer, the second shield gate polysilicon layer, the second isolation layer, the third shield gate oxide layer and the third shield gate polysilicon layer are located in the second trench, the third shield gate polysilicon layer is located above the second shield gate polysilicon layer and is spaced from the second shield gate polysilicon layer by the second isolation layer, the second shield gate oxide layer is located between the outer wall of the second shield gate polysilicon layer and the inner wall of the second trench, the third shield gate oxide layer is located between the outer wall of the third shield gate polysilicon layer and the inner wall of the second trench, and the second shield gate polysilicon layer and the third shield gate polysilicon layer are connected to the source electrode. The P-type body region, the N-type source region and the source metal layer, the P-type body region is located on the upper surface layer of the N-type epitaxial layer, the N-type source region is located on the upper surface layer of the P-type body region, and the source metal layer is electrically connected with the P-type body region and the N-type source region.

9. The shielded gate trench device having a MGD structure of claim 8, wherein: The number of the first trenches in one of the shield gate trench transistor regions is M, and the number of the second trenches in one of the adjacent MOS gate-controlled diode regions is N, wherein N≥1 and M≥N.

10. The shielded gate trench device having a MGD structure of claim 9, wherein: M / N≥5.

11. The shielded gate trench device having a MGD structure of claim 8, wherein: The thickness of the third shield gate oxide layer is less than the thickness of the control gate oxide layer.

12. The shielded gate trench device having a MGD structure of claim 11, wherein: The thickness of the third shield gate oxide layer is in the range of 60 angstroms to 70 angstroms, and the thickness of the control gate oxide layer is in the range of 250 angstroms to 350 angstroms.

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