Three-level converter SVPWM method and system based on multi-vector synthesis

Abstract

The present invention relates to a three-level converter SVPWM method and system based on multi-vector synthesis, the method comprising: dividing a three-level space voltage vector diagram into a plurality of sectors; controlling the duty ratio of a small vector and a middle vector in each sector to be equal, obtaining the constraint conditions of the small vector and the middle vector, combining the constraint conditions of the small vector and the middle vector, calculating the duty ratio of the output voltage vector in each sector; according to the duty ratio of the output voltage vector, combining the preset output voltage vector arrangement sequence, obtaining the output state of the three-phase bridge arm voltage in the three-level converter and the driving signal of each phase switch tube. The present invention uses multi-vectors to synthesize space vectors, and only needs to simply divide the space vector diagram into six sectors, and calculate the time for the synthetic vectors in the six sectors to act respectively, which significantly reduces the amount of calculation, and the implementation process is simple. By controlling the time for the small vector and the middle vector to act in each sector, the balance problem of the three-level midpoint voltage is solved.

Description

Technical Field

[0001] The present invention relates to the field of power electronics technology, and in particular to a three-level converter SVPWM method and system based on multi-vector synthesis. Background Art

[0002] With the rapid development of new energy technologies, such as the widespread application of renewable energy such as solar energy and wind energy, the demand for high-voltage and high-power grid-connected converters has increased dramatically. Three-level pulse width modulation (PWM) converters are superior to traditional PWM converters in terms of voltage level, power density, and current waveform quality. Therefore, three-level PWM converters are widely used in medium- and high-voltage, high-power, and high-performance equipment.

[0003] PWM modulation technology is one of the key technologies of three-level converters. The main methods currently include: carrier-based sinusoidal pulse width modulation (CB-SPWM), space vector pulse width modulation (SVPWM), specific harmonic elimination pulse width modulation (SHEPWM) and model predictive control without carrier modulation.

[0004] The traditional three-level converter SVPWM method usually uses the adjacent three-vector principle to synthesize the reference vector. This method requires dividing the voltage space vector diagram into 6 large sectors, and then into 24 small triangular areas or 36 small areas. Since each area needs to calculate the action time of three voltage vectors, and involves the calculation of trigonometric functions, the amount of calculation is large and the implementation process is complicated. Secondly, the switching between each large sector involves the switching of the switch tube, and the transition cannot be smooth. In addition, when the modulation is relatively small, only small vectors and zero vectors are used to synthesize the space vector Vr, so that the output line voltage of the three-level converter contains only three levels of ±Ebat / 2 and 0. The performance of its output line voltage is similar to that of the two-level SVPWM, and it cannot give full play to the advantages of the three-level converter. Summary of the invention

[0005] In view of this, it is necessary to provide a three-level converter SVPWM method based on multi-vector synthesis to solve the above-mentioned defects of the prior art.

[0006] In order to solve the above problems, in a first aspect, an embodiment of the present invention provides a three-level converter SVPWM method based on multi-vector synthesis, comprising:

[0007] Step S1, based on the three-level converter topology, defining the output voltage vector of the three-level converter, drawing the three-level converter space voltage vector diagram, and dividing the three-level space voltage vector diagram into a plurality of sectors; wherein the output voltage vector includes a large vector, a medium vector, a small vector and a zero vector;

[0008] Step S2, calculating the duty cycle of the large vector and the zero vector in each sector according to the volt-second balance principle;

[0009] Step S3, controlling the duty ratios of the small vector and the medium vector in each sector to be equal, and obtaining the constraint condition of the duty ratio of the output voltage vector;

[0010] Step S4, calculating the duty cycle of the output voltage vector in each sector according to the volt-second balance principle and the constraint condition of the duty cycle of the output voltage vector;

[0011] Step S5, according to the duty cycle of the output voltage vector and the preset arrangement sequence of the output voltage vector, the output state of the three-phase bridge arm voltage in the three-level converter and the driving signal of each phase switch are obtained.

[0012] Preferably, in step S1, based on the three-level converter topology structure, defining the output voltage vector of the three-level converter and drawing the three-level converter space voltage vector diagram include:

[0013] The three-level converter includes an A-phase bridge arm, a B-phase bridge arm and a C-phase bridge arm, and each phase bridge arm includes four switching devices and a pair of clamping diodes;

[0014] Each phase bridge arm of the three-level converter outputs three different voltage levels, including positive level P, zero level O and negative level N;

[0015] Based on the three possible output states P, O, and N of each phase bridge arm, 27 output voltage vectors of the three-level converter are defined; and a spatial voltage vector diagram of the three-level converter is drawn according to the output voltage vectors.

[0016] Preferably, in step S2, the calculation formula for obtaining the duty cycle of the large vector and the zero vector in each sector according to the volt-second balance principle is:

[0017]

[0018] In the formula, V r represents a space vector, T s is the switching cycle, V 21 and V 22 represents two large vectors, V 01 represents the zero vector, d _1 is the large vector V 21 The duty cycle, d _2 is the large vector V 22 The duty cycle, d_0 is the zero vector V 01 The duty cycle, i Represents space vector V r Located in the i-th sector.

[0019] Preferably, in step S4, the duty cycle of the output voltage vectors in the six sectors is calculated based on the volt-second balance principle and in combination with the constraints of the small vector and the middle vector, including:

[0020] Using multiple output voltage vectors to synthesize space vector V r According to the volt-second balance principle, we get:

[0021]

[0022] In the formula, d j1 , d j2 , d j3 , d j4 , d j5 , d j6 and d j7 Respectively represent the duty cycle of the corresponding output voltage vector; where, j =1, 2, 3, 4, 5, 6;

[0023] The duty cycles of the small vector and the medium vector are equal, and the constraint condition is obtained:

[0024] d j2 = d j4 = d j6

[0025] According to the volt-second balance, constraints and the relationship between the large vector, the medium vector and the small vector, the expression is obtained:

[0026]

[0027] In the formula, V 11 and V 12 represents two small vectors, V 01 and V 02 represents two zero vectors, V 31 represents the mid vector,d i_com is an intermediate variable within the six sectors, k i_com is the corresponding proportional adjustment coefficient;

[0028] According to the above expression, the duty cycle of the output voltage vector in the six sectors is obtained as follows:

[0029] .

[0030] Preferably, before step S5, the method further comprises:

[0031] Determine the arrangement order of the output voltage vectors of each sector; wherein each sector uses a zero vector as a starting vector;

[0032] In each sector, the output voltage vector is arranged in the order of zero vector V 01 , small vector V 11 , Large Vector V 21 , Medium Vector V 31 , Large Vector V 22 , small vector V 12 and zero vector V 02 .

[0033] In a second aspect, an embodiment of the present invention provides a three-level converter SVPWM system based on multi-vector synthesis, comprising:

[0034] A vector diagram partitioning module, for defining an output voltage vector of a three-level converter based on a three-level converter topology, drawing a three-level converter space voltage vector diagram, and dividing the three-level space voltage vector diagram into a plurality of sectors; wherein the output voltage vector includes a large vector, a medium vector, a small vector and a zero vector;

[0035] A first calculation module is used to calculate the duty cycle of the large vector and the zero vector in each sector according to the volt-second balance principle;

[0036] A vector constraint module is used to control the duty ratio of the small vector and the medium vector in each sector to be equal, and obtain the constraint condition of the duty ratio of the output voltage vector;

[0037] The second calculation module is used to calculate the duty cycle of the output voltage vector in each sector according to the volt-second balance principle and the constraint condition of the duty cycle of the output voltage vector;

[0038] The signal output module is used to obtain the output state of the three-phase bridge arm voltage in the three-level converter and the driving signal of each phase switch tube according to the duty cycle of the output voltage vector and the preset output voltage vector arrangement order.

[0039] In a third aspect, the present invention further provides an electronic device, including a memory and a processor, wherein:

[0040] The memory is used to store programs;

[0041] The processor is coupled to the memory and is used to execute the program stored in the memory to implement the steps in the three-level converter SVPWM method based on multi-vector synthesis as described in the embodiment of the first aspect of the present invention.

[0042] In a fourth aspect, the present invention further provides a computer-readable storage medium for storing computer-readable programs or instructions, which, when executed by a processor, can implement the steps in the three-level converter SVPWM method based on multi-vector synthesis as described in the embodiment of the first aspect of the present invention.

[0043] The three-level converter SVPWM method and system based on multi-vector synthesis provided by the present invention have the following beneficial effects compared with the prior art:

[0044] 1) The three-level converter SVPWM method provided by the present invention adopts multiple vectors to synthesize the space vector. It only needs to simply divide the space vector diagram into six sectors, and only needs to calculate the time when the synthesized vectors in the six sectors act respectively, which significantly reduces the amount of calculation and is simple to implement.

[0045] 2) Since each sector uses the zero vector as the starting vector, the switching between sectors is guaranteed to be smooth.

[0046] 3) When the modulation is relatively small, the output line voltage of the three-level converter still contains five levels, which can ensure a high-quality output voltage waveform.

[0047] 4) By controlling the action time of the small vector and the middle vector in each sector, the average value of the midpoint current on the DC side of the three-level converter in each switching cycle is made zero, thus solving the balance problem of the three-level midpoint voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 A flow chart of a three-level converter SVPWM method based on multi-vector synthesis provided by the present invention;

[0049] Figure 2 A topological structure diagram of the main circuit of an NPC three-level converter provided in an embodiment of the present invention;

[0050] Figure 3 A spatial voltage vector diagram of a three-level converter provided by the present invention;

[0051] Figure 4 The output voltage vector diagram of sector I provided by the present invention;

[0052] Figure 5 Output voltage vector switching and duty cycle in sector I provided by the present invention;

[0053] Figure 6 The voltage waveform of the upper and lower capacitors on the DC side provided by the embodiment of the present invention;

[0054] FIG7 (a) is a three-phase output current waveform of a three-level converter provided by an embodiment of the present invention;

[0055] FIG7( b ) is a three-phase current waveform in an enlarged region provided by an embodiment of the present invention;

[0056] FIG8 (a) is a line voltage waveform of a three-level converter provided by an embodiment of the present invention;

[0057] FIG8( b ) is an enlarged regional line voltage waveform provided by an embodiment of the present invention;

[0058] Fig. 9 This is a structural block diagram of the electronic device provided by the present invention. DETAILED DESCRIPTION

[0059] The preferred embodiments of the present invention are described in detail below in conjunction with the accompanying drawings, wherein the accompanying drawings constitute a part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, but are not used to limit the scope of the present invention.

[0060] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0061] The traditional three-level converter SVPWM method usually uses the adjacent three-vector principle to synthesize the reference vector. This method requires dividing the voltage space vector diagram into 6 large sectors, and then into 24 small triangular areas or 36 small areas. Since each area needs to calculate the action time of three voltage vectors, and involves the calculation of trigonometric functions, the amount of calculation is large and the implementation process is complicated. Secondly, the switching between each large sector involves the switching of the switch tube, and the transition cannot be smooth. In addition, when the modulation is relatively small, only small vectors and zero vectors are used to synthesize the space vector Vr, so that the output line voltage of the three-level converter contains only three levels of ±Ebat / 2 and 0. The performance of its output line voltage is similar to that of the two-level SVPWM, and it cannot give full play to the advantages of the three-level converter.

[0062] In view of this, in order to simplify the implementation of the modulation wave, reduce the amount of calculation, reduce the switching of vectors between sectors, and ensure high-quality output waveforms under low modulation ratios, while eliminating the influence of small vectors and medium vectors in each sector on the midpoint voltage. The present invention provides a three-level converter SVPWM method based on multi-vector synthesis, which uses multi-vectors to synthesize space vectors. It only needs to simply divide the space vector diagram into six sectors, and only needs to calculate the time for the synthetic vectors in the six sectors to act respectively, which significantly reduces the amount of calculation and is simple to implement. The following will be explained and introduced through multiple embodiments.

[0063] Figure 1 The flowchart of the SVPWM method of the three-level converter based on multi-vector synthesis provided by the present invention is shown in FIG. Figure 1 As shown, the three-level converter SVPWM method based on multi-vector synthesis includes the following steps S1 to S5, wherein:

[0064] Step S1, based on the three-level converter topology, define the output voltage vector of the three-level converter, draw the three-level converter space voltage vector diagram, and divide the three-level space voltage vector diagram into a plurality of sectors; the number of sectors is preferably 6. The output voltage vector includes a large vector, a medium vector, a small vector and a zero vector.

[0065] In this embodiment, the application of an NPC three-level converter in an energy storage system is taken as an example to illustrate the SVPWM (Space Vector Pulse Width Modulation) method provided by the present invention. Figure 2 The topological structure diagram of the main circuit of the NPC three-level converter in the energy storage system provided by the embodiment of the present invention is shown in FIG. Figure 2 The three-level converter includes an A-phase bridge arm, a B-phase bridge arm and a C-phase bridge arm. Each phase bridge arm includes four switching devices and a pair of clamping diodes; the switching devices and two capacitors of equal capacitance (C up and Cdown ) is the midpoint O 1 The input end of the DC side of the three-level converter is connected to the energy storage battery, and the AC side is connected to the grid through the LCL filter. When only the switches S1 and S2 of the A-phase bridge arm are turned on at the same time, the output voltage of the bridge arm v ao is equal to E bat / 2, the state of the bridge arm voltage is defined as P. When only the switches S2 and S3 of the bridge arm of phase A are turned on at the same time, the output voltage of the bridge arm is v ao is equal to 0, and the state of the bridge arm voltage is defined as 0. When only the switches S3 and S4 of the A phase bridge arm are turned on at the same time, the bridge arm output voltage v ao equals - E bat / 2, the state of the bridge arm voltage is defined as N. Similarly, the output voltage of the bridge arm of phase B and C is v bo, v co is similar.

[0066] Space voltage vector of three-phase three-level converter V r It can be expressed as:

[0067] (1)

[0068] Each phase bridge arm of the three-level converter outputs three different voltage levels, including a positive level P, a zero level O, and a negative level N. That is, the output voltage of each phase bridge arm has three states: P, O, and N.

[0069] In this embodiment, based on the three possible output states P, O, and N of each phase bridge arm, 27 output voltage vectors of the three-level converter are defined. E The vector of bat / 3 is defined as a large vector, such as PPN, NPN. E The vector of bat / 3 is defined as the middle vector, such as PON, NPO. E The vector of bat / 3 is defined as a small vector, such as PPO, OPO; in addition, there are zero vectors, such as NNN, PPP. Next, the spatial voltage vector diagram of the three-level converter is drawn according to the output voltage vector, and the obtained spatial voltage vector diagram of the three-level converter is as follows: Figure 3 shown.

[0070] In step S1, the three-level space voltage vector diagram is divided into six sectors, each of which is an equilateral triangle and is respectively denoted as I, II, III, IV, V and VI. Figure 3 shown.

[0071] Figure 4The output voltage vector diagram of sector I provided by the present invention. In this embodiment, taking sector I as an example, the large vectors PNN and PPN are respectively used V 21 and V 22 Indicates that the medium vector PON is V 31 Indicates that the small vector ONN and PPO are respectively used V 11 and V 12 Indicates that the zero vectors NNN and PPP are respectively V 01 and V 02 Indicates that Figure 4 As shown. The large vector, medium vector and small vector are interrelated. V 21 =2 V 11 , V 22 =2 V 12 , V 21 + V 22 =2 V 31 , V 11 + V 12 = V 31 By analogy, the same relationship exists between large vectors, medium vectors, and small vectors in other sectors.

[0072] It can be understood that the conventional three-level converter SVPWM method usually uses the adjacent three-vector principle to synthesize the reference vector. When the modulation is relatively small, only the small vector and the zero vector are used to synthesize the space vector, so that the output line voltage of the three-level converter contains only three levels of ±Ebat / 2 and 0. The performance of its output line voltage is similar to that of the two-level SVPWM, and it is unable to give full play to the advantages of the three-level converter. In this embodiment, when the modulation is relatively small, the large vector, the medium vector, the small vector and the zero vector are still used to synthesize the space vector, so that the output line voltage of the three-level converter contains ± E bat, ± E bat / 2 and 0 to ensure high quality output voltage waveform.

[0073] Step S2, according to the volt-second balance principle, calculate the duty cycle of the large vector and the zero vector in each sector.

[0074] Specifically, the volt-second balance principle is an important concept in physics, especially in circuit analysis and switching power supply design. It means that in a steady-state inductor, the volt-seconds (voltage multiplied by time) of the switch on time (current rising section) must be numerically equal to the volt-seconds when the switch is off (current falling section). In this embodiment, the volt-second balance principle is applied to the three-level converter SVPWM method based on multi-vector synthesis.

[0075] In this embodiment, according to the volt-second balance principle, the calculation formula for the duty cycle of the large vector and the zero vector in each sector is obtained as follows:

[0076] (2)

[0077] In the formula, V r represents a space vector, T s is the switching cycle, V 21 and V 22 represents two large vectors, V 01 represents the zero vector, d _1 is the large vector V 21 The duty cycle, d _2 is the large vector V 22 The duty cycle, d _0 is the zero vector V 01 The duty cycle, i Represents space vector V r Located in the i-th sector.

[0078] In this embodiment, the above formula (2) is used to calculate the action time or duty cycle of the large vector and the zero vector in the six sectors, as shown in Table 1.

[0079] Table 1 Six sectors large vectors and zero vectors and their duty cycles

[0080]

[0081] In Table 1, the expressions of x, y and z are:

[0082] (3)

[0083] In the formula, vα and vβ Respectively represent the voltage of the two-phase stationary coordinate system (which can be obtained from the three-phase voltage v ao, v bohev co is obtained by Clarke transformation)

[0084] Step S3, controlling the duty cycle of the small vector and the medium vector in each sector to be equal, and obtaining the constraint condition of the duty cycle of the output voltage vector.

[0085] In this embodiment, in order to eliminate the fluctuation of the midpoint voltage, the time or duty cycle of the two small vectors and the midpoint vector selected in each sector is controlled to be equal. Here, the midpoint voltage refers to the midpoint of the upper and lower capacitors on the DC side ( Figure 2 Medium 1 ) voltage at .

[0086] Specifically, the medium vector and the small vector will generate the midpoint current, thus causing the midpoint voltage to fluctuate, as shown in Table 2, while the large vector and the zero vector will not generate the midpoint current and will not affect the midpoint voltage. As shown in Table 2, for vectors ONN, PPO and PON, the generated midpoint current i np is equal to i a, i c, i b. For a three-phase three-wire converter, the sum of the three-phase currents is equal to zero, that is, i a+ i c+ i b=0. If the three vectors act for the same time or have the same duty cycle in one switching cycle, then i np= i a+ i c+ i b=0, the synthesis of these three vectors will not affect the midpoint voltage. In order to eliminate the influence of the midpoint voltage on the midpoint voltage by the midpoint vector and two small vectors in the six sectors, it is necessary to make the action time or duty cycle of the small vector and the midpoint vector in each sector equal.

[0087] Table 2 Small and medium vectors and their corresponding midpoint currents

[0088]

[0089] In this embodiment, by controlling the action time of the small vector and the middle vector in each sector, the average value of the DC side midpoint current of the three-level converter in each switching cycle is made zero, thereby solving the balance problem of the three-level midpoint voltage.

[0090] Step S4, calculating the duty cycle of the output voltage vector in each sector according to the volt-second balance principle and the constraint condition of the duty cycle of the output voltage vector;

[0091] Specifically, the present invention uses multiple output voltage vectors to synthesize the space vector V r According to the volt-second balance principle, we get:

[0092] (4)

[0093] In the formula, d j1 , d j2 , d j3 , d j4 , d j5 , d j6 and d j7 Respectively represent the duty cycle of the corresponding output voltage vector; where, j =1, 2, 3, 4, 5, 6;

[0094] From equation (4), we can see that there are 7 unknowns in this equation. In order to solve the duty cycle of multiple voltage vectors, we need to reduce the number of free variables. Usually, the duty cycle of zero vector NNN and PPP is equal, that is:

[0095] d j1 = d j7 (5)

[0096] Since the duty cycles of the small vector and the medium vector in step S3 are equal, the constraint condition is obtained:

[0097] d j2 = d j4 = d j6 (6)

[0098] It should be noted that before calculating the duty cycle of the output voltage vector in each sector in step S4, it is also necessary to determine the duty cycle of the output voltage vector in each sector. Figure 3 , the relationship between the large vector, the medium vector and the small vector is:

[0099] (7)

[0100] In the formula, V 11 and V 12 represents two small vectors, V 01 and V 02 represents two zero vectors, V 31 represents the mid vector, d i_com(i=1, 2, 3, 4, 5, 6) is an intermediate variable in the six sectors. k i_com is the corresponding proportional adjustment coefficient.

[0101] Then, according to the volt-second balance principle expression, constraint conditions, and the relationship between the large vector, the medium vector, and the small vector, that is, combining formulas (2), (5), (6), and (7), the duty cycle expressions of the output voltage vectors in the six sectors are obtained as follows:

[0102] (8)

[0103] From formula (7) and formula (8), we can see that k i_com It can be used to adjust the duty cycle of the medium and small vectors in the six sectors. k i_com When it is close to zero, the action time of the middle vector and the small vector in the six sectors is almost zero, the modulation of the three-level is similar to that of the two-level, and the output line voltage waveform quality is close to the effect of the two-level. k i_com When it is close to 1, the action time of the zero vector or large vector will be close to zero. Therefore, in this embodiment k i_com The value of 0.8 is more appropriate. Substituting it into equation (8), we can get the duty cycle of the output voltage vector in each sector.

[0104] Step S5, according to the duty cycle of the output voltage vector and the preset arrangement sequence of the output voltage vector, the output state of the three-phase bridge arm voltage in the three-level converter and the driving signal of each phase switch are obtained.

[0105] In this embodiment, after obtaining the duty cycle of the output voltage vector in each sector, combined with the arrangement order of the output voltage vector, the state of the three-phase bridge arm voltage and the driving signal of each phase switch tube can be obtained, such as Figure 5 These drive signals will control the on and off of the switch tube, thereby realizing the SVPWM modulation of the three-level converter.

[0106] The three-level converter SVPWM method provided by the present invention adopts multiple vectors to synthesize space vectors. It only needs to simply divide the space vector diagram into six sectors, and only needs to calculate the time when the synthesized vectors in the six sectors act respectively, which significantly reduces the amount of calculation and has a simple implementation process.

[0107] In a preferred embodiment of the present invention, before step S5, the three-level converter SVPWM method provided by the present invention further includes:

[0108] The arrangement order of the output voltage vectors of each sector is determined; wherein each sector uses a zero vector as a starting vector.

[0109] In each sector, the output voltage vector is arranged in the order of zero vector V 01 , small vector V 11 , Large Vector V 21 , Medium Vector V 31 , Large Vector V 22 , small vector V 12 and zero vector V 02 .

[0110] For example, when the space vector V r Located in sector I, the output voltage vectors NNN, ONN, PNN, PON, PPN, PPO, PPP are selected in sequence to synthesize V r , you can also reverse the order of these output voltage vectors to synthesize V r . This arrangement allows the switching state of each phase to move in the manner of N→O→P or P→O→N, and at the same time only one phase performs switching action each time switching occurs, thereby ensuring a smooth output voltage waveform. When the reference vector is in other sectors, the output voltage vector used to synthesize the reference vector is shown in Table 3, and the order of the output voltage vectors in the table can also be reversed. It can be seen from Table 3 that the starting output voltage vectors between different sectors are all zero vectors (NNN or PPP), so the switching between sectors is smooth, there is no switching action, and the output voltage waveform is not affected.

[0111] Table 3 Corresponding output voltage vectors in six sectors

[0112]

[0113] In a preferred embodiment of the present invention, a simulation model is built by MATLAB and corresponding simulation conditions are set to verify the effectiveness of the three-level converter SVPWM method provided by the present invention.

[0114] In this embodiment, the simulation working condition takes the constant power discharge of the battery as an example, the output voltage of the battery is 750V, power is transmitted to the grid through the converter, and the output current of the three-level converter is 20A (amplitude).

[0115] Figure 6The waveforms of the upper and lower capacitor voltages on the DC side are given, and the simulation results show that the voltage fluctuations of the upper and lower capacitors on the DC side are small, which is an important indicator of the midpoint voltage balance. It can be seen that the SVPWM modulation method provided by the present invention effectively achieves the balance of the midpoint voltage, thereby ensuring the stable operation and high-quality output of the three-level converter.

[0116] Figure 7 (a) shows the three-phase output current waveform of the three-level converter, and Figure 7 (b) shows the three-phase current waveform in the enlarged area of ​​Figure 7 (a). Referring to Figures 7 (a) and 7 (b), the current waveform is very close to the ideal sine waveform. Figure 8 (a) shows the three-level output line voltage (the voltage between the A and B phase bridge arms) V ab Figure 8(b) shows the line voltage waveform in the enlarged area of ​​Figure 8(a). From the simulation results, we can see that V ab It has five levels of ±Ebat, ±Ebat / 2 and 0, thereby ensuring that the three-level converter has a high-quality output voltage waveform. Therefore, the SVPWM modulation method proposed by the present invention can not only ensure the balance of the midpoint voltage, but also make the waveform high in quality.

[0117] In a preferred embodiment of the present invention, the present invention further provides a three-level converter SVPWM system based on multi-vector synthesis, the system comprising:

[0118] A vector diagram partitioning module, for defining an output voltage vector of a three-level converter based on a three-level converter topology, drawing a three-level converter space voltage vector diagram, and dividing the three-level space voltage vector diagram into a plurality of sectors; wherein the output voltage vector includes a large vector, a medium vector, a small vector and a zero vector;

[0119] A first calculation module is used to calculate the duty cycle of the large vector and the zero vector in each sector according to the volt-second balance principle;

[0120] A vector constraint module is used to control the duty ratio of the small vector and the medium vector in each sector to be equal, and obtain the constraint condition of the duty ratio of the output voltage vector;

[0121] The second calculation module is used to calculate the duty cycle of the output voltage vector in each sector according to the volt-second balance principle and the constraint condition of the duty cycle of the output voltage vector;

[0122] The signal output module is used to obtain the output state of the three-phase bridge arm voltage in the three-level converter and the driving signal of each phase switch tube according to the duty cycle of the output voltage vector and the preset output voltage vector arrangement order.

[0123] The three-level converter SVPWM system based on multi-vector synthesis provided by the present invention executes the three-level converter SVPWM method based on multi-vector synthesis provided by the above-mentioned embodiments through the above-mentioned modules. The three-level converter SVPWM method based on multi-vector synthesis has been described in detail in the above-mentioned embodiments, and will not be repeated in this embodiment.

[0124] Fig. 9 The structural block diagram of the electronic device provided by the present invention is as follows: Fig. 9 As shown, the present invention also provides an electronic device, and the electronic device 900 can be a computing device such as a mobile terminal, a desktop computer, a notebook, a palm computer, and a server. The electronic device 900 includes a processor 901 and a memory 902, wherein the memory 902 stores a three-level converter SVPWM program 903 based on multi-vector synthesis.

[0125] In some embodiments, the memory 902 may be an internal storage unit of a computer device, such as a hard disk or memory of the computer device. In other embodiments, the memory 902 may also be an external storage device of the computer device, such as a plug-in hard disk, a smart memory card (Smart Media Card, SMC), a secure digital (SecureDigital, SD) card, a flash card (Flash Card), etc. equipped on the computer device. Furthermore, the memory 902 may also include both an internal storage unit of the computer device and an external storage device. The memory 902 is used to store application software and various types of data installed in the computer device, such as program codes installed in the computer device. The memory 902 can also be used to temporarily store data that has been output or is to be output. In one embodiment, when the three-level converter SVPWM program 903 based on multi-vector synthesis is executed by the processor 901, the following steps are implemented:

[0126] Step S1, based on the three-level converter topology, defining the output voltage vector of the three-level converter, drawing the three-level converter space voltage vector diagram, and dividing the three-level space voltage vector diagram into a plurality of sectors; wherein the output voltage vector includes a large vector, a medium vector, a small vector and a zero vector;

[0127] Step S2, calculating the duty cycle of the large vector and the zero vector in each sector according to the volt-second balance principle;

[0128] Step S3, controlling the duty ratios of the small vector and the medium vector in each sector to be equal, and obtaining the constraint condition of the duty ratio of the output voltage vector;

[0129] Step S4, calculating the duty cycle of the output voltage vector in each sector according to the volt-second balance principle and the constraint condition of the duty cycle of the output voltage vector;

[0130] Step S5, according to the duty cycle of the output voltage vector and the preset arrangement sequence of the output voltage vector, the output state of the three-phase bridge arm voltage in the three-level converter and the driving signal of each phase switch are obtained.

[0131] In some embodiments, the processor 901 may be a central processing unit (CPU), a microprocessor or other data processing chip, used to run program codes or process data stored in the memory 902, such as executing a three-level converter SVPWM program based on multi-vector synthesis.

[0132] This embodiment further provides a computer-readable storage medium, on which a three-level converter SVPWM program based on multi-vector synthesis is stored. When the three-level converter SVPWM program based on multi-vector synthesis is executed by a processor, the following steps are implemented:

[0133] Step S1, based on the three-level converter topology, defining the output voltage vector of the three-level converter, drawing the three-level converter space voltage vector diagram, and dividing the three-level space voltage vector diagram into a plurality of sectors; wherein the output voltage vector includes a large vector, a medium vector, a small vector and a zero vector;

[0134] Step S2, calculating the duty cycle of the large vector and the zero vector in each sector according to the volt-second balance principle;

[0135] Step S3, controlling the duty ratios of the small vector and the medium vector in each sector to be equal, and obtaining the constraint condition of the duty ratio of the output voltage vector;

[0136] Step S4, calculating the duty cycle of the output voltage vector in each sector according to the volt-second balance principle and the constraint condition of the duty cycle of the output voltage vector;

[0137] Step S5, according to the duty cycle of the output voltage vector and the preset arrangement sequence of the output voltage vector, the output state of the three-phase bridge arm voltage in the three-level converter and the driving signal of each phase switch are obtained.

[0138] In summary, the three-level converter SVPWM method and system based on multi-vector synthesis provided by the present invention has the following beneficial effects compared with the prior art:

[0139] 1) The three-level converter SVPWM method provided by the present invention adopts multiple vectors to synthesize the space vector. It only needs to simply divide the space vector diagram into six sectors, and only needs to calculate the time when the synthesized vectors in the six sectors act respectively, which significantly reduces the amount of calculation and is simple to implement.

[0140] 2) Since each sector uses the zero vector as the starting vector, the switching between sectors is guaranteed to be smooth.

[0141] 3) When the modulation is relatively small, the output line voltage of the three-level converter still contains five levels, which can ensure a high-quality output voltage waveform.

[0142] 4) By controlling the action time of the small vector and the middle vector in each sector, the average value of the midpoint current on the DC side of the three-level converter in each switching cycle is made zero, thus solving the balance problem of the three-level midpoint voltage.

[0143] The above-described embodiments only express several implementation methods of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the present invention. It should be pointed out that, for a person of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the attached claims.

[0144] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A three-level converter SVPWM method based on multi-vector synthesis, characterized in that: include: Step S1, based on the three-level converter topology, defining the output voltage vector of the three-level converter, drawing the three-level converter space voltage vector diagram, and dividing the three-level space voltage vector diagram into a plurality of sectors; wherein the output voltage vector includes a large vector, a medium vector, a small vector and a zero vector; Step S2, calculating the duty cycle of the large vector and the zero vector in each sector according to the volt-second balance principle; Step S3, controlling the duty ratios of the small vector and the medium vector in each sector to be equal, and obtaining the constraint condition of the duty ratio of the output voltage vector; Step S4, calculating the duty cycle of the output voltage vector in each sector according to the volt-second balance principle and the constraint condition of the duty cycle of the output voltage vector; Step S5, according to the duty cycle of the output voltage vector and the preset arrangement sequence of the output voltage vector, the output state of the three-phase bridge arm voltage in the three-level converter and the driving signal of each phase switch are obtained.

2. The three-level converter SVPWM method based on multi-vector synthesis according to claim 1, characterized in that: In step S1, based on the three-level converter topology structure, the output voltage vector of the three-level converter is defined, and the spatial voltage vector diagram of the three-level converter is drawn, including: The three-level converter includes an A-phase bridge arm, a B-phase bridge arm and a C-phase bridge arm, and each phase bridge arm includes four switching devices and a pair of clamping diodes; Each phase bridge arm of the three-level converter outputs three different voltage levels, including positive level P, zero level O and negative level N; Based on the three possible output states P, O, and N of each phase bridge arm, 27 output voltage vectors of the three-level converter are defined; and a spatial voltage vector diagram of the three-level converter is drawn according to the output voltage vectors.

3. The three-level converter SVPWM method based on multi-vector synthesis according to claim 2, characterized in that: In step S2, the calculation formula for obtaining the duty cycle of the large vector and the zero vector in each sector according to the volt-second balance principle is: In the formula, V r represents a space vector, T s is the switching cycle, V 21 and V 22 represents two large vectors, V 01 represents the zero vector, d _1 is the large vector V 21 The duty cycle, d _2 is the large vector V 22 The duty cycle, d _0 is the zero vector V 01 The duty cycle, i Represents space vector V r Located in i within a sector.

4. The three-level converter SVPWM method based on multi-vector synthesis according to claim 3 is characterized in that: In step S4, the duty cycle of the output voltage vectors in the six sectors is calculated based on the volt-second balance principle and the constraints of the small vector and the medium vector, including: Using multiple output voltage vectors to synthesize space vector V r According to the volt-second balance principle, we get: In the formula, d j1 , d j2 , d j3 , d j4 , d j5 , d j6 and d j7 Respectively represent the duty cycle of the corresponding output voltage vector; where, j =1, 2, 3, 4, 5, 6; The duty cycles of the small vector and the medium vector are equal, and the constraint condition is obtained: d j2 ＝ d j4 ＝ d j6 According to the volt-second balance, constraints and the relationship between the large vector, the medium vector and the small vector, the expression is obtained: In the formula, V 11 and V 12 represents two small vectors, V 01 and V 02 represents two zero vectors, V 31 represents the vector, d i_com is an intermediate variable within the six sectors, k i_com is the corresponding proportional adjustment coefficient; According to the above expression, the duty cycle of the output voltage vector in the six sectors is obtained as follows: 。 5. The three-level converter SVPWM method based on multi-vector synthesis according to claim 4, characterized in that: Before step S5, the method further includes: Determine the arrangement order of the output voltage vectors of each sector; wherein each sector uses a zero vector as a starting vector; In each sector, the output voltage vector is arranged in the order of zero vector V 01 , small vector V 11 , Large Vector V 21 , Medium Vector V 31 , Large Vector V 22 , small vector V 12 and zero vector V 02 .

6. A three-level converter SVPWM system based on multi-vector synthesis, characterized in that: include: A vector diagram partitioning module, for defining an output voltage vector of a three-level converter based on a three-level converter topology, drawing a three-level converter space voltage vector diagram, and dividing the three-level space voltage vector diagram into a plurality of sectors; wherein the output voltage vector includes a large vector, a medium vector, a small vector and a zero vector; A first calculation module is used to calculate the duty cycle of the large vector and the zero vector in each sector according to the volt-second balance principle; A vector constraint module is used to control the duty ratio of the small vector and the medium vector in each sector to be equal, and obtain the constraint condition of the duty ratio of the output voltage vector; The second calculation module is used to calculate the duty cycle of the output voltage vector in each sector according to the volt-second balance principle and the constraint condition of the duty cycle of the output voltage vector; The signal output module is used to obtain the output state of the three-phase bridge arm voltage in the three-level converter and the driving signal of each phase switch tube according to the duty cycle of the output voltage vector and the preset output voltage vector arrangement order.

7. An electronic device, It is characterized in that comprising a memory and a processor, wherein: The memory is used to store programs; The processor is coupled to the memory and is used to execute the program stored in the memory to implement the steps in the three-level converter SVPWM method based on multi-vector synthesis as described in any one of claims 1 to 5 above.

8. A computer-readable storage medium, characterized in that: Used to store computer-readable programs or instructions, which, when executed by a processor, can implement the steps of the three-level converter SVPWM method based on multi-vector synthesis as described in any one of claims 1 to 5 above.

Images