Polyphase digital predistortion processing method, apparatus, device, medium and program product

Abstract

The application discloses a kind of multi-phase digital pre-distortion processing method, device, equipment, medium and program product, the method includes: according to digital pre-distortion memory polynomial model, setting polynomial calculation module and filter module;According to target processing clock frequency, determine the input road number of the polynomial calculation module;Then the polynomial calculation module is used to carry out polynomial calculation to multiple signal components, and multiple polynomial calculation results are obtained;Wherein, multiple signal components are obtained after the transmission signal to be input to power amplifier is decomposed according to the input road number;The filter module is used to combine the polynomial calculation result, and the transmission signal after pre-distortion processing is obtained, so that the processing clock frequency of digital pre-distortion DPD can be reduced, high-speed pre-distortion processing is completed using lower rate, and the burden of system is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of wireless communication, and in particular to a multi-phase digital pre-distortion processing method, device, equipment, medium and program product. BACKGROUND

[0002] A power amplifier (PA) is a key element in a radio frequency transceiver chip. When the PA works in a saturation condition, due to inherent problems such as changes in input impedance of a transistor inside the PA and electro-thermal coupling, in-band signal distortion is caused.

[0003] Digital pre-distortion (DPD) is a commonly used method for processing PA distortion. However, the DPD technology generally requires five times the signal bandwidth for pre-calibration. For example, a 100M signal requires a 500M bandwidth and a corresponding clock frequency for DPD processing. In the current communication with a large bandwidth, the requirement for the clock frequency is high, which often brings a great burden to the system. SUMMARY

[0004] To solve the problems in the prior art, the embodiments of the present application provide a multi-phase digital pre-distortion processing method, device, equipment, medium and program product, which can reduce the requirement for the system clock frequency, realize the completion of high-speed pre-distortion processing at a lower rate, and effectively reduce the burden of the system.

[0005] In a first aspect, the embodiments of the present application provide a multi-phase digital pre-distortion processing method, comprising:

[0006] According to a digital pre-distortion memory polynomial model, a polynomial calculation module and a filter module are set;

[0007] According to a target processing clock frequency, the input path number of the polynomial calculation module is determined;

[0008] The polynomial calculation module is used to perform polynomial calculation on a plurality of signal components to obtain a plurality of polynomial calculation results; wherein the plurality of signal components are obtained by decomposing a transmission signal to be input to a power amplifier according to the input path number;

[0009] The filter module is used to combine the polynomial calculation results to obtain a pre-distortion processed transmission signal.

[0010] As an improvement of the above-mentioned scheme, the method further comprises:

[0011] When the polynomial memory depth of the polynomial calculation module is greater than the input path number, a memory module is set;

[0012] The memory module delays the multiple signal components to generate new signal components, and inputs the new signal components into the polynomial calculation module for polynomial calculation.

[0013] As an improvement of the above scheme, the memory depth of the memory module is calculated according to the input channel number and the polynomial memory depth.

[0014] As an improvement of the above scheme, the polynomial calculation on the multiple signal components by the polynomial calculation module includes:

[0015] In the polynomial calculation module, the polynomial calculation on each of the signal components is performed according to the preset polynomial memory depth, the preset polynomial order, and the input channel number, to obtain multiple polynomials.

[0016] The multiple polynomials corresponding to each of the signal components are combined to obtain the polynomial calculation result of each channel.

[0017] As an improvement of the above scheme, the filter module includes at least one filter, and the input of each filter includes the polynomial calculation result of at least one channel of the polynomial calculation module.

[0018] As an improvement of the above scheme, the combination of the polynomial calculation results by the filter module to obtain the pre-distortion processed transmission signal includes:

[0019] The filter module determines the polynomial complex coefficients of the polynomial calculation results of each channel according to the polynomial memory depth and the polynomial order of the polynomial calculation module.

[0020] The polynomial calculation results of each channel are weighted and summed according to the polynomial complex coefficients to obtain the filter results of each channel.

[0021] The filter results of each channel are combined to obtain the pre-distortion processed transmission signal.

[0022] As an improvement of the above scheme, when the filter module includes one filter, the combination of the filter results of each channel to obtain the pre-distortion processed transmission signal includes:

[0023] The filter results of each channel are summed by the filter to obtain the pre-distortion processed transmission signal.

[0024] As an improvement of the above scheme, when the filter module includes multiple filters, the combination of the polynomial calculation results by the filter module to obtain the pre-distortion processed transmission signal includes:

[0025] The multiple polynomial calculation results are combined and multiplexed to obtain final polynomial calculation results of each channel;

[0026] According to the polynomial memory depth and the polynomial order of the polynomial calculation module, polynomial complex coefficients of the polynomial calculation results of each channel are determined;

[0027] According to the polynomial complex coefficients of the polynomial calculation results of each channel, the corresponding polynomial calculation results are weighted and summed to obtain the pre-distortion processed transmission signals of each channel.

[0028] As an improvement of the above scheme, the combination of the polynomial calculation results by the filtering module to obtain the pre-distortion processed transmission signals comprises:

[0029] According to the target output clock frequency, the number of output channels of the filtering module is determined, and a corresponding number of filters is set according to the number of output channels;

[0030] The multiple polynomial calculation results are combined and multiplexed to obtain final polynomial calculation results of each channel;

[0031] According to the polynomial memory depth and the polynomial order of the polynomial calculation module, polynomial complex coefficients of the polynomial calculation results of each channel are determined;

[0032] According to the polynomial complex coefficients of the polynomial calculation results of each channel, the corresponding polynomial calculation results are weighted and summed to obtain the pre-distortion processed transmission signals of each channel.

[0033] As an improvement of the above scheme, the memory depth of the memory module is calculated according to the input channel number, the polynomial memory depth and the output channel number.

[0034] In a second aspect, an embodiment of the present application provides a multi-phase digital pre-distortion processing device, comprising a polynomial calculation module and a filtering module; wherein the polynomial calculation module and the filtering module are set according to a digital pre-distortion model;

[0035] The polynomial calculation module is configured to perform polynomial calculation on multiple signal components to obtain multiple polynomial calculation results; wherein the multiple signal components are obtained by decomposing a transmission signal to be input to a power amplifier according to an input channel number of the polynomial calculation module; and the input channel number is determined according to a target processing clock frequency.

[0036] The filtering module is configured to combine the polynomial calculation results to obtain pre-distortion processed transmission signals.

[0037] As an improvement of the above scheme, the device further comprises:

[0038] a memory module configured to delay the plurality of signal components, generate new signal components, and input the new signal components to the polynomial calculation module for polynomial calculation, wherein the memory module is configured when the polynomial memory depth of the polynomial calculation module is greater than the number of input channels.

[0039] As an improvement of the above-mentioned scheme, the filter module comprises at least one filter, and the input of each filter comprises the polynomial calculation result of at least one channel of the polynomial calculation module.

[0040] In a third aspect, an embodiment of the present application provides a multi-phase digital pre-distortion processing device, comprising a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, and the processor implements the multi-phase digital pre-distortion processing method according to any one of the first aspect when executing the computer program.

[0041] In a fourth aspect, an embodiment of the present application provides a computer readable storage medium, which stores a computer program, wherein the computer readable storage medium controls a device where the computer readable storage medium is located to execute the multi-phase digital pre-distortion processing method according to any one of the first aspect when the computer program runs.

[0042] In a fifth aspect, an embodiment of the present application provides a computer program product, comprising computer programs / instructions, which implement the multi-phase digital pre-distortion processing method according to any one of the first aspect when executed by a processor.

[0043] Compared with the prior art, the multi-phase digital pre-distortion processing method, device, equipment, medium and program product of the embodiment of the present application set a polynomial calculation module and a filter module according to a digital pre-distortion memory polynomial model, determine the number of input channels of the polynomial calculation module according to a target processing clock frequency, then perform polynomial calculation on a plurality of signal components through the polynomial calculation module to obtain a plurality of polynomial calculation results, wherein the plurality of signal components are obtained by decomposing a transmission signal to be input to a power amplifier according to the number of input channels, and combine the polynomial calculation results through the filter module to obtain a pre-distortion processed transmission signal, thereby reducing the processing clock frequency of the digital pre-distortion DPD, realizing the pre-distortion processing at a high rate by using a lower rate, and reducing the burden of the system. BRIEF DESCRIPTION OF DRAWINGS

[0044] In order to more clearly illustrate the technical solutions of the present application, the drawings used in the embodiments will be briefly introduced as follows. Obviously, the drawings described in the following embodiments are only some of the embodiments of the present application, and all other drawings obtained by those of ordinary skill in the art without creative effort based on these drawings also belong to the protection scope of the present application.

[0045] Figure 1 is a schematic diagram of the pre-distortion basic structure and principle provided by the embodiment of the present application;

[0046] Figure 2 is a flow chart of a polyphase digital pre-distortion processing method provided by the embodiment of the present application;

[0047] Figure 3 is a structural block diagram of a polyphase digital pre-distortion device with polyphase input provided by the embodiment of the present application;

[0048] Figure 4 is a schematic diagram of a polyphase digital pre-distortion device with 4-way input provided by the embodiment of the present application;

[0049] Figure 5 is a structural block diagram of a polyphase digital pre-distortion device with setting memory module provided by the embodiment of the present application;

[0050] Figure 6 is a structural block diagram of a polyphase digital pre-distortion device with polyphase input and polyphase output provided by the embodiment of the present application;

[0051] Figure 7 is a structural block diagram of a polyphase digital pre-distortion device with setting two filters provided by the embodiment of the present application;

[0052] Figure 8 is a structural block diagram of a polyphase digital pre-distortion processing device provided by the embodiment of the present application;

[0053] Figure 9 is a structural block diagram of a polyphase digital pre-distortion processing device provided by the embodiment of the present application. DETAILED DESCRIPTION

[0054] The technical solutions in the embodiments of the present application will be described clearly and completely with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, and not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort also belong to the protection scope of the present application.

[0055] It should be noted that the relational terms herein such as first and second and the like are used solely to distinguish one from another entity or action, without necessarily requiring or implying any actual relationship or order between such entities or actions. The terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. The terms "plurality" or "a plurality" refer to two or more, and "plurality" or "a plurality" of items refers to two or more of such items. The term "and / or" describes associating objects and refers to three relationships: both, either, and neither. The character " / " generally represents an "or" relationship between the associated objects.

[0056] Some terms and related technologies involved in the embodiments of the present application are explained below.

[0057] The DPD technology is to input the nonlinear characteristics opposite to the power amplifier in the digital domain through a predistorter, and then cascade to the power amplifier to couple out the linearized signal, as shown in Figure 1 .

[0058] The formula of the commonly used memory polynomial (MP) model in DPD is as follows:

[0059]

[0060] Wherein, K represents the polynomial order, Q represents the polynomial memory depth, a kq represents the polynomial complex coefficient, x(n), y(n) is the value obtained by discretely sampling the power amplifier input x(t) and output y(t) at t time using the Nyquist sampling theorem, n∈N, N represents the sampling number, |x(n-q)| represents the modulus of the input signal x(n-q).

[0061] Please refer to Figure 2 , Figure 2 is a flowchart of a polyphase digital predistortion processing method provided by the embodiments of the present application. The polyphase digital predistortion processing method specifically comprises:

[0062] S11: According to the digital predistortion memory polynomial model, set the polynomial calculation module and the filter module;

[0063] S12: determining the input channel number of the polynomial calculation module according to the target processing clock frequency;

[0064] S13: performing polynomial calculation on the multi-channel signal components by the polynomial calculation module to obtain multi-channel polynomial calculation results; wherein the multi-channel signal components are obtained by decomposing the transmission signal to be input to the power amplifier;

[0065] S14: combining the polynomial calculation results by the filtering module to obtain the pre-distortion processed transmission signal.

[0066] It should be noted that the multi-phase digital pre-distortion processing method described in the embodiments of the present application can be executed by a multi-phase digital pre-distortion device. For the transmission signal output by the baseband circuit and to be processed by the power amplifier, the pre-distortion processing needs to be performed by the multi-phase digital pre-distortion device to reduce the distortion of the transmission signal caused by the gain nonlinearity of the power amplifier, the input impedance variation of the transistor therein, the electro-thermal coupling and other problems.

[0067] In the embodiments of the present application, the digital pre-distortion memory polynomial model is first decomposed into a polynomial part and a coefficient part, for example, the digital pre-distortion memory polynomial model represented by the above formula (1) can be disassembled into the combination of the polynomial part x(n-q)|x(n-q) k-1 and the coefficient part a kq . Then, the polynomial calculation module with multi-phase input is set based on the polynomial part x(n-q)|x(n-q) k-1 , the filtering module is set based on the coefficient part a kq , the input channel number of the polynomial calculation module is determined according to the target processing clock frequency and the original processing clock frequency of the multi-phase digital pre-distortion device, and the transmission signal is decomposed based on the input channel number to obtain a corresponding number of signal components. Then, each channel of the signal components is input into the polynomial calculation module for polynomial calculation, and the obtained polynomial calculation results are output to the filtering module; the filtering module combines the polynomial calculation results to obtain the pre-distortion processed transmission signal. The input channel number of the polynomial calculation module is equal to the quotient of the original processing clock frequency and the target processing clock frequency, for example, Figure 3As shown in the figure, the input number D of the polynomial calculation module is the original processing clock rate CLK1 / target processing clock frequency CLK2, and the original processing clock rate of the transmission signal in the polynomial calculation module and the filtering module is reduced to 1 / D of the original processing clock rate. As can be seen, by decomposing the digital pre-distortion memory polynomial model into the polynomial calculation module and the filtering module, and setting the polyphase input of the polynomial calculation module, the processing clock frequency of the digital pre-distortion DPD can be effectively reduced, the high-speed pre-distortion processing can be completed at a lower rate, and the burden of the system is reduced.

[0068] Specifically, the polynomial calculation on the multiple signal components by the polynomial calculation module includes:

[0069] In the polynomial calculation module, according to the preset polynomial memory depth, the preset polynomial order and the input number, the polynomial calculation is performed on each of the signal components to obtain a plurality of polynomials.

[0070] The plurality of polynomials corresponding to each of the signal components are combined to obtain the polynomial calculation result of each of the signal components.

[0071] Exemplarily, assuming that the input number of the polynomial calculation module is D, for a digital pre-distortion memory polynomial model with a polynomial memory depth not more than the input number, i.e., the polynomial memory depth Q≤D, the memory depth of the split polynomial calculation module can be reset according to the input number. At this time, after polyphase decomposition of the value obtained by Nyquist sampling theorem discrete sampling on the transmission signal, the D-channel signal components can be transformed into x(Dn-d), d∈D. It should be understood that, considering that the even-order terms of the nonlinear order have less influence on the pre-distortion processing, only the odd-order terms of the nonlinear order are considered in the embodiment of the present application, and the polynomial calculation result of each of the signal components can be obtained, for example, the polynomial calculation result X(Dn-d) of the dth signal component is 2 |, x(Dn-d)| 4 ,..., x(Dn-d)| k-1}; wherein k∈K, K represents the nonlinear order of the memory polynomial, and k takes an odd number.

[0072] Assuming that the nonlinear order K=5 and the original processing clock rate is reduced by 4 times, at this time D=4, the polyphase digital pre-distortion structure is as shown in the figure Figure 4 The 4-channel signal components are x(4n-1), x(4n-2), x(4n-3) and x(4n-4) respectively, and the 4-channel polynomial calculation results output after the 4-channel signal components are processed by the polynomial calculation module are as follows:

[0073] X(4n-1) = {x(4n-1), x(4n-1) | x(4n-1) 2 , x(4n-1) | x(4n-1) 4} ;

[0074] X(4n-2) = {x(4n-2), x(4n-2) | x(4n-2) 2 , x(4n-2) | x(4n-2) 4} ;

[0075] X(4n-3) = {x(4n-3), x(4n-3) | x(4n-3) 2 , x(4n-3) | x(4n-3) 4} ;

[0076] X(4n-4) = {x(4n-4), x(4n-4) | x(4n-4) 2 , x(4n-4) | x(4n-4) 4}.

[0077] Specifically, the filter module combines the polynomial calculation results to obtain a pre-distortion processed transmission signal.

[0078] The filter module determines polynomial complex coefficients of the polynomial calculation results of each channel according to a polynomial memory depth and a polynomial order of the polynomial calculation module.

[0079] The filter module weights and sums the polynomial calculation results of each channel according to the polynomial complex coefficients to obtain filter results of each channel.

[0080] The filter module combines the filter results of each channel to obtain a pre-distortion processed transmission signal.

[0081] For example, the filter module has a total of [(K+1)(D+1)] / 2 polynomial complex coefficients. For a signal component x(Dn-d), a polynomial complex coefficient corresponding to the filter module of the polynomial calculation result of the signal component x(Dn-d) is a k(d-1) .

[0082] Specifically, the filter module includes at least one filter, and an input of each filter includes a polynomial calculation result of at least one channel of the polynomial calculation module.

[0083] In the embodiment of the present application, the filter module can include one filter, two filters, or the same number of filters as the input channels of the polynomial calculation module, which is not specifically limited in the embodiment of the present application. For example, for the case of including only one filter, the multiple polynomial calculation results can be weighted and summed according to the corresponding polynomial complex coefficients to obtain the filtering result; for the case of including at least two filters, the multiple polynomial calculation results can be multiplexed and then weighted and summed according to the corresponding polynomial complex coefficients to obtain the filtering result.

[0084] When the filter module includes one filter, the filtering results of the channels are combined to obtain the pre-distortion processed transmission signal, including:

[0085] The filtering results of the channels are summed by the filter to obtain the pre-distortion processed transmission signal.

[0086] For example, for the case of the filter module including only one filter, taking the above 4-channel polynomial results as an example, the first-channel polynomial calculation result X(4n-1)={x(4n-1), x(4n-1)|x(4n-1) 2 , x(4n-1)|x(4n-1) 4}, the corresponding polynomial complex coefficients are {a 10 , a 30 , a 50}; the filtering result after the filter module is:

[0087] y(4n-1)=a 10 x(4n-1)+a 30 x(4n-1)|x(4n-1) 2 +a 50 x(4n-1)|x(4n-1) 4 .

[0088] The second-channel polynomial calculation result X(4n-2)={x(4n-2), x(4n-2)|x(4n-2) 2 , x(4n-2)|x(4n-2) 4}, the corresponding polynomial complex coefficients are {a 11 , a 31 , a 51}; the filtering result after the filter module is:

[0089] y(4n-2)=a 11 x(4n-1)+a 31 x(4n-2)|x(4n-2) 2 +a 51x(4n-2) | x(4n-2) 4 .

[0090] By analogy, the required polynomial complex coefficients of the remaining two-way polynomial calculation results are not described again.

[0091] After the filtering module, the 4-way filtering results are all added to obtain the pre-distortion processed transmission signal y(n), completing the digital pre-distortion DPD operation, and realizing 4 times reduction of the processing clock rate.

[0092] Further, the method further comprises:

[0093] When the polynomial memory depth of the polynomial calculation module is greater than the input number of ways, a memory module is set;

[0094] The memory module is used to delay process the multiple-way signal components to generate new signal components, and the newly generated signal components are input to the polynomial calculation module for polynomial calculation.

[0095] The memory depth of the memory module is calculated according to the input number of ways and the polynomial memory depth.

[0096] For example, for a digital pre-distortion memory polynomial model with a polynomial memory depth greater than an input number of ways, that is, Q>D, a memory module needs to be added, as shown in Figure 5 To meet the deeper memory depth, the memory depth M of the memory module to be prepared is M=Q+1-D according to the polynomial memory depth Q and the input number of ways D.

[0097] The memory module records the value of x(Dn-m), and m∈M. The result input to the polynomial calculation module is x(Dn-(m+D)). When m>D, only the corresponding value needs to be delayed for one original processing time frequency CLK1 in the memory module.

[0098] Specifically, when the filtering module comprises a plurality of filters, the polynomial calculation results are combined by the filtering module to obtain the pre-distortion processed transmission signal, comprising:

[0099] The multiple-way polynomial calculation results are merged and multiplexed to obtain the final polynomial calculation results of each way;

[0100] According to the polynomial memory depth and the polynomial order of the polynomial calculation module, the polynomial complex coefficients of the polynomial calculation results of each way are determined;

[0101] According to the polynomial complex coefficients of the polynomial calculation results of each path, the corresponding polynomial calculation results are weighted and summed to obtain each path of the pre-distortion processed transmission signal.

[0102] For example, for the case where the filtering module includes multiple filters, since each input signal component will become a combination of multiple polynomials after passing through the polynomial calculation module, for example, X(Dn-d) = {x(Dn-d), x(Dn-d) | x(Dn-d) 2 , x(Dn-d) | x(Dn-d) 4 ,..., x(Dn-d) | x(Dn-d) k-1}. The digital pre-distortion memory polynomial model in the above formula (1) can actually be regarded as a combination of polynomials and filters, where the polynomials of each path have partial overlaps. Without considering the filters, the calculation of the polynomials can be separated out to find that the polynomials required for each output y(Dn-d), 0 < d <= D are as follows:

[0103] y(Dn-1) = X(Dn-1) + X(Dn-2) +... + X(Dn-(Q+1));

[0104] y(Dn-2) = X(Dn-2) + X(Dn-3) +... + X(Dn-(Q+2));

[0105] y(Dn-3) = X(Dn-3) + X(Dn-4) +... + X(Dn-(Q+3));

[0106]

[0107] y(Dn-D) = X(Dn-D) + X(Dn-D-1) +... + X(Dn-(Q+D));

[0108] Taking y(Dn-1) as an example, from X(Dn-2) to X(Dn-(Q+1)) can reuse the polynomials behind, which saves the polynomial calculation resources compared to simple polynomial operations. The digital pre-distortion memory polynomial model can be changed to the structure shown in the following formula (2). Figure 6

[0109] ​In the embodiment of the present application, a multi-phase digital pre-distortion device structure of a multi-input multi-output architecture is designed, and a digital pre-distortion memory polynomial model is calculated by splitting into a polynomial calculation module, a filtering module and a memory module. The output result of the polynomial calculation module is multiplexed, thereby reducing the calculation cost and the polynomial calculation unit. The memory depth required by the memory module is Q, the target processing clock frequency of the DPD operation is the original processing clock frequency CLK1 / input number D, thereby ensuring that the clock frequency of the input and output terminals remains unchanged, meeting the scene with high-rate channel requirements, and ensuring that there is still a high clock frequency at the output port to reduce the DPD bandwidth without aliasing of the band-limited filter.

[0110] Specifically, the polynomial calculation result is combined by the filtering module to obtain a pre-distortion processed transmission signal.

[0111] According to the target output clock frequency, the output number of the filtering module is determined, and a corresponding number of filters is set according to the output number;

[0112] The multiple polynomial calculation results are multiplexed to obtain the final polynomial calculation result input to each of the currently set filters;

[0113] According to the polynomial memory depth and the polynomial order of the polynomial calculation module, the polynomial complex coefficients of each polynomial calculation result are determined;

[0114] According to the polynomial complex coefficients of each polynomial calculation result, the corresponding polynomial calculation results are weighted and summed to obtain each pre-distortion processed transmission signal.

[0115] For example, for the case where the filtering module includes multiple filters, for example Figure 7 The digital pre-distortion device structure shown in the figure can further control the output clock frequency by the combination of the filters, thereby realizing a digital pre-distortion device with a configurable input and output clock frequency. For example, the output number of the filtering module can be determined by a preset target output clock frequency, thereby further setting a corresponding number of filters; wherein the number of filters=output number B=target output clock frequency CLK3 / target processing clock frequency CLK2, at this time the target output clock frequency is B times of the target processing clock frequency, that is, the target processing clock frequency in the DPD operation process is CLK1 / D, and the target output clock frequency after the DPD operation is CLK×N / D.

[0116] Wherein the memory depth M of the memory module is updated as M=Q+B-D.

[0117] For example, the filtering module in Figure 7 sets two filters, and the output results of the two filters are respectively

[0118] y(2n-1) = X(2n-1) + X(2n-2) +... + X(2n-(Q+1));

[0119] y(2n-2) = X(2n-2) + X(2n-3) +... + X(2n-(Q+1))

[0120] + X(2n-(Q+2));

[0121] Wherein, the input two filter polynomials merge multiplexing principle is same as above, here no longer repeat.

[0122] In the embodiment of the application, the filter resources can be saved according to the needs, the consumption of the circuit is reduced, the processing clock frequency and the output clock frequency of the DPD operation are freely selected, the adjustable scheme of the processing clock frequency and the output clock frequency is realized, the configuration flexibility of the clock frequency of the digital pre-distortion device is improved, and different system clock frequency requirements can be met.

[0123] Compared with the prior art, the embodiment of the application can effectively reduce the processing clock frequency of the digital pre-distortion DPD by decomposing the digital pre-distortion memory polynomial model into a polynomial calculation module and a filter module and setting a multi-phase input, realize the pre-distortion processing at a high speed by using a lower speed, and reduce the burden of the system. Secondly, a plurality of filters can be set to realize multi-phase output, maintain the clock frequency of the input and output end unchanged, and meet the scene with high-speed channel requirements. In addition, the output clock frequency can be controlled by the combination of the filters, and the filter resources are saved.

[0124] The embodiment of the application can freely select the processing clock frequency and the output clock frequency of the DPD operation, realize the adjustable scheme of the processing clock frequency and the output clock frequency, improve the configuration flexibility of the clock frequency of the digital pre-distortion device, and meet different system clock frequency requirements.

[0125] Referring to Figure 8 , Figure 8 The embodiment of the application provides a structure block diagram of a multi-phase digital pre-distortion processing device, the multi-phase digital pre-distortion processing device comprises a polynomial calculation module 11 and a filter module 12; wherein the polynomial calculation module 11 and the filter module 12 are set according to a digital pre-distortion model;

[0126] The polynomial calculation module 11 is used for performing polynomial calculation on a plurality of signal components to obtain a plurality of polynomial calculation results; wherein the plurality of signal components are obtained by decomposing a transmission signal to be input to a power amplifier according to the input channel number of the polynomial calculation module; the input channel number is determined according to a target processing clock frequency.

[0127] The filter module 12 is configured to combine the polynomial calculation results to obtain a pre-distortion processed transmission signal.

[0128] In an alternative embodiment, the device further comprises:

[0129] A memory module is configured to perform delay processing on the multiple signal components to generate new signal components, and input the newly generated signal components to the polynomial calculation module for polynomial calculation; wherein the memory module is set when the polynomial memory depth of the polynomial calculation module is greater than the input channel number.

[0130] In an alternative embodiment, the memory depth of the memory module is calculated according to the input channel number and the polynomial memory depth.

[0131] In an alternative embodiment, the polynomial calculation module 11 comprises:

[0132] A polynomial calculation unit is configured to perform polynomial calculation on each of the signal components according to the preset polynomial memory depth, the preset polynomial order and the input channel number, to obtain a plurality of polynomials.

[0133] A polynomial combination unit is configured to combine the plurality of polynomials corresponding to each of the signal components to obtain a polynomial calculation result of each channel.

[0134] In an alternative embodiment, the filter module 12 comprises at least one filter, and the input of each filter comprises the polynomial calculation result of at least one channel of the polynomial calculation module.

[0135] In an alternative embodiment, the filter module 12 comprises:

[0136] A first coefficient determination unit is configured to determine the polynomial complex coefficient of each of the polynomial calculation results according to the polynomial memory depth and the polynomial order of the polynomial calculation module.

[0137] A first weighted summation unit is configured to perform weighted summation on each of the polynomial calculation results according to the polynomial complex coefficient to obtain a filter result of each channel.

[0138] A filter result combination unit is configured to combine the filter results of each channel to obtain a pre-distortion processed transmission signal.

[0139] In an alternative embodiment, when the filter module 12 comprises one filter, the filter comprises the above-mentioned first coefficient determination unit, the first weighted summation unit and the filter result combination unit.

[0140] The filter result combination unit is configured to add the filter results of each channel to obtain the pre-distortion processed transmission signal.

[0141] In an alternative embodiment, when the filter module 12 includes a plurality of filters, each filter includes a first multiplexing unit, a second coefficient determination unit, and a second weighted sum unit.

[0142] The first multiplexing unit is configured to multiplex the polynomial calculation results of multiple channels to obtain the final polynomial calculation results of each channel.

[0143] The second coefficient determination unit is configured to determine the polynomial complex coefficients of the polynomial calculation results of each channel according to the polynomial memory depth and the polynomial order of the polynomial calculation module.

[0144] The second weighted sum unit is configured to perform weighted sum on the corresponding polynomial calculation results according to the polynomial complex coefficients of the polynomial calculation results of each channel to obtain the pre-distortion processed transmission signal of each channel.

[0145] In an alternative embodiment, when the filter module 12 includes at least two filters, the device further includes a filter setting module, each filter includes a second multiplexing unit, a third coefficient determination unit, and a third weighted sum unit.

[0146] The filter setting module is configured to determine the number of output channels of the filter module according to the target output clock frequency, and set a corresponding number of filters according to the number of output channels.

[0147] The second multiplexing unit is configured to multiplex the polynomial calculation results of multiple channels to obtain the final polynomial calculation results input to each filter currently set.

[0148] The second coefficient determination unit is configured to determine the polynomial complex coefficients of the polynomial calculation results of each channel according to the polynomial memory depth and the polynomial order of the polynomial calculation module.

[0149] The third weighted sum unit is configured to perform weighted sum on the corresponding polynomial calculation results according to the polynomial complex coefficients of the polynomial calculation results of each channel to obtain the pre-distortion processed transmission signal of each channel.

[0150] In an alternative embodiment, the memory depth of the memory module is calculated according to the number of input channels, the polynomial memory depth, and the number of output channels.

[0151] It should be noted that the working processes of the various modules in the polyphase digital pre-distortion processing apparatus according to the embodiments of the present application can refer to the working processes of the polyphase digital pre-distortion processing methods according to the embodiments of the present application, and the technical effects achieved are the same as those of the polyphase digital pre-distortion processing methods according to the embodiments of the present application, which will not be described herein again.

[0152] Referring to Figure 9 , Figure 9 is a structural block diagram of the polyphase digital pre-distortion processing apparatus according to the embodiments of the present application. The polyphase digital pre-distortion processing apparatus includes a processor 21, a memory 22, and a computer program stored in the memory 22 and executable on the processor 21. The processor 21 implements the steps in the various polyphase digital pre-distortion processing method embodiments described above when executing the computer program, such as steps S11-S14.

[0153] For example, the computer program can be divided into one or more modules / units, which are stored in the memory 22 and executed by the processor 21 to complete the present application. The one or more modules / units can be a series of computer program instruction segments capable of completing a specific function, which are used to describe the execution process of the computer program in the polyphase digital pre-distortion processing apparatus.

[0154] The polyphase digital pre-distortion processing apparatus can include, but is not limited to, the processor 21 and the memory 22. Those skilled in the art can understand that the schematic diagram is only an example of the polyphase digital pre-distortion processing apparatus and does not limit the polyphase digital pre-distortion processing apparatus, which can include more or fewer components than the diagram, or combine certain components, or different components, for example, the polyphase digital pre-distortion processing apparatus can also include an input / output device, a network access device, a bus, etc.

[0155] The processor 21 can be a central processing unit (CPU), and can also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gates or transistor logic components, discrete hardware components, etc. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor. The processor 21 is a control center of the multi-phase digital predistortion processing device, and connects various parts of the multi-phase digital predistortion processing device through various interfaces and lines.

[0156] The memory 22 can be used to store computer programs and / or modules. The processor 21 realizes various functions of the multi-phase digital predistortion processing device by running or executing computer programs and / or modules stored in the memory 22, and calling data stored in the memory 22. The memory 22 can mainly include a program storage area and a data storage area. The program storage area can store an operating system, at least one application program required for a function (such as a sound playing function, an image playing function, etc.), etc. The data storage area can store data created according to use of the mobile phone (such as audio data, a phone book, etc.), etc. In addition, the memory 22 can include a high-speed random access memory, and can also include a non-volatile memory, such as a hard disk, a memory, a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, at least one disk storage device, a flash memory device, or other volatile solid-state memory device.

[0157] The modules / units integrated in the multi-phase digital pre-distortion processing device can be stored in a computer readable storage medium if they are realized in the form of software function units and sold or used as independent products. Based on this understanding, all or part of the processes in the above-mentioned embodiment methods can also be completed by a computer program instructing related hardware. The computer program can be stored in a computer readable storage medium. When the computer program is executed by the processor 21, the steps of the above-mentioned various method embodiments can be realized. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or some intermediate forms, etc. The computer readable medium can include any entity or device capable of carrying the computer program code, recording medium, U disk, mobile hard disk, magnetic disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signal, telecommunication signal, and software distribution medium, etc.

[0158] It should be noted that the above-described device embodiments are only schematic, and the units described as separate components can or can not be physically separated, and the components shown as units can or can not be physical units, i.e. they can be located in one place or distributed on multiple network units. Part or all of the modules can be selected to achieve the purpose of the embodiment scheme according to actual needs. In addition, the connection relationship between the modules in the device embodiment figures of the present application indicates that there is a communication connection between them, which can be realized as one or more communication buses or signal lines. Those skilled in the art can understand and implement it without creative labor.

[0159] The above is the preferred embodiment of the present application. It should be noted that those skilled in the art can make many improvements and refinements without departing from the principles of the present application, and these improvements and refinements are also considered within the protection scope of the present application.

Claims

1. A polyphase digital predistortion processing method, characterized by, The application relates to a digital pre-distortion memory polynomial model. The digital pre-distortion memory polynomial model is divided into a polynomial part and a coefficient part, and a polynomial calculation module and a filter module are respectively arranged; According to the original processing clock frequency and the target processing clock frequency, the input channel number of the polynomial calculation module is determined; The polynomial calculation module is used for performing polynomial calculation on the multiple signal components to obtain multiple polynomial calculation results, wherein the multiple signal components are obtained by decomposing a transmission signal to be input to a power amplifier according to the input channel number; When the polynomial memory depth of the polynomial calculation module is greater than the input channel number, a memory module is arranged; The memory module is used for performing delay processing on the multiple signal components to generate new signal components, and the new signal components are input to the polynomial calculation module for polynomial calculation; The filter module is used for combining the polynomial calculation results to obtain a pre-distortion processed transmission signal.

2. The polyphase digital predistortion processing method of claim 1, wherein, The memory depth of the memory module is calculated according to the input channel number and the polynomial memory depth.

3. The polyphase digital predistortion processing method of claim 1, wherein, The polynomial calculation module is used for performing polynomial calculation on the multiple signal components to obtain multiple polynomial calculation results, wherein the multiple signal components are obtained by decomposing a transmission signal to be input to a power amplifier according to the input channel number; In the polynomial calculation module, polynomial calculation is performed on each of the signal components according to a preset polynomial memory depth, a preset polynomial order and the input channel number to obtain multiple polynomials; The multiple polynomials corresponding to the signal components are combined to obtain the polynomial calculation results of the signal components.

4. The polyphase digital predistortion processing method of claim 1, wherein, The filter module includes at least one filter, and the input of each filter includes the polynomial calculation results of at least one channel of the polynomial calculation module.

5. The polyphase digital predistortion processing method of claim 1, wherein, The filter module is used for combining the polynomial calculation results to obtain a pre-distortion processed transmission signal. The filter module determines the polynomial complex coefficients of the polynomial calculation results of the channels according to the polynomial memory depth and the polynomial order of the polynomial calculation module; The filter module is used for combining the polynomial calculation results to obtain a pre-distortion processed transmission signal. When the filter module includes one filter, the filter module is used for combining the filter results of the channels to obtain a pre-distortion processed transmission signal.

6. The polyphase digital predistortion processing method of claim 5, wherein, When the filter module includes multiple filters, the filter module is used for combining the polynomial calculation results to obtain a pre-distortion processed transmission signal. The multiple polynomial calculation results are multiplexed to obtain the final polynomial calculation results of the channels; 7. The polyphase digital predistortion processing method of claim 1, wherein, The filter module determines the polynomial complex coefficients of the polynomial calculation results of the channels according to the polynomial memory depth and the polynomial order of the polynomial calculation module; The filter module is used for combining the polynomial calculation results to obtain a pre-distortion processed transmission signal. ​ ​ 8. The polyphase digital predistortion processing method of claim 1, wherein, The polynomial calculation results are combined by the filter module to obtain a pre-distortion processed transmission signal. According to a target output clock frequency, the number of output paths of the filter module is determined, and a corresponding number of filters is set according to the number of output paths. The multiple polynomial calculation results are merged and multiplexed to obtain polynomial calculation results finally input to each filter currently set. According to the polynomial memory depth and polynomial order of the polynomial calculation module, polynomial complex coefficients of each polynomial calculation result are determined. According to the polynomial complex coefficients of each polynomial calculation result, corresponding polynomial calculation results are weighted and summed to obtain each pre-distortion processed transmission signal.

9. The polyphase digital predistortion processing method of claim 1, wherein, The memory depth of the memory module is calculated according to the number of input paths, the polynomial memory depth and the number of output paths of the filter module.

10. A polyphase digital predistortion processing apparatus, characterized by It comprises: a polynomial calculation module, a filter module and a memory module; wherein the polynomial calculation module and the filter module are respectively set according to the polynomial part and the coefficient part of the digital pre-distortion model; The polynomial calculation module is configured to perform polynomial calculation on multiple signal components to obtain multiple polynomial calculation results; wherein the multiple signal components are obtained by decomposing a transmission signal to be input to a power amplifier according to the number of input paths of the polynomial calculation module; and the number of input paths is determined according to an original processing clock frequency and a target processing clock frequency. The memory module is configured to perform delay processing on the multiple signal components to generate new signal components, and input the newly generated signal components to the polynomial calculation module for polynomial calculation; wherein the memory module is set when the polynomial memory depth of the polynomial calculation module is greater than the number of input paths. The filter module is configured to combine the polynomial calculation results to obtain a pre-distortion processed transmission signal.

11. The polyphase digital predistortion processing apparatus of claim 10, wherein, The filter module comprises at least one filter, and the input of each filter comprises at least one polynomial calculation result of the polynomial calculation module.

12. A polyphase digital predistortion processing device, characterized by It comprises: a processor, a memory and a computer program stored in the memory and configured to be executed by the processor, wherein the processor executes the computer program to implement the polyphase digital pre-distortion processing method of any one of claims 1 to 9.

13. A computer-readable storage medium, characterized in that, The computer readable storage medium stores a computer program, wherein when the computer program runs, the device where the computer readable storage medium is located executes the polyphase digital pre-distortion processing method of any one of claims 1 to 9.

14. A computer program product comprising computer programs / instructions, characterized in that, The computer program / instruction is executed by the processor to implement the polyphase digital pre-distortion processing method of any one of claims 1 to 9.

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