Capacitor array mismatch correction method, circuit, device, equipment and medium

Abstract

The present disclosure relates to a capacitor array mismatch correction method, circuit, device, equipment and medium in the field of communication technology. The method includes: performing capacitor array mismatch correction from the highest capacitor of the capacitor array to the low capacitor; judging whether the ratio of the capacitance value of the high capacitor connected to the reference voltage to the parallel value of the remaining grounded capacitors is greater than the design ratio; if it is greater than the design ratio, the high capacitor is suspended and replaced by the next capacitor of the high capacitor connected to the reference voltage, until the ratio of the parallel value of the capacitor connected to the reference voltage to the remaining grounded capacitors is not greater than the design ratio, selecting a suitable capacitor configuration and recording the register setting. The method replaces and configures capacitors on the basis of the existing capacitor array to achieve a pre-designed voltage divider effect, and can achieve good capacitor mismatch correction without adding additional circuits.

Description

Technical Field

[0001] The present disclosure relates to the field of communication technology, and in particular to a capacitor array mismatch correction method, circuit, device, equipment, and medium. Background Art

[0002] An analog-to-digital converter (ADC) converts analog signals into digital signals, such as temperature, humidity, pressure, and position. Successive approximation register (SAR) ADCs offer low power consumption and high sampling rates, making them a mainstream solution for RF transceiver chips. The principle of a SAR ADC is to maintain an analog signal via a capacitor and compare it with different reference voltages, ultimately achieving the desired accuracy through binary division. A digital register records the results of each comparison and ultimately outputs a digital signal. The overall comparison operation is controlled by the ADC's logic unit. A capacitive N-bits digital-to-analog converter (DAC) is used to generate these different references. Capacitive DACs are typically implemented using capacitor arrays. However, the accuracy of the DAC unit capacitors can affect the ADC's nonlinearity, noise floor, and harmonics.

[0003] Current technology addresses capacitor mismatch through two main approaches: one is to compensate for the mismatch by adding an additional capacitor array, or at least a portion of the capacitors. This approach adds additional circuit cost to the chip. The other approach is to determine the extent of the mismatch through testing and then, through an Engineering Change Order (ECO), modify the chip to pre-add capacitors. This approach does not increase the chip circuit cost, but does increase the chip's R&D cycle and R&D cost. Summary of the Invention

[0004] In order to solve the above technical problems, the present disclosure provides a capacitor array mismatch correction method, circuit, device, equipment and medium, which can achieve zero-overhead capacitor array mismatch correction.

[0005] The present disclosure provides a capacitor array mismatch correction method, which is applied to a successive approximation ADC, comprising:

[0006] Perform capacitor array mismatch correction from the highest capacitor to the lowest capacitor in the capacitor array;

[0007] Determine whether the ratio of the capacitance value of the high-level capacitor connected to the reference voltage to the parallel value of the remaining grounding capacitors is greater than the designed ratio;

[0008] If it is greater than the design ratio, the high-order capacitor is left floating and replaced by connecting the next capacitor of the high-order capacitor to the reference voltage until the ratio of the parallel value of the capacitor connected to the reference voltage and the remaining grounded capacitors is no greater than the design ratio. Select the appropriate capacitor configuration and record the register settings.

[0009] Exemplarily, determining whether a ratio of a capacitance value of a high-order capacitor connected to a reference voltage to a parallel value of other grounded capacitors is greater than a designed ratio includes:

[0010] Input a DC full-swing single-tone signal, keep the high-position capacitor connected to the reference voltage, and gradually reduce the parallel value of the ground capacitor through the capacitance of the floating ground capacitor;

[0011] If the received interference signal situation gradually worsens as the parallel value of the grounding capacitor decreases, it is determined that the ratio of the capacitance value of the high-order capacitor connected to the reference voltage to the parallel value of the remaining grounding capacitors is greater than the designed ratio.

[0012] Exemplarily, the capacitor array mismatch correction from the highest capacitor to the lower capacitor of the capacitor array includes: highest capacitor mismatch correction and other capacitor mismatch correction, and the highest capacitor mismatch correction includes:

[0013] Determine whether the ratio of the capacitance value of the high-level capacitor connected to the reference voltage to the parallel value of the remaining ground capacitors is greater than 1:1;

[0014] If it is greater than 1:1, the highest capacitor is left floating and replaced by connecting the second highest capacitor to the reference voltage. If the ratio of the parallel value of the second highest capacitor and the remaining grounded capacitors is greater than 1:1, the second highest capacitor is left floating and replaced by connecting the third capacitor to the reference voltage until the ratio of the parallel value of the capacitor connected to the reference voltage and the remaining grounded capacitors is no more than 1:1. Select the appropriate capacitor configuration and record the register settings.

[0015] Exemplarily, when performing the other-position capacitor mismatch correction, the design ratio of the parallel value of the other-position capacitor connected to the reference voltage and the grounded capacitor is a symmetrical ratio. After performing half of the optimization of the other-position capacitor mismatch correction, the grounding and reference voltage connection of the completed half of the optimization are reversed, and the remaining half of the optimization is completed.

[0016] Exemplarily, the method further includes:

[0017] If it is not greater than the design ratio, select the appropriate capacitor configuration and record the register settings.

[0018] Exemplarily, selecting a suitable capacitor configuration and recording register settings includes:

[0019] Select the capacitor configuration with the minimum interference signal through traversal, trend judgment and other methods, and record the capacitor value and corresponding register settings.

[0020] The present disclosure provides a capacitor array, comprising:

[0021] N+1 capacitors connected in parallel, where N is a natural number greater than or equal to 2;

[0022] The top plate of the capacitor array is connected to the common terminal of the intermediate relay;

[0023] The bottom plate of the capacitor array is connected to a predetermined reference voltage, an input voltage and a ground voltage through a set of switching arrays, and each switching switch in the switch array corresponds to a capacitor in the capacitor array one by one;

[0024] The N capacitors from high to low are all provided with a floating position that can be connected through the switching switch.

[0025] The present disclosure provides a capacitor array mismatch correction device, comprising:

[0026] A sequential correction module is configured to perform capacitor array mismatch correction from the highest capacitor to the lowest capacitor in the capacitor array;

[0027] a judgment module configured to judge whether a ratio of a capacitance value of a high-level capacitor connected to a reference voltage to a parallel value of other grounding capacitors is greater than a designed ratio;

[0028] The replacement module is configured to leave the high-order capacitor suspended if it is greater than the design ratio, and replace it with the next capacitor of the high-order capacitor connected to the reference voltage until the ratio of the parallel value of the capacitor connected to the reference voltage and the remaining grounded capacitors is no greater than the design ratio, select the appropriate capacitor configuration and record the register setting.

[0029] The present disclosure provides an electronic device, comprising:

[0030] processor and memory;

[0031] The processor is used to execute the steps of any of the above methods by calling the program or instructions stored in the memory.

[0032] The present disclosure provides a computer-readable storage medium, wherein the computer-readable storage medium stores a program or instruction, wherein the program or instruction enables a computer to execute the steps of any one of the above methods.

[0033] The technical solution provided by the present disclosure has the following advantages compared with the existing technology:

[0034] The present disclosure provides a capacitor array mismatch correction method, circuit, device, equipment and medium. The capacitor array mismatch correction method includes: performing capacitor array mismatch correction from the highest capacitor of the capacitor array to the lowest capacitor; judging whether the ratio of the capacitance value of the high-order capacitor connected to the reference voltage to the parallel value of the remaining grounded capacitors is greater than the design ratio; if it is greater than the design ratio, the high-order capacitor is suspended and replaced by the next capacitor of the high-order capacitor connected to the reference voltage until the ratio of the parallel value of the capacitor connected to the reference voltage to the remaining grounded capacitors is not greater than the design ratio, selecting a suitable capacitor configuration and recording register settings. The capacitor array mismatch correction method replaces and configures capacitors on the basis of the existing capacitor array to achieve the designed voltage divider effect. Without adding additional circuits, good capacitor mismatch correction can be achieved, saving circuit costs and shortening the research and development cycle. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0036] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0037] Figure 1 Schematic diagram of the circuit structure of an N-bits capacitive DAC in the prior art;

[0038] Figure 2 A flow chart of a capacitor array mismatch correction method provided in an embodiment of the present disclosure;

[0039] Figure 3 A schematic diagram of the circuit structure of an N-bits capacitive DAC provided in an embodiment of the present disclosure;

[0040] Figure 4 A schematic diagram of a capacitor mismatch correction logic flow provided by an embodiment of the present disclosure;

[0041] Figure 5 A structural block diagram of a capacitor array calibration device provided in an embodiment of the present disclosure;

[0042] Figure 6 A schematic structural diagram of an electronic device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0043] In order to more clearly understand the above-mentioned objectives, features and advantages of the present disclosure, the scheme of the present disclosure will be further described below. It should be noted that the embodiments of the present disclosure and the features therein can be combined with each other in the absence of conflict.

[0044] In the following description, many specific details are set forth to facilitate a full understanding of the present disclosure, but the present disclosure may also be implemented in other ways different from those described herein; it is obvious that the embodiments in the specification are only part of the embodiments of the present disclosure, rather than all of the embodiments.

[0045] It should be understood that the various steps described in the method embodiments of the present disclosure may be performed in different orders and / or in parallel. In addition, the method embodiments may include additional steps and / or omit the steps shown. The scope of the present disclosure is not limited in this respect.

[0046] It should be noted that the concepts of "first" and "second" mentioned in this disclosure are only used to distinguish different devices, modules or units, and are not used to limit the order or interdependence of the functions performed by these devices, modules or units.

[0047] It should be noted that the modifications of "one" and "multiple" mentioned in the present disclosure are illustrative rather than restrictive. Those skilled in the art should understand that unless otherwise clearly indicated in the context, they should be understood as "one or more".

[0048] The names of the messages or information exchanged between multiple devices in the embodiments of the present disclosure are only used for illustrative purposes and are not used to limit the scope of these messages or information.

[0049] The successive approximation register (SAR) ADC uses a capacitor to hold the analog signal and compare it with different reference voltages one by one, ultimately achieving the desired accuracy through binary division. A digital register records the result of each comparison and ultimately outputs a digital signal. The overall comparison operation is controlled by the ADC's logic unit. The capacitive N-bits DAC is used to achieve the generation of different references, and a capacitor array is generally used to implement the capacitive DAC. Figure 1 FIG. 1 is a schematic diagram of the circuit structure of an N-bits capacitive DAC in the prior art, as shown in FIG. Figure 1 As shown in Figure 2, the comparison process of SAR ADC is:

[0050] 1. Charge all capacitors with analog inputs via switches. in , Common Terminal (the common terminal of the intermediate relay, referred to as CT) is grounded. Further, CT is disconnected and all capacitors are grounded. At this time, CT = -V in ;

[0051] 2. The highest bit MSB capacitor is connected to the reference voltage V REF , the rest of the capacitors remain grounded. Since the capacitance of the MSB capacitor is equal to the parallel capacitance of the other capacitors, according to the capacitor voltage divider theorem, CT = -V in +0.5*V REF , compare CT and 0 through the comparator (op amp), that is, V in and 0.5*V RRF ;

[0052] 3. According to the theory, the second highest capacitor is compared in turn, and the second highest capacitor is connected to the reference voltage V REF , and so on until the smallest bit capacitance LSB, each capacitor is divided according to the capacitance value, CT n =-V in +0.5 n *V REF (n=2 for the next highest position, and so on);

[0053] 4. Through the formula: CT n =-V in +0.5 n *V REF It can be seen that the accuracy of the DAC unit capacitance will significantly affect the ADC's nonlinearity, noise floor, and harmonics.

[0054] Since the deviation of the highest-order capacitor value has the greatest impact on the output digital signal (determining the highest-order digital bit), the current correction method is to visually observe the noise floor and harmonics of the signal from the digital output end and adjust the highest-order capacitor value. In current technology, there are two main solutions for dealing with capacitor mismatch: one is to add an additional column of capacitor arrays or at least a portion of capacitors to compensate for the capacitor mismatch. This solution increases the circuit cost of the chip; the other solution is to determine the degree of capacitor mismatch through testing, and then modify the chip through ECO to increase the capacitance in advance. Although this solution does not increase the chip circuit cost, it increases the chip R&D cycle and R&D cost.

[0055] In order to solve the above technical problems, the embodiments of the present disclosure provide a capacitor array mismatch correction method, circuit, device, equipment and medium, the method comprising: performing capacitor array mismatch correction from the highest capacitor of the capacitor array to the low capacitor; judging whether the ratio of the capacitance value of the high capacitor connected to the reference voltage to the parallel value of the remaining grounded capacitors is greater than the design ratio; if it is greater than the design ratio, the high capacitor is left floating and replaced by connecting the next capacitor of the high capacitor to the reference voltage until the ratio of the parallel value of the capacitor connected to the reference voltage to the remaining grounded capacitors is not greater than the design ratio, selecting a suitable capacitor configuration and recording the register setting. This capacitor array mismatch correction method achieves a pre-designed voltage divider effect by replacing capacitors and selecting corresponding capacitor configurations on the basis of the existing capacitor array. It can achieve good capacitor mismatch correction without adding additional circuits, saving circuit costs and shortening the research and development cycle.

[0056] The following combination Figure 2-Figure 6 , the capacitor array mismatch correction method, circuit, device, equipment and medium provided by the embodiments of the present disclosure are described.

[0057] The present disclosure provides a capacitor array mismatch correction method for a successive approximation ADC. Figure 2 A flow chart of a capacitor array mismatch correction method provided by an embodiment of the present disclosure is shown in FIG. Figure 2 As shown, the method includes:

[0058] S01, performing capacitor array mismatch correction from the highest capacitor to the lowest capacitor in the capacitor array;

[0059] It can be understood that the mismatch of the highest capacitor in the capacitor array has the greatest impact on the overall performance, and the impact gradually decreases from the second highest, third to the lowest. Therefore, the capacitor array mismatch correction is performed one by one from the highest capacitor to the lowest capacitor in the capacitor array.

[0060] The capacitor array mismatch correction from the highest capacitor to the lower capacitors of the capacitor array includes: the highest capacitor mismatch correction and the other capacitor mismatch correction.

[0061] S02, determining whether the ratio of the capacitance value of the high-level capacitor connected to the reference voltage to the parallel value of the remaining grounding capacitors is greater than the designed ratio;

[0062] Take the highest capacitor mismatch correction as an example: the highest capacitor is connected to the reference voltage V REF , the remaining capacitors remain grounded. Therefore, the voltage divider is the value of the highest capacitor and the other capacitors in parallel. Input a DC full-swing single-tone signal, and perform spectrum analysis at the digital receiving end to see the single-tone signal spectrum and other interference spectra such as harmonics caused by mismatch. Keep the highest capacitor connected to the reference voltage V REF, the parallel value of the grounding capacitor is gradually reduced by the capacitance in the suspended grounding capacitor; if the received interference signal situation gradually worsens with the reduction of the parallel value of the grounding capacitor, it is determined that the ratio of the capacitance value of the highest-order capacitor connected to the reference voltage to the parallel value of the remaining grounding capacitors is greater than the designed ratio of 1:1.

[0063] The remaining capacitors need to meet the design ratio of 1:1 for non-highest capacitors. The design ratio of the remaining capacitors can be derived from the following formula:

[0064]

[0065] Where, the numerator is the reference voltage V REF The denominator is the overall capacitance value, and m is the number of bits compared, where the highest bit is 1 and the second highest bit is 2. S03: If it is greater than the design ratio, leave the high-order capacitor unconnected and replace it with the next capacitor after the high-order capacitor connected to the reference voltage until the ratio of the parallel value of the capacitor connected to the reference voltage and the remaining grounded capacitors is no greater than the design ratio. Select a suitable capacitor configuration and record the register settings.

[0066] Take the highest capacitor mismatch correction as an example: if step S02 determines that the ratio of the capacitance value of the highest capacitor connected to the reference voltage to the parallel value of the other grounded capacitors is greater than 1:1, then the highest capacitor is left floating and replaced by the second highest capacitor connected to the reference voltage V REF If the ratio of the parallel value of the second-highest capacitor to the remaining grounded capacitors is greater than 1:1, leave the second-highest capacitor floating and replace it with a third capacitor connected to the reference voltage. Repeat this process until the ratio of the parallel value of the capacitor connected to the reference voltage to the remaining grounded capacitors is no greater than 1:1. Then, select the appropriate capacitor configuration and record the register settings.

[0067] If step S02 determines that the ratio of the capacitance value of the highest-order capacitor connected to the reference voltage to the parallel value of the remaining grounded capacitors is not greater than 1:1, then an appropriate capacitor configuration is selected and the register settings are recorded. For example, a capacitor configuration with minimal interference signal is selected through traversal, trend determination, or other methods, and the capacitance value and corresponding register settings are recorded.

[0068] In an embodiment of the present disclosure, a capacitor array mismatch correction method includes: performing capacitor array mismatch correction from the highest capacitor of the capacitor array to the lowest capacitor; judging whether the ratio of the capacitance value of the high-order capacitor connected to the reference voltage to the parallel value of the remaining grounded capacitors is greater than the design ratio; if it is greater than the design ratio, the high-order capacitor is left floating and replaced by connecting the next capacitor of the high-order capacitor to the reference voltage until the ratio of the parallel value of the capacitor connected to the reference voltage to the remaining grounded capacitors is no greater than the design ratio, selecting a suitable capacitor configuration and recording the register setting. This capacitor array mismatch correction method replaces capacitors and configures capacitor combinations based on the existing capacitor array to achieve a pre-designed voltage divider effect. It can achieve good capacitor mismatch correction without adding additional circuits, saving circuit costs and shortening the R&D cycle.

[0069] An embodiment of the present disclosure also provides a capacitor array for use in a successive approximation ADC, the capacitor array comprising: N+1 capacitors connected in parallel, where N is a natural number greater than or equal to 2; the top plate of the capacitor array is connected to the common terminal of an intermediate relay; the bottom plate of the capacitor array is connected to a predetermined reference voltage, an input voltage, and a ground voltage via a set of switching switch arrays, wherein each switching switch in the switch array corresponds one-to-one to a capacitor in the capacitor array; the N capacitors from high to low are all provided with a floating position that can be connected via the switching switch. Figure 3 A schematic diagram of the circuit structure of an N-bits capacitive DAC provided in an embodiment of the present disclosure. In some embodiments, as Figure 3 As shown, Figure 2 Compared to the prior art N-bits capacitive DAC shown in FIG, the N-bits capacitive DAC provided by the present embodiment merely adds a floating capacitor position. By setting the floating capacitor position, the capacitor mismatch correction method provided by the present embodiment can float any capacitor position, enabling high-position capacitor replacement and arbitrary capacitor combination configuration to ensure that the ratio of the actual reference voltage capacitor value to the parallel value of the ground capacitor approaches the designed ratio.

[0070] Figure 4 A schematic diagram of a capacitance mismatch correction logic flow is provided in an embodiment of the present disclosure. In some embodiments, as Figure 4 As shown, capacitance mismatch correction and correction scheme can be implemented.

[0071] Since the performance degradation caused by the capacitance mismatch of higher bits is greater, the correction scheme starts from the most significant bit.

[0072] S1, highest bit capacitance mismatch correction

[0073] To correct the mismatch of the highest-order capacitor, the highest-order capacitor mismatch must first be determined.

[0074] S11, the highest capacitance mismatch judgment

[0075] Connect the highest capacitor to the reference voltage V REF The remaining capacitors are grounded. Therefore, the voltage divider is the value of the highest-order capacitor in parallel with the other capacitors. A full-rail DC single-tone signal is input. Spectrum analysis at the digital receiver reveals the spectrum of the single tone, along with other interference spectra such as harmonics caused by mismatch.

[0076] S111, gradually reduce the parallel capacitance value

[0077] Keep the highest capacitor connected to the reference voltage V REF , the parallel capacitance value of the grounding is gradually reduced by the floating capacitor, and the capacitance is [1,1,2,…,2 (n-1) ]C, so the range of the parallel capacitance value is [1,2 n ]C, reduce the step to 1C.

[0078] S112. Determine mismatch

[0079] When gradually reducing the parallel capacitance value, analyze the spectrum of the digital receiving end respectively. If the interference signal situation gradually worsens as the capacitance value in parallel decreases (signal power such as harmonics rises), it is explained that the highest bit capacitance value is greater than the sum of the other capacitance values ​​in parallel, and it is impossible to optimize by reducing the parallel value of the grounding capacitor, record the current mismatch situation, turn to the next step S12, replace the optimization scheme of the high-order capacitance; If the interference signal situation is alleviated as the capacitance value in parallel decreases (signal power such as harmonics decreases), then step S113 is performed, and suitable capacitance value is selected to obtain the optimal solution. Proceed to step S21, the mismatch correction of the next capacitance position.

[0080] S113, select the appropriate capacitance value to obtain the optimal solution

[0081] The optimal capacitance value is selected by traversal, trend judgment and other methods, that is, the capacitance configuration when the interference signal condition is the best (the harmonic signal power is the minimum) is selected, and the capacitance configuration and the corresponding register setting information are recorded.

[0082] S12. Optimization solution for replacing high-position capacitors

[0083] The optimization solution of replacing the high-order capacitor is used to solve the situation when the highest-order capacitor value is greater than the sum of the remaining capacitors in parallel.

[0084] S121, replace high-position capacitors

[0085] The high-position capacitor selected in step S11 is suspended or grounded, and the second-highest position of the capacitor is connected to the reference voltage V REF , the total value of the grounded shunt capacitors can be changed by grounding or floating the remaining capacitors.

[0086] S122. Determine the mismatch situation

[0087] With reference to step S112, when gradually reducing the parallel capacitance value, the spectrum of the digital receiving end is analyzed respectively. If the interference signal situation gradually worsens as the capacitance value decreases (the signal power such as harmonics increases), it is indicated that the highest bit capacitance value is greater than the sum of the remaining ground capacitance values ​​in parallel. By reducing the ground capacitance parallel value, it is impossible to optimize, record the current mismatch situation, proceed to step S12, and replace the high-order capacitance. If the interference signal situation is alleviated as the capacitance decreases (the signal power such as harmonics decreases), then turn to step S123 and select the appropriate capacitance value to obtain the optimal solution.

[0088] S123, select the appropriate capacitance value to obtain the optimal solution

[0089] Referring to step S113, the optimal capacitance value is selected through traversal, trend judgment, and other methods. That is, the capacitance configuration with the best interference signal (minimum harmonic and other signal power) is selected, and the capacitance value and corresponding register setting information are recorded. Then, the process proceeds to step S21 of the next capacitor mismatch correction.

[0090] S13. When there is no fully matching optimal solution, select the alternative optimal solution (in S112 and S122).

[0091] If no fully matched optimal solution can be obtained by traversing all of them step by step, the optimal solution is selected according to the mismatch conditions recorded in step S112 and step S122, the corresponding register setting information is recorded, and the next step is capacitor mismatch correction S21.

[0092] S21, other capacitor mismatch correction

[0093] The capacitor matching for the remaining bits is similar to that for the highest bit. The difference is that the capacitors for the remaining bits need to meet the design ratio of 1:1, which is not the highest bit. The capacitors for the remaining bits need to meet the design ratio as follows:

[0094]

[0095] The numerator is the reference voltage V FEF The denominator is the overall capacitance value, and m is the number of bits compared, where the highest bit is 1 and the second highest bit is 2.

[0096] When m is 1, When m is 2, n∈{1,2}, when n is 1, When n is 2 When m is 3, n∈{1,2,3,4}, when n is 1, When n is 2,

[0097] When n is 3, When n is 4 It can be seen that the ratio is symmetrical, and only half of the correction needs to be completed. The remaining half can be achieved by reversing the connection of the capacitors to ground and to the reference voltage. The design ratio of the parallel value of the other capacitors connected to the reference voltage and the grounded capacitor is symmetrical. After optimizing half of the other capacitor mismatch correction, the grounding and reference voltage connection of the completed half of the optimization are reversed to complete the remaining half of the optimization, which simplifies the correction process and improves the correction efficiency.

[0098] For ease of understanding, this embodiment analyzes the case where the capacitance value of the portion connected to the reference voltage is relatively small. In particular, when mismatch correction is performed on the remaining portions, after applying the high-position capacitor replacement solution once, since the capacitance values ​​of the reference voltage and ground portions have the aforementioned ratio, the adjustment solution is more flexible and can directly perform mismatch adjustment. If the ideal mismatch adjustment cannot be achieved, the high-position capacitor replacement solution can be continued.

[0099] In an embodiment of the present disclosure, capacitor array mismatch correction is performed from the highest capacitor to the lowest capacitor in the capacitor array; it is determined whether the ratio of the capacitance value of the high-order capacitor connected to the reference voltage to the parallel value of the remaining grounded capacitors is greater than the designed ratio; if it is greater than the designed ratio, the high-order capacitor is left floating and replaced by the next capacitor of the high-order capacitor connected to the reference voltage, until the ratio of the parallel value of the capacitor connected to the reference voltage to the remaining grounded capacitors is no greater than the designed ratio, and a suitable capacitor configuration is selected and the register setting is recorded. This capacitor array mismatch correction method replaces and configures capacitors on the basis of an existing capacitor array to achieve the designed voltage divider effect. It can achieve good capacitor mismatch correction without adding additional circuits, saving circuit costs and shortening the R&D cycle.

[0100] The following takes a 6-bits ADC as an example to illustrate the capacitor array mismatch correction method according to the embodiment of the present disclosure.

[0101] The design values ​​and actual values ​​of the 6-bits ADC capacitor array of one embodiment are shown in Table 1, where the numerical values ​​reflect the corresponding relationship between the capacitance values.

[0102] Table 1

[0103]

[0104] As can be seen from Table 1, the actual values ​​of the first three capacitors deviate significantly from the designed values, which leads to inaccurate voltage division and introduces nonlinearity, resulting in spectral harmonics and spurious interference signals.

[0105] Since the mismatch of the first three capacitors has a significant impact on performance, the following is the correction process for the mismatch of the first three capacitors:

[0106] A1. Spectrum analysis shows that the value of the highest capacitor is greater than the value of the remaining capacitors in parallel (36:35 (1+1+2+4+9+18)). Record the current mismatch and proceed to step S12 to replace the high-order capacitor.

[0107] A2. Apply the optimization solution of replacing the high-order capacitor. Leave the highest-order capacitor unconnected and connect the second-order capacitor to the reference voltage Vref. Spectrum analysis shows that the value of this capacitor is greater than the value of the remaining capacitors connected in parallel (18:17 (1+1+2+4+9)).

[0108] A3. Again, apply the optimization solution of replacing the high-position capacitor, leaving the second capacitor unconnected and the third capacitor connected to Vref. Spectrum analysis shows that the value of this capacitor is greater than the value of the remaining capacitors connected in parallel (9:8 (1+1+2+4)).

[0109] A4. The optimization solution of replacing high-position capacitors was applied again, leaving the third capacitor unconnected and the fourth capacitor connected to Vref. Spectrum analysis showed that the nonlinearity was significantly alleviated (4:4(1+1+2)). The current capacitor and register configurations were recorded as shown in Table 2:

[0110] Table 2

[0111]

[0112] A5. Regarding the second digit, theoretically, the value of the second capacitor should be 1:3 compared to the value of the other capacitors in parallel. After spectrum analysis, the ratio of the second capacitor is (18:53 (1+1+2+4+9+36)), which is higher than the ratio value.

[0113] A6. Apply the optimized solution of replacing the high-order capacitor, leaving the second-order capacitor disconnected from Vref. Spectrum analysis reveals the optimal matching solution (13(9+4):39(36+1+2)). The current register configuration is shown in Table 3.

[0114] Table 3

[0115]

[0116] A7. Based on the symmetry, the capacitor configuration for the second reverse (3:1) can be directly obtained as shown in Table 4:

[0117] Table 4

[0118]

[0119] At the same time, when judging the highest-order capacitance, the highest-order capacitance value is 36, and the remaining digits are 35; similarly, when judging the second-order and third-order capacitance, the higher the digit, the greater the deviation in the performance.

[0120] A8. Based on the four situations of the third digit, the first ratio is 1:7. After spectrum analysis, the ratio of the third digit capacitance is (9:62(1+1+2+4+18+36)), which is higher than the ratio value of 1:7.

[0121] A 9. Apply the optimization solution of replacing the high-position capacitor and disconnect the third-position capacitor from Vref. After spectrum analysis, the optimal matching solution (4(4):28(18+9+1)) is selected. The current register configuration solution is recorded as shown in Table 5:

[0122] Table 5

[0123]

[0124] A10. Similarly, based on symmetry, the capacitor configuration for the third reverse situation (7:1) can be directly obtained as shown in Table 6:

[0125] Table 6

[0126]

[0127]

[0128] A11. Four scenarios for the third digit are considered, one of which is a 3:5 ratio. Spectrum analysis shows that the optimal solution for the third digit capacitor ratio is 27(9+18):44(36+4+2+1+1), which is higher than the 3:5 ratio.

[0129] A12. Apply the optimized solution of replacing the high-position capacitors, leaving the third capacitor disconnected from Vref. Spectrum analysis determined the optimal matching solution (6(4+2):10(9+1)). The current register configuration is shown in Table 7.

[0130] Table 7

[0131]

[0132] A13. Similarly, based on symmetry, the capacitor configuration for the third reverse situation (5:3) can be directly obtained as shown in Table 8:

[0133] Table 8

[0134]

[0135] After completing the calibration of the first three capacitors, the mismatch calibration of the entire capacitor array can be completed because the performance impact of the fourth capacitor and subsequent capacitors is negligible. Alternatively, calibration can be completed when the interference caused by capacitor mismatch is lower than the noise floor.

[0136] The design values ​​and actual values ​​of the 6-bits ADC capacitor array of another embodiment are shown in Table 9, where the numerical values ​​reflect the corresponding relationship between the capacitance values.

[0137] Table 9

[0138]

[0139]

[0140] It can be seen that the first two capacitors have large deviations from the design values, which leads to inaccurate voltage division and introduces nonlinearity, resulting in spectral harmonics and spurious interference signals.

[0141] The following is the correction process for the first two digits (which have a greater impact on performance):

[0142] B1. Spectrum analysis shows that the value of the highest-order capacitor is greater than the value of the remaining capacitors in parallel (36:31(1+1+2+4+9+14)).

[0143] B 2. Apply the optimization solution of replacing the high-order capacitor. Leave the highest-order capacitor unconnected and connect the second-order capacitor to Vref. Spectrum analysis shows that the value of this capacitor is smaller than the value of the remaining capacitors in parallel. Spectrum analysis also shows that the nonlinearity is significantly alleviated (14:14(9+4+1)). The current register configuration is shown in Table 10:

[0144] Table 10

[0145]

[0146] A3. Regarding the second-order judgment, theoretically, the value of the second-order capacitor should be 1:3 compared to the value of the other capacitors in parallel. After spectrum analysis, the optimal matching solution is selected as shown in Table 11. The ratio of the second-order capacitor is (14:42 (2+4+36)).

[0147] Table 11

[0148]

[0149] A4. Based on the symmetry, the capacitor configuration for the second reverse (3:1) can be directly obtained as shown in Table 12:

[0150] Table 12

[0151]

[0152] Record the capacitor configuration and register configuration to complete the first two-digit correction.

[0153] Figure 5 A structural block diagram of a capacitor array calibration device provided in an embodiment of the present disclosure is shown in FIG. Figure 5As shown, the device 500 includes:

[0154] A sequential correction module 501 is configured to perform capacitor array mismatch correction from the highest capacitor to the lowest capacitor in the capacitor array;

[0155] The judging module 502 is configured to judge whether the ratio of the capacitance value of the high-level capacitor connected to the reference voltage to the parallel value of the remaining grounding capacitors is greater than a designed ratio;

[0156] The replacement module 503 is configured to, if the ratio is greater than the design ratio, leave the high-order capacitor suspended and replace it with the next capacitor of the high-order capacitor connected to the reference voltage, until the ratio of the parallel value of the capacitor connected to the reference voltage and the remaining grounded capacitors is no greater than the design ratio, select a suitable capacitor configuration and record the register setting.

[0157] Exemplarily, the determination module 502 includes:

[0158] The input module is configured to input a DC full-swing single-tone signal, keep the high-order capacitor connected to the reference voltage, and gradually reduce the parallel value of the ground capacitor through the capacitance of the floating ground capacitor;

[0159] The judgment submodule is configured to judge that the ratio of the capacitance value of the high-order capacitor connected to the reference voltage to the parallel value of the remaining grounding capacitors is greater than the designed ratio if the received interference signal gradually deteriorates as the parallel value of the grounding capacitor decreases.

[0160] Exemplarily, the sequence correction module 501 is configured to include:

[0161] A high-bit correction module configured to correct the highest-bit capacitance mismatch;

[0162] The other bit correction modules are configured to correct capacitance mismatches of other bits.

[0163] The high-order correction module is configured to determine whether the ratio of the capacitance value of the high-order capacitor connected to the reference voltage to the parallel value of the remaining grounded capacitors is greater than 1:1; if it is greater than 1:1, the highest-order capacitor is left floating and replaced by the second-highest-order capacitor connected to the reference voltage; if the ratio of the second-highest-order capacitor to the parallel value of the remaining grounded capacitors is greater than 1:1, the second-highest-order capacitor is left floating and replaced by the third-order capacitor connected to the reference voltage, until the ratio of the parallel value of the capacitor connected to the reference voltage to the remaining grounded capacitors is no greater than 1:1, and a suitable capacitor configuration is selected and the register settings are recorded.

[0164] Exemplarily, the other-bit correction module is further configured to, when performing the other-bit capacitor mismatch correction, perform half of the optimization of the other-bit capacitor mismatch correction based on the design ratio of the parallel value of the other-bit capacitor connected to the reference voltage and the grounded capacitor being a symmetrical ratio, and then reverse the grounding and reference voltage connection of the completed half of the optimized capacitors, thereby completing the remaining half of the optimization.

[0165] Exemplarily, the apparatus 500 further includes:

[0166] The selection module is configured to select a suitable capacitor configuration and record the register setting if it is not greater than the design ratio.

[0167] Exemplarily, the replacement module 503 is further configured to select a capacitor configuration with the minimum interference signal through methods such as traversal and trend judgment, and record the capacitance value and the corresponding register setting.

[0168] In an embodiment of the present disclosure, capacitor array mismatch correction is performed from the highest capacitor to the lowest capacitor in the capacitor array; it is determined whether the ratio of the capacitance value of the high-order capacitor connected to the reference voltage to the parallel value of the remaining grounded capacitors is greater than the designed ratio; if it is greater than the designed ratio, the high-order capacitor is left floating and replaced by the next capacitor of the high-order capacitor connected to the reference voltage, until the ratio of the parallel value of the capacitor connected to the reference voltage to the remaining grounded capacitors is no greater than the designed ratio, and a suitable capacitor configuration is selected and the register setting is recorded. This capacitor array mismatch correction method replaces and configures capacitors on the basis of an existing capacitor array to achieve the designed voltage divider effect. It can achieve good capacitor mismatch correction without adding additional circuits, saving circuit costs and shortening the R&D cycle.

[0169] Figure 6 A schematic diagram of the structure of an electronic device provided in an embodiment of the present disclosure is shown in FIG. Figure 6 As shown, the electronic device 600 includes: a processor 601 and a memory 602; the processor 600 calls the program or instruction stored in the memory 602 to execute the steps of any of the above capacitor array mismatch correction methods to achieve corresponding effects.

[0170] The present disclosure provides a computer-readable storage medium storing one or more programs, which can be executed by one or more processors to implement the above-mentioned virtual conference interaction method. The computer-readable storage medium can be a volatile memory (volatile memory), such as a random-access memory (RAM); or a non-volatile memory (non-volatile memory), such as a read-only memory (ROM), a flash memory, a hard disk drive (HDD), or a solid-state drive (SSD); or it can be a respective device including one or any combination of the above-mentioned memories, such as a mobile phone, a computer, a tablet device, a personal digital assistant, etc.

[0171] It should be noted that the computer-readable storage medium mentioned above in the present disclosure may be a computer-readable signal medium or a computer-readable storage medium, or any combination of the two. The computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or device, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present disclosure, a computer-readable storage medium may be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, device, or device. In the present disclosure, a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, which carries computer-readable program code. This propagated data signal may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium that can transmit, propagate, or transport a program for use by or in conjunction with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium may be transmitted using any suitable medium, including but not limited to wires, optical cables, RF (radio frequency), etc., or any suitable combination thereof.

[0172] In embodiments of the present disclosure, computer program code for performing the operations of the present disclosure may be written in one or more programming languages ​​or a combination thereof, including but not limited to object-oriented programming languages ​​such as Java, Smalltalk, C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the computer, partially on the computer, as a separate software package, partially on the computer and partially on a remote computer, or entirely on the remote computer or server. In cases involving a remote computer, the remote computer may be connected to the computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0173] It should be noted that, in this document, terms such as "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0174] The foregoing description is intended only to provide specific embodiments of the present disclosure, intended to enable those skilled in the art to understand and implement the present disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure is not intended to be limited to the embodiments described herein, but rather to be construed in the broadest manner consistent with the principles and novel features disclosed herein.

Claims

1. A capacitor array mismatch correction method, applied to a successive approximation ADC, characterized in that: include: Perform capacitor array mismatch correction from the highest capacitor to the lowest capacitor in the capacitor array; Determine whether the ratio of the capacitance value of the high-level capacitor connected to the reference voltage to the parallel value of the remaining ground capacitors is greater than the designed ratio, including: Input a DC full-swing single-tone signal, keep the high-position capacitor connected to the reference voltage, and gradually reduce the parallel value of the ground capacitor through the capacitance of the floating ground capacitor; If the received interference signal situation gradually worsens as the parallel value of the grounding capacitor decreases, it is determined that the ratio of the capacitance value of the high-order capacitor connected to the reference voltage to the parallel value of the remaining grounding capacitors is greater than the designed ratio; If it is greater than the design ratio, the high-order capacitor will be left floating and replaced by connecting the next capacitor of the high-order capacitor to the reference voltage until the ratio of the parallel value of the capacitor connected to the reference voltage and the remaining grounded capacitors is no greater than the design ratio. Select the capacitor configuration with the smallest interference signal and record the capacitance value and the corresponding register setting.

2. The method according to claim 1, characterized in that The capacitor array mismatch correction from the highest capacitor to the lower capacitor of the capacitor array includes: the highest capacitor mismatch correction and the other capacitor mismatch correction, and the highest capacitor mismatch correction includes: Determine whether the ratio of the capacitance value of the high-level capacitor connected to the reference voltage to the parallel value of the remaining ground capacitors is greater than 1:1; If it is greater than 1:1, the highest capacitor will be left floating and replaced by connecting the second highest capacitor to the reference voltage. If the ratio of the parallel value of the second highest capacitor and the remaining grounded capacitors is greater than 1:1, the second highest capacitor will be left floating and replaced by connecting the third capacitor to the reference voltage until the ratio of the parallel value of the capacitor connected to the reference voltage and the remaining grounded capacitors is no more than 1:

1. Select the capacitor configuration with the smallest interference signal and record the capacitance value and the corresponding register setting.

3. The method according to claim 2, characterized in that When performing the other-position capacitor mismatch correction, the design ratio of the parallel value of the other-position capacitor connected to the reference voltage and the grounded capacitor is a symmetrical ratio. After performing half of the optimization of the other-position capacitor mismatch correction, the grounding and reference voltage connection of the completed half of the optimization are reversed to complete the remaining half of the optimization.

4. The method according to claim 1, wherein Also includes: If it is not greater than the design ratio, select the capacitor configuration with the minimum interference signal and record the capacitance value and the corresponding register setting.

5. The method according to any one of claims 2 to 4, characterized in that: The selecting of the capacitor configuration with the minimum interference signal and recording the capacitance value and the corresponding register setting includes: Select the capacitor configuration with the minimum interference signal by traversal or trend judgment, and record the capacitor value and corresponding register setting.

6. A capacitor array mismatch correction device, characterized in that: include: A sequential correction module is configured to perform capacitor array mismatch correction from the highest capacitor to the lowest capacitor in the capacitor array; A judgment module is configured to judge whether the ratio of the capacitance value of the high-order capacitor connected to the reference voltage to the parallel value of the remaining grounding capacitors is greater than a designed ratio; the judgment module includes: an input module, configured to input a DC full-swing single-tone signal, keep the high-order capacitor connected to the reference voltage, and gradually reduce the parallel value of the grounding capacitor through the capacitance in the suspended grounding capacitor; a judgment submodule, configured to judge whether the ratio of the capacitance value of the high-order capacitor connected to the reference voltage to the parallel value of the remaining grounding capacitors is greater than a designed ratio if the received interference signal situation gradually deteriorates as the parallel value of the grounding capacitor decreases; The replacement module is configured to leave the high-order capacitor suspended if it is greater than the design ratio, and replace it with the next capacitor of the high-order capacitor connected to the reference voltage, until the ratio of the parallel value of the capacitor connected to the reference voltage and the remaining grounded capacitors is no greater than the design ratio, select the capacitor configuration with the smallest interference signal, and record the capacitance value and the corresponding register setting.

7. An electronic device, characterized in that: include: processor and memory; The processor is configured to execute the steps of the method according to any one of claims 1 to 5 by calling the program or instructions stored in the memory.

8. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a program or instruction, and the program or instruction enables a computer to execute the steps of the method according to any one of claims 1 to 5.

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