A chip test mode entry circuit and method

Abstract

The present invention discloses a chip test mode entry circuit and method, comprising a chip, a test clock source Q1, a first test data source Q2, a second test data source Q3, a switch S1 and a power supply V1, wherein the output end of the test clock source Q1 is connected to a function pin LED1 of the chip, the output end of the first test data source Q2 is connected to one end of the switch S1, the other end of the switch S1 is connected to a function pin LED2 of the chip, the output end of the second test data source Q3 is connected to a function pin LED3 of the chip, the positive electrode of the power supply V1 is connected to a function pin VBAT of the chip, and the negative electrode of the power supply V1 is connected to a function pin GND of the chip and grounded. The present invention does not require additional pins, can safely enter the test mode, and will not mistakenly enter the test mode during normal operation.

Description

Technical Field

[0001] The present invention relates to a test mode entry circuit and method, in particular to a chip test mode entry circuit and method, belonging to the technical field of semiconductor integrated circuits. Background Art

[0002] After chip manufacturing is completed and before packaging, wafer-level testing will be performed to check the basic functions of each bare core and eliminate unqualified chips. After packaging and before shipment, comprehensive functional and performance testing is required to prevent packaging wire bonding, parasitic inductance, parasitic resistance, parasitic capacitance, etc. from affecting chip functions. These two testing methods ensure that the chip meets specification requirements.

[0003] Designing test modes can improve test coverage. Compared with testing in normal operation mode, test modes can directly skip some unnecessary functions or put the circuit into an easy-to-test state, reducing test time and cost and improving production efficiency. If a problem is found in the chip during testing, the test mode can help locate the specific fault area, which is conducive to later fault analysis.

[0004] In the field of ambient lighting applications, peripheral applications are developing towards extreme simplicity, such as Figure 8 As shown in the figure, the packaged chip only needs a few key interfaces: high-voltage LED drive port, high-voltage power supply interface (VBAT), and high-voltage bus pins (LIN) for communication. This feature makes it impossible to introduce additional pins when designing the test mode. Fig. 9 As shown, when the LED is working normally, the brightness is adjusted by the PWM signal, so the LED voltage is periodically switched between high level and low level. The commonly used voltage comparison or single data and password matching method is used, which is easy to enter the test mode by mistake during normal operation. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide a chip test mode entry circuit and method, which can enter the test mode without affecting normal operation and will not mistakenly enter the test mode during normal operation.

[0006] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0007] A chip test mode entry circuit comprises a chip, a test clock source Q1, a first test data source Q2, a second test data source Q3, a switch S1 and a power supply V1, wherein the output end of the test clock source Q1 is connected to a function pin LED1 of the chip, the output end of the first test data source Q2 is connected to one end of the switch S1, the other end of the switch S1 is connected to a function pin LED2 of the chip, the output end of the second test data source Q3 is connected to a function pin LED3 of the chip, the positive pole of the power supply V1 is connected to a function pin VBAT of the chip, and the negative pole of the power supply V1 is connected to a function pin GND of the chip and is grounded.

[0008] Furthermore, the chip includes a voltage conversion module, a mode data analysis module, an interface switching module, a processor and a module to be tested, the first input end of the voltage conversion module inputs a test clock LED1, the second input end of the voltage conversion module inputs a first test data LED2, the third input end of the conversion module inputs a second test data LED3, the first output end of the voltage conversion module is connected to the first input end of the mode data analysis module and inputs the converted test clock LED1_1v, the second output end of the voltage conversion module is connected to the second input end of the mode data analysis module and inputs the converted first test data LED2_1v, the third output end of the voltage conversion module is connected to the third input end of the mode data analysis module and inputs the converted second test data LED3_1v, the first output end of the mode data analysis module The first output end of the interface switching module is connected to the first input end of the interface switching module and inputs the converted test clock LED1_1v, the second output end of the mode data parsing module is connected to the second input end of the interface switching module and inputs the converted second test data LED3_1v, the third output end of the mode data parsing module is connected to the third input end of the interface switching module and the fourth input end of the voltage conversion module and inputs the signal EN_FT, the fourth input end of the interface switching module inputs the internal clock signal SClk, the fifth input end of the interface switching module inputs the internal data signal Sdata, the first output end of the interface switching module is connected to the first input end of the processor and outputs the clock signal Clk, the second output end of the interface switching module is connected to the second input end of the processor and outputs the data signal Data, and the output end of the processor is connected to the module to be tested.

[0009] Furthermore, the voltage conversion module comprises an NMOS tube N1, an NMOS tube N2, an NMOS tube N3, an NMOS tube N4, a PMOS tube P1, a diode D1, a delay pulse generating module, a digital buffer Buffer1, a digital buffer Buffer2 and a digital buffer Buffer3, the drain of the NMOS tube N1 serves as the first input end of the voltage conversion module and inputs the test clock LED1, the gate of the NMOS tube N1 is connected to the power supply VDD, the source of the NMOS tube N1 is connected to the input end of the digital buffer Buffer1, and the digital buffer Buffer3 is connected to the power supply VDD. The output end of r1 is used as the first output end of the voltage conversion module and outputs the converted test clock LED1_1v. The drain of the NMOS tube N2 is connected to the cathode of the diode D1 and is used as the second input end of the voltage conversion module to input the first test data LED2. The anode of the diode D1 is connected to the drain of the PMOS tube P1. The source of the PMOS tube P1 is connected to the power supply VDD. The input end of the delay pulse generating module is used as the fourth input end of the voltage conversion module and inputs the signal EN_FT. The first output end of the delay pulse generating module is connected to the gate of the PMOS tube P1 and outputs the signal EN_FTP. The second output end of the delay pulse generating module is connected to the gate of the NMOS tube N4 and outputs the signal EN_FTN, the gate of the NMOS tube N2 is connected to the power supply VDD, the source of the NMOS tube N2 is connected to the drain of the NMOS tube N4 and the input end of the digital buffer Buffer2, the source of the NMOS tube N4 is grounded, the output end of the digital buffer Buffer2 serves as the second output end of the voltage conversion module and outputs the converted first test data LED2_1v, the drain of the NMOS tube N3 serves as the third input end of the voltage conversion module and inputs the second test data LED3, the gate of the NMOS tube N3 is connected to the power supply VDD, the source of the NMOS tube N3 is connected to the input end of the digital buffer Buffer3, the output end of the digital buffer Buffer3 serves as the third output end of the voltage conversion module and outputs the converted second test data LED3_1v.

[0010] Furthermore, when the signal EN_FT jumps to high, the delay pulse generating module will generate a pulse signal and output it from the function pin LED2 of the chip.

[0011] Furthermore, when the voltage of the signal EN_FT is 0, the voltage of the signal EN_FTP is equal to the power supply VDD, the PMOS tube P1 is not turned on, the voltage of the signal EN_FTN is 0, the NMOS tube N4 is not turned on, and the voltage conversion module receives the data input by the function pin LED2 of the chip; when the signal EN_FT jumps to high, it is delayed for a period of time, and the delay time is determined according to the time required for the function pin LED2 of the chip to switch from the input state to the output state. During the delay period, the voltage of the signal EN_FT is equal to the power supply VDD, the voltage of the signal EN_FTN is equal to the power supply VDD, the NMOS tube N4 is turned on, and the function pin LED2 of the chip is pulled down to the ground; after the delay time After that, the voltage of signal EN_FTP is 0, the voltage of signal EN_FTN is 0, PMOS tube P1 is turned on, the function pin LED2 of the chip is pulled up to the power supply VDD, and signal EN_FTP is at a low level for a period of time. During the period when signal EN_FTP is at a low level, the converted first test data LED2_1v is continuously high; the voltage of signal EN_FTP is equal to the power supply VDD, the voltage of signal EN_FTN is equal to VDD, NMOS tube N4 is turned on, and the function pin LED2 of the chip is pulled down to the ground; therefore, a pulse signal can be observed from the function pin LED2 of the chip, and this pulse signal can be observed only after the password is matched successfully.

[0012] Furthermore, the delayed pulse generating module comprises a first delay circuit, a second delay circuit, a NOT gate A1, an OR gate A2 and an AND gate A3, the input end of the first delay circuit is connected to the signal EN_FT, the output end of the first delay circuit is connected to the input end of the second delay circuit and the input end of the NOT gate A1 and outputs a signal VA, the output end of the NOT gate A1 is connected to the first input end of the OR gate A2, the output end of the second delay circuit is connected to the second input end of the OR gate A2 and outputs a signal VB, the output end of the OR gate A2 is connected to the first input end of the AND gate A3 and outputs a signal EN_FTP, the second input end of the AND gate A3 is connected to the signal EN_FT, and the output end of the AND gate A3 outputs a signal EN_FTN.

[0013] A chip test mode entry method based on a chip test mode entry circuit comprises the following steps:

[0014] After the chip is powered on, it will be delayed for a while to wait for the chip to work stably;

[0015] The three function pins LED1, LED2 and LED3 of the multiplexed chip are inputted with the test clock LED1 into the function pin LED1 of the chip, the first test data LED2 into the function pin LED2 of the chip, and the second test data LED3 into the function pin LED3 of the chip;

[0016] The mode data analysis module stores the first test mode entry password and the second test mode entry password. When the data sequence of the first test data LED2 input by the chip's function pin LED2 successfully matches the first test mode entry password, and the data sequence of the second test data LED3 input by the chip's function pin LED3 also successfully matches the second test mode entry password, the mode data analysis module inter-signal EN_FT is pulled high and locked;

[0017] Disconnect switch S1, switch the chip's function pin LED2 from input state to output observation port, input signal EN_FT to voltage conversion module, output a pulse signal on the chip's function pin LED2 through voltage conversion module, when the pulse signal is observed on the chip's function pin LED2, it indicates that the password is matched successfully and enters test mode;

[0018] After entering the test mode, the interface switching module switches the output clock signal Clk from the internal clock signal SClk to the test clock LED1, and switches the output data signal Data from the internal data signal Sdata to the converted second test data LED3_1v, thereby achieving synchronization between the clock and the data;

[0019] Different second test data LED3 are fed into the function pin LED3 of the chip, and the processor selects the corresponding module to be tested for testing according to the fed second test data LED3;

[0020] After the test is completed, the chip receives a reset signal and exits the test mode.

[0021] Further, the first test mode entry password and the second test mode entry password are not regular periodic signals, and the first test mode entry password and the second test mode entry password have different periods in the same time period.

[0022] Compared with the prior art, the present invention has the following advantages and effects: the present invention provides a chip test mode entry circuit and method, which does not require additional pins, can safely enter the test mode, and will not mistakenly enter the test mode during normal operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a schematic diagram of a chip test mode entry circuit of the present invention.

[0024] Figure 2 It is a schematic diagram of the architecture of a chip test mode entry circuit of the present invention.

[0025] Figure 3 is a circuit diagram of the voltage conversion module of the present invention.

[0026] Figure 4It is a circuit diagram of the delayed pulse generating module of the present invention.

[0027] Figure 5 It is a schematic diagram of the voltage waveform of the delayed pulse generating module of the present invention.

[0028] Figure 6 The present invention is a flowchart of a method for entering a chip test mode.

[0029] Figure 7 It is a schematic diagram of the voltage waveform of the chip test mode of the present invention.

[0030] Figure 8 It is a schematic diagram of the pins of the atmosphere light in the prior art.

[0031] Fig. 9 It is a schematic diagram of LED voltage waveform in the ambient light application of the prior art. DETAILED DESCRIPTION

[0032] In order to elaborate on the technical scheme adopted by the present invention to achieve the predetermined technical purpose, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only partial embodiments of the present invention, rather than all embodiments, and the technical means or technical features in the embodiments of the present invention can be replaced without paying creative work. The present invention will be described in detail below with reference to the drawings and in conjunction with the embodiments.

[0033] like Figure 1 As shown, a chip test mode entry circuit of the present invention includes a chip, a test clock source Q1, a first test data source Q2, a second test data source Q3, a switch S1 and a power supply V1, the output end of the test clock source Q1 is connected to a function pin LED1 of the chip, the output end of the first test data source Q2 is connected to one end of the switch S1, the other end of the switch S1 is connected to a function pin LED2 of the chip, the output end of the second test data source Q3 is connected to a function pin LED3 of the chip, the positive pole of the power supply V1 is connected to a function pin VBAT of the chip, and the negative pole of the power supply V1 is connected to a function pin GND of the chip and grounded.

[0034] like Figure 2As shown, the chip includes a voltage conversion module, a mode data parsing module, an interface switching module, a processor and a module to be tested. The first input end of the voltage conversion module inputs a test clock LED1, the second input end of the voltage conversion module inputs a first test data LED2, the third input end of the conversion module inputs a second test data LED3, the first output end of the voltage conversion module is connected to the first input end of the mode data parsing module and inputs the converted test clock LED1_1v, the second output end of the voltage conversion module is connected to the second input end of the mode data parsing module and inputs the converted first test data LED2_1v, the third output end of the voltage conversion module is connected to the third input end of the mode data parsing module and inputs the converted second test data LED3_1v, the first output end of the mode data parsing module is connected to the The first input end of the interface switching module is connected to and inputs the converted test clock LED1_1v, the second output end of the mode data analysis module is connected to the second input end of the interface switching module and inputs the converted second test data LED3_1v, the third output end of the mode data analysis module is connected to the third input end of the interface switching module and the fourth input end of the voltage conversion module and inputs the signal EN_FT, the fourth input end of the interface switching module inputs the internal clock signal SClk, the fifth input end of the interface switching module inputs the internal data signal Sdata, the first output end of the interface switching module is connected to the first input end of the processor and outputs the clock signal Clk, the second output end of the interface switching module is connected to the second input end of the processor and outputs the data signal Data, and the output end of the processor is connected to the module to be tested.

[0035] like Figure 3As shown, the voltage conversion module includes NMOS tube N1, NMOS tube N2, NMOS tube N3, NMOS tube N4, PMOS tube P1, diode D1, delay pulse generation module, digital buffer Buffer1, digital buffer Buffer2 and digital buffer Buffer3. The drain of NMOS tube N1 serves as the first input end of the voltage conversion module and inputs the test clock LED1. The gate of NMOS tube N1 is connected to the power supply VDD. The source of NMOS tube N1 is connected to the input end of digital buffer Buffer1. The output end of digital buffer Buffer1 serves as the first output end of the voltage conversion module and outputs the converted test clock LED1_1v. The drain of NMOS tube N2 is connected to the cathode of diode D1 and serves as the second input end of the voltage conversion module to input the first test data LED2. The anode of diode D1 is connected to the drain of PMOS tube P1. The source of PMOS tube P1 is connected to the power supply VDD. The input end of the delay pulse generation module serves as the fourth input end of the voltage conversion module and inputs the signal EN_FT. The first output end of the delay pulse generation module is connected to the gate of PMOS tube P1 and outputs the signal EN_FTP. The second output end of the delay pulse generating module is connected to the gate of the NMOS tube N4 and outputs the signal EN_FTN, the gate of the NMOS tube N2 is connected to the power supply VDD, the source of the NMOS tube N2 is connected to the drain of the NMOS tube N4 and the input end of the digital buffer Buffer2, the source of the NMOS tube N4 is grounded, the output end of the digital buffer Buffer2 serves as the second output end of the voltage conversion module and outputs the converted first test data LED2_1v, the drain of the NMOS tube N3 serves as the third input end of the voltage conversion module and inputs the second test data LED3, the gate of the NMOS tube N3 is connected to the power supply VDD, the source of the NMOS tube N3 is connected to the input end of the digital buffer Buffer3, the output end of the digital buffer Buffer3 serves as the third output end of the voltage conversion module and outputs the converted second test data LED3_1v.

[0036] Diode D1 is a high-voltage diode, and the high-voltage signal on the LED backflows to the internal power supply VDD. NMOS tubes N1, NMOS tubes N2 and NMOS tubes N3 are high-voltage NMOS tubes, because the chip function pins LED1, LED2, LED3 will have high-voltage signals, and the high-voltage NMOS tube drain end is connected to the input port to withstand high voltage, which can isolate the high-voltage signal and prevent the internal circuit from being damaged by high voltage. The gate terminal is connected to the internal power supply of the chip, and the source terminal is connected to the digital buffer. The digital buffer will shape the low-voltage signal at the source end converted by the open NMOS tubes N1, NMOS tubes N2 and NMOS tubes N3, increase the driving capability, and then output it to the data analysis module.

[0037] When the signal EN_FT jumps to high, the delay pulse generation module will generate a pulse signal and output it from the chip's functional pin LED2.

[0038] like Figure 4 As shown, the delayed pulse generating module includes a first delay circuit, a second delay circuit, a NOT gate A1, an OR gate A2 and an AND gate A3, the input end of the first delay circuit is connected to the signal EN_FT, the output end of the first delay circuit is connected to the input end of the second delay circuit and the input end of the NOT gate A1 and outputs a signal VA, the output end of the NOT gate A1 is connected to the first input end of the OR gate A2, the output end of the second delay circuit is connected to the second input end of the OR gate A2 and outputs a signal VB, the output end of the OR gate A2 is connected to the first input end of the AND gate A3 and outputs a signal EN_FTP, the second input end of the AND gate A3 is connected to the signal EN_FT, and the output end of the AND gate A3 outputs a signal EN_FTN.

[0039] like Figure 5 and Figure 7 As shown, when the voltage of the signal EN_FT is 0, the voltage of the signal EN_FTP is equal to the power supply VDD, the PMOS tube P1 is not turned on, the voltage of the signal EN_FTN is 0, the NMOS tube N4 is not turned on, and the voltage conversion module receives the data input by the chip's function pin LED2; when the signal EN_FT jumps to high, it is delayed for a period of time, and the delay time is determined according to the time required for the chip's function pin LED2 to switch from input to output state. During the delay period, the voltage of the signal EN_FT is equal to the power supply VDD, the voltage of the signal EN_FTN is equal to the power supply VDD, the NMOS tube N4 is turned on, and the chip's function pin LED2 is pulled down to ground; after the delay time After that, the voltage of signal EN_FTP is 0, the voltage of signal EN_FTN is 0, PMOS tube P1 is turned on, the function pin LED2 of the chip is pulled up to the power supply VDD, and the signal EN_FTP is at a low level for a period of time. During the period when the signal EN_FTP is at a low level, the converted first test data LED2_1v is continuously high; the voltage of signal EN_FTP is equal to the power supply VDD, the voltage of signal EN_FTN is equal to VDD, NMOS tube N4 is turned on, and the function pin LED2 of the chip is pulled down to the ground; therefore, a pulse signal can be observed from the function pin LED2 of the chip, and this pulse signal can be observed only after the password is matched successfully.

[0040] like Figure 6 As shown, a chip test mode entry method based on a chip test mode entry circuit comprises the following steps:

[0041] After the chip is powered on, there is a delay to wait for the chip to work stably.

[0042] The three function pins LED1, LED2, and LED3 of the multiplexed chip are input with the test clock LED1 being input to the function pin LED1 of the chip, the first test data LED2 being input to the function pin LED2 of the chip, and the second test data LED3 being input to the function pin LED3 of the chip. The test clock LED1 and the first test data LED2 and the second test data LED3 can be offset by half a clock cycle to ensure that the data is sampled in the middle.

[0043] The mode data analysis module stores the first test mode entry password and the second test mode entry password. When the data sequence of the first test data LED2 input by the chip's function pin LED2 successfully matches the first test mode entry password, and the data sequence of the second test data LED3 input by the chip's function pin LED3 also successfully matches the second test mode entry password, the signal EN_FT between the mode data analysis modules is pulled high and locked. The signal EN_FT will be locked and pulled high as long as the password matches successfully, and other signals input by the subsequent pins will not affect the signal unless a reset signal is received. If a reset signal is received, the signal will be pulled low again, and re-entry requires the password to match again.

[0044] Disconnect switch S1 and switch the chip's functional pin LED2 from the input state to the output observation port. The signal EN_FT is input to the voltage conversion module, and a pulse signal is output on the chip's functional pin LED2 through the voltage conversion module. When a pulse signal is observed on the chip's functional pin LED2, it indicates that the password matches successfully and enters the test mode.

[0045] After entering the test mode, the interface switching module switches the output clock signal Clk from the internal clock signal SClk to the test clock LED1, and switches the output data signal Data from the internal data signal Sdata to the converted second test data LED3_1v, thereby achieving synchronization of clock and data.

[0046] Different second test data LED3 are fed into the function pin LED3 of the chip, and the processor selects a corresponding module to be tested for testing according to the fed second test data LED3.

[0047] After the test is completed, the chip receives a reset signal and exits the test mode. Once a reset occurs, the chip exits the test mode. The reset signal can be a specific sequence of pulses or a power failure.

[0048] The first test mode entry password and the second test mode entry password are not regular periodic signals, and the first test mode entry password and the second test mode entry password have different periods in the same period. In normal working mode, the PWM period is generally fixed, and even if LED1, LED2, and LED3 output pulse waveforms, the period is the same and fixed. In this way, the test mode sequence is distinguished from the normal working mode to prevent misentry.

[0049] The present invention provides a chip test mode entry circuit and method, which can enter the test mode safely without additional pins and will not mistakenly enter the test mode during normal operation.

[0050] The above is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent replacement and improvement made to the above embodiments without departing from the content of the technical solution of the present invention, based on the technical essence of the present invention, within the spirit and principles of the present invention, still fall within the protection scope of the technical solution of the present invention.

Claims

1. A chip test mode entry circuit, characterized in that: It comprises a chip, a test clock source Q1, a first test data source Q2, a second test data source Q3, a switch S1 and a power supply V1, wherein the output end of the test clock source Q1 is connected to a function pin LED1 of the chip, the output end of the first test data source Q2 is connected to one end of the switch S1, the other end of the switch S1 is connected to a function pin LED2 of the chip, the output end of the second test data source Q3 is connected to a function pin LED3 of the chip, the positive electrode of the power supply V1 is connected to a function pin VBAT of the chip, and the negative electrode of the power supply V1 is connected to a function pin GND of the chip and is grounded; The chip includes a voltage conversion module, a mode data analysis module, an interface switching module, a processor and a module to be tested. The first input end of the voltage conversion module inputs a test clock LED1, the second input end of the voltage conversion module inputs a first test data LED2, the third input end of the voltage conversion module inputs a second test data LED3, the first output end of the voltage conversion module is connected to the first input end of the mode data analysis module and inputs the converted test clock LED1_1v, the second output end of the voltage conversion module is connected to the second input end of the mode data analysis module and inputs the converted first test data LED2_1v, the third output end of the voltage conversion module is connected to the third input end of the mode data analysis module and inputs the converted second test data LED3_1v, the first output end of the mode data analysis module The first input terminal of the interface switching module is connected to the converted test clock LED1_1v, the second output terminal of the mode data analysis module is connected to the second input terminal of the interface switching module and inputs the converted second test data LED3_1v, the third output terminal of the mode data analysis module is connected to the third input terminal of the interface switching module and the fourth input terminal of the voltage conversion module and inputs the signal EN_FT, the fourth input terminal of the interface switching module inputs the internal clock signal SClk, the fifth input terminal of the interface switching module inputs the internal data signal Sdata, the first output terminal of the interface switching module is connected to the first input terminal of the processor and outputs the clock signal Clk, the second output terminal of the interface switching module is connected to the second input terminal of the processor and outputs the data signal Data, and the output terminal of the processor is connected to the module to be tested.

2. A chip test mode entry circuit according to claim 1, characterized in that: The voltage conversion module comprises an NMOS tube N1, an NMOS tube N2, an NMOS tube N3, an NMOS tube N4, a PMOS tube P1, a diode D1, a delay pulse generating module, a digital buffer Buffer1, a digital buffer Buffer2 and a digital buffer Buffer3. The drain of the NMOS tube N1 serves as the first input end of the voltage conversion module and inputs the test clock LED1. The gate of the NMOS tube N1 is connected to the power supply VDD. The source of the NMOS tube N1 is connected to the input end of the digital buffer Buffer1. The output end of the digital buffer Buffer1 serves as the first output end of the voltage conversion module and outputs the converted test clock LED1_1v. The drain of the NMOS tube N2 is connected to the cathode of the diode D1 and serves as the second input end of the voltage conversion module to input the first test data LED2. The anode of the diode D1 is connected to the drain of the PMOS tube P1. The source of the PMOS tube P1 is connected to the power supply VDD. The input end of the delay pulse generating module serves as the fourth input end of the voltage conversion module and inputs the signal EN_FT. The first output end of the delay pulse generating module is connected to the gate of the PMOS tube P1 and outputs the signal EN_FTP. The second output end of the delay pulse generating module is connected to the gate of the NMOS tube N4 and outputs the signal EN_FTN, the gate of the NMOS tube N2 is connected to the power supply VDD, the source of the NMOS tube N2 is connected to the drain of the NMOS tube N4 and the input end of the digital buffer Buffer2, the source of the NMOS tube N4 is grounded, the output end of the digital buffer Buffer2 serves as the second output end of the voltage conversion module and outputs the converted first test data LED2_1v, the drain of the NMOS tube N3 serves as the third input end of the voltage conversion module and inputs the second test data LED3, the gate of the NMOS tube N3 is connected to the power supply VDD, the source of the NMOS tube N3 is connected to the input end of the digital buffer Buffer3, the output end of the digital buffer Buffer3 serves as the third output end of the voltage conversion module and outputs the converted second test data LED3_1v.

3. A chip test mode entry circuit according to claim 2, characterized in that: When the signal EN_FT jumps to high, the delay pulse generation module will generate a pulse signal and output it from the chip's functional pin LED2.

4. A chip test mode entry circuit according to claim 2, characterized in that: When the voltage of signal EN_FT is 0, the voltage of signal EN_FTP is equal to the power supply VDD, PMOS tube P1 is not turned on, the voltage of signal EN_FTN is 0, NMOS tube N4 is not turned on, and the voltage conversion module receives the data input by the chip's function pin LED2; when signal EN_FT jumps to high, it will delay for a period of time. The delay time is determined according to the time required for the chip's function pin LED2 to switch from input to output state. During the delay period, the voltage of signal EN_FT is equal to the power supply VDD, the voltage of signal EN_FTN is equal to the power supply VDD, and NMOS tube N4 is turned on to pull the chip's function pin LED2 down to ground; after the delay time, , the voltage of signal EN_FTP is 0, the voltage of signal EN_FTN is 0, the PMOS tube P1 is turned on, the function pin LED2 of the chip is pulled up to the power supply VDD, the signal EN_FTP is continuously at a low level for a certain period of time, and during the period when the signal EN_FTP is continuously at a low level, the converted first test data LED2_1v is continuously high; the voltage of signal EN_FTP is equal to the power supply VDD, the voltage of signal EN_FTN is equal to VDD, the NMOS tube N4 is turned on, and the function pin LED2 of the chip is pulled down to the ground; therefore, a pulse signal can be observed from the function pin LED2 of the chip, and this pulse signal can only be observed after the password is matched successfully.

5. A chip test mode entry circuit according to claim 2, characterized in that: The delayed pulse generating module comprises a first delay circuit, a second delay circuit, a NOT gate A1, an OR gate A2 and an AND gate A3, the input end of the first delay circuit is connected to a signal EN_FT, the output end of the first delay circuit is connected to the input end of the second delay circuit and the input end of the NOT gate A1 and outputs a signal VA, the output end of the NOT gate A1 is connected to a first input end of the OR gate A2, the output end of the second delay circuit is connected to a second input end of the OR gate A2 and outputs a signal VB, the output end of the OR gate A2 is connected to a first input end of the AND gate A3 and outputs a signal EN_FTP, the second input end of the AND gate A3 is connected to a signal EN_FT, and the output end of the AND gate A3 outputs a signal EN_FTN.

6. A chip test mode entry method based on the chip test mode entry circuit according to any one of claims 1 to 5, characterized in that The following steps are involved: After the chip is powered on, it will be delayed for a while to wait for the chip to work stably; The three function pins LED1, LED2 and LED3 of the multiplexed chip are inputted with the test clock LED1 into the function pin LED1 of the chip, the first test data LED2 into the function pin LED2 of the chip, and the second test data LED3 into the function pin LED3 of the chip; The mode data parsing module stores the first test mode entry password and the second test mode entry password. When the data sequence of the first test data LED2 input by the chip's function pin LED2 successfully matches the first test mode entry password, and the data sequence of the second test data LED3 input by the chip's function pin LED3 also successfully matches the second test mode entry password, the mode data parsing module pulls up the signal EN_FT and locks it. Disconnect switch S1, switch the chip's function pin LED2 from input state to output observation port, input signal EN_FT to voltage conversion module, output a pulse signal on the chip's function pin LED2 through voltage conversion module, when the pulse signal is observed on the chip's function pin LED2, it indicates that the password is matched successfully and enters test mode; After entering the test mode, the interface switching module switches the output clock signal Clk from the internal clock signal SClk to the test clock LED1, and switches the output data signal Data from the internal data signal Sdata to the converted second test data LED3_1v, thereby achieving synchronization between the clock and the data; Different second test data LED3 are fed into the function pin LED3 of the chip, and the processor selects the corresponding module to be tested for testing according to the fed second test data LED3; After the test is completed, the chip receives a reset signal and exits the test mode.

7. The chip test mode entry method according to claim 6, characterized in that: The first test mode entry password and the second test mode entry password are not regular periodic signals, and the periods of the first test mode entry password and the second test mode entry password in the same time period are different.

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