An electromagnetic net trap control circuit

Abstract

The application discloses an electromagnetic net catcher control circuit, which comprises a control circuit composed of multiple control units. The control unit comprises a fourth resistor, an eleventh resistor, a twelfth adjustable resistor, a thirteenth resistor, a fifth flip-flop, a sixth digital potentiometer, a seventh inverter, a second MOS tube, a first diode and a second diode. The drain electrode of the second MOS tube, the 1PR anti-pin of the fifth flip-flop, one end of the twelfth adjustable resistor and a power supply are connected. The other end of the twelfth adjustable resistor is connected with the A1 pin of the sixth digital potentiometer. The U / D of the sixth digital potentiometer is connected with one end of the thirteenth resistor and the 1Q pin of the fifth flip-flop. The CS pin of the sixth digital potentiometer is connected with one end of the eleventh resistor, the 1D pin of the fifth flip-flop, the 1Q anti-pin of the fifth flip-flop. The 1CLR anti-pin of the fifth flip-flop is connected with one end of the fourth resistor and the source electrode of the second MOS tube. The gate electrode of the second MOS tube is connected with the output end of the seventh inverter. The input end of the seventh inverter is connected with a switching signal VIN_3.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electromagnetic transmitter, in particular to an electromagnetic net catcher control circuit. BACKGROUND

[0002] The existing pulse transmitter needs to use multiple groups of coils in series for acceleration, and photoelectric modules are arranged between the coils to detect the position of the projectile. When the projectile passes through the optimal working interval of the coil, the photoelectric module disconnects the power supply of the coil to avoid the phenomenon of back pulling. However, in the coupling process of the photoelectric module, the signal will have transmission delay due to hysteresis, which causes the actual position of the projectile to be beyond the midpoint of the coil before the power is disconnected. This will cause the coil to pull back the projectile, and the coils at the end will be affected more seriously by the delay power-off, and the back pulling phenomenon will be more serious. SUMMARY

[0003] In view of the above technical problems, the purpose of the present application is to provide an electromagnetic net catcher control circuit, which comprises a control circuit composed of multiple control units, the control unit comprising a fourth resistor R4, an eleventh resistor R11, a twelfth adjustable resistor R12, a thirteenth resistor R13, a fifth flip-flop U5, a sixth digital potentiometer U6, a seventh inverter U7, a second MOS tube Q2, a first diode D1, a second diode D2, the drain electrode of the second MOS tube Q2, the fourth pin of the fifth flip-flop U5, one end of the twelfth adjustable resistor R12 and the power supply are connected, the other end of the twelfth adjustable resistor R12 and the third pin of the sixth digital potentiometer U6 are connected, the second pin of the sixth digital potentiometer U6 and one end of the thirteenth resistor R13, the fifth pin of the fifth flip-flop U5 are connected, the seventh pin of the sixth digital potentiometer U6 and one end of the eleventh resistor R11, the second pin of the fifth flip-flop U5, the sixth pin of the fifth flip-flop U5 are connected, the first pin of the fifth flip-flop U5 and one end of the fourth resistor R4, the source electrode of the second MOS tube Q2 are connected, the gate electrode of the second MOS tube Q2 and the output end of the seventh inverter U7 are connected, the input end of the seventh inverter U7 and the switching signal VIN_3 are connected, the third pin of the fifth flip-flop U5 is connected with the cathode of the first diode D1 and the cathode of the second diode D2, the anode of the first diode D1 is connected with the firing signal VIN_1, the anode of the second diode D2 is connected with the photoelectric module signal VIN_2, the fifth pin of the sixth digital potentiometer U6, the sixth pin of the sixth digital potentiometer U6, the other end of the fourth resistor R4, the other end of the eleventh resistor R11, the other end of the thirteenth resistor R13 and the ground terminal are connected.

[0004] Further, the control unit further comprises a second adjustable resistor R2, a fifteenth resistor R15, a sixteenth resistor R16, an eighteenth resistor R18, a nineteenth resistor R19, a third operational amplifier U3, a first triode Q1, a third MOS Q3, a third thyristor D3, a first relay S1, a second relay S2, a first capacitor C1, the third MOS Q3 drain and the firing signal VIN_1 are connected, the third MOS Q3 gate, the first relay S1 coil one end and the switching signal VIN_3 are connected, the third MOS Q3 source and the third thyristor D3 control electrode are connected, the third thyristor D3 anode and the first triode Q1 collector are connected, the first triode Q1 emitter and the nineteenth resistor R19 one end are connected, the other end of the nineteenth resistor R19 and the power supply are connected, the first triode Q1 base and the eighteenth resistor R18 one end are connected, the third thyristor D3 cathode and the second relay S2 coil one end are connected, the other end of the second relay S2 coil and the sixteenth resistor R16 one end are connected, the second relay S2 common end and the first capacitor C1 one end, the third operational amplifier U3 non-inverting terminal are connected, the second relay S2 first connection end and the first relay S1 common end are connected, the second relay S2 second connection end and the second adjustable resistor R2 one end, the second adjustable resistor R2 tap end are connected, the other end of the first relay S1 coil and the fifteenth resistor R15 one end are connected, the first relay S1 second connection end and the sixth digital potentiometer U6 third pin are connected, the other end of the first capacitor C1, the other end of the second adjustable resistor R2, the other end of the fifteenth resistor R15, the other end of the sixteenth resistor R16, the other end of the eighteenth resistor R18, the first relay S1 first connection end and the ground are connected.

[0005] Further, the control unit further comprises a first resistor R1, a third resistor R3, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, a twenty-first resistor R21, a first operational amplifier U1, a second operational amplifier U2, a fourth operational amplifier U4, an eighth inverter U8, a fifth transistor Q5, a seventh transistor Q7, one end of the third resistor R3, the collector of the fifth transistor Q5, the collector of the seventh transistor Q7, and a power supply are connected, the emitter of the fifth transistor Q5 and the base of the first transistor Q1 are connected, the base of the fifth transistor Q5 and the output end of the first operational amplifier U1 are connected, the same phase end of the first operational amplifier U1 and one end of the first resistor R1, the other end of the third resistor R3, the same phase end of the fourth operational amplifier U4 are connected, the opposite phase end of the fourth operational amplifier U4 and one end of the tenth resistor R10 are connected, the output end of the fourth operational amplifier U4 and one end of the ninth resistor R9, the other end of the tenth resistor R10 are connected, the other end of the ninth resistor R9 and one end of the eighth resistor R8, one end of the twenty-first resistor R21, the same phase end of the second operational amplifier U2 are connected, the other end of the eighth resistor R8 and one end of the seventh resistor R7, the output end of the third operational amplifier U3 are connected, the other end of the seventh resistor R7 and the opposite phase end of the third operational amplifier U3 are connected, one end of the fifth resistor R5 and one end of the sixth resistor R6 are connected, the other end of the fifth resistor R5 and the opposite phase end of the first operational amplifier U1, the output end of the second operational amplifier U2 are connected, the emitter of the seventh transistor Q7 and the other end of the twenty-first resistor R21 are connected, the base of the seventh transistor Q7 and the output end of the eighth inverter U8 are connected, and the input end of the eighth inverter U8 and the switching signal VIN_3 are connected.

[0006] Further, the control unit further comprises a twentieth resistor R20, one end of the twentieth resistor R20 and the emitter of the first transistor Q1 are connected, and the other end of the twentieth resistor R20 and a ground end are connected.

[0007] Further, the control unit further comprises a fourteenth resistor R14, a fourth transistor Q4, one end of the fourteenth resistor R14 and the gate of the second MOS Q2 are connected, the base of the fourth transistor Q4 and the reset signal VIN_4 are connected, the collector of the fourth transistor Q4 and the sixth pin of the fifth flip-flop U5 are connected, the other end of the fourteenth resistor R14, the emitter of the fourth transistor Q4 and a ground end are connected.

[0008] Further, the control unit further comprises a twenty-third resistor R23, one end of the twenty-third resistor R23 and the common end of the second relay S2 are connected, and the other end of the twenty-third resistor R23 and a ground end are connected.

[0009] Further, the control unit further comprises a sixth MOS tube Q6, a fourth diode D4, a fifth diode D5, the anode of the fourth diode D4 is connected with the base of the fifth diode Q5, the cathode of the fourth diode D4 and the anode of the fifth diode D5 and the source of the sixth MOS tube Q6 are connected, the cathode of the fifth diode D5 is connected with the actual power-off signal Vout_1, the gate of the sixth MOS tube Q6 is connected with the gate of the second MOS tube Q2, and the drain of the sixth MOS tube Q6 is connected with the photoelectric module signal VIN_2.

[0010] Further, the control unit further comprises a seventeenth resistor R17, one end of the seventeenth resistor R17 is connected with the gate of the third MOS tube Q3, and the other end of the seventeenth resistor R17 is connected with the ground end.

[0011] Further, the first capacitor C1 is a variable capacitor.

[0012] The present application has the following beneficial effects compared with the prior art:

[0013] The present application can avoid the coil pulling back the emitted object caused by the signal transmission delay of the photoelectric module through testing and adjustment, has parameter adjustment, and can avoid the problems of the output not corresponding to the adjustment parameter and the coil misbreaking after delay adjustment. BRIEF DESCRIPTION OF DRAWINGS

[0014] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the prior art and embodiments, and obviously, the drawings in the following description can only be some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0015] Figure 1 The circuit structure schematic diagram provided by the present application. DETAILED DESCRIPTION

[0016] In order to make the purpose and advantages of the present application more clear and explicit, the following will specifically describe the present application combined with embodiments, and it should be understood that the following text is only used to describe one or several specific embodiments of the present application, and does not strictly limit the specific protection scope of the present application.

[0017] Considering that the photoelectric module has transmission delay in the coupling process signal backhitch, resulting in the actual position of the projectile being beyond the midpoint of the coil before power-off, the embodiment aims to solve the problem of coil pulling back the projectile caused by signal transmission delay of the photoelectric module. The control circuit has multiple control units, each corresponding to a coil control signal and a photoelectric module. The VIN_1 signal is the firing signal, the VIN_2 signal is the photoelectric module signal, the VIN_3 signal is the switching signal, the VIN_4 signal is the reset signal, and the Vout_1 signal is the actual coil power-off signal. The VIN_1, VIN_3, and VIN_4 of each control unit are connected in parallel, the VIN_2 is connected to the corresponding photoelectric module, the Vout_1 is connected to the corresponding coil power-off control signal, and the initial state is first tested to detect the feedback interval of each photoelectric module signal. During testing, the VIN_1 sends the firing signal, the signal is input to the third pin of the fifth flip-flop U5 through the first diode D1, the fifth pin of the fifth flip-flop U5 outputs the signal feedback to the second pin of the sixth digital potentiometer U6, the sixth pin of the fifth flip-flop U5 outputs the signal to the seventh pin of the sixth digital potentiometer U6, the sixth digital potentiometer U6 starts and adjusts according to the output state of the fifth pin of the fifth flip-flop U5, changes the resistance ratio of the third pin of the sixth digital potentiometer U6 and the twelfth adjustable resistor R12, and the connection end voltage. When the projectile passes through the current coil, the VIN_2 output signal is input to the third pin of the fifth flip-flop U5 through the second diode D2, the fifth pin and the sixth pin of the fifth flip-flop U5 output jump, so that the twelfth adjustable resistor R12 and the connection end voltage of the sixth digital potentiometer U6 retain the voltage corresponding to the interval length of the VIN_2 signal sent by the photoelectric module. When each control unit is completed, the VIN_3 input signal can be input, the signal is fed back to the seventh inverter U7, the seventh inverter U7 outputs to the gate of the second MOS tube Q2, and there is no conduction between the source and the drain of the second MOS tube Q2, which is negative voltage difference. The second MOS tube Q2 is cut off, the first pin of the fifth flip-flop U5 is reset through the fourth resistor R4 to lock the voltage retained by the twelfth adjustable resistor R12 and the connection end voltage of the sixth digital potentiometer U6, avoiding voltage changes caused by the fifth pin output of the fifth flip-flop U5 when the VIN_1 sends the signal again. Adjust the knob of the twelfth adjustable resistor R12 to change the retained end voltage, and when the VIN_1 outputs again, the voltage is corresponding to the RC circuit, and the constant is corresponding to the interval length of the VIN_2, so as to remove the delay.

[0018] This embodiment considers the signal loop control after the initial test is completed, and the element sharing when multiple control units, while the VIN_3 input signal, the signal is also fed back to the first relay S1 coil, the first relay S1 is closed after the twelfth adjustable resistor R12 and the sixth digital potentiometer U6 third pin end voltage through the first relay S1, the second relay S2 is input to the first capacitor C1 and the third operational amplifier U3 same phase end, the other road is input to the third MOS tube Q3 gate, the third MOS tube Q3 is turned on for VIN_1 signal input feedback, in this embodiment, the third operational amplifier U3 inverting terminal is not connected with the third operational amplifier U3 output terminal through the seventh resistor R7, but sets the reference signal, when VIN_1 sends the signal again, the signal is input to the third MOS tube Q3 through the third MOS tube Q3, and the third thyristor D3 is turned on. The nineteenth resistor R19 end power supply signal is input to the first transistor Q1 and the eighteenth resistor R18 loop, when the third thyristor D3 is turned on, the first transistor Q1 collector signal is input to the third thyristor D3, the second relay S2 and the sixteenth resistor R16 loop, the second relay S2 is closed, the first capacitor C1 end voltage is input to the second adjustable resistor R2 end loop, the second adjustable resistor R2 and the first capacitor C1 can change the constant curve, when the first capacitor C1 has no voltage, the third operational amplifier U3 output disconnects the coil power supply, completes the signal loop control, when multiple control loops are connected, the seventh inverter U7, the third MOS tube Q3, the fourth transistor Q4, the fourteenth resistor R14 and the seventeenth resistor R17 can be packaged separately, and the remaining elements can be integrated to be a module. The third operational amplifier U3 output terminal of this embodiment is directly connected with Vout_1, the twenty-third resistor R23 is used for the third operational amplifier U3 same phase end loop when the first capacitor C1 has no input, to avoid virtual short, the sixteenth resistor R16 and the fifteenth resistor R15 are used for the first relay S1 and the second relay S2 coil loop, to avoid overcurrent.

[0019] The embodiment considers that the reference voltage detection of the first capacitor C1 voltage by the third operational amplifier U3 will cause the first capacitor C1 to not correspond to the parameters and interval duration of the second adjustable resistor R2 loop if the reference voltage amplitude is too high, and it is unable to filter out signal interference to cause the third operational amplifier U3 to malfunction and the coil to appear false break, and the circuit reset problem when the coil is disconnected, therefore, the embodiment removes the reference signal directly provided to the third operational amplifier U3, the first operational amplifier U1 replaces the third operational amplifier U3 to output the Vout_1 signal, and the first capacitor C1 end voltage is fed back to the non-inverting terminal of the third operational amplifier U3, the third operational amplifier U3 follows the input to the non-inverting terminal of the second operational amplifier U2 through the eighth resistor R8, while the third resistor R3 and the first resistor R1 divide the reference voltage to the non-inverting terminal of the first operational amplifier U1 and the non-inverting terminal of the fourth operational amplifier U4, when there is no input of the initial VIN_3, the eighth inverter U8 outputs the signal to the base of the seventh transistor Q7, the seventh transistor Q7 is turned on to output the reference voltage bias signal which is fed back to the non-inverting terminal of the second operational amplifier U2 through the twenty-first resistor R21, while the fourth operational amplifier U4 is followed by the ninth resistor R9 to output to the non-inverting terminal of the second operational amplifier U2, the fourth operational amplifier U4 and the third operational amplifier U3 avoid multi-end input interference, the second operational amplifier U2 feeds back the multi-end input to the inverting terminal of the first operational amplifier U1, when there is interference, the inverting terminal of the first operational amplifier U1 exists voltage bias in the initial state, and the first operational amplifier U1 is in the cutoff state, when the VIN_3 input signal, the eighth inverter U8 is cut off and the seventh transistor Q7 has no output, the voltage at the third pin of the twelfth adjustable resistor R12 and the sixth digital potentiometer U6 is input to the first capacitor C1 through the first relay S1 and the second relay S2, the voltage at the first capacitor C1 end is input to the non-inverting terminal of the second operational amplifier U2 through the non-inverting terminal of the third operational amplifier U3 and the eighth resistor R8, while the VIN_3 signal is also input to the eighth inverter U8, the eighth inverter U8 and the seventh transistor Q7 are cut off, the third operational amplifier U3 replaces the seventh transistor Q7 input, while the first operational amplifier U1 is still cut off, because the third operational amplifier U3 follows the isolation of the first capacitor C1 end voltage to directly input the second operational amplifier U2, the loop parameters of the second adjustable resistor R2 and the first capacitor C1 are unchanged, and after the first capacitor C1 end voltage is input through the second adjustable resistor R2, the second relay S2 and the ground loop, the end voltage is less than the reference voltage at the non-inverting terminal of the first operational amplifier U1, the output signal of the first operational amplifier U1 is output, one way is input to the Vout_1 disconnected coil power supply through the fourth diode D4 and the fifth diode D5, and the other way is fed back to the base of the fifth transistor Q5, the fifth transistor Q5 is turned on, the first transistor Q1 is cut off to make the third thyristor D3 cut off, the second relay S2 is disconnected for reset,The signal directly fed back by VIN_2 in the initial test stage in this embodiment is fed back through the sixth MOS tube Q6 and the fifth diode D5, when the VIN_3 input signal, the sixth digital potentiometer U6 is cut off by the first operational amplifier U1 for output, avoiding the emission of the power-off signal after the photoelectric module, and resetting the VIN_4 input signal, the fourth triode Q4 is turned on, the seventh pin of the sixth digital potentiometer U6 is pulled down through the fourth triode Q4, at this time the second pin of the sixth digital potentiometer U6 is opposite to the VIN_1 input signal before the test, the sixth digital potentiometer U6 is reset, after VIN_3 has no input, the VIN_1 input signal is input again to complete the test again or reset the test result, the first pin of the sixth digital potentiometer U6 is used for inputting the clock signal.

[0020] It will be obvious to a person skilled in the art that the application is not limited to the details of the foregoing exemplary embodiments and can be implemented in other concrete forms without departing from the spirit or essential characteristics of the application. The embodiments should therefore be considered in all respects as illustrative and not restrictive, the scope of the application being defined by the appended claims rather than that of the foregoing description, and it is therefore intended that all changes that come within the meaning and range of equivalency of the claims are resolvable position the application. Any reference signs in the claims should not be construed as limiting the claims concerned.

Claims

1. An electromagnetic net-trap control circuit, characterized by The control circuit comprises a plurality of control units, and the control unit comprises a fourth resistor, an eleventh resistor, a twelfth adjustable resistor, a thirteenth resistor, a fifth flip-flop, a sixth digital potentiometer, a seventh inverter, a second MOS tube, a first diode and a second diode, the drain electrode of the second MOS tube, the 1PR back pin of the fifth flip-flop, one end of the twelfth adjustable resistor and a power supply are connected, the other end of the twelfth adjustable resistor and the A1 pin of the sixth digital potentiometer are connected, the U / D of the sixth digital potentiometer and one end of the thirteenth resistor and the 1Q pin of the fifth flip-flop are connected, the CS pin of the sixth digital potentiometer and one end of the eleventh resistor, the 1D pin of the fifth flip-flop, the 1Q back pin of the fifth flip-flop are connected, the 1CLR back pin of the fifth flip-flop and one end of the fourth resistor and the source electrode of the second MOS tube are connected, the gate electrode of the second MOS tube and the output end of the seventh inverter are connected, the input end of the seventh inverter and a switching signal VIN_3 are connected, the 1CLK pin of the fifth flip-flop and the cathode of the first diode and the cathode of the second diode are connected, the anode of the first diode and a firing signal VIN_1 are connected, the anode of the second diode and an optoelectronic module signal VIN_2 are connected, the W1 pin of the sixth digital potentiometer, the B1 pin of the sixth digital potentiometer, the other end of the fourth resistor, the other end of the eleventh resistor, the other end of the thirteenth resistor and a ground terminal are connected.

2. The electromagnetic net-trap control circuit of claim 1, wherein, The control circuit comprises a plurality of control units, and the control unit further comprises a second adjustable resistor, a fifteenth resistor, a sixteenth resistor, an eighteenth resistor, a nineteenth resistor, a third operational amplifier, a first triode, a third MOS tube, a third thyristor, a first relay, a second relay and a first capacitor, the drain electrode of the third MOS tube and a firing signal VIN_1 are connected, the gate electrode of the third MOS tube, one end of the coil of the first relay and a switching signal VIN_3 are connected, the source electrode of the third MOS tube and the control electrode of the third thyristor are connected, the anode of the third thyristor and the collector of the first triode are connected, the emitter of the first triode and one end of the nineteenth resistor are connected, the other end of the nineteenth resistor and a power supply are connected, the base of the first triode and one end of the eighteenth resistor are connected, the cathode of the third thyristor and one end of the coil of the second relay are connected, the other end of the coil of the second relay and one end of the sixteenth resistor are connected, the common terminal of the second relay and one end of the first capacitor and the non-inverting terminal of the third operational amplifier are connected, the first connecting terminal of the second relay and the common terminal of the first relay are connected, the second connecting terminal of the second relay and one end of the second adjustable resistor and the tap terminal of the second adjustable resistor are connected, the other end of the coil of the first relay and one end of the fifteenth resistor are connected, the second connecting terminal of the first relay and the A1 pin of the sixth digital potentiometer are connected, the other end of the first capacitor, the other end of the second adjustable resistor, the other end of the fifteenth resistor, the other end of the sixteenth resistor, the other end of the eighteenth resistor, the first connecting terminal of the first relay and a ground terminal are connected.

3. The electromagnetic net-trap control circuit of claim 2, wherein, The control circuit comprises a plurality of control units, and the control unit further comprises a first resistor, a third resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, a twenty-first resistor, a first operational amplifier, a second operational amplifier, a fourth operational amplifier, an eighth inverter, a fifth transistor, and a seventh transistor.

4. The electromagnetic net-trap control circuit of claim 2, wherein, The control circuit comprises a plurality of control units, and the control unit further comprises a twentieth resistor, one end of the twentieth resistor is connected with the emitter of the first transistor, and the other end of the twentieth resistor is connected with the ground end.

5. The electromagnetic net-trap control circuit of claim 1, wherein, The control circuit comprises a plurality of control units, and the control unit further comprises a fourteenth resistor and a fourth transistor, one end of the fourteenth resistor is connected with the gate of the second MOS transistor, the base of the fourth transistor is connected with a reset signal VIN_4, the collector of the fourth transistor is connected with the inverse pin of the fifth flip-flop 1Q, the other end of the fourteenth resistor, the emitter of the fourth transistor and the ground end are connected.

6. The electromagnetic net-trap control circuit of claim 2, wherein, The control circuit comprises a plurality of control units, and the control unit further comprises a twenty-third resistor, one end of the twenty-third resistor is connected with the common end of the second relay, and the other end of the twenty-third resistor is connected with the ground end.

7. The electromagnetic net-trap control circuit of claim 3, wherein, The control circuit comprises a plurality of control units, and the control unit further comprises a sixth MOS transistor, a fourth diode and a fifth diode, the anode of the fourth diode is connected with the base of the fifth transistor, the cathode of the fourth diode is connected with the anode of the fifth diode and the source of the sixth MOS transistor, the cathode of the fifth diode is connected with an actual power-off signal Vout_1, the gate of the sixth MOS transistor is connected with the gate of the second MOS transistor, and the drain of the sixth MOS transistor is connected with a photoelectric module signal VIN_2.

8. The electromagnetic net-trap control circuit of claim 2, wherein, The control circuit comprises a plurality of control units, and the control unit further comprises a seventeenth resistor, one end of the seventeenth resistor is connected with the gate of the third MOS transistor, and the other end of the seventeenth resistor is connected with the ground end.

9. The electromagnetic net-trap control circuit of claim 2, wherein, The first capacitor is a variable capacitor. The first capacitor is a variable capacitor.

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