A firmware upgrade method for storage device and storage device

Abstract

The present invention provides a method for upgrading the firmware of a storage device and a storage device. The storage device has a firmware installation mode and a programming mode. The firmware upgrading method comprises the following steps: adjusting the storage device to the firmware installation mode, downloading and installing a new version of the firmware in the firmware installation mode; adjusting the storage device to the programming mode, running the new version of the firmware in the programming mode; and after installing the new version of the firmware and before adjusting to the programming mode, and / or after adjusting to the programming mode and before running the new version of the firmware, tuning and processing the clock signal of the storage device according to the clock signal and voltage parameters of the new version of the firmware, reducing or eliminating the phase difference between the clock signal of the new version of the firmware and the system clock. The present invention provides a method for upgrading the firmware of a storage device and a storage device. The firmware upgrading efficiency is high and the error checking and correction after the firmware upgrade can be ensured to operate normally.

Description

Technical Field

[0001] The present invention relates to the field of storage technology, and in particular to a firmware upgrade method for a storage device and a storage device. Background Art

[0002] Error Checking and Correcting (ECC) is a technology used to check whether the stored data is erroneous and correct the erroneous data. Error checking and correction can detect multi-bit data errors and can also specify the erroneous digits and correct them. Therefore, error checking and correction is related to the accuracy of reading and writing data of storage devices, and error checking and correction are involved in many functions of storage devices. Therefore, the normal operation of the error checking and correction system is related to the normal operation of storage devices. Summary of the invention

[0003] The object of the present invention is to provide a firmware upgrade method for a storage device and a storage device, which has high firmware upgrade efficiency and can ensure that the ECC can operate normally after the firmware upgrade.

[0004] In order to solve the above technical problems, the present invention is achieved through the following technical solutions:

[0005] The present invention provides a method for upgrading the firmware of a storage device, wherein the storage device has a firmware installation mode and a programming mode, and the method for upgrading the firmware comprises the following steps:

[0006] Adjusting the storage device to the firmware installation mode, and downloading and installing a new version of the firmware in the firmware installation mode;

[0007] adjusting the storage device to the programming mode, and running the new version of the firmware in the programming mode; and

[0008] After installing the new version of the firmware and before adjusting to the programming mode, and / or after adjusting to the programming mode and before running the new version of the firmware, the clock signal of the storage device is tuned and processed according to the clock signal and voltage parameters of the new version of the firmware to reduce or eliminate the phase difference between the clock signal of the new version of the firmware and the system clock.

[0009] In one embodiment of the present invention, before tuning the clock signal of the storage device, the clock frequency of the new version of the firmware is adjusted until the clock frequency of the new version of the firmware is consistent with the frequency of the system clock.

[0010] In one embodiment of the present invention, the step of tuning and processing the clock signal of the storage device includes:

[0011] Obtaining a clock input signal of the new version of the firmware;

[0012] Setting a delay range, and dividing the delay range into a plurality of clock windows;

[0013] Delay processing is performed on the clock input signal in sequence according to the clock window until the delay range is traversed to obtain multiple clock output signals; and

[0014] The phases of the clock output signal and the clock input signal are compared, an optimal delay window is obtained from the multiple clock windows, and a value is taken from the optimal delay window as a delay parameter of the clock signal in the tuning process step.

[0015] In one embodiment of the present invention, the step of obtaining the optimal delay window includes:

[0016] Obtaining phase differences between the plurality of clock output signals and the clock input signal, and taking the clock output signal with the smallest phase difference as the best clock output signal; and

[0017] The clock window corresponding to the optimal clock output signal is used as the optimal delay window.

[0018] In an embodiment of the present invention, the step of obtaining the delay parameter includes: obtaining a middle value of the optimal delay window, and rounding the middle value to an integer to obtain the delay parameter.

[0019] In one embodiment of the present invention, in the step of setting the delay range, the delay range is positively correlated with the frequency of the clock input signal, and the delay range does not exceed one cycle of the system clock.

[0020] In one embodiment of the present invention, the step of running the new version of the firmware includes:

[0021] Running the new version of the firmware;

[0022] Writing data to the storage device and reading the written data;

[0023] Obtaining an error correction code of the storage device, if the step of obtaining the error correction code does not report an error, the firmware upgrade is successful; and

[0024] If the step of obtaining the error correction code reports an error, the firmware upgrade fails, and the new version of the firmware is downloaded, installed and debugged again.

[0025] In one embodiment of the present invention, before tuning the clock signal of the storage device, the voltage parameters of the new version firmware and the old version firmware are unified and adjusted to the system voltage.

[0026] The present invention provides a storage device, the storage device having a firmware installation mode and a programming mode, the storage device comprising:

[0027] flash memory;

[0028] A main controller, electrically connected to the flash memory and the host computer;

[0029] A memory for storing firmware, wherein the main controller calls and executes the firmware according to the system clock, wherein when the firmware is upgraded, the main controller adjusts the storage device to the firmware installation mode, downloads and installs the new version of the firmware in the firmware installation mode, and runs the new version of the firmware in the programming mode; and

[0030] The main controller includes a tuning module. After installing the new version of the firmware and before adjusting to the programming mode, and / or after adjusting to the programming mode and before running the new version of the firmware, the tuning module tunes and processes the clock signal of the storage device according to the clock signal and voltage parameters of the new version of the firmware, so as to reduce or eliminate the phase difference between the clock signal of the new version of the firmware and the system clock.

[0031] In one embodiment of the present invention, the tuning module includes a delay unit, an input end of the delay unit receives a clock input signal, and an output end of the delay unit outputs a clock output signal, wherein the clock output signal is the delayed clock input signal.

[0032] As described above, the present invention provides a storage device firmware upgrade method and storage device, which can realize online firmware upgrade of the storage device, and can unify the use environment of the new version of firmware and the old version of firmware, thereby improving the compatibility of the new version of firmware. In addition, through the storage device firmware upgrade method and storage device provided by the present invention, the upgrade efficiency is high, and the normal operation of ECC error correction can still be guaranteed after the firmware upgrade, reducing the probability of ECC error correction errors caused by firmware upgrade, thereby improving the data storage stability and security of the storage device.

[0033] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0035] Figure 1 The figure is a functional diagram of a host computer and a storage device in one embodiment of the present invention.

[0036] Figure 2 The figure is a flowchart of a method for upgrading firmware of a storage device according to an embodiment of the present invention.

[0037] Figure 3 FIG. 4 is a schematic diagram of the structure of a storage device in an embodiment of the present invention.

[0038] Figure 4 FIG. 4 is a schematic diagram of the structure of a tuning module in an embodiment of the present invention.

[0039] Figure 5 This is a schematic diagram of a clock signal without tuning.

[0040] Figure 6 Flow chart of steps S21 to S26 in one embodiment of the present invention.

[0041] Figure 7 FIG. 4 is a schematic diagram of a tuned clock signal according to an embodiment of the present invention.

[0042] In the figure: 100, host computer; 200, storage device; 210, main controller; 211, microprocessor; 212, host interface controller; 213, cache controller; 214, flash memory controller; 215, buffer; 216, error correction module; 220, flash memory; 230, memory; 300, tuning module; 301, input buffer; 302, delay unit; 303, multiplexer; 304, output buffer; CK_REF, clock input signal; CK_OUT, clock output signal. DETAILED DESCRIPTION

[0043] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0044] Firmware is a program written into an Erasable Programmable Read-Only Memory (EPROM) or an Electrically Erasable Programmable Read-Only Memory (EEPROM). In hardware development, firmware upgrade is inevitable. In this embodiment, the storage medium of the storage device 200 is a flash memory, and specifically can be a NAND flash memory. Among them, the storage device 200 can be an SM flash card, a CF card, a Multi Media Card (MMC), a Secure Digital Card (SD card), a memory stick, a micro hard disk, and the like. In this embodiment, the storage device 200 is an embedded MultiMedia Card (eMMC), and the firmware can be upgraded online. In the online upgrade process of the firmware, the storage device 200 receives a firmware upgrade message, and the firmware upgrade message can be an online upgrade message or an offline upgrade message. The storage device 200 does not process the offline upgrade message. If the firmware upgrade message is an online upgrade message, the firmware upgrade task is added to the online upgrade queue. The online upgrade queue includes multiple firmware upgrade tasks. According to the time when the firmware upgrade tasks are added, the firmware upgrade tasks are processed in sequence to upgrade the firmware.

[0045] See also Figure 1 As shown, in the firmware upgrade method of the storage device 200, the upper computer 100 sends an online upgrade message to the lower computer. After the lower computer starts processing the firmware upgrade task, it returns the hardware type and firmware version to the upper computer 100, and then performs the firmware upgrade. The lower computer is the storage device 200. In this embodiment, the firmware upgrade method of the storage device 200 includes steps S10 to S40.

[0046] Step S10: adjust the storage device 200 to the firmware online upgrade mode, download and install the new version of the firmware.

[0047] Step S20: Perform a first tuning process on the tuning module of the storage device 200 according to the clock signal and voltage parameters of the new version of the firmware.

[0048] Step S30: adjust the storage device 200 to the programming mode, and perform a second tuning process on the tuning module of the storage device 200 before running the new version of the firmware.

[0049] Step S40: Run the new version of the firmware, and determine whether the firmware upgrade is successful based on the verification data of the new version of the firmware.

[0050] See also Figure 1and Figure 2 As shown, in one embodiment of the present invention, before step S10, it is determined whether the storage device 200 supports online firmware upgrade. In this embodiment, taking the embedded memory as an example, the command CMD8 is sent to the storage device 200, and it is checked whether Bit0 of the project SUPPORT_MODES is 1. If Bit0 of the project SUPPORT_MODES is 1, the storage device 200 supports online firmware upgrade, and steps S10 to S40 are executed. If Bit0 of the project SUPPORT_MODES is 0, the storage device 200 does not support online firmware upgrade, returns the execution result to the host computer 100, and stops the firmware upgrade. It should be noted that the storage device 200 has a firmware installation mode and a programming mode. The firmware installation mode also includes a firmware online upgrade mode. In the firmware installation mode, the new version of the firmware can be downloaded and installed. In the firmware online upgrade mode, the storage device 200 can receive and download the firmware sent by the host computer 100, and debug the firmware. In the programming mode, the storage device 200 stops the firmware upgrade process and executes storage-related instructions. After the firmware upgrade process stops, it is determined whether the firmware upgrade fails or the firmware upgrade is terminated according to the settings of different storage devices 200. If the firmware upgrade fails, the firmware upgrade is performed again when the host computer 100 sends a firmware upgrade message. If the firmware upgrade is terminated, when the storage device 200 returns to the firmware online upgrade mode, the firmware upgrade task is continued from the stopped position.

[0051] See also Figure 1 and Figure 3As shown, in one embodiment of the present invention, the storage device 200 includes a main controller 210, a flash memory 220 and a memory 230. The main controller 210 includes a microprocessor 211, a host interface controller 212, a cache controller 213, a flash memory controller 214 and a buffer 215, and an error correction module 216. The microprocessor 211 is a reduced instruction system computer (RISC), and is specifically an ARM processor. The microprocessor 211 is electrically connected to the host interface controller 212, the cache controller 213 and the flash memory controller 214. The host interface controller 212 is electrically connected to the host computer 100 through an interface to receive instructions and data from the host computer 100, and to feed back data from the main controller 210. The connection interface between the host computer 100 and the main controller 210 can be a SATA hard disk, a high-speed serial computer expansion bus interface (Peripheral Component Interconnect express, PCIe), or a SAS interface. The cache controller 213 is electrically connected to the memory 230 and the buffer 215 to control the transfer and storage of data. In this embodiment, the flash memory controller 214 is electrically connected to the error correction module 216 to perform error correction on the data read out of the flash memory 220 during the reading process of the flash memory 220. The error correction module 216 can complete the error checking and correction of the flash memory 220 through the low density parity check code (Low Density Parity-Check Code, LDPC).

[0052] See also Figure 1 and Figure 2 As shown, in one embodiment of the present invention, in step S10, the storage device 200 is adjusted to the firmware online upgrade mode. Taking the embedded memory as an example, the host computer 100 sends the command CMD6 to the storage device 200 to configure the storage device 200 to the firmware online upgrade mode. In the step summary of downloading and installing the new version of the firmware, the host computer 100 writes the new version of the firmware into the memory 230. Taking the embedded memory as an example, the host computer 100 sends the command CMD25 to the storage device 200 to write the new version of the firmware into the memory 230. After the new version of the firmware is written, the host computer 100 sends the command CMD6 to the storage device 200 to adjust the storage device 200 to the firmware installation mode. In the firmware installation mode, the storage device 200 installs the written new version of the firmware. In this embodiment, the storage device 200 includes an online upgrade system, and the online upgrade system can execute the firmware upgrade method of the storage device 200 provided by the present invention, and the storage device 200 downloads, installs and adjusts the firmware through the online upgrade system.

[0053] See also Figure 1 and Figure 4As shown, in one embodiment of the present invention, in step S20, the voltage parameters and clock signals of different versions of firmware may be different. For example, the voltage parameter of the old version of firmware may be 1.8V, while the voltage parameter of the new version of firmware may be 3.3V. Therefore, in step S20, after the new version of firmware is written, the voltage parameter of the new version of firmware is first obtained, and the new version of firmware is adjusted to the voltage parameter of the storage device 200. Then, the clock signal of the new version of firmware is adjusted. The clock signal of the new version of firmware is the system clock of the central processing unit.

[0054] See also Figure 1 , Figures 4 to 6 As shown, in one embodiment of the present invention, the storage device 200 also includes a tuning module 300. The tuning module 300 includes an input buffer 301, a delay unit 302, a multiplexer 303 and an output buffer 304. The input buffer 301 is used to receive a clock input signal CK_REF, the delay unit 302 is used to tune the clock input signal CK_REF, and the output buffer 304 is used to output the clock output signal CK_OUT after the tuning process. In this embodiment, one clock input signal CK_REF corresponds to one clock output signal CK_OUT. In other embodiments of the present invention, the multiplexer 303 is used to realize multi-channel signal transmission. In the case of multiple signal inputs, after the multiple input signals are processed, one of the signals can be selected for output. In step S20, in the step of tuning the tuning module 300 of the storage device 200, the delay time of the clock input signal CK_REF by the delay unit 302 is related to the period of the clock input signal CK_REF, and the delay time of the clock input signal CK_REF does not exceed the period of the clock input signal CK_REF. The specific delay time is related to the frequency of the clock signal. For example, the clock input signal CK_REF can be delayed by 1 period, 0.5 period, 0.8 period, etc. In this embodiment, step S20 includes steps S21 to S26.

[0055] Step S21: unify the voltage parameters of the new version firmware and the old version firmware.

[0056] Step S22: Obtain the clock input signal of the new version of the firmware.

[0057] Step S23: setting a delay range, and dividing the delay range into a plurality of clock windows.

[0058] Step S24, delay processing is performed on the clock input signal in sequence according to the clock window to obtain a clock output signal until the delay range is traversed.

[0059] Step S25: Obtain phase errors between clock input signals and clock output signals in multiple clock windows.

[0060] Step S26: taking the clock window with the smallest phase error as the optimal delay window, and taking a value from the optimal delay window as the delay parameter of the tuning module.

[0061] See also Figure 1 , Figures 4 to 7 As shown, in one embodiment of the present invention, in step S21, the voltage parameters of the new version of the firmware and the old version of the firmware are unified. In this embodiment, the voltage parameters of the new version of the firmware and the old version of the firmware are unified to the operating voltage of the storage device 200. In step S22, the clock input signal CK_REF of the new version of the firmware is obtained, and the clock input signal is sent to the input buffer 301 as the initial clock signal. In step S23, the delay range is the delay time range of the delay unit 302. In this embodiment, the delay range is, for example, one cycle of the clock input signal CK_REF. The delay range is divided into multiple clock windows. Wherein multiple clock windows are continuous and non-overlapping. In this embodiment, the spans of multiple clock windows may be equal or unequal. For example, the delay range is 20ms. In step S23, the delay range is divided into 1ps~3ps, 3ps~5ps, 5ps~7ps, 7ps~9ps, 10ps~12ps, 12ps~14ps, 14ps~16ps, 16ps~18ps, 18ps~20ps. In step S23, the delay range can also be divided into 1ps~5ps, 5ps~7ps, 7ps~10ps, 10ps~15ps, 15ps~17ps, 17ps~20ps. It should be noted that the ports on both sides of the clock window are natural numbers.

[0062] See also Figure 1 , Figures 4 to 7 As shown, in one embodiment of the present invention, in step S24, in the step of delaying the initial clock signal according to the clock window, a value is randomly obtained from the clock window as the delay time of the delay unit 302. The clock input signal CK_REF is delayed according to the delay time to obtain a clock output signal. Specifically, after the input buffer 301 receives the clock input signal CK_REF, the delay unit 302 retrieves the clock input signal CK_REF from the input buffer 301, and after the delay time, outputs the clock input signal CK_REF to the multiplexer 303 and the output buffer 304, thereby obtaining the clock output signal CK_OUT. It should be noted that the actual phase error of the clock input signal is a black box state, and the error of the new version of the firmware in the storage device 200 cannot be known in advance. Therefore, in this embodiment, the multiple clock windows that are delayed cannot all play a role in eliminating errors.

[0063] See also Figure 1 , Figures 4 to 7As shown, in one embodiment of the present invention, in step S25, a clock output signal CK_OUT is obtained. There is a phase error between the clock output signal and the clock input signal. In this embodiment, in step S24, the clock window is traversed to obtain multiple clock output signals. Among them, the clock input signal is consistent. In step S25, the phase error between the clock input signal and the multiple clock output signals is obtained. Specifically, each clock window corresponds to a phase error. In this embodiment, a phase error is obtained once each clock output signal is obtained. In other embodiments of the present invention, the phase errors of multiple clock output signals and the clock input signal can also be uniformly obtained after traversing multiple clock windows. In this embodiment, a phase error threshold and an allowable error range are pre-set. The present invention does not limit the phase error threshold. The allowable error range here refers to the numerical range that exceeds the phase error threshold. In step S26, when the difference between the phase error and the phase error threshold exceeds the allowable error range, the corresponding clock window is discarded. It should be noted that the phase error can be lower than the phase error threshold, and when the phase error is greater than the phase error threshold and the difference between the two exceeds the allowable error range, the corresponding clock window is discarded. When the difference between the phase error and the phase error threshold is within the allowable error range, and there are multiple clock windows that meet this condition, the clock window with the smallest phase error is obtained from the multiple clock windows as the optimal delay window. It should be noted that when multiple phase errors do not meet the conditions, return to step S23, increase the number of clock windows, reduce the span of the clock windows, and re-divide the clock windows. And re-execute steps S24 to S26.

[0064] See also Figure 1 , Figures 4 to 7 As shown, in one embodiment of the present invention, the obtained optimal delay window is a numerical range. In step S26, a value is taken from the optimal delay window as the delay parameter of the tuning module 300. In this embodiment, the middle value integer of the optimal delay window is taken as the delay parameter of the tuning module 300. Among them, the middle value integer means that when the middle value of the optimal delay window is not an integer, the middle value is rounded. In rounding the middle value, the closest integer can be taken as the delay parameter of the tuning module 300. For example, the optimal delay window is 5ms~8ms. Then the middle value of the optimal delay window is 6.5ms. Then 6ms or 7ms can be taken as the delay parameter of the tuning module 300.

[0065] See also Figure 1 and Figure 2 As shown, in one embodiment of the present invention, step S30 and step S20 may both be performed, such as Figure 2 In another embodiment of the present invention, only step S20 may be performed. Figure 2In another embodiment of the present invention, only step S30 may be performed. Figure 2 Route A shown. In one embodiment of the present invention, after the tuning module 300 is tuned, step S30 is executed. In step S30, the storage device 200 is adjusted to the programming mode. Specifically, the host computer 100 sends a CMD6 command to the storage device 200 to adjust the storage device 200 from the firmware installation mode to the programming mode. In the programming mode, the memory 230 loads the new version of the firmware, and then executes step S30. In step S30, the new version of the firmware is tuned again to adjust the delay parameters of the tuning module 300. In this embodiment, the number of clock windows tuned in step S20 may be less than the number of clock windows tuned in step S30. Step S30 can, based on step S20 and based on different modes, further reduce the phase error of the clock output signal CK_OUT and the clock input signal CK_REF, thereby improving the accuracy of the firmware during operation.

[0066] See also Figures 1 to 3 As shown, in one embodiment of the present invention, in step S40, after the tuning module 300 is tuned, the new version of the firmware is run. In this embodiment, when the new version of the firmware is run, the host computer 100 writes verification data to the storage device 200 and reads the verification data. If the error correction module 216 does not report an error, the firmware upgrade is successful. If the read verification data is inconsistent with the written verification data, or the error correction module 216 reports an error, the firmware upgrade fails, and the process returns to step S10 to download and install the firmware again.

[0067] The present invention provides a firmware upgrade method for a storage device and a storage device, wherein the storage device has a firmware installation mode and a programming mode, and the firmware upgrade method comprises the following steps: adjusting the storage device to the firmware installation mode, and downloading and installing the new version of the firmware in the firmware installation mode. Adjusting the storage device to the programming mode, and running the new version of the firmware in the programming mode. After installing the new version of the firmware and before adjusting to the programming mode, and / or after adjusting to the programming mode and before running the new version of the firmware, the clock signal of the storage device is tuned and processed according to the clock signal and voltage parameters of the new version of the firmware to reduce or eliminate the phase difference between the clock signal of the new version of the firmware and the system clock. The present invention provides a firmware upgrade method for a storage device and a storage device, which have high firmware upgrade efficiency and can ensure that the ECC can operate normally after the firmware upgrade.

[0068] The embodiments of the present invention disclosed above are only used to help illustrate the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A method for upgrading firmware of a storage device, characterized in that: The storage device has a firmware installation mode and a programming mode, and the firmware upgrade method comprises the following steps: Adjusting the storage device to the firmware installation mode, and downloading and installing a new version of the firmware in the firmware installation mode; adjusting the storage device to the programming mode, and running the new version of the firmware in the programming mode; and After installing the new version of the firmware and before adjusting to the programming mode, and / or after adjusting to the programming mode and before running the new version of the firmware, tune and process the clock signal of the storage device according to the clock signal and voltage parameters of the new version of the firmware to reduce or eliminate the phase difference between the clock signal of the new version of the firmware and the system clock; The step of tuning and processing the clock signal of the storage device comprises: Obtaining a clock input signal of the new version of the firmware; Setting a delay range, and dividing the delay range into a plurality of clock windows; Delay processing is performed on the clock input signal in sequence according to the clock window until the delay range is traversed to obtain multiple clock output signals; and The phases of the clock output signal and the clock input signal are compared, an optimal delay window is obtained from the multiple clock windows, and a value is taken from the optimal delay window as a delay parameter of the clock signal in the tuning process step.

2. The method for upgrading the firmware of a storage device according to claim 1, characterized in that: Before tuning and processing the clock signal of the storage device, the clock frequency of the new version of the firmware is adjusted until the clock frequency of the new version of the firmware is consistent with the frequency of the system clock.

3. The method for upgrading the firmware of a storage device according to claim 1, characterized in that: The step of obtaining the optimal delay window comprises: Obtaining phase differences between the plurality of clock output signals and the clock input signal, and taking the clock output signal with the smallest phase difference as the best clock output signal; and The clock window corresponding to the optimal clock output signal is used as the optimal delay window.

4. The method for upgrading the firmware of a storage device according to claim 3, characterized in that: The step of obtaining the delay parameter includes: obtaining a middle value of the optimal delay window, and rounding the middle value to an integer as the delay parameter.

5. The method for upgrading the firmware of a storage device according to claim 1, characterized in that: In the step of setting the delay range, the delay range is positively correlated with the frequency of the clock input signal, and the delay range does not exceed one cycle of the system clock.

6. The method for upgrading the firmware of a storage device according to claim 1, characterized in that: The steps to run the new firmware include: Running the new version of the firmware; Writing data to the storage device and reading the written data; Obtaining an error correction code of the storage device, if the step of obtaining the error correction code does not report an error, the firmware upgrade is successful; and If the step of obtaining the error correction code reports an error, the firmware upgrade fails, and the new version of the firmware is downloaded, installed and debugged again.

7. The method for upgrading the firmware of a storage device according to claim 1, characterized in that: Before tuning and processing the clock signal of the storage device, the voltage parameters of the new version firmware and the old version firmware are unified and adjusted to the system voltage.

8. A storage device, characterized in that: The storage device has a firmware installation mode and a programming mode, and the storage device includes: flash memory; A main controller, electrically connected to the flash memory and the host computer; A memory for storing firmware, wherein the main controller calls and executes the firmware according to the system clock, wherein when the firmware is upgraded, the main controller adjusts the storage device to the firmware installation mode, downloads and installs the new version of the firmware in the firmware installation mode, and runs the new version of the firmware in the programming mode; and The main controller includes a tuning module, after installing the new version of the firmware and before adjusting to the programming mode, and / or after adjusting to the programming mode and before running the new version of the firmware, the tuning module tunes and processes the clock signal of the storage device according to the clock signal and voltage parameters of the new version of the firmware, so as to reduce or eliminate the phase difference between the clock signal of the new version of the firmware and the system clock; The step of tuning and processing the clock signal of the storage device comprises: Obtaining a clock input signal of the new version of the firmware; Setting a delay range, and dividing the delay range into a plurality of clock windows; Delay processing is performed on the clock input signal in sequence according to the clock window until the delay range is traversed to obtain multiple clock output signals; and The phases of the clock output signal and the clock input signal are compared, an optimal delay window is obtained from the multiple clock windows, and a value is taken from the optimal delay window as a delay parameter of the clock signal in the tuning process step.

9. A storage device according to claim 8, characterized in that: The tuning module includes a delay unit, an input end of the delay unit receives a clock input signal, and an output end of the delay unit outputs a clock output signal, wherein the clock output signal is the delayed clock input signal.

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