Testing system for inertial measurement control single machine

Abstract

The invention provides a test system for an inertial measurement control single machine, and belongs to the technical field of test equipment, the test system comprises a lower computer and an upper computer, the lower computer comprises a master control module and a slave control module, the modules realize the design of the lower computer through an MLVDS bus in a one-master multi-slave mode, and the master control module is connected with the slave control module. The module unit can independently realize a test function, one end of the lower computer is connected with an inertial measurement combination or control single-machine equipment through a test interface, and the other end of the lower computer is connected with the upper computer through a transmission cable. The master control module is integrated with an HDLC bus controller, and the protocol is integrated with the functions of flow control and error check, so that the system has the characteristics of high reliability, high transmission efficiency, strong adaptability and the like; by integrating the MLVDS bus controller, the problem of multi-node interconnection is effectively solved. All the modules are tightly connected through an MLVDS high-speed bus, efficient data communication is achieved, and meanwhile the accuracy and reliability of testing are guaranteed.

Description

Technical Field

[0001] The present invention relates to the technical field of testing equipment, and in particular to a testing system for an inertial measurement control unit. Background Art

[0002] The basic principle of inertial navigation technology is to sense the acceleration of the carrier during its motion through inertial measurement elements based on the laws of mechanics of relative inertial space proposed by Newton, and to obtain the acceleration, geographic location, and current heading attitude and other navigation parameters through the processor through integration operations. The inertial navigation system is mainly composed of an inertial measurement unit and a navigation computer. The inertial measurement unit is generally composed of a three-axis accelerometer and a gyroscope, which are used to measure the angular velocity and acceleration information of the three axes of the onboard equipment [2]. The navigation computer receives the acceleration and angular velocity information sent by the inertial measurement unit, and calculates the speed, position and attitude information of the carrier through the navigation algorithm. Due to the autonomy, concealment, and ability to obtain complete motion information of the carrier equipment, inertial navigation technology has gained a broad application space and has played a key role in applications such as system precision navigation and positioning.

[0003] The control stand-alone product is a sub-functional module of the control system that realizes one or more functions through functional division, and includes multiple functional units such as computers, distributors, controllers, etc. Taking a computer with a more complex interface as an example, its main function is to collect and process information from external components, and send control information to other stand-alone products based on the processing results. The reliability of the control stand-alone determines the system reliability of the entire product equipment, and is the core component of the entire control unit.

[0004] In order to ensure the integrity, reliability and comprehensiveness of the functions of inertial measurement units and single-machine control products during the design and development, debugging and testing, environmental testing, and product delivery stages, dedicated testing equipment is required to conduct a comprehensive assessment of product performance. This process continues throughout the product's life cycle, and through assessment tests, a product health record is formed to achieve full life cycle monitoring of product performance.

[0005] Traditional test equipment mostly adopts standard industrial test architecture as the design basis, such as CPCI, PXI, PXI-Express architecture industrial test equipment, which implements performance testing of the tested product through standard instrument chassis and purchased or self-made functional boards. This test solution has the advantages of high reliability, standardization, and meeting the production requirements of complex industrial environments. However, it also has some shortcomings in some aspects: due to the use of standard industrial architecture specifications for design, the system design is implemented by adding test boards to the backplane. In terms of expansion functions, the number of slots on the backplane limits the scalability of the test system interface; in terms of structure, due to the structural limitations of the backplane slots, the test system cannot achieve portability and compactness; in terms of real-time performance, the main controller of the test system mostly adopts the X86 architecture and is developed based on the Windows system. Due to the non-real-time nature of the Windows system, for high-real-time sensor devices such as inertial measurement units, data frame loss and other problems are prone to occur; in terms of economic benefits, industrial test equipment based on the above-mentioned architecture bus is relatively expensive compared to traditional embedded architecture test equipment, and is not suitable for large-scale layout and use in industrial production. Summary of the invention

[0006] The present invention provides a test system for inertial measurement control stand-alone machines to solve the defects of the prior art. It realizes the design, development and test verification of high real-time and multi-interface application scenarios of inertial measurement sensor products and control stand-alone products through industrial test system test equipment, and has great application promotion value.

[0007] In a first aspect, the present invention provides a test system for an inertial control stand-alone machine, comprising: an upper computer and a lower computer, wherein the lower computer comprises a main control module and a slave control module;

[0008] The master control module is connected to multiple slave control modules through MLVDS, and is used to integrate the HDLC bus controller and the MLVDS bus controller; the HDLC bus controller is used for protocol integrated flow control and error checking, and the MLVDS bus controller is used for data transmission and the transfer of control instructions;

[0009] The slave control module is connected to the device to be tested via MLVDS, and is used to receive the control instructions sent by the master control module, and configure the test tasks according to the control instructions to provide different test items.

[0010] Furthermore, the main control module also includes a data processing timing module, and the data processing timing module includes: a data acquisition unit, a parsing processing unit and a data storage unit;

[0011] The data acquisition unit is used to obtain the serial port receiving FIFO data, and complete the decoding of the current time stamp data and positioning data information to obtain the sampled data;

[0012] The analysis processing unit is used to receive the sampled data and cache the sampled data into the FIFO, and determine the FIFO state to obtain state information, wherein the sampled data corresponds to the state information one by one;

[0013] The data storage unit is used to perform clock management on the valid data cached by the analysis and processing module, realize data sampling second data conversion, and complete data storage.

[0014] Furthermore, the status information includes: waiting state, flag sampling state, frame header determination state, data receiving state and data receiving completion state.

[0015] Furthermore, the data processing timing module also includes a data retrieval unit, which is used to parse the stored data, determine the current time-scale data format, complete the current format time-scale second-to-second data conversion, and perform status judgment on the current received signal to realize data storage.

[0016] Perform data length judgment and determine the length of the current received signal to achieve data storage.

[0017] Further, the state judgment, data length judgment, and data storage based on the current received signal length information include:

[0018] The buffer FIFO is read as non-empty. If the FIFO is not empty, the read buffer area state is valid. The retrieved data is read. When the retrieved data satisfies the frame identifier ASCII code, the frame header judgment state is entered.

[0019] In the frame header judgment state, the frame header is read. If it meets the requirements, the data receiving state is entered. If the data does not meet the requirements, the waiting state is returned.

[0020] In the data receiving state, if the receiving FIFO is empty, it enters the waiting state and determines whether the data acquisition time has timed out. If so, it is considered not to be a frame of data and continues to enter the waiting state. Otherwise, the data reception is completed, the data frame reception is entered into the data frame reception completion state, and waits for an external pulse to reset and enter the waiting state to start the next reception.

[0021] Further, the HDLC bus controller includes: a receiving unit, a sending unit and a processor interface unit;

[0022] The receiving unit is used to perform frame header detection and zero-decoding on the synchronous serial port and bus data, adjust the data format of the synchronous serial port and bus data according to the HDLC protocol specification, and transmit the processed synchronous serial port and bus data to the host computer through the processor interface unit in an interrupt mode;

[0023] The sending unit is used to receive the data to be sent input by the processor interface unit, add CRC check code to the data, perform zero insertion coding and serial-to-parallel conversion according to the HDLC protocol, and then store it in the sending buffer area.

[0024] Further, the receiving unit includes a receiving channel, a flag detection subunit, a zero removal subunit, a sending controller, a receiving synchronization subunit and a check sequence subunit;

[0025] The receiving channel is used to perform frame header detection, zero removal and frame error flag output on synchronous serial port data;

[0026] A flag detection subunit, used for performing frame header detection and synchronous clock sampling on bus data;

[0027] A zero removal subunit, used for performing zero removal decoding according to the HDLC protocol;

[0028] The sending controller is used for the receiving controller to control the scheduling;

[0029] A receiving synchronization subunit, used for performing cross-clock domain signal synchronization;

[0030] The check sequence subunit is used to perform CRC check.

[0031] Further, the MLVDS bus controller includes: a communication link unit and a protocol control unit;

[0032] The communication link unit is used to encode and decode the bus data, perform CRC check and serial-to-parallel conversion, and then send it to the protocol control unit;

[0033] The protocol control unit is used to receive and cache valid data transmitted by the communication link unit, as well as to implement interface data interaction, automatic cyclic reading of data modules and error retransmission.

[0034] Further, the communication link unit includes a receiving subunit and a sending subunit;

[0035] The receiving subunit is used to perform data recovery, code conversion, data caching and CRC verification after receiving the MLVDS bus data at the data receiving end, obtain valid data with correct verification, store the valid data in the command module for caching and then pass it to the protocol control unit;

[0036] The sending subunit is used to receive data from the protocol control unit, add CRC check bits, perform asynchronous data buffering, data conversion and re-encoding, and then send the data to the MLVDS transceiver to realize bus data transmission.

[0037] Further, the protocol control unit includes a first processing subunit and a second processing subunit;

[0038] The first processing sub-unit is used to receive the valid data buffer transmitted by the communication link unit and store it in the corresponding register according to different slave numbers and addresses;

[0039] The second processing sub-unit is used for receiving the data written by the processor through the interface control register when data is sent, and sending the data to the communication link unit to add a check bit to realize the sending and receiving processing of MLVDS bus data.

[0040] The inertial measurement control stand-alone provided by the present invention consists of two parts: a lower computer and an upper computer. The lower computer includes a main control module and a slave control module. The module uses the MLVDS bus to implement the lower computer design in a one-master-multiple-slave form, and the module unit can independently implement the test function. The main control module integrates the HDLC bus controller, and the protocol integrates the flow control and error checking functions. It has the characteristics of high reliability, high transmission efficiency, and strong adaptability. By integrating the MLVDS bus controller, the problem of multi-node interconnection is effectively solved. By closely connecting each module through the MLVDS high-speed bus, efficient data communication and power management are achieved, while ensuring the accuracy and reliability of the test. Based on the above architecture, the present invention realizes the design, development and test verification of high real-time and multi-interface application scenarios for inertial sensor products and control stand-alone products through industrial test system test equipment, which has great application promotion value. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0042] Figure 1 This is one of the structural schematic diagrams of an optional test system for an inertial measurement control stand-alone machine provided by an embodiment of the present invention;

[0043] Figure 2 This is a second structural schematic diagram of an optional test system for an inertial measurement control stand-alone machine provided by an embodiment of the present invention;

[0044] Figure 3 is a schematic structural diagram of an optional main control module provided by an embodiment of the present invention;

[0045] Figure 4 is a schematic structural diagram of an optional data processing timing module provided by an embodiment of the present invention;

[0046] Figure 5is a schematic structural diagram of an optional HDLC frame transceiver provided in an embodiment of the present invention;

[0047] Figure 6 It is a schematic diagram of the structure of an optional MLVDS bus controller provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0048] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0049] It should be noted that in the description of the embodiments of the present invention, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "include one..." do not exclude the existence of other identical elements in the process, method, article or device including the elements. The orientation or position relationship indicated by the terms "upper", "lower" and the like is based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the system or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present invention. Unless otherwise clearly specified and limited, the terms "installed", "connected" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, or it can be the internal communication of two elements. For those skilled in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0050] The terms "first", "second", etc. in this application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0051] Combine the following Figure 1-Figure 6 A test system for an inertial control stand-alone machine provided by an embodiment of the present invention is described.

[0052] Figure 1 is one of the structural schematic diagrams of an optional test system for an inertial control stand-alone machine provided by an embodiment of the present invention, such as Figure 1 As shown, the system comprises:

[0053] A host computer and a slave computer, wherein the slave computer comprises a master control module and a slave control module;

[0054] The master control module is connected to multiple slave control modules through MLVDS, and is used to integrate the HDLC bus controller and the MLVDS bus controller; the HDLC bus controller is used for protocol integrated flow control and error checking, and the MLVDS bus controller is used for data transmission and the transfer of control instructions;

[0055] The slave control module is connected to the device to be tested via MLVDS, and is used to receive the control instructions sent by the master control module, and configure the test tasks according to the control instructions to provide different test items.

[0056] In one embodiment, the test system consists of a lower computer and a host computer. The lower computer includes a master control module and a slave control module. The modules use the MLVDS bus and adopt a one-master-multiple-slave form to implement the lower computer design. One end of the lower computer is connected to the inertial measurement combination or control single-machine equipment through a test interface, and the other end is connected to the host computer through a transmission cable.

[0057] The test system host computer is used to provide a human-computer interaction interface, and is connected to the test system slave computer via UART / ETHERNET. It manages and controls the test system resources in two ways, such as protocol transparent transmission and protocol stack integration in the slave computer.

[0058] The lower computer of the test system includes: a master control module and a slave control module; the master control module is connected to multiple slave control modules through MLVDS, and is used to integrate the HDLC bus controller, which has the functions of protocol integrated flow control and error checking, and integrates the MLVDS bus controller to solve the problem of multi-node interconnection. The slave control module is used to connect to the inertial measurement combination / control stand-alone equipment through MLVDS, and adopts a modular design in structure, which can independently realize the test function.

[0059] Figure 2 This is a second structural diagram of an optional test system for an inertial control stand-alone machine provided by an embodiment of the present invention, such as Figure 2As shown, the lower computer of the test system adopts a modular design in structure, including a main control module and a power distribution acquisition module, as well as a slave control module for implementing different test items. The power distribution acquisition module is responsible for providing a stable power supply for the test system and monitoring and managing the electric energy in the system. The unit is connected to other modules through a multi-point interconnected MLVDS high-speed bus, and dynamically adjusts the power distribution according to different test requirements to ensure the smooth progress of the test process. Electrically, the present invention uses a multi-point interconnected MLVDS high-speed bus to achieve different test requirements through different test modules for assembly to meet the test requirements, thereby achieving high utilization and wide coverage of hardware equipment.

[0060] Figure 3 is a schematic diagram of the structure of an optional main control module provided by an embodiment of the present invention, such as Figure 3 As shown, the main control module can be designed in the form of a core board plus an interface board. In terms of structural design, the core board and the interface board are interconnected through a stacking socket.

[0061] In one embodiment, the core board uses Xilinx's high-performance Zynq-7000 SOC (system on chip) processor chip to implement the design. The chip adopts a system-on-chip architecture, and integrates a dual-core Cortex-A9 processor system (PS) and programmable logic (PL) inside the chip. Among them, the programmable logic (PL) resources can be benchmarked against Xilinx's Artix-7 and Kintex-7 series FPGAs, and the processor system (PS) realizes the integration of on-chip memory, external memory interface and rich external bus interface.

[0062] The main control module mainly realizes the integration of the processor minimum system on the core board, and realizes system clock control through the clock circuit. The processor system (PS) side realizes DDR3 random access memory design through the memory interface for large-capacity data cache, and realizes NorFLASH non-volatile memory expansion through the SPI interface, realizes program burning and solidification, and power-on program loading.

[0063] The interface board mainly realizes the expansion of bus driver circuit. Through the integration of bus driver, the interface board realizes the compatibility of commonly used 1553B, serial port (synchronous, asynchronous), CAN, Ethernet, and MLVDS bus electrical protocols.

[0064] In terms of software implementation, the solution integrates MLVDS, UART, 1553B, MLVDS, CAN, and SPI bus controller soft cores on the Zynq-7000 SOC (system on chip) programmable logic (PL) side, and enables the bus controller on the processor system (PS) side. Compared with the traditional embedded system through bus controller hard core integration and bus expansion chip interface expansion, this approach has better versatility. The software defines the hardware inside the SOC to achieve multi-functional multiplexing of the interface. Taking the serial port as an example, the protocol interchange of the interface is achieved through the integration of HDLC (synchronous serial port) and UART (asynchronous serial port) controller IP cores. Compared with traditional embedded solutions, this approach has better flexibility and ease of use.

[0065] Based on the above embodiments, as an optional embodiment, the main control module in the test system for inertial control stand-alone provided by the present invention also includes a data processing timing module. The data processing timing module includes: a data acquisition unit, an analysis processing unit and a data storage unit.

[0066] The data acquisition unit is used to obtain the serial port receiving FIFO data, and complete the decoding of the current time stamp data and positioning data information to obtain the sampled data;

[0067] The analysis processing unit is used to receive the sampled data and cache the sampled data into the FIFO, and determine the FIFO state to obtain state information, wherein the sampled data corresponds to the state information one by one;

[0068] The data storage unit is used to perform clock management on the valid data cached by the analysis and processing module, realize data sampling second data conversion, and complete data storage.

[0069] The status information includes: waiting status, flag sampling status, frame header determination status, data receiving status and data receiving completion status.

[0070] In one embodiment, the data processing timing module also includes a data retrieval unit, which is used to parse and store data, determine the current time-scale data format, complete the current format time-scale second-to-second data conversion, perform status judgment, perform data length judgment, and realize data storage based on the current received signal length information.

[0071] Specifically, the state judgment, data length judgment, and data storage based on the current received signal length information include:

[0072] The buffer FIFO is read as non-empty. If the FIFO is not empty, the read buffer area state is valid. The retrieved data is read. When the retrieved data satisfies the frame identifier ASCII code, the frame header judgment state is entered.

[0073] In the frame header judgment state, the frame header is read. If it meets the requirements, the data receiving state is entered. If the data does not meet the requirements, the waiting state is returned.

[0074] In the data receiving state, if the receiving FIFO is empty, it enters the waiting state and determines whether the data acquisition time has timed out. If so, it is considered not to be a frame of data and continues to enter the waiting state. Otherwise, the data reception is completed, the data frame reception is entered into the data frame reception completion state, and waits for an external pulse to reset and enter the waiting state to start the next reception.

[0075] Figure 4 FIG. 1 is a schematic diagram of a block state transition diagram of an optional data processing timing module provided by an embodiment of the present invention. Figure 4 As shown, the data processing timing submodule completes the function of decoding the serial port receiving FIFO data.

[0076] The data receiving status is divided into 5 states, namely, the waiting state C_IDLE, the flag sampling state C_FIND_DOLLAR, the frame header determination state C_DECODE_HEADR, the data receiving state C_DECODE_DATE and the data receiving completion state C_DONE.

[0077] like Figure 4 As shown in the figure, it can be seen from the state transition diagram that the reset program enters the waiting state C_IDLE state, reads the cache FIFO to determine whether it is empty or not, the FIFO is not empty, the read buffer state rx_fifo_valid_i is valid, reads the collected data, and the collected data meets the frame identifier ASCII code, enters the C_DECODE_HEADR state, determines the frame header, receives 5 8-bit data continuously, reads the frame header, meets the requirements, enters C_DECODE_DATE, the data does not match, and returns to the C_IDLE state;

[0078] Enter the C_DECODE_DATE state. If the data acquisition time is greater than 1ms, it is considered not a frame of data and continues to enter the C_IDLE state.

[0079] After entering the C_DECODE_DATE state, the data reception is completed without timeout, and the data reception completion state C_DONE state is entered, and the external pulse reset is waited for to enter the waiting state C_IDLE state to start the next reception.

[0080] When the data is not updated in real time, the data processing timing submodule needs to use its own clock crystal oscillator for timing. During the process, the second count data sent by the satellite receiver needs to be converted into a custom perpetual calendar frame format.

[0081] Based on the above embodiments, as an optional embodiment, the present invention provides a test system HDLC bus controller for an inertial measurement control stand-alone machine, comprising: the HDLC bus controller comprises: a receiving unit, a sending unit and a processor interface unit;

[0082] The receiving unit is used to perform frame header detection and zero-decoding on the synchronous serial port and bus data, adjust the data format of the synchronous serial port and bus data according to the HDLC protocol specification, and transmit the processed synchronous serial port and bus data to the host computer through the processor interface unit in an interrupt mode;

[0083] The sending unit is used to receive the data to be sent input by the processor interface unit, add CRC check code to the data, perform zero insertion coding and serial-to-parallel conversion according to the HDLC protocol, and then store it in the sending buffer area.

[0084] Among them, the processor interface unit is used to: interact with the receiving unit to exchange data: transfer the data processed by the receiving unit to the processor, and receive the control signal of the processor to the receiving unit; interact with the receiving unit to transmit the data to be sent by the processor to the sending unit, and transfer the control signal of the processor to the sending unit.

[0085] In one embodiment, the receiving unit includes a receiving channel, a flag detection subunit, a zero removal subunit, a transmission controller, a receiving synchronization subunit and a check sequence subunit;

[0086] The receiving channel is used to perform frame header detection, zero removal and frame error flag output on synchronous serial port data;

[0087] A flag detection subunit, used for performing frame header detection and synchronous clock sampling on bus data;

[0088] A zero removal subunit, used for performing zero removal decoding according to the HDLC protocol;

[0089] The sending controller is used for the receiving controller to control the scheduling;

[0090] A receiving synchronization subunit, used for performing cross-clock domain signal synchronization;

[0091] The check sequence subunit is used to perform CRC check.

[0092] Figure 5 is a schematic diagram of the structure of an optional HDLC frame transceiver provided by an embodiment of the present invention, such as Figure 5As shown, the functional flow of the receiving unit is as follows: the synchronous serial port data realizes frame header detection, zero removal operation, frame error flag output, and frame reception enable through the receiving channel, the bus data realizes frame header detection through the flag detection subunit, synchronous clock sampling, and zero removal decoding operation (according to the HDLC protocol, the valid data is 5 consecutive 1s plus 0s) through the zero removal subunit, the sending controller mainly realizes the control and scheduling function of the receiving controller, frame error flag output, reception error frame interrupt output, frame reception enable, and the processed data completes cross-clock domain signal synchronization through the receiving synchronization subunit, the check sequence subunit realizes CRC check, and the valid data is output to the input rx buffer.

[0093] The processor interface unit receives data through the If_blk module interrupt mode;

[0094] The sending unit includes a synchronization check subunit, a synchronization sending subunit, a sending channel, a sending synchronization subunit, a sending controller, a sending message mid-end control and a flag mechanism subunit. The enabling process of the sending unit is as follows: the processor inputs data into the sending buffer area, the valid data adds CRC check to the last 16 bits through the synchronization check subunit, the data is output to the synchronization sending subunit to realize the synchronous serial port clock synchronization, the data inputs the sending channel, and the sending controller realizes the valid detection of the sending data frame. The sending message mid-end control is the core control module of the sending submodule. The sending message mid-end control is used as an encoding module to realize the zero insertion operation (according to the HDLC protocol, zero is added after 5 consecutive 1s), completes the data serial-to-parallel conversion, and the data is sent to the flag mechanism subunit to complete the sending process control, add the frame header and frame tail, and move the data out.

[0095] Based on the above embodiments, as an optional embodiment, the HDLC bus controller of the test system for inertial measurement control stand-alone provided by the present invention includes: a receiving unit, a sending unit and a processor interface unit. The MLVDS bus controller includes: a communication link unit and a protocol control unit;

[0096] The communication link unit is used to encode and decode the bus data, perform CRC check and serial-to-parallel conversion, and then send it to the protocol control unit;

[0097] The protocol control unit is used to receive and cache valid data transmitted by the communication link unit, as well as to implement interface data interaction, automatic cyclic reading of data modules and error retransmission.

[0098] In one embodiment, the communication link unit includes a receiving subunit and a transmitting subunit;

[0099] The receiving subunit is used to perform data recovery, code conversion, data caching and CRC verification after receiving the MLVDS bus data at the data receiving end, obtain valid data with correct verification, store the valid data in the command module for caching and then pass it to the protocol control unit;

[0100] The sending subunit is used to receive data from the protocol control unit, add CRC check bits, perform asynchronous data buffering, data conversion and re-encoding, and then send the data to the MLVDS transceiver to realize bus data transmission.

[0101] In one embodiment, the protocol control unit includes a first processing subunit and a second processing subunit;

[0102] The first processing sub-unit is used to receive the valid data buffer transmitted by the communication link unit and store it in the corresponding register according to different slave numbers and addresses;

[0103] The second processing sub-unit is used for receiving the data written by the processor through the interface control register when data is sent, and sending the data to the communication link unit to add a check bit to realize the sending and receiving processing of MLVDS bus data.

[0104] Figure 6 is a schematic diagram of the structure of an optional MLVDS bus controller provided by an embodiment of the present invention, such as Figure 6 As shown, the communication link unit mainly implements link layer functions such as bus data encoding and decoding, CRC check, serial-to-parallel conversion, etc. The protocol control unit implements data interaction with the processor, automatic cyclic data reading, error retransmission and other functions.

[0105] The controller implements the function flow as follows:

[0106] The receiving subunit is used to first recover the MLVDS bus data through the receive module in the receiving subunit at the data receiving end, and then convert the received 10-bit encoded data into 8-bit valid data through the decode8b / 10b module, cache the data through the ser_path_async_fifo, perform CRC check on the data through the crc_32_1 module, and if the check is correct, store the valid data into the cmd_path command module for data caching, and the cmd_path command module passes the valid data to the protocol control unit.

[0107] The protocol control unit receives valid data transmitted by the communication link unit and caches it, as well as implements interface data interaction, automatic cycle reading of data modules and error retransmission. The reg_read_only module in the first processing subunit stores the received data in the corresponding register according to different slave numbers and addresses. The second processing subunit can read and wait for the slave data to arrive by accessing the control register, and read the slave data.

[0108] The sending subunit is used for the processor to control register access through the interface second processing subunit at the data sending end, write the data into the reg_write_only module in the first processing subunit corresponding to the slave and the corresponding address, send the data to the data sending buffer area, and the protocol control unit sends the data to the crc_gen module in the receiving subunit of the communication link to add the CRC check bit, send the data to async_fifo to realize asynchronous data caching, realize the 8-bit to 10-bit conversion of valid data through the decode8b / 10b module, re-encode the data, convert the parallel data into serial data, and send the data to the MLVDS transceiver to realize bus data transmission.

[0109] The system embodiment described above is merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art may understand and implement it without creative work.

[0110] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0111] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A test system for an inertial control stand-alone machine, characterized in that: include: A host computer and a slave computer, wherein the slave computer comprises a master control module and a slave control module; The master control module is connected to multiple slave control modules through MLVDS, and is used to integrate the HDLC bus controller and the MLVDS bus controller; the HDLC bus controller is used for protocol integrated flow control and error checking, and the MLVDS bus controller is used for data transmission and the transfer of control instructions; The slave control module is connected to the device to be tested via MLVDS, and is used to receive the control instructions sent by the master control module, and configure the test tasks according to the control instructions to provide different test items.

2. The test system for inertial control stand-alone machine according to claim 1, characterized in that: The main control module also includes a data processing timing module, which includes: a data acquisition unit, an analysis processing unit and a data storage unit; The data acquisition unit is used to obtain the serial port receiving FIFO data, and complete the decoding of the current time stamp data and positioning data information to obtain the sampled data; The analysis processing unit is used to receive the sampled data and cache the sampled data into the FIFO, and determine the FIFO state to obtain state information, wherein the sampled data corresponds to the state information one by one; The data storage unit is used to perform clock management on the valid data cached by the analysis and processing module, realize data sampling second data conversion, and complete data storage.

3. The test system for inertial control stand-alone machine according to claim 2, characterized in that: The state information includes: waiting state, flag sampling state, frame header determination state, data receiving state and data receiving completion state.

4. The test system for inertial control stand-alone machine according to claim 3, characterized in that: The data processing timing module also includes a data retrieval unit, which is used to parse and store data, determine the current time-scale data format, complete the current format time-scale second-to-second data conversion, and perform status judgment on the current received signal to realize data storage.

5. The test system for inertial control stand-alone machine according to claim 4, characterized in that: The state judgment, data length judgment, and data storage according to the current received signal length information include: The buffer FIFO is read as non-empty. If the FIFO is not empty, the read buffer area state is valid. The retrieved data is read. When the retrieved data satisfies the frame identifier ASCII code, the frame header judgment state is entered. In the frame header judgment state, the frame header is read. If it meets the requirements, the data receiving state is entered. If the data does not meet the requirements, the waiting state is returned. In the data receiving state, if the receiving FIFO is empty, it enters the waiting state and determines whether the data acquisition time has timed out. If so, it is considered not to be a frame of data and continues to enter the waiting state. Otherwise, the data reception is completed, the data frame reception is entered into the data frame reception completion state, and waits for an external pulse to reset and enter the waiting state to start the next reception.

6. The test system for inertial control stand-alone machine according to claim 1, characterized in that: The HDLC bus controller includes: a receiving unit, a sending unit and a processor interface unit; The receiving unit is used to perform frame header detection and zero-decoding on the synchronous serial port and bus data, adjust the data format of the synchronous serial port and bus data according to the HDLC protocol specification, and transmit the processed synchronous serial port and bus data to the host computer through the processor interface unit in an interrupt mode; The sending unit is used to receive the data to be sent input by the processor interface unit, add CRC check code to the data, perform zero insertion coding and serial-to-parallel conversion according to the HDLC protocol, and then store it in the sending buffer area.

7. The test system for inertial control stand-alone machine according to claim 6, characterized in that: The receiving unit includes a receiving channel, a flag detection subunit, a zero removal subunit, a sending controller, a receiving synchronization subunit and a check sequence subunit; The receiving channel is used to perform frame header detection, zero removal and frame error flag output on synchronous serial port data; A flag detection subunit, used for performing frame header detection and synchronous clock sampling on bus data; A zero removal subunit, used for performing zero removal decoding according to the HDLC protocol; The sending controller is used for the receiving controller to control the scheduling; A receiving synchronization subunit, used for performing cross-clock domain signal synchronization; The check sequence subunit is used to perform CRC check.

8. The test system for inertial control stand-alone machine according to claim 1, characterized in that: The MLVDS bus controller includes: a communication link unit and a protocol control unit; The communication link unit is used to encode and decode the bus data, perform CRC check and serial-to-parallel conversion, and then send it to the protocol control unit; The protocol control unit is used to receive and cache valid data transmitted by the communication link unit, as well as to implement interface data interaction, automatic cyclic reading of data modules and error retransmission.

9. The test system for inertial control stand-alone machine according to claim 1, characterized in that: The communication link unit includes a receiving subunit and a sending subunit; The receiving subunit is used to perform data recovery, code conversion, data caching and CRC verification after receiving the MLVDS bus data at the data receiving end, obtain valid data with correct verification, store the valid data in the command module for caching and then pass it to the protocol control unit; The sending subunit is used to receive data from the protocol control unit, add CRC check bits, perform asynchronous data buffering, data conversion and re-encoding, and then send the data to the MLVDS transceiver to realize bus data transmission.

10. The test system for inertial control stand-alone machine according to claim 1, characterized in that: The protocol control unit includes a first processing subunit and a second processing subunit; The first processing sub-unit is used to receive the valid data buffer transmitted by the communication link unit and store it in the corresponding register according to different slave numbers and addresses; The second processing sub-unit is used for receiving the data written by the processor through the interface control register when data is sent, and sending the data to the communication link unit to add a check bit to realize the sending and receiving processing of MLVDS bus data.

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