Redundant channel software cycle synchronization method and system meeting functional safety requirements

Abstract

The embodiment of the present invention provides a redundant channel software cycle synchronization method and system that meets functional safety requirements, and belongs to the field of control technology of automobile systems. The method includes: obtaining a first signal to be synchronized, a second signal, an internal clock, and a delay value of the previous cycle; determining a first time point and a second time point according to the first signal and the second signal; determining a first output signal and a second output signal, a delay value of the next cycle, a first reset signal, and a second reset signal according to the first time point, the second time point, the internal clock, and the delay value of the previous cycle. The method and system combine the impact of the environment on the software, and when calculating the synchronization time point of the next cycle of the software, the cycle end time of the redundant channel and the self-test result of the cycle synchronizer are combined to calculate the starting time point of the next cycle of the software, thereby enhancing the reliability and robustness of the system operation.

Description

Technical Field

[0001] The present invention relates to the technical field of automobile system control, and in particular to a redundant channel software cycle synchronization method and system that meet functional safety requirements. Background Art

[0002] In systems with redundant channel software cycle synchronization control and functional safety requirements such as automotive electronics, rail transportation, aerospace, medical electronics, and industrial control, the redundant channel software cycle synchronization control accuracy has a great impact on the safety, reliability, and performance of the system.

[0003] There are two technical solutions among various redundant channel periodic synchronization technologies currently in use.

[0004] Solution 1: Software synchronization solution. Redundant channels use software communication messages to transmit synchronization status. After receiving the synchronization message from the redundant channel, the receiving channel parses the cycle number in the message and then determines and adjusts the start time of the next cycle of its own channel. Due to uncertain factors such as communication delay, this solution will cause large synchronization errors in the software operation cycle between redundant channels, and cannot be used in safety systems with high requirements for control accuracy.

[0005] Solution 2: Hardwired synchronization solution. Independent hardware outside the redundant channel periodically sends pulses to the redundant channel through hard wiring, and the redundant channel calculates the start time of the next cycle according to the pulse count. This solution ensures the accuracy and consistency of the synchronization trigger time of the dual-channel software operation cycle. However, in actual application environments, the operating environment of electronic systems is often complex and changeable. The end time of the software cycle of the redundant channel of the electronic system will have a certain degree of volatility due to environmental reasons. The hardwired synchronization solution cannot solve the problem of redundant channel software cycle fluctuations. In long-term operation scenarios, it is easy to cause the system to crash because the software operation cycle exceeds the synchronization cycle regularly triggered by the hardwire. Summary of the invention

[0006] The purpose of the embodiments of the present invention is to provide a redundant channel software cycle synchronization method and system that meet functional safety requirements. The method and system can overcome the defects of the commonly used synchronization methods in the prior art.

[0007] In order to achieve the above object, an embodiment of the present invention provides a redundant channel software cycle synchronization method that meets functional safety requirements, including:

[0008] Obtaining the first signal to be synchronized, the second signal, the internal clock and the delay value of the previous cycle;

[0009] Determine a first time point and a second time point according to the first signal and the second signal;

[0010] The first output signal and the second output signal, the delay value of the next cycle, the first reset signal and the second reset signal are determined according to the first time point, the second time point, the internal clock and the delay value of the previous cycle.

[0011] Optionally, the first time point is the end time of a cycle of an input signal of a CH1 channel, and the second time point is the end time of a cycle of an input signal of a CH2 channel.

[0012] Optionally, determining the first output signal and the second output signal, the delay value of the next cycle, the first reset signal and the second reset signal according to the first time point, the second time point, the internal clock and the delay value of the previous cycle includes:

[0013] When the second time point is greater than the first time point, and the first time point is greater than the sum of the internal clock and a preset maximum tolerance value, determining the time difference to be a first preset value;

[0014] Determine the delay value of the next cycle as the sum of the internal clock and the first preset value;

[0015] Determine the first output signal as the sum of the internal clock and the delay value of the previous cycle;

[0016] Determine the second output signal as the sum of the internal clock and the delay value of the previous cycle;

[0017] determining the first reset signal to be a value of an internal self-test result;

[0018] determining the second reset signal to be a value of the internal self-test result;

[0019] When it is determined that the first time point is greater than the internal clock and less than the sum of the internal clock and a preset maximum tolerance value, and the second time point is greater than the sum of the internal clock and the maximum tolerance value, the time difference is calculated according to the following formula (1):

[0020] , (1)

[0021] in, is the time difference, is the internal clock, is the first time point;

[0022] Determine the delay value of the next cycle as the sum of the internal clock and the time difference;

[0023] Determine the first output signal as the sum of the internal clock and the delay value of the previous cycle;

[0024] Determine the second output signal as the sum of the internal clock and the delay value of the previous cycle;

[0025] Determining the first reset signal as a second preset value;

[0026] determining the second reset signal to be the second preset value;

[0027] When it is determined that the first time point is greater than the internal clock, the second time point is greater than the first time point, and the second time point is less than the sum of the internal clock and a preset maximum tolerance value, the time difference is calculated according to the following formula (2):

[0028] , (2)

[0029] in, is the time difference, is the internal clock, is the first time point, is the second time point;

[0030] Determine the delay value of the next cycle as the sum of the internal clock and the time difference;

[0031] Determine the first output signal as the sum of the internal clock and the delay value of the previous cycle;

[0032] Determine the second output signal as the sum of the internal clock and the delay value of the previous cycle;

[0033] Determining the first reset signal as a second preset value;

[0034] The second reset signal is determined to be the second preset value.

[0035] Optionally, determining the first output signal and the second output signal, the delay value of the next cycle, the first reset signal and the second reset signal according to the first time point, the second time point, the internal clock and the delay value of the previous cycle includes:

[0036] In the case where it is determined that the first time point is less than the difference between the internal clock and a preset maximum tolerance value, and the second time point is greater than the sum of the internal clock and the maximum tolerance value, determining the time difference as a first preset value;

[0037] Determine the delay value of the next cycle as the sum of the internal clock and the time difference;

[0038] Determine the first output signal as the sum of the internal clock and the delay value of the previous cycle;

[0039] Determine the second output signal as the sum of the internal clock and the delay value of the previous cycle;

[0040] Determining the first reset signal as a second preset value;

[0041] determining the second reset signal to be the second preset value;

[0042] When it is determined that the first time point is less than the difference between the internal clock and the preset maximum tolerance value, and the second time point is greater than the internal clock, and the second time point is less than the sum of the internal clock and the maximum tolerance value, the time difference is calculated according to the following formula (3):

[0043] , (3)

[0044] in, is the time difference, is the internal clock, is the second time point;

[0045] Determine the delay value of the next cycle as the sum of the internal clock and the time difference;

[0046] Determine the first output signal as the sum of the internal clock and the delay value of the previous cycle;

[0047] Determine the second output signal as the sum of the internal clock and the delay value of the previous cycle;

[0048] Determining the first reset signal as a second preset value;

[0049] determining the second reset signal to be the second preset value;

[0050] When it is determined that the first time point is greater than the difference between the internal clock and a preset maximum tolerance value, and the first time point is less than the internal clock, and the second time point is greater than the sum of the internal clock and the maximum tolerance value, the time difference is calculated according to formula (4):

[0051] , (4)

[0052] in, is the time difference, is the internal clock, is the first time point;

[0053] Determine the delay value of the next cycle as the sum of the internal clock and the time difference;

[0054] Determine the first output signal as the sum of the internal clock and the delay value of the previous cycle;

[0055] Determine the second output signal as the sum of the internal clock and the delay value of the previous cycle;

[0056] Determining the first reset signal as a second preset value;

[0057] determining the second reset signal to be the second preset value;

[0058] When it is determined that the first time point is greater than the difference between the internal clock and a preset maximum tolerance value, the first time point is less than the internal clock, and the second time point is greater than the internal clock, and the second time point is less than the sum of the internal clock and the maximum tolerance value, the time difference is calculated according to formula (5):

[0059] , (5)

[0060] in, is the time difference, is the internal clock, is the first time point, is the second time point;

[0061] Determine the delay value of the next cycle as the sum of the internal clock and the time difference;

[0062] Determine the first output signal as the sum of the internal clock and the delay value of the previous cycle;

[0063] Determine the second output signal as the sum of the internal clock and the delay value of the previous cycle;

[0064] Determining the first reset signal as a second preset value;

[0065] The second reset signal is determined to be the second preset value.

[0066] Optionally, determining the first output signal and the second output signal, the delay value of the next cycle, the first reset signal and the second reset signal according to the first time point, the second time point, the internal clock and the delay value of the previous cycle includes:

[0067] In the case where it is determined that the first time point is less than the second time point, and the second time point is less than the difference between the internal clock and a preset maximum tolerance value, determining the time difference as a first preset value;

[0068] Determine the delay value of the next cycle as the sum of the internal clock and the time difference;

[0069] Determine the first output signal as the sum of the internal clock and the delay value of the previous cycle;

[0070] Determine the second output signal as the sum of the internal clock and the delay value of the previous cycle;

[0071] Determining the first reset signal as a second preset value;

[0072] determining the second reset signal to be the second preset value;

[0073] When it is determined that the first time point is less than the difference between the internal clock and a preset maximum tolerance value, and the second time point is greater than the difference between the internal clock and the maximum tolerance value, and the second time point is less than the internal clock, the time difference is calculated according to the following formula (6):

[0074] , (6)

[0075] in, is the time difference, is the internal clock, is the second time point;

[0076] Determine the delay value of the next cycle as the sum of the internal clock and the time difference;

[0077] Determine the first output signal as the sum of the internal clock and the delay value of the previous cycle;

[0078] Determine the second output signal as the sum of the internal clock and the delay value of the previous cycle;

[0079] Determining the first reset signal as a second preset value;

[0080] determining the second reset signal to be the second preset value;

[0081] When it is determined that the first time point is greater than the difference between the internal clock and the preset maximum tolerance value, the second time point is greater than the first time point, and the second time point is less than the internal clock, the time difference is calculated according to the following formula (7):

[0082] , (7)

[0083] in, is the time difference, is the internal clock, is the first time point, is the second time point;

[0084] Determine the delay value of the next cycle as the sum of the internal clock and the time difference;

[0085] Determine the first output signal as the sum of the internal clock and the delay value of the previous cycle;

[0086] Determine the second output signal as the sum of the internal clock and the delay value of the previous cycle;

[0087] Determining the first reset signal as a second preset value;

[0088] The second reset signal is determined to be the second preset value.

[0089] Optionally, determining the first output signal and the second output signal, the delay value of the next cycle, the first reset signal and the second reset signal according to the first time point, the second time point, the internal clock and the delay value of the previous cycle includes:

[0090] In the case where it is determined that the second time point is greater than the sum of the internal clock and a preset maximum tolerance value, and the first time point is greater than the second time point, determining the time difference as a first preset value;

[0091] Determine the delay value of the next cycle as the sum of the internal clock and the time difference;

[0092] Determine the first output signal as the sum of the internal clock and the delay value of the previous cycle;

[0093] Determine the second output signal as the sum of the internal clock and the delay value of the previous cycle;

[0094] Determining the first reset signal as a second preset value;

[0095] determining the second reset signal to be the second preset value;

[0096] When it is determined that the second time point is greater than the internal clock, and the second time point is less than the sum of the internal clock and a preset maximum tolerance value, and the first time point is greater than the sum of the internal clock and the maximum tolerance value, the time difference is calculated according to formula (8):

[0097] , (8)

[0098] in, is the time difference, is the internal clock, is the first time point;

[0099] Determine the delay value of the next cycle as the sum of the internal clock and the time difference;

[0100] Determine the first output signal as the sum of the internal clock and the delay value of the previous cycle;

[0101] Determine the second output signal as the sum of the internal clock and the delay value of the previous cycle;

[0102] Determining the first reset signal as a second preset value;

[0103] determining the second reset signal to be the second preset value;

[0104] When it is determined that the second time point is greater than the internal clock, the first time point is greater than the second time point, and the first time point is less than the sum of the internal clock and a preset maximum tolerance value, the time difference is calculated according to formula (9):

[0105] , (9)

[0106] in, is the time difference, is the internal clock, is the first time point, is the second time point;

[0107] Determine the delay value of the next cycle as the sum of the internal clock and the time difference;

[0108] Determine the first output signal as the sum of the internal clock and the delay value of the previous cycle;

[0109] Determine the second output signal as the sum of the internal clock and the delay value of the previous cycle;

[0110] Determining the first reset signal as a second preset value;

[0111] The second reset signal is determined to be the second preset value.

[0112] Optionally, determining the first output signal and the second output signal, the delay value of the next cycle, the first reset signal and the second reset signal according to the first time point, the second time point, the internal clock and the delay value of the previous cycle includes:

[0113] In the case where it is determined that the second time point is less than the difference between the internal clock and a preset maximum tolerance value, and the first time point is greater than the sum of the internal clock and the maximum tolerance value, the time difference is determined as a first preset value;

[0114] Determine the delay value of the next cycle as the sum of the internal clock and the time difference;

[0115] Determine the first output signal as the sum of the internal clock and the delay value of the previous cycle;

[0116] Determine the second output signal as the sum of the internal clock and the delay value of the previous cycle;

[0117] Determining the first reset signal as a second preset value;

[0118] determining the second reset signal to be the second preset value;

[0119] When it is determined that the second time point is less than the difference between the internal clock and a preset maximum tolerance value, the first time point is greater than the internal clock, and the first time point is less than the difference between the internal clock and the maximum tolerance value, the time difference is calculated according to the following formula (10):

[0120] , (10)

[0121] in, is the time difference, is the internal clock, is the first time point;

[0122] Determine the delay value of the next cycle as the sum of the internal clock and the time difference;

[0123] Determine the first output signal as the sum of the internal clock and the delay value of the previous cycle;

[0124] Determine the second output signal as the sum of the internal clock and the delay value of the previous cycle;

[0125] Determining the first reset signal as a second preset value;

[0126] determining the second reset signal to be the second preset value;

[0127] When it is determined that the second time point is greater than the difference between the internal clock and a preset maximum tolerance value, the second time point is less than the internal clock, and the first time point is greater than the sum of the internal clock and the maximum tolerance value, the time difference is calculated according to formula (11):

[0128] , (11)

[0129] in, is the time difference, is the internal clock, is the second time point;

[0130] Determine the delay value of the next cycle as the sum of the internal clock and the time difference;

[0131] Determine the first output signal as the sum of the internal clock and the delay value of the previous cycle;

[0132] Determine the second output signal as the sum of the internal clock and the delay value of the previous cycle;

[0133] Determining the first reset signal as a second preset value;

[0134] determining the second reset signal to be the second preset value;

[0135] When it is determined that the second time point is greater than the difference between the internal clock and a preset maximum tolerance value, the second time point is less than the internal clock, the first time point is greater than the internal clock, and the first time point is less than the sum of the internal clock and the maximum tolerance value, the time difference is calculated according to the following formula (12):

[0136] , (12)

[0137] in, is the time difference, is the internal clock, is the first time point, is the second time point;

[0138] Determine the delay value of the next cycle as the sum of the internal clock and the time difference;

[0139] Determine the first output signal as the sum of the internal clock and the delay value of the previous cycle;

[0140] Determine the second output signal as the sum of the internal clock and the delay value of the previous cycle;

[0141] Determining the first reset signal as a second preset value;

[0142] The second reset signal is determined to be the second preset value.

[0143] Optionally, determining the first output signal and the second output signal, the delay value of the next cycle, the first reset signal and the second reset signal according to the first time point, the second time point, the internal clock and the delay value of the previous cycle includes:

[0144] In the case where it is determined that the second time point is less than the first time point, and the first time point is less than the difference between the internal clock and a preset maximum tolerance value, determining the time difference as a first preset value;

[0145] Determine the delay value of the next cycle as the sum of the internal clock and the time difference;

[0146] Determine the first output signal as the sum of the internal clock and the delay value of the previous cycle;

[0147] Determine the second output signal as the sum of the internal clock and the delay value of the previous cycle;

[0148] Determining the first reset signal as a second preset value;

[0149] determining the second reset signal to be the second preset value;

[0150] When it is determined that the second time point is less than the difference between the internal clock and a preset maximum tolerance value, the first time point is greater than the difference between the internal clock and the maximum tolerance value, and the first time point is less than the internal clock, the time difference is calculated according to formula (13):

[0151] , (13)

[0152] in, is the time difference, is the internal clock, is the first time point;

[0153] Determine the delay value of the next cycle as the sum of the internal clock and the time difference;

[0154] Determine the first output signal as the sum of the internal clock and the delay value of the previous cycle;

[0155] Determine the second output signal as the sum of the internal clock and the delay value of the previous cycle;

[0156] Determining the first reset signal as a second preset value;

[0157] determining the second reset signal to be the second preset value;

[0158] When it is determined that the second time point is greater than the difference between the internal clock and the preset maximum tolerance value, the first time point is greater than the second time point, and the first time point is less than the internal clock, the time difference is calculated according to formula (14):

[0159] , (9)

[0160] in, is the time difference, is the internal clock, is the first time point, is the second time point;

[0161] Determine the delay value of the next cycle as the sum of the internal clock and the time difference;

[0162] Determine the first output signal as the sum of the internal clock and the delay value of the previous cycle;

[0163] Determine the second output signal as the sum of the internal clock and the delay value of the previous cycle;

[0164] Determining the first reset signal as a second preset value;

[0165] The second reset signal is determined to be the second preset value.

[0166] On the other hand, the present invention further provides a redundant channel software cycle synchronization system that meets functional safety requirements. The system includes a processor, and the processor is configured to execute any of the methods described above.

[0167] In another aspect, the present invention further provides a redundant channel software cycle synchronization system that meets functional safety requirements, the synchronization system comprising:

[0168] CH1 input port, used to obtain the first signal;

[0169] CH2 input port, used to obtain the second signal;

[0170] DIAG component, used to generate configuration parameters;

[0171] A register component, used to store the configuration parameters;

[0172] PLL components and timers for generating internal clocks;

[0173] A delay register, used to store a delay value;

[0174] An arbitration component, used to execute any of the above methods;

[0175] CH1 output port, used for outputting a first output signal;

[0176] CH2 output port, used to output the second output signal.

[0177] Through the above technical scheme, the implementation mode of the present invention provides a redundant channel software cycle synchronization method and system that meets the functional safety requirements. The method and system combine the impact of the environment on the software. When calculating the synchronization time point of the next cycle of the software, the cycle end time of the redundant channel and the self-test result of the cycle synchronizer are combined to calculate the starting time point of the next cycle of the software, thereby enhancing the reliability and robustness of the system operation.

[0178] Other features and advantages of the embodiments of the present invention will be described in detail in the subsequent detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0179] The accompanying drawings are used to provide a further understanding of the embodiments of the present invention and constitute a part of the specification. Together with the following specific implementations, they are used to explain the embodiments of the present invention, but do not constitute a limitation on the embodiments of the present invention. In the accompanying drawings:

[0180] Figure 1 is a flow chart of a redundant channel software cycle synchronization method that meets functional safety requirements according to an embodiment of the present invention;

[0181] Figure 2 is a structural block diagram of a redundant channel software cycle synchronization system that meets functional safety requirements according to an embodiment of the present invention;

[0182] Figure 3 is one of the example diagrams of the relative relationship between the flag bit SYN signal and the first time point, the second time point, the internal clock, and the maximum tolerance value according to an embodiment of the present invention;

[0183] Figure 4 This is a second example diagram of the relative relationship between the flag bit SYN signal and the first time point, the second time point, the internal clock, and the maximum tolerance value according to an embodiment of the present invention;

[0184] Figure 5 is a third example diagram of the relative relationship between the flag bit SYN signal and the first time point, the second time point, the internal clock, and the maximum tolerance value according to an embodiment of the present invention;

[0185] Figure 6 It is a schematic diagram of the magnitude relationship between a first time point, a second time point, and an internal clock according to an embodiment of the present invention. DETAILED DESCRIPTION

[0186] The specific implementation of the embodiment of the present invention is described in detail below in conjunction with the accompanying drawings. It should be understood that the specific implementation described here is only used to illustrate and explain the embodiment of the present invention, and is not used to limit the embodiment of the present invention.

[0187] like Figure 1 FIG. 1 is a flowchart of a redundant channel software cycle synchronization method that meets functional safety requirements according to an embodiment of the present invention. Figure 1 In the method, the method may include the following steps:

[0188] In step S10, the first signal to be synchronized, the second signal, the internal clock and the delay value of the previous cycle are obtained;

[0189] In step S11, a first time point and a second time point are determined according to the first signal and the second signal;

[0190] In step S12, the first output signal and the second output signal, the delay value of the next cycle, the first reset signal and the second reset signal are determined according to the first time point, the second time point, the internal clock and the delay value of the previous cycle.

[0191] In this Figure 1 In the method shown, the first signal and the second signal are two groups of signals to be synchronized, and the first output signal and the second output signal are two groups of signals after the synchronization period. The two groups of signals are used for signal transmission and interaction inside the electronic device. The first reset signal and the second reset signal are used to perform a reset operation when the delay between the two groups of signals is too large.

[0192] In this Figure 1 In the method shown, step S10 can be used to obtain the first signal to be synchronized, the second signal, the internal clock and the delay value of the previous cycle. In this embodiment, the first signal can be the input signal of the CH1 input port. The second signal can be the input signal of the CH2 input port. The internal clock can be generated by the PLL component and the timer. The delay value of the previous cycle can be stored by the delay register. The connection relationship between the CH1 input port, the CH2 input port, the PLL component, the timer, and the delay register can be as follows Figure 2 shown.

[0193] Step S11 can be used to determine a first time point and a second time point according to the first signal and the second signal. In this embodiment, when the first signal is an input signal of the CH1 input port and the second signal is an input signal of the CH2 input port, the first time point can be the cycle end time of the input signal of the CH1 channel. The second time point can be the cycle end time of the input signal of the CH2 channel.

[0194] Step S12 can be used to determine the first output signal and the second output signal, the delay value of the next cycle, the first reset signal and the second reset signal according to the first time point, the second time point, the internal clock and the delay value of the previous cycle.

[0195] In this embodiment, in order to ensure that the first output signal, the second output signal, the delay value, the first reset signal and the second reset signal can be dynamically adjusted according to the changes of the first time point, the second time point and the internal clock, the various relative size relationships of the first time point, the second time point and the internal clock can be analyzed separately, and each relative size relationship can be combined to generate the corresponding first output signal, the second output signal, the delay value, the first reset signal and the second reset signal.

[0196] Before determining the first output signal, the second output signal, the delay value, the first reset signal and the second reset signal, the relative relationship between the flag SYN signal of each cycle and the first time point, the second time point, the internal clock and the maximum tolerance value can be analyzed to determine the size relationship between the first time point, the second time point and the internal clock.

[0197] Specifically, Figure 3 As shown, the second flag SYN signal is taken as an example. The SYN signal arrives earlier than the first time point T1 and the second time point T2. At this time, if the maximum tolerance value can be If the current cycle task is completed within the time limit, the next cycle task will start immediately. If the maximum tolerance value after CH1 input interface 01 and / or CH2 input interface 02 receives the SYN signal If the task is not completed within the time limit, the timed-out channel (CH1 input interface 01, CH1 output interface 09 and / or CH2 input interface 02, CH2 output port 10) enters the safe state.

[0198] Then Figure 3 Take the third flag SYN signal in as an example. The SYN signal arrives later than the first time point T1 and the second time point T2, then the CH1 input interface 01 and the CH2 input interface 02 start timing after sending the T1 and T2 signals. If the SYN signal is received within the specified time, the next cycle task will start immediately. If the task is not completed within the specified time, the timed-out channel (CH1 input interface 01, CH1 output interface 09 and / or CH2 input interface 02, CH2 output port 10) enters the safe state.

[0199] In this embodiment, it is also possible to Figure 4 The third flag bit SYN signal shown in is taken as an example. The second time point T2 is later than It appears that the maximum tolerance value is exceeded Therefore, the CH2 input interface 02 and the CH2 output port 10 enter a safe state and the cycle synchronizer can also send a RESET2 signal to the CH2 input interface 02 and the CH2 output port 10 to ensure that the CH2 input interface 02 and the CH2 output port 10 enter a safe state, and at the same time reset and restart the CH2 input interface 02 and the CH2 output port 10 to increase system availability.

[0200] In this embodiment, it is also possible to Figure 5Take the second flag SYN signal shown in as an example. The first time point T1 exceeds the lower limit of the maximum tolerance value, so the CH2 input interface 02 and the CH2 output port 10 enter the safe state and the cycle synchronizer also sends a RESET1 signal to the CH1 input interface 01 and the CH1 output interface 09 to ensure that the CH1 input interface 01 and the CH1 output interface 09 enter the safe state, and at the same time, the CH1 input interface 01 and the CH1 output interface 09 are reset and restarted to increase system availability.

[0201] In this implementation, the magnitude relationship between the first time point, the second time point, and the internal clock can be divided into the following: Figure 6 Specifically, for these 20 different situations, step S12 may further include the following steps:

[0202] When the second time point is greater than the first time point, and the first time point is greater than the sum of the internal clock and the preset maximum tolerance value, the time difference can be determined to be the first preset value, the delay value of the next cycle can be determined to be the sum of the internal clock and the first preset value, the first output signal can be determined to be the sum of the internal clock and the delay value of the previous cycle, the second output signal can be determined to be the sum of the internal clock and the delay value of the previous cycle, the first reset signal can be determined to be the value of the internal self-test result, and the second reset signal can be determined to be the value of the internal self-test result. Among them, the specific numerical value of the first preset value can be a variety known to those skilled in the art. In this example, the first preset value can be 0. Based on this, the situation can also be expressed by the following formula:

[0203] if ;

[0204] So, , , ;

[0205] in, is the time difference, is the internal clock, is the maximum tolerance value, For the first time point, For the second time point, This is the result of internal self-test. is the first output signal, is the second output signal.

[0206] When it is determined that the first time point is greater than the internal clock and less than the sum of the internal clock and the preset maximum tolerance value, and the second time point is greater than the sum of the internal clock and the maximum tolerance value, the time difference is calculated according to the following formula (1):

[0207] , (1)

[0208] in, is the time difference, is the internal clock, For the first time point, the delay value of the next cycle is determined as the sum of the internal clock and the time difference, the first output signal is determined as the sum of the internal clock and the delay value of the previous cycle, the second output signal is determined as the sum of the internal clock and the delay value of the previous cycle, the first reset signal is determined as the second preset value, and the second reset signal is determined as the second preset value. Among them, the specific value of the second preset value can be a variety known to those skilled in the art. In this example, the second preset value can be 1. Based on this, the situation can also be expressed by the following formula:

[0209] if ;

[0210] So , , , .

[0211] When it is determined that the first time point is greater than the internal clock, the second time point is greater than the first time point, and the second time point is less than the sum of the internal clock and the preset maximum tolerance value, the time difference is calculated according to the following formula (2):

[0212] , (2)

[0213] in, is the time difference, is the internal clock, For the first time point, For the second time point, the delay value of the next cycle is determined as the sum of the internal clock and the time difference, the first output signal is determined as the sum of the internal clock and the delay value of the previous cycle, the second output signal is determined as the sum of the internal clock and the delay value of the previous cycle, the first reset signal is determined as the second preset value, and the second reset signal is determined as the second preset value. Based on this, the situation can also be expressed by the following formula:

[0214] if ;

[0215] So , , , .

[0216] When it is determined that the first time point is less than the difference between the internal clock and the preset maximum tolerance value, and the second time point is greater than the sum of the internal clock and the maximum tolerance value, the time difference is determined as the first preset value, the delay value of the next cycle is determined as the sum of the internal clock and the time difference, the first output signal is determined as the sum of the internal clock and the delay value of the previous cycle, the second output signal is determined as the sum of the internal clock and the delay value of the previous cycle, the first reset signal is determined as the second preset value, and the second reset signal is determined as the second preset value. Based on this, the situation can also be expressed by the following formula:

[0217] if ;

[0218] So , , , .

[0219] When it is determined that the first time point is less than the difference between the internal clock and the preset maximum tolerance value, and the second time point is greater than the internal clock, and the second time point is less than the sum of the internal clock and the maximum tolerance value, the time difference is calculated according to the following formula (3):

[0220] , (3)

[0221] in, is the time difference, is the internal clock, For the second time point, the delay value of the next cycle is determined as the sum of the internal clock and the time difference, the first output signal is determined as the sum of the internal clock and the delay value of the previous cycle, the second output signal is determined as the sum of the internal clock and the delay value of the previous cycle, the first reset signal is determined as the second preset value, and the second reset signal is determined as the second preset value. Based on this, the situation can also be expressed by the following formula:

[0222] if ;

[0223] So , , , .

[0224] When it is determined that the first time point is greater than the difference between the internal clock and the preset maximum tolerance value, and the first time point is less than the internal clock, and the second time point is greater than the sum of the internal clock and the maximum tolerance value, the time difference is calculated according to formula (4):

[0225] , (4)

[0226] in, is the time difference, is the internal clock, For the first time point, the delay value of the next cycle is determined as the sum of the internal clock and the time difference, the first output signal is determined as the sum of the internal clock and the delay value of the previous cycle, the second output signal is determined as the sum of the internal clock and the delay value of the previous cycle, the first reset signal is determined as the second preset value, and the second reset signal is determined as the second preset value. Based on this, the situation can also be expressed by the following formula:

[0227] if ;

[0228] So , , , .

[0229] When it is determined that the first time point is greater than the difference between the internal clock and the preset maximum tolerance value, the first time point is less than the internal clock, and the second time point is greater than the internal clock, and the second time point is less than the sum of the internal clock and the maximum tolerance value, the time difference is calculated according to formula (5):

[0230] , (5)

[0231] in, is the time difference, is the internal clock, For the first time point, For the second time point, the delay value of the next cycle is determined as the sum of the internal clock and the time difference, the first output signal is determined as the sum of the internal clock and the delay value of the previous cycle, the second output signal is determined as the sum of the internal clock and the delay value of the previous cycle, the first reset signal is determined as the second preset value, and the second reset signal is determined as the second preset value. Based on this, the situation can also be expressed by the following formula:

[0232] if ;

[0233] So , , , .

[0234] When it is determined that the first time point is less than the second time point, and the second time point is less than the difference between the internal clock and the preset maximum tolerance value, the time difference is determined as the first preset value, the delay value of the next cycle is determined as the sum of the internal clock and the time difference, the first output signal is determined as the sum of the internal clock and the delay value of the previous cycle, the second output signal is determined as the sum of the internal clock and the delay value of the previous cycle, the first reset signal is determined as the second preset value, and the second reset signal is determined as the second preset value. Based on this, the situation can also be expressed by the following formula:

[0235] if ;

[0236] So , , , .

[0237] When it is determined that the first time point is less than the difference between the internal clock and the preset maximum tolerance value, and the second time point is greater than the difference between the internal clock and the maximum tolerance value, and the second time point is less than the internal clock, the time difference is calculated according to the following formula (6):

[0238] , (6)

[0239] in, is the time difference, is the internal clock, For the second time point, the delay value of the next cycle is determined as the sum of the internal clock and the time difference, the first output signal is determined as the sum of the internal clock and the delay value of the previous cycle, the second output signal is determined as the sum of the internal clock and the delay value of the previous cycle, the first reset signal is determined as the second preset value, and the second reset signal is determined as the second preset value. Based on this, the situation can also be expressed by the following formula:

[0240] if ;

[0241] So , , , .

[0242] When it is determined that the first time point is greater than the difference between the internal clock and the preset maximum tolerance value, the second time point is greater than the first time point, and the second time point is less than the internal clock, the time difference is calculated according to the following formula (7):

[0243] , (7)

[0244] in, is the time difference, is the internal clock, For the first time point, For the second time point, the delay value of the next cycle is determined as the sum of the internal clock and the time difference, the first output signal is determined as the sum of the internal clock and the delay value of the previous cycle, the second output signal is determined as the sum of the internal clock and the delay value of the previous cycle, the first reset signal is determined as the second preset value, and the second reset signal is determined as the second preset value. Based on this, the situation can also be expressed by the following formula:

[0245] if ;

[0246] So , , , .

[0247] When it is determined that the second time point is greater than the sum of the internal clock and the preset maximum tolerance value, and the first time point is greater than the second time point, the time difference is determined to be the first preset value, the delay value of the next cycle is determined to be the sum of the internal clock and the time difference, the first output signal is determined to be the sum of the internal clock and the delay value of the previous cycle, the second output signal is determined to be the sum of the internal clock and the delay value of the previous cycle, the first reset signal is determined to be the second preset value, and the second reset signal is determined to be the second preset value. Based on this, the situation can also be expressed by the following formula:

[0248] if ;

[0249] So , , , .

[0250] When it is determined that the second time point is greater than the internal clock, and the second time point is less than the sum of the internal clock and the preset maximum tolerance value, and the first time point is greater than the sum of the internal clock and the maximum tolerance value, the time difference is calculated according to formula (8):

[0251] , (8)

[0252] in, is the time difference, is the internal clock, For the first time point, the delay value of the next cycle is determined as the sum of the internal clock and the time difference, the first output signal is determined as the sum of the internal clock and the delay value of the previous cycle, the second output signal is determined as the sum of the internal clock and the delay value of the previous cycle, the first reset signal is determined as the second preset value, and the second reset signal is determined as the second preset value. Based on this, the situation can also be expressed by the following formula:

[0253] if ;

[0254] So , , , .

[0255] When it is determined that the second time point is greater than the internal clock, the first time point is greater than the second time point, and the first time point is less than the sum of the internal clock and the preset maximum tolerance value, the time difference is calculated according to formula (9):

[0256] , (9)

[0257] in, is the time difference, is the internal clock, For the first time point, For the second time point, the delay value of the next cycle is determined as the sum of the internal clock and the time difference, the first output signal is determined as the sum of the internal clock and the delay value of the previous cycle, the second output signal is determined as the sum of the internal clock and the delay value of the previous cycle, the first reset signal is determined as the second preset value, and the second reset signal is determined as the second preset value. Based on this, the situation can also be expressed by the following formula:

[0258] if ;

[0259] So , , , .

[0260] When it is determined that the second time point is less than the difference between the internal clock and the preset maximum tolerance value, and the first time point is greater than the sum of the internal clock and the maximum tolerance value, the time difference is determined as the first preset value, the delay value of the next cycle is determined as the sum of the internal clock and the time difference, the first output signal is determined as the sum of the internal clock and the delay value of the previous cycle, the second output signal is determined as the sum of the internal clock and the delay value of the previous cycle, the first reset signal is determined as the second preset value, and the second reset signal is determined as the second preset value. Based on this, the situation can also be expressed by the following formula:

[0261] if ;

[0262] So , , , .

[0263] When it is determined that the second time point is less than the difference between the internal clock and the preset maximum tolerance value, the first time point is greater than the internal clock, and the first time point is less than the difference between the internal clock and the maximum tolerance value, the time difference is calculated according to the following formula (10):

[0264] , (10)

[0265] in, is the time difference, is the internal clock, For the first time point, the delay value of the next cycle is determined as the sum of the internal clock and the time difference, the first output signal is determined as the sum of the internal clock and the delay value of the previous cycle, the second output signal is determined as the sum of the internal clock and the delay value of the previous cycle, the first reset signal is determined as the second preset value, and the second reset signal is determined as the second preset value. Based on this, the situation can also be expressed by the following formula:

[0266] if ;

[0267] So , , , .

[0268] When it is determined that the second time point is greater than the difference between the internal clock and the preset maximum tolerance value, the second time point is less than the internal clock, and the first time point is greater than the sum of the internal clock and the maximum tolerance value, the time difference is calculated according to formula (11):

[0269] , (11)

[0270] in, is the time difference, is the internal clock, For the second time point, the delay value of the next cycle is determined as the sum of the internal clock and the time difference, the first output signal is determined as the sum of the internal clock and the delay value of the previous cycle, the second output signal is determined as the sum of the internal clock and the delay value of the previous cycle, the first reset signal is determined as the second preset value, and the second reset signal is determined as the second preset value. Based on this, the situation can also be expressed by the following formula:

[0271] if ;

[0272] So , , , .

[0273] When it is determined that the second time point is greater than the difference between the internal clock and the preset maximum tolerance value, the second time point is less than the internal clock, the first time point is greater than the internal clock, and the first time point is less than the sum of the internal clock and the maximum tolerance value, the time difference is calculated according to the following formula (12):

[0274] , (12)

[0275] in, is the time difference, is the internal clock, For the first time point, For the second time point, the delay value of the next cycle is determined as the sum of the internal clock and the time difference, the first output signal is determined as the sum of the internal clock and the delay value of the previous cycle, the second output signal is determined as the sum of the internal clock and the delay value of the previous cycle, the first reset signal is determined as the second preset value, and the second reset signal is determined as the second preset value. Based on this, the situation can also be expressed by the following formula:

[0276] if ;

[0277] So , , , .

[0278] When it is determined that the second time point is less than the first time point, and the first time point is less than the difference between the internal clock and the preset maximum tolerance value, the time difference is determined as the first preset value, the delay value of the next cycle is determined as the sum of the internal clock and the time difference, the first output signal is determined as the sum of the internal clock and the delay value of the previous cycle, the second output signal is determined as the sum of the internal clock and the delay value of the previous cycle, the first reset signal is determined as the second preset value, and the second reset signal is determined as the second preset value. Based on this, the situation can also be expressed by the following formula:

[0279] if ;

[0280] So , , , .

[0281] When it is determined that the second time point is less than the difference between the internal clock and the preset maximum tolerance value, the first time point is greater than the difference between the internal clock and the maximum tolerance value, and the first time point is less than the internal clock, the time difference is calculated according to formula (13):

[0282] , (13)

[0283] in, is the time difference, is the internal clock, For the first time point, the delay value of the next cycle is determined as the sum of the internal clock and the time difference, the first output signal is determined as the sum of the internal clock and the delay value of the previous cycle, the second output signal is determined as the sum of the internal clock and the delay value of the previous cycle, the first reset signal is determined as the second preset value, and the second reset signal is determined as the second preset value. Based on this, the situation can also be expressed by the following formula:

[0284] if ;

[0285] So , , , .

[0286] When it is determined that the second time point is greater than the difference between the internal clock and the preset maximum tolerance value, the first time point is greater than the second time point, and the first time point is less than the internal clock, the time difference is calculated according to formula (14):

[0287] , (9)

[0288] in, is the time difference, is the internal clock, For the first time point, For the second time point, the delay value of the next cycle is determined as the sum of the internal clock and the time difference, the first output signal is determined as the sum of the internal clock and the delay value of the previous cycle, the second output signal is determined as the sum of the internal clock and the delay value of the previous cycle, the first reset signal is determined as the second preset value, and the second reset signal is determined as the second preset value. Based on this, the situation can also be expressed by the following formula:

[0289] if ;

[0290] So , , , .

[0291] On the other hand, the present invention further provides a redundant channel software cycle synchronization system that meets functional safety requirements. The system includes a processor, and the processor is configured to execute any of the methods described above.

[0292] In another aspect, the present invention further provides a redundant channel software cycle synchronization system that meets functional safety requirements, such as Figure 2As shown, the synchronization system may include a CH1 input port 01, a CH2 input port 02, a DIAG component 03, a register component 04, a PLL component 05, a timer 06, a delay register 07, an arbitration component 08, a CH1 output port 09, and a CH2 output port 10. Among them, the CH1 input port 01 can be used to obtain a first signal. The CH2 input port 02 can be used to obtain a second signal. The DIAG component 03 can be used to generate configuration parameters. The register component 04 can be used to store configuration parameters. The PLL component 05 and the timer 06 can be used to generate an internal clock. The delay register 07 can be used to store a delay value. The arbitration component 08 can be used to execute any of the methods described above. The CH1 output port 09 can be used to output a first output signal. The CH2 output port 10 can be used to output a second output signal.

[0293] In one embodiment of the present invention, in order to ensure that Figure 2 The synchronization system shown can work accurately, and the synchronization system can also be preset with a periodic synchronizer self-test method. The periodic synchronizer self-test method can be managed by the DIAG component 03. After the arbitration component 08 sends the self-test command to the outside, the DIAG component 03 starts to initiate a self-test command to the surrounding components. Specifically, the self-test method can include the following steps:

[0294] Step 1: Send self-test commands to the register component 04, the PLL component 05, the timer 06, the arbitration component 08, and the delay register 07 respectively, and control the DIAG component 03 itself to enter the self-test mode;

[0295] Step 2: The register component 04, the PLL component 05, the timer 06, the arbitration component 08, the delay register 07, and the DIAG component 03 respectively perform self-test operations, and summarize the self-test results to the DIAG component 03, thereby generating an internal self-test result.

[0296] The specific self-test methods for the register component 04, the PLL component 05, the timer 06, the arbitration component 08, the delay register 07, and the DIAG component 03 may be in various forms known to those skilled in the art. In one example of the present invention, the self-test method may further include the following steps:

[0297] Step 1-1: Register component 04, PLL component 05, timer 06, arbitration component 08, delay register 07, and DIAG component 03 enter self-test mode respectively, and the external input and output are set to high impedance state;

[0298] Step 1-2: Perform self-test on each internally configured register in turn. When each register is detected, the register content will be copied to a blank register of the same size, and then 0xAA will be written to the detected register and then read out to check consistency. If it is consistent, 0x55 will be written and then read out to check consistency. If the test passes, the copied content will be copied back, and all storage addresses will be tested in a loop;

[0299] Step 1-3: Simulate all external input data to the internal input interface and then detect whether the internal output logic meets the requirements to determine whether the processing logic self-test passes.

[0300] Through the above technical scheme, the implementation mode of the present invention provides a redundant channel software cycle synchronization method and system that meets the functional safety requirements. The method and system combine the impact of the environment on the software. When calculating the synchronization time point of the next cycle of the software, the cycle end time of the redundant channel and the self-test result of the cycle synchronizer are combined to calculate the starting time point of the next cycle of the software, thereby enhancing the reliability and robustness of the system operation.

[0301] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0302] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0303] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0304] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0305] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0306] The memory may include non-permanent memory in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. The memory is an example of a computer-readable medium.

[0307] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0308] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0309] The above are only embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included within the scope of the claims of the present application.

Claims

1. A redundant channel software cycle synchronization method that meets functional safety requirements, characterized in that: The method comprises: Obtaining the first signal to be synchronized, the second signal, the internal clock and the delay value of the previous cycle; Determine a first time point and a second time point according to the first signal and the second signal; Determine a first output signal and a second output signal, a delay value of a next cycle, a first reset signal and a second reset signal according to the first time point, the second time point, an internal clock and a delay value of a previous cycle; The first time point is the end time of the cycle of the input signal of the CH1 channel, and the second time point is the end time of the cycle of the input signal of the CH2 channel; Determining a first output signal and a second output signal, a delay value of a next cycle, a first reset signal, and a second reset signal according to the first time point, the second time point, an internal clock, and a delay value of a previous cycle, including: When the second time point is greater than the first time point, and the first time point is greater than the sum of the internal clock and a preset maximum tolerance value, determining the time difference to be a first preset value; Determine the delay value of the next cycle as the sum of the internal clock and the first preset value; Determine the first output signal as the sum of the internal clock and the delay value of the previous cycle; Determine the second output signal as the sum of the internal clock and the delay value of the previous cycle; determining the first reset signal to be a value of an internal self-test result; determining the second reset signal to be a value of the internal self-test result; When it is determined that the first time point is greater than the internal clock and less than the sum of the internal clock and a preset maximum tolerance value, and the second time point is greater than the sum of the internal clock and the maximum tolerance value, the time difference is calculated according to the following formula (1): Wherein, ΔT is the time difference, T0 is the internal clock, and T1 is the first time point; Determine the delay value of the next cycle as the sum of the internal clock and the time difference; Determine the first output signal as the sum of the internal clock and the delay value of the previous cycle; Determine the second output signal as the sum of the internal clock and the delay value of the previous cycle; Determining the first reset signal as a second preset value; determining the second reset signal to be the second preset value; When it is determined that the first time point is greater than the internal clock, the second time point is greater than the first time point, and the second time point is less than the sum of the internal clock and a preset maximum tolerance value, the time difference is calculated according to the following formula (2): Wherein, ΔT is the time difference, T0 is the internal clock, T1 is the first time point, and T2 is the second time point; Determine the delay value of the next cycle as the sum of the internal clock and the time difference; Determine the first output signal as the sum of the internal clock and the delay value of the previous cycle; Determine the second output signal as the sum of the internal clock and the delay value of the previous cycle; Determining the first reset signal as a second preset value; The second reset signal is determined to be the second preset value.

2. The method according to claim 1, characterized in that Determining a first output signal and a second output signal, a delay value of a next cycle, a first reset signal, and a second reset signal according to the first time point, the second time point, an internal clock, and a delay value of a previous cycle, including: In the case where it is determined that the first time point is less than the difference between the internal clock and a preset maximum tolerance value, and the second time point is greater than the sum of the internal clock and the maximum tolerance value, determining the time difference as a first preset value; Determine the delay value of the next cycle as the sum of the internal clock and the time difference; Determine the first output signal as the sum of the internal clock and the delay value of the previous cycle; Determine the second output signal as the sum of the internal clock and the delay value of the previous cycle; Determining the first reset signal as a second preset value; determining the second reset signal to be the second preset value; When it is determined that the first time point is less than the difference between the internal clock and the preset maximum tolerance value, and the second time point is greater than the internal clock, and the second time point is less than the sum of the internal clock and the maximum tolerance value, the time difference is calculated according to the following formula (3): Wherein, ΔT is the time difference, T0 is the internal clock, and T2 is the second time point; Determine the delay value of the next cycle as the sum of the internal clock and the time difference; Determine the first output signal as the sum of the internal clock and the delay value of the previous cycle; Determine the second output signal as the sum of the internal clock and the delay value of the previous cycle; Determining the first reset signal as a second preset value; determining the second reset signal to be the second preset value; When it is determined that the first time point is greater than the difference between the internal clock and a preset maximum tolerance value, and the first time point is less than the internal clock, and the second time point is greater than the sum of the internal clock and the maximum tolerance value, the time difference is calculated according to formula (4): Wherein, ΔT is the time difference, T0 is the internal clock, and T1 is the first time point; Determine the delay value of the next cycle as the sum of the internal clock and the time difference; Determine the first output signal as the sum of the internal clock and the delay value of the previous cycle; Determine the second output signal as the sum of the internal clock and the delay value of the previous cycle; Determining the first reset signal as a second preset value; determining the second reset signal to be the second preset value; When it is determined that the first time point is greater than the difference between the internal clock and a preset maximum tolerance value, the first time point is less than the internal clock, and the second time point is greater than the internal clock, and the second time point is less than the sum of the internal clock and the maximum tolerance value, the time difference is calculated according to formula (5): Wherein, ΔT is the time difference, T0 is the internal clock, T1 is the first time point, and T2 is the second time point; Determine the delay value of the next cycle as the sum of the internal clock and the time difference; Determine the first output signal as the sum of the internal clock and the delay value of the previous cycle; Determine the second output signal as the sum of the internal clock and the delay value of the previous cycle; Determining the first reset signal as a second preset value; The second reset signal is determined to be the second preset value.

3. The method according to claim 1, characterized in that Determining a first output signal and a second output signal, a delay value of a next cycle, a first reset signal, and a second reset signal according to the first time point, the second time point, an internal clock, and a delay value of a previous cycle, including: In the case where it is determined that the first time point is less than the second time point, and the second time point is less than the difference between the internal clock and a preset maximum tolerance value, determining the time difference as a first preset value; Determine the delay value of the next cycle as the sum of the internal clock and the time difference; Determine the first output signal as the sum of the internal clock and the delay value of the previous cycle; Determine the second output signal as the sum of the internal clock and the delay value of the previous cycle; Determining the first reset signal as a second preset value; determining the second reset signal to be the second preset value; When it is determined that the first time point is less than the difference between the internal clock and a preset maximum tolerance value, and the second time point is greater than the difference between the internal clock and the maximum tolerance value, and the second time point is less than the internal clock, the time difference is calculated according to the following formula (6): Wherein, ΔT is the time difference, T0 is the internal clock, and T2 is the second time point; Determine the delay value of the next cycle as the sum of the internal clock and the time difference; Determine the first output signal as the sum of the internal clock and the delay value of the previous cycle; Determine the second output signal as the sum of the internal clock and the delay value of the previous cycle; Determining the first reset signal as a second preset value; determining the second reset signal to be the second preset value; When it is determined that the first time point is greater than the difference between the internal clock and a preset maximum tolerance value, the second time point is greater than the first time point, and the second time point is less than the internal clock, the time difference is calculated according to the following formula (7): Wherein, ΔT is the time difference, T0 is the internal clock, T1 is the first time point, and T2 is the second time point; Determine the delay value of the next cycle as the sum of the internal clock and the time difference; Determine the first output signal as the sum of the internal clock and the delay value of the previous cycle; Determine the second output signal as the sum of the internal clock and the delay value of the previous cycle; Determining the first reset signal as a second preset value; The second reset signal is determined to be the second preset value.

4. The method according to claim 1, characterized in that: Determining a first output signal and a second output signal, a delay value of a next cycle, a first reset signal, and a second reset signal according to the first time point, the second time point, an internal clock, and a delay value of a previous cycle, including: In the case where it is determined that the second time point is greater than the sum of the internal clock and a preset maximum tolerance value, and the first time point is greater than the second time point, determining the time difference as a first preset value; Determine the delay value of the next cycle as the sum of the internal clock and the time difference; Determine the first output signal as the sum of the internal clock and the delay value of the previous cycle; Determine the second output signal as the sum of the internal clock and the delay value of the previous cycle; Determining the first reset signal as a second preset value; determining the second reset signal to be the second preset value; When it is determined that the second time point is greater than the internal clock, and the second time point is less than the sum of the internal clock and a preset maximum tolerance value, and the first time point is greater than the sum of the internal clock and the maximum tolerance value, the time difference is calculated according to formula (8): Wherein, ΔT is the time difference, T0 is the internal clock, and T1 is the first time point; Determine the delay value of the next cycle as the sum of the internal clock and the time difference; Determine the first output signal as the sum of the internal clock and the delay value of the previous cycle; Determine the second output signal as the sum of the internal clock and the delay value of the previous cycle; Determining the first reset signal as a second preset value; determining the second reset signal to be the second preset value; When it is determined that the second time point is greater than the internal clock, the first time point is greater than the second time point, and the first time point is less than the sum of the internal clock and a preset maximum tolerance value, the time difference is calculated according to formula (9): Wherein, ΔT is the time difference, T0 is the internal clock, T1 is the first time point, and T2 is the second time point; Determine the delay value of the next cycle as the sum of the internal clock and the time difference; Determine the first output signal as the sum of the internal clock and the delay value of the previous cycle; Determine the second output signal as the sum of the internal clock and the delay value of the previous cycle; Determining the first reset signal as a second preset value; The second reset signal is determined to be the second preset value.

5. The method according to claim 1, characterized in that: Determining a first output signal and a second output signal, a delay value of a next cycle, a first reset signal, and a second reset signal according to the first time point, the second time point, an internal clock, and a delay value of a previous cycle, including: In the case where it is determined that the second time point is less than the difference between the internal clock and a preset maximum tolerance value, and the first time point is greater than the sum of the internal clock and the maximum tolerance value, the time difference is determined as a first preset value; Determine the delay value of the next cycle as the sum of the internal clock and the time difference; Determine the first output signal as the sum of the internal clock and the delay value of the previous cycle; Determine the second output signal as the sum of the internal clock and the delay value of the previous cycle; Determining the first reset signal as a second preset value; determining the second reset signal to be the second preset value; When it is determined that the second time point is less than the difference between the internal clock and a preset maximum tolerance value, the first time point is greater than the internal clock, and the first time point is less than the difference between the internal clock and the maximum tolerance value, the time difference is calculated according to the following formula (10): Wherein, ΔT is the time difference, T0 is the internal clock, and T1 is the first time point; Determine the delay value of the next cycle as the sum of the internal clock and the time difference; Determine the first output signal as the sum of the internal clock and the delay value of the previous cycle; Determine the second output signal as the sum of the internal clock and the delay value of the previous cycle; Determining the first reset signal as a second preset value; determining the second reset signal to be the second preset value; When it is determined that the second time point is greater than the difference between the internal clock and a preset maximum tolerance value, the second time point is less than the internal clock, and the first time point is greater than the sum of the internal clock and the maximum tolerance value, the time difference is calculated according to formula (11): Wherein, ΔT is the time difference, T0 is the internal clock, and T2 is the second time point; Determine the delay value of the next cycle as the sum of the internal clock and the time difference; Determine the first output signal as the sum of the internal clock and the delay value of the previous cycle; Determine the second output signal as the sum of the internal clock and the delay value of the previous cycle; Determining the first reset signal as a second preset value; determining the second reset signal to be the second preset value; When it is determined that the second time point is greater than the difference between the internal clock and a preset maximum tolerance value, the second time point is less than the internal clock, the first time point is greater than the internal clock, and the first time point is less than the sum of the internal clock and the maximum tolerance value, the time difference is calculated according to the following formula (12): Wherein, ΔT is the time difference, T0 is the internal clock, T1 is the first time point, and T2 is the second time point; Determine the delay value of the next cycle as the sum of the internal clock and the time difference; Determine the first output signal as the sum of the internal clock and the delay value of the previous cycle; Determine the second output signal as the sum of the internal clock and the delay value of the previous cycle; Determining the first reset signal as a second preset value; The second reset signal is determined to be the second preset value.

6. The method according to claim 1, characterized in that Determining a first output signal and a second output signal, a delay value of a next cycle, a first reset signal, and a second reset signal according to the first time point, the second time point, an internal clock, and a delay value of a previous cycle, including: In the case where it is determined that the second time point is less than the first time point, and the first time point is less than the difference between the internal clock and a preset maximum tolerance value, determining the time difference as a first preset value; Determine the delay value of the next cycle as the sum of the internal clock and the time difference; Determine the first output signal as the sum of the internal clock and the delay value of the previous cycle; Determine the second output signal as the sum of the internal clock and the delay value of the previous cycle; Determining the first reset signal as a second preset value; determining the second reset signal to be the second preset value; When it is determined that the second time point is less than the difference between the internal clock and a preset maximum tolerance value, the first time point is greater than the difference between the internal clock and the maximum tolerance value, and the first time point is less than the internal clock, the time difference is calculated according to formula (13): Wherein, ΔT is the time difference, T0 is the internal clock, and T1 is the first time point; Determine the delay value of the next cycle as the sum of the internal clock and the time difference; Determine the first output signal as the sum of the internal clock and the delay value of the previous cycle; Determine the second output signal as the sum of the internal clock and the delay value of the previous cycle; Determining the first reset signal as a second preset value; determining the second reset signal to be the second preset value; When it is determined that the second time point is greater than the difference between the internal clock and the preset maximum tolerance value, the first time point is greater than the second time point, and the first time point is less than the internal clock, the time difference is calculated according to formula (14): Wherein, ΔT is the time difference, T0 is the internal clock, T1 is the first time point, and T2 is the second time point; Determine the delay value of the next cycle as the sum of the internal clock and the time difference; Determine the first output signal as the sum of the internal clock and the delay value of the previous cycle; Determine the second output signal as the sum of the internal clock and the delay value of the previous cycle; Determining the first reset signal as a second preset value; The second reset signal is determined to be the second preset value.

7. A redundant channel software cycle synchronization system that meets functional safety requirements, characterized in that: The system comprises a processor configured to execute the method according to any one of claims 1 to 6.

8. A redundant channel software cycle synchronization system that meets functional safety requirements, characterized in that: The synchronization system comprises: CH1 input port, used to obtain the first signal; CH2 input port, used to obtain the second signal; DIAG component, used to generate configuration parameters; A register component, used for storing the configuration parameters; PLL components and timers for generating internal clocks; A delay register for storing a delay value; An arbitration component, configured to execute the method according to any one of claims 1 to 6; CH1 output port, used for outputting a first output signal; CH2 output port, used to output the second output signal.

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