A GPGPU-based thread reorganization method, device and medium

Abstract

The embodiments of this specification disclose a GPGPU-based thread reorganization method, device and medium, which relate to the technical field of thread branch management. The method includes: monitoring multiple thread bundles executed in a current processing unit, and collecting current thread execution information corresponding to each thread bundle in a current clock cycle; monitoring the execution performance according to current execution performance information in the current thread execution information and pre-acquired historical execution performance information corresponding to a previous clock cycle, so as to determine the current adjusted active thread threshold data corresponding to the current clock cycle; setting the active thread state identifier of each thread bundle based on the current adjusted active thread threshold data and the current active thread information corresponding to each thread bundle, so as to perform thread reorganization on multiple specified thread bundles through the active thread state identifier of each thread bundle and the current thread bundle execution PC information, and adopting different reorganization methods for thread bundles with different numbers of active threads to reduce the reorganization overhead.

Description

Technical Field

[0001] The present specification relates to the technical field of thread branch management, and in particular to a GPGPU-based thread reorganization method, device, and medium. Background Art

[0002] General-Purpose computing on Graphics Processing Units (GPGPU) generates thread branches during execution, which will lead to a waste of computing resources and thus affect the performance of the program. Currently, there are two main methods on hardware to optimize the non-uniform control flow in GPUs: multi-way alternating execution and reorganization. The multi-way alternating execution method has limited improvement on thread-level parallelism. It is essentially an improvement on the stack-based reconvergence mechanism, and there is still no good solution to the choice of reconvergence timing. Although the warp reorganization strategy can greatly improve thread-level parallelism, not all reorganizations are effective, and the hardware overhead of reorganization cannot be ignored.

[0003] For warps with fewer active threads, reorganization can significantly improve parallel efficiency and reduce the number of warps. However, for warps with more active threads, reorganization may destroy the continuity of data between threads, especially when these threads originally access memory continuously. Reorganization will lead to an increase in the number of memory access requests, thereby offsetting the performance advantage brought by the GPGPU memory access merging mechanism and adding additional reorganization overhead. Therefore, the current traditional thread reorganization strategy does not consider the differences in thread reorganization between different numbers of active threads. The same reorganization method is used for thread bundles with different numbers of active threads, which has the risk of destroying the continuity of data between threads and increases additional reorganization overhead. Summary of the invention

[0004] One or more embodiments of the present specification provide a GPGPU-based thread reorganization method, device, and medium for solving the following technical problems: the traditional thread reorganization strategy does not take into account the thread reorganization differences between different numbers of active threads, and adopts the same reorganization method for thread bundles with different numbers of active threads, which has the risk of destroying the continuity of data between threads and increases additional reorganization overhead.

[0005] One or more embodiments of this specification adopt the following technical solutions:

[0006] One or more embodiments of the present specification provide a GPGPU-based thread reorganization method, the method comprising: monitoring multiple thread bundles executed in a current processing unit, collecting current thread execution information corresponding to each of the thread bundles in a current clock cycle, wherein the current thread execution information comprises current execution performance information, current thread bundle execution PC information, and current active thread information; monitoring execution performance according to the current execution performance information in the current thread execution information and pre-acquired historical execution performance information corresponding to a previous clock cycle, so as to determine current adjusted active thread threshold data corresponding to the current clock cycle, wherein the execution performance information comprises the number of memory accesses during the execution process and the number of execution channel conflicts; setting an active thread state identifier of each of the thread bundles based on the current adjusted active thread threshold data and the current active thread information corresponding to each of the thread bundles, so as to perform thread reorganization on multiple specified thread bundles through the active thread state identifier of each of the thread bundles and the current thread bundle execution PC information.

[0007] One or more embodiments of this specification provide a GPGPU-based thread reorganization device, including:

[0008] at least one processor; and,

[0009] a memory communicatively connected to the at least one processor; wherein,

[0010] The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the above method.

[0011] One or more embodiments of the present specification provide a non-volatile computer storage medium storing computer executable instructions, wherein the computer executable instructions are configured to execute the above method.

[0012] At least one of the above technical solutions adopted in the embodiments of this specification can achieve the following beneficial effects: through the above technical solution, by dynamically monitoring and adjusting the active thread state of the thread bundle and performing targeted thread reorganization, the problem that the difference between different numbers of active threads is not considered in the traditional thread reorganization strategy is effectively solved; by dynamically adjusting the active thread threshold data and setting the active thread state identifier according to the current active thread information of each thread bundle, it is possible to more accurately control which thread bundles need to be reorganized, and the targeted reorganization strategy reduces unnecessary reorganization operations, thereby reducing additional reorganization overhead; it is possible to dynamically adjust the active thread threshold data and perform thread reorganization according to the execution performance information in the current clock cycle, which makes it possible to more flexibly respond to different workloads and scenarios. Whether processing high-load tasks or low-load tasks, the system can improve performance by optimizing the active thread state and reorganization strategy of the thread bundle; by comprehensively considering the execution performance information and active thread information, it is possible to avoid performance degradation or system crash caused by blind reorganization, improve parallel efficiency, protect data continuity, reduce reorganization overhead, and improve system flexibility and stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of this specification or the prior art, the following briefly introduces the drawings required for use in the embodiments or the prior art description. Obviously, the drawings described below are only some embodiments recorded in this specification. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative labor. In the drawings:

[0014] Figure 1 A flowchart of a GPGPU-based thread reorganization method provided in an embodiment of this specification;

[0015] Figure 2 A thread self-adjusting pipeline framework diagram provided in an embodiment of this specification;

[0016] Figure 3 A functional schematic diagram of a performance monitoring module provided in an embodiment of this specification;

[0017] Figure 4 A functional schematic diagram of a self-adjusting thread reorganization unit provided in an embodiment of this specification;

[0018] Figure 5 A schematic diagram of the structure of a GPGPU-based thread reorganization device provided in an embodiment of this specification. DETAILED DESCRIPTION

[0019] In order to enable those skilled in the art to better understand the technical solutions in this specification, the technical solutions in the embodiments of this specification will be clearly and completely described below in conjunction with the drawings in the embodiments of this specification. Obviously, the described embodiments are only part of the embodiments of this specification, not all of the embodiments. Based on the embodiments of this specification, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of this specification.

[0020] The embodiment of this specification provides a thread reorganization method based on GPGPU. It should be noted that the execution subject in the embodiment of this specification can be a server or any device with data processing capabilities. Figure 1 A flowchart of a GPGPU-based thread reorganization method provided in an embodiment of this specification is shown in FIG. Figure 1 As shown, it mainly includes the following steps:

[0021] Step S101 : monitoring multiple thread warps executed in the current processing unit, and collecting current thread execution information corresponding to each thread warp in the current clock cycle.

[0022] In one embodiment of the present specification, multiple thread bundles executed in the current processing unit are monitored, and the current thread execution information corresponding to each thread bundle in the current clock cycle is collected, wherein the current thread execution information includes current execution performance information, current thread bundle execution PC information and current active thread information. The current processing unit refers to a streaming multiprocessor (SM), that is, an SM processing unit. It should be noted that the current execution performance information here includes the number of memory accesses during the execution process and the number of execution channel conflicts. The number of memory accesses refers to the number of times the thread bundle accesses the memory during the execution process. Since the access speed of the memory is much lower than the execution speed of the processor, too many memory access operations will cause the processor to wait for the memory response, thereby reducing the overall performance; the number of execution channel conflicts refers to the number of conflicts caused by resource competition (such as register files, execution units, etc.) during the execution of the thread bundle. These conflicts will cause the execution of the thread bundle to be suspended or delayed; the number of memory accesses of the thread bundle can be recorded in real time through the hardware performance counters usually equipped with GPGPU, and the number of execution channel conflicts can be detected through special performance analysis tools. It should be noted that the English full name of the PC in the thread bundle execution PC is Program Counter, that is, the program counter, which is used to store the address of the execution instruction.

[0023] Step S102 , monitoring the execution performance according to the current execution performance information in the current thread execution information and the pre-acquired historical execution performance information corresponding to the previous clock cycle, to determine the current adjusted active thread threshold data corresponding to the current clock cycle.

[0024] The execution performance information includes the number of memory accesses during the execution process and the number of execution channel conflicts;

[0025] In one embodiment of the present specification, when monitoring multiple executed thread warps in each clock cycle, the thread execution information corresponding to each thread warp in each clock cycle is stored to obtain the historical execution performance information corresponding to the previous clock cycle of the current clock cycle. The execution performance is monitored through the current execution performance information in the current thread execution information and the historical execution performance information corresponding to the previous clock cycle, and the current adjusted active thread threshold data corresponding to the current clock cycle is determined through the change of the thread warp execution performance.

[0026] The execution performance is monitored according to the current execution performance information in the current thread execution information and the historical execution performance information corresponding to the previous clock cycle obtained in advance, so as to determine the current adjusted active thread threshold data corresponding to the current clock cycle, specifically including: determining the current execution performance evaluation index corresponding to the current clock cycle and the historical execution performance evaluation index corresponding to the previous clock cycle respectively according to the current execution performance information and the historical execution performance information corresponding to each thread bundle; determining the execution performance change type of the current clock cycle relative to the previous clock cycle through the current execution performance evaluation index and the historical execution performance evaluation index, wherein the execution performance change type includes any one of performance improvement and performance reduction; obtaining the historical active thread threshold data corresponding to the previous clock cycle, adjusting the historical active thread threshold data based on the execution performance change type, and determining the current adjusted active thread threshold data corresponding to the current clock cycle.

[0027] In one embodiment of the present specification, according to the current execution performance information and the historical execution performance information corresponding to each thread bundle, the current execution performance evaluation index corresponding to the current clock cycle and the historical execution performance evaluation index corresponding to the previous clock cycle are respectively determined. When the current average execution performance evaluation index is greater than the historical average execution performance evaluation index, the execution performance change type is determined to be performance reduction; when the current average execution performance evaluation index is less than the historical average execution performance evaluation index, the execution performance change type is determined to be performance improvement. The historical active thread threshold data corresponding to the previous clock cycle is obtained. It should be noted that if the previous clock cycle is not the first clock cycle, the historical active thread threshold data corresponding to the previous clock cycle is obtained based on the previous clock cycle of the previous clock cycle. For the execution process of the first round of clock cycles, the corresponding initial active thread threshold data can be set according to actual needs, for example, it can be set to half of the maximum number of threads that can be accommodated in the thread bundle. In each round of execution, based on the execution performance change type, the historical active thread threshold data of the previous round is adjusted to determine the current adjusted active thread threshold data corresponding to the current clock cycle.

[0028] According to the current execution performance information and the historical execution performance information corresponding to each thread bundle, the current execution performance evaluation index corresponding to the current clock cycle and the historical execution performance evaluation index corresponding to the previous clock cycle are determined respectively, specifically including: accumulating the number of current execution process memory accesses and the number of current execution channel conflicts in the current execution performance information corresponding to each thread bundle to determine the first execution performance evaluation index of each thread bundle; averaging the first execution performance evaluation index corresponding to each thread bundle to determine the current execution performance evaluation index corresponding to the current clock cycle; accumulating the number of historical execution process memory accesses and the number of historical execution channel conflicts in each historical execution performance information to determine multiple second historical execution performance evaluation indicators, and performing average processing to determine the historical execution performance evaluation index corresponding to the previous clock cycle.

[0029] In one embodiment of the present specification, the execution performance information includes the number of memory accesses during the execution process and the number of execution channel conflicts. For each thread bundle, the total number of memory accesses by all threads in the current clock cycle is counted, and the number of conflicts caused by threads in the thread bundle trying to access the same resource (such as a register file, shared memory, or global memory) at the same time in the current clock cycle is counted. For each thread bundle, the above two indicators are added to obtain the first execution performance evaluation indicator of the thread bundle. The first execution performance evaluation indicators of all thread bundles are averaged to obtain the current execution performance evaluation indicator of the current clock cycle, which is used to represent the average execution efficiency of all thread bundles in the current clock cycle.

[0030] The historical execution performance information is processed in the same way to obtain the historical execution performance evaluation index in the previous clock cycle. For each thread bundle, the number of memory accesses in the historical execution process and the number of conflicts in the historical execution channels are added to obtain the second historical execution performance evaluation index of the thread bundle. The second historical execution performance evaluation index of the previous clock cycle is calculated and averaged to obtain the historical execution performance evaluation index of the previous clock cycle, which is used to represent the average execution efficiency of all thread bundles in the previous clock cycle.

[0031] Based on the execution performance change type, the historical active thread threshold data is adjusted to determine the current adjusted active thread threshold data corresponding to the current clock cycle, specifically including: determining a performance change index through the current execution performance evaluation index and the historical execution performance evaluation index; determining the performance change rate of the current clock cycle according to the performance change index and the historical execution performance evaluation index, and determining the threshold adjustment amount based on the performance change rate and the historical active thread threshold data; determining a rounding method and a threshold adjustment method corresponding to the threshold adjustment amount through the execution performance change type, wherein the rounding method includes any one of rounding up and rounding down, and the threshold adjustment method includes any one of threshold increase and threshold decrease; rounding the threshold adjustment amount according to the rounding method to determine the threshold adjustment step; according to the threshold adjustment method, based on the historical active thread threshold data, adjusting according to the threshold adjustment step to determine the current adjusted active thread threshold data corresponding to the current clock cycle.

[0032] In one embodiment of the present specification, the difference between the current execution performance evaluation index and the historical execution performance evaluation index is calculated, and the absolute value of the difference is the performance change index. According to the ratio of the performance change index to the historical execution performance evaluation index, the performance change rate is obtained. Based on the performance change rate and the historical active thread threshold data, the threshold adjustment amount can be calculated. It should be noted that the threshold adjustment amount obtained here may be a non-integer. In the case of a non-integer, it is necessary to perform a rounding operation in the corresponding direction on the obtained threshold adjustment amount according to the execution performance change type, such as rounding up or rounding down. For example, when the execution performance change type is performance degradation, in order to ensure that the final adjusted value is reduced compared with the previous value, it can be rounded up here to ensure that the value obtained after the threshold adjustment step length is reduced by the historical active thread threshold data is a relatively small value. When the execution performance change type is performance improvement, it can be rounded down here to provide a safety margin. According to the selected rounding method, the threshold adjustment amount is rounded to obtain the threshold adjustment step length, and the threshold adjustment step length here refers to the adjusted threshold amount. In addition, based on the execution performance change type, a threshold increase or threshold decrease is selected, where the threshold increase or threshold decrease refers to the direction of adjustment, that is, increase or decrease in quantity. According to the selected threshold adjustment method and the calculated threshold adjustment step, adjustments are made based on the historical active thread threshold data to obtain the current adjusted active thread threshold data corresponding to the current clock cycle. The threshold adjustment step is increased or decreased by the historical active thread threshold data to obtain the current adjusted active thread threshold data.

[0033] Step S103, based on the current adjusted active thread threshold data and the current active thread information corresponding to each thread warp, the active thread state flag of each thread warp is set, so as to perform thread reorganization on multiple specified thread warps through the active thread state flag of each thread warp and the current thread warp execution PC information.

[0034] In one embodiment of the present specification, the current active thread information corresponding to each thread bundle is compared with the current adjusted active thread threshold data, and the active thread state flag of each thread bundle is set according to the comparison result, and the thread bundle with a value lower than the current adjusted active thread threshold data is set to a low active state, and the thread bundle with a value not lower than the current adjusted active thread threshold data is set to a high active state. Through the active thread state flag of each thread bundle and the current thread bundle execution PC information, multiple specified thread bundles are thread reorganized.

[0035] The method comprises the following steps: performing thread reorganization on multiple designated thread bundles through the active thread state identifier of each thread bundle and the PC information of the current thread bundle, specifically comprising: screening multiple thread bundles through the active thread state identifier of each thread bundle and the PC information of the current thread bundle to determine multiple first thread bundles that meet preset requirements, wherein the active thread state identifier of the first thread bundle is a low active state, and the current thread bundle execution PC information corresponding to the multiple first thread bundles is the same; determining the number of thread bundles to be reorganized among the multiple first thread bundles, and obtaining a pre-generated thread bundle reorganization number threshold; when the number of thread bundles to be reorganized is greater than the thread bundle reorganization number threshold, determining multiple designated thread bundles that meet the preset requirements among the multiple first thread bundles according to the designated execution performance evaluation factor of each first thread bundle, so as to perform thread reorganization, wherein the number of the multiple designated thread bundles is the thread bundle reorganization number threshold.

[0036] In one embodiment of the present specification, all the thread bundles are traversed through the active thread state identifier of each thread bundle and the PC information of the current thread bundle execution, and the thread bundles with the active thread state identifier being the low active state and the current execution PC information are determined, and multiple first thread bundles are obtained in the above manner. The number of first thread bundles obtained is counted, and a pre-generated thread bundle reorganization number threshold is obtained. It should be noted that the thread bundle reorganization number threshold here is used to represent the number threshold of thread bundles reorganized each time, which is usually a positive integer not less than 2. The number of thread bundles may be a large number of thread bundles each time they are reorganized. The thread bundle reorganization number threshold limits a threshold so that the thread bundles participating in this reorganization will not be higher than this threshold value. When the number of thread bundles to be reorganized is not greater than the thread bundle reorganization number threshold, all the multiple first thread bundles obtained are reorganized. If the number of thread bundles to be reorganized is greater than the thread bundle reorganization number threshold, it is necessary to screen among the multiple first thread bundles, and according to the specified execution performance evaluation factor of each of the first thread bundles, multiple specified thread bundles that meet the preset requirements can be determined from the multiple first thread bundles, and threads are reorganized for the multiple specified thread bundles. It should be noted that the number of the multiple specified thread bundles is the thread bundle reorganization number threshold.

[0037] Obtaining a pre-generated thread bundle reorganization number threshold specifically includes: obtaining a historical thread bundle reorganization number threshold corresponding to a previous time period; determining a current execution process memory access count corresponding to each of the thread bundles in the current time period, and determining a current average memory access count in the current time period based on multiple current execution process access counts; determining a historical average memory access count in the previous time period based on multiple historical execution process memory access counts corresponding to the previous time period; and when the current average memory access count is greater than the historical average memory access count, reducing the number of units based on the historical thread bundle reorganization number threshold to determine the thread bundle reorganization number threshold.

[0038] In one embodiment of the present specification, a historical thread warp reorganization number threshold corresponding to the previous time period is obtained, and the number of memory accesses of the current execution process corresponding to each thread warp in the current time period is determined, and the current average number of memory accesses in the current time period is determined based on multiple access times of the current execution process. In the same way, the historical average number of memory accesses in the previous clock cycle is calculated, that is, the historical average number of memory accesses in the previous time period is determined based on multiple historical number of memory accesses of the execution process corresponding to the previous time period. If the current average number of memory accesses is greater than the historical average number of memory accesses, then the historical thread warp reorganization number threshold is subtracted by one to determine the thread warp reorganization number threshold, but the minimum thread warp reorganization number threshold is 2. It should be noted that the initial thread warp reorganization number threshold can be set to half of the maximum number of thread warps that can be accommodated by an SM. If the current average number of memory accesses is not greater than the historical average number of memory accesses, the historical thread warp reorganization number threshold is used as the thread warp reorganization number threshold.

[0039] According to the specified execution performance evaluation factor of each of the first thread bundles, a plurality of specified thread bundles that meet preset requirements are determined from the plurality of the first thread bundles to perform thread reorganization, specifically including: accumulating the number of memory accesses of the current execution process and the number of conflicts of the current execution channel in the current execution performance information corresponding to each of the first thread bundles to determine the specified execution performance evaluation factor of each of the first thread bundles; sorting the plurality of first thread bundles in descending order according to the specified execution performance evaluation factor of each of the first thread bundles, and determining a corresponding number of specified thread bundles in turn according to a threshold value of the number of thread bundle reorganization to perform thread reorganization.

[0040] In one embodiment of the present specification, the number of memory accesses of the current execution process and the number of conflicts in the current execution channel in the current execution performance information corresponding to each first thread bundle are accumulated to determine the designated execution performance evaluation factor of each first thread bundle, which can be determined by the first execution performance evaluation index of each thread bundle in the above steps. All first thread bundles are sorted according to the accumulated designated execution performance evaluation factors. The sorting order should be from large to small, because thread bundles with higher memory access times and conflict times are more likely to become performance bottlenecks, so they should be given priority for reorganization. According to the sorted order, a specified number of thread bundles are selected in turn as designated thread bundles, and the specified number is equal to the previously determined thread bundle reorganization number threshold, and the obtained designated thread bundles will perform subsequent thread reorganization operations.

[0041] The method comprises: obtaining a PC-Warp lookup table corresponding to the current processing unit, wherein the PC-Warp lookup table comprises a thread bundle identification table entry, a thread bundle execution PC table entry and an active thread state identification table entry; updating the active thread state identification of each thread bundle and the current thread bundle execution PC information in the PC-Warp lookup table, determining to update the PC-Warp lookup table, and determining a plurality of specified thread bundles according to the updated PC-Warp lookup table, so as to perform thread reorganization on the plurality of specified thread bundles.

[0042] In one embodiment of the present specification, multiple designated thread warps can be thread reorganized by using the active thread state identifier of each thread warp and the current thread warp execution PC information in the form of a PC-Warp lookup table. The PC-Warp lookup table is used as an example for explanation. First, the PC-Warp lookup table corresponding to the current processing unit is obtained. The PC-Warp lookup table includes a thread warp identifier table item, a thread warp execution PC table item, and an active thread state identifier table item. The thread warp identifier table item is used to store the thread warp ID, the thread warp execution PC table item is used to store the thread warp execution PC, and the active thread state identifier table item is used to store the active thread state of the thread warp. In addition to the above table items, additional table items can be added to store related parameters such as the execution performance evaluation index of each thread warp. According to the active thread state identifier of each thread warp and the current thread warp execution PC information, the table item is updated in the PC-Warp lookup table, and the PC-Warp lookup table is updated to determine the updated PC-Warp lookup table, so as to determine multiple designated thread warps according to the updated PC-Warp lookup table, so as to perform thread reorganization on the multiple designated thread warps. When updating the PC-Warp lookup table, the table entries are checked. When the number of active threads in the warp is lower than the threshold value, that is, it corresponds to the low-activity state, it is reorganized with the warp with the same PC in the PC-Warp and also in the low-activity state and sent to the Warp pool to wait for scheduling. When it is higher than the threshold value, that is, the active thread state is marked as a high-activity state, it is determined that no reorganization is required and it is directly sent to the Warp pool to wait for scheduling.

[0043] Through the above technical solution, by dynamically monitoring and adjusting the active thread status of thread bundles and performing targeted thread reorganization, the problem that the differences between different numbers of active threads are not considered in the traditional thread reorganization strategy is effectively solved; by dynamically adjusting the active thread threshold data and setting the active thread status identifier according to the current active thread information of each thread bundle, it is possible to more accurately control which thread bundles need to be reorganized, and the targeted reorganization strategy reduces unnecessary reorganization operations, thereby reducing additional reorganization overhead; the active thread threshold data can be dynamically adjusted and the thread reorganization can be performed according to the execution performance information in the current clock cycle, which makes it possible to more flexibly respond to different workloads and scenarios. Whether processing high-load tasks or low-load tasks, the system can improve performance by optimizing the active thread status and reorganization strategy of the thread bundle; by comprehensively considering the execution performance information and active thread information, it is possible to avoid performance degradation or system crash caused by blind reorganization, improve parallel efficiency, protect data continuity, reduce reorganization overhead, and improve system flexibility and stability.

[0044] In one embodiment of the present specification, in order to improve the performance of the program when encountering a branch, reduce the overhead of thread warp reorganization, and improve the efficiency of thread reorganization, different reorganization methods are adopted for thread warps with different numbers of active threads. A performance monitoring unit is set to monitor the performance of the currently executed thread reorganization method, and dynamically adjust the thread reorganization conditions according to the execution performance, and a self-adjusting thread reorganization unit is set to reorganize the thread warps that meet the reorganization conditions.

[0045] Figure 2 A thread self-adjusting pipeline framework diagram provided in the embodiment of this specification, such as Figure 2 As shown, the self-tuning architecture includes a thread scheduler, a pipeline unit, a register file unit, a parallel execution unit, a performance monitoring module, a self-tuning thread reorganization unit, a thread scheduler, and a cache storage unit. The thread scheduler uses a specific scheduling strategy to schedule and execute thread bundles based on the obtained thread bundle information; the pipeline unit includes functions such as instruction fetching, decoding, scoreboard, and instruction issuance to implement pipeline execution of instructions, and the register file unit is used to store the operand information required for the execution of each thread. Figure 2 In the example, the parallel execution unit is demonstrated as an arithmetic logic unit (ALU), which is used to perform specific operations on operands based on the information of instruction execution. The performance monitoring module is used to collect information during the thread execution process and send the integrated information to the self-tuning thread reorganization unit. The self-tuning thread reorganization unit automatically adjusts the thread bundle reorganization method based on the information fed back by the performance monitoring module to achieve the result of improving the program execution performance. The cache storage unit is used to store the data of instruction execution, which can be loaded through the load / store unit (Load / Store Unit, LSU), that is, through the LSU module.

[0046] First, the thread scheduler schedules instruction fetching based on the thread bundles fed back by the self-tuning thread reorganization unit, takes out the instructions of the corresponding thread bundles from the instruction unit, and sends them to the pipeline unit for execution. It mainly performs instruction decoding, scoreboard checking conflicts, and sends the thread bundles that meet the requirements and have obtained operands from the register file to the subsequent execution unit. After executing the thread bundle instructions, the performance monitoring module will collect the number of memory accesses and execution channel conflicts during the execution process to dynamically adjust the threshold value. The adjusted threshold value will be sent to the self-tuning thread reorganization unit, which will screen the thread bundles that need to be reorganized based on the threshold value, and put the reorganized and non-reorganized thread bundles into the Warp pool for the scheduler to select.

[0047] Figure 3 A functional schematic diagram of a performance monitoring module provided in an embodiment of this specification, such as Figure 3As shown, the performance monitoring module function collects the number of memory accesses and the number of conflicts in the execution channel during the execution process and accumulates them, and then increases (increases) the active thread threshold value. After that, after the next round of pipeline thread bundle reorganization, the sum of the number of memory accesses and the number of execution channel conflicts is used to determine whether the performance has improved. When the total number decreases, the performance has improved, and when the total number increases, the performance has decreased. When the performance has improved, the active thread threshold value will continue to be increased, and when the performance has decreased, the active thread threshold value will be lowered. This is a cyclic dynamic adjustment. The active thread threshold value will be sent to the self-adjusting thread reorganization unit after each adjustment. In addition to adjusting the active thread threshold value, the number of memory accesses during the execution process is collected, and the number of memory accesses is compared with the historical number of memory accesses to determine whether the number of memory accesses has increased. If so, the thread bundle number threshold value is reduced. If not, the previous thread bundle number threshold value is kept unchanged, and the obtained thread bundle number threshold value is sent to the self-adjusting thread reorganization unit.

[0048] Figure 4 A functional schematic diagram of a self-adjusting thread reorganization unit provided in an embodiment of this specification, such as Figure 4 As shown, the module generates a PC-Warp lookup table in each clock cycle, and the lookup table contains the ID of the Warp, the PC it executes, and the number of active threads. After that, the table entries of the lookup table are checked to perform the condition 1 judgment process of the number of active threads and the threshold value of active thread bundles. When the number of active threads in the Warp is not lower than the threshold value, it is determined that no reorganization is required, and it directly enters the Warp pool to wait for scheduling. When the number of active threads in the Warp is lower than the threshold value, the number of thread bundles whose active thread numbers are lower than the threshold value is determined, and it is determined whether this number is greater than the threshold value of the number of thread bundles. If not, all thread bundles with the same PC that meet the above conditions in the PC-Warp are reorganized; if so, the thread bundles with the same PC that meet condition 1 and have a lower number of active threads in the PC-Warp are preferentially selected for reorganization. It is also possible to select thread bundles with the same number of memory accesses and higher number of conflicts as the threshold value of the number of thread bundles from thread bundles that meet condition 1 and have the same PC for reorganization. After reorganization, it is sent to the Warp pool to wait for scheduling.

[0049] Through the above technical solution, after each instruction is executed, the threshold value can be adaptively and dynamically adjusted according to the performance of the program execution to meet the needs of program blocks with different functions, thereby reducing the overhead of thread reorganization and having higher flexibility and better branch execution performance.

[0050] The embodiment of this specification also provides a thread reorganization device based on GPGPU, such as Figure 5As shown, the device includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the above method.

[0051] The embodiments of the present specification also provide a non-volatile computer storage medium storing computer executable instructions, wherein the computer executable instructions are configured to execute the above method.

[0052] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device, equipment, and non-volatile computer storage medium embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0053] The above is a description of a specific embodiment of the specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the embodiments and still achieve the desired results. In addition, the processes depicted in the drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0054] The devices and media provided in the embodiments of this specification correspond one-to-one to the methods. Therefore, the devices and media also have similar beneficial technical effects as the corresponding methods. Since the beneficial technical effects of the methods have been described in detail above, the beneficial technical effects of the devices and media will not be repeated here.

[0055] Those skilled in the art will appreciate that the embodiments of this specification may be provided as methods, systems, or computer program products. Therefore, this specification may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, this specification may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0056] This specification is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of this specification. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0057] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0058] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0059] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0060] Memory may include non-permanent storage in a computer-readable medium, in the form of random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of a computer-readable medium.

[0061] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0062] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0063] The above description is only one or more embodiments of this specification and is not intended to limit this specification. For those skilled in the art, one or more embodiments of this specification may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of one or more embodiments of this specification shall be included in the scope of the claims of this specification.

Claims

1. A thread reorganization method based on GPGPU, characterized in that: The method comprises: Monitor multiple thread warps executed in the current processing unit, and collect current thread execution information corresponding to each thread warp in the current clock cycle, wherein the current thread execution information includes current execution performance information, current thread warp execution PC information, and current active thread information; Monitoring the execution performance according to the current execution performance information in the current thread execution information and the pre-acquired historical execution performance information corresponding to the previous clock cycle, so as to determine the current adjusted active thread threshold data corresponding to the current clock cycle, wherein the execution performance information includes the number of memory accesses during the execution process and the number of execution channel conflicts; Based on the current adjusted active thread threshold data and the current active thread information corresponding to each of the thread warps, an active thread state flag of each of the thread warps is set, so as to perform thread reorganization on a plurality of designated thread warps through the active thread state flag of each of the thread warps and the current thread warp execution PC information; Performing thread reorganization on multiple specified thread warps according to the active thread state identifier of each thread warp and the PC information of the current thread warp execution, specifically including: Screening the plurality of thread warps by using the active thread state identifier of each of the thread warps and the current thread warp execution PC information to determine a plurality of first thread warps that meet preset requirements, wherein the active thread state identifier of the first thread warp is a low active state, and the current thread warp execution PC information corresponding to the plurality of first thread warps is the same; Determine the number of to-be-reorganized thread warps of the plurality of first thread warps, and obtain a pre-generated thread warp reorganization number threshold; When the number of the to-be-reorganized thread warps is greater than the thread warp reorganization number threshold, a plurality of designated thread warps that meet preset requirements are determined from the plurality of first thread warps according to the designated execution performance evaluation factor of each of the first thread warps, so as to perform thread reorganization, wherein the number of the plurality of designated thread warps is the thread warp reorganization number threshold.

2. The thread reorganization method based on GPGPU according to claim 1, characterized in that: Monitoring the execution performance according to the current execution performance information in the current thread execution information and the pre-acquired historical execution performance information corresponding to the previous clock cycle to determine the current adjusted active thread threshold data corresponding to the current clock cycle, specifically including: Determine, according to the current execution performance information and the historical execution performance information corresponding to each thread warp, a current execution performance evaluation index corresponding to the current clock cycle and a historical execution performance evaluation index corresponding to the previous clock cycle; Determining, by means of the current execution performance evaluation index and the historical execution performance evaluation index, a type of execution performance change of the current clock cycle relative to the previous clock cycle, wherein the execution performance change type includes any one of performance improvement and performance degradation; The historical active thread threshold data corresponding to the previous clock cycle is obtained, and based on the execution performance change type, the historical active thread threshold data is adjusted to determine the current adjusted active thread threshold data corresponding to the current clock cycle.

3. The thread reorganization method based on GPGPU according to claim 2, characterized in that: Determining, according to the current execution performance information and the historical execution performance information corresponding to each thread warp, a current execution performance evaluation index corresponding to the current clock cycle and a historical execution performance evaluation index corresponding to the previous clock cycle, respectively, specifically includes: Accumulating the number of memory accesses during the current execution process and the number of conflicts in the current execution channel in the current execution performance information corresponding to each thread warp to determine a first execution performance evaluation index for each thread warp; Taking an average of the first execution performance evaluation index corresponding to each of the thread warps to determine a current execution performance evaluation index corresponding to the current clock cycle; Based on the accumulation of the number of memory accesses in the historical execution process and the number of conflicts in the historical execution channels in each of the historical execution performance information, multiple second historical execution performance evaluation indicators are determined to perform average processing to determine the historical execution performance evaluation indicator corresponding to the previous clock cycle.

4. The GPGPU-based thread reorganization method according to claim 2, characterized in that: Based on the execution performance change type, adjusting the historical active thread threshold data to determine the current adjusted active thread threshold data corresponding to the current clock cycle specifically includes: Determining a performance change indicator by using the current execution performance evaluation indicator and the historical execution performance evaluation indicator; Determine the performance change rate of the current clock cycle according to the performance change index and the historical execution performance evaluation index, and determine the threshold adjustment amount based on the performance change rate and the historical active thread threshold data; Determine, by means of the execution performance change type, a rounding method and a threshold adjustment method corresponding to the threshold adjustment amount, wherein the rounding method includes any one of rounding up and rounding down, and the threshold adjustment method includes any one of threshold increase and threshold decrease; Rounding the threshold adjustment amount according to the rounding method to determine the threshold adjustment step length; According to the threshold adjustment method, based on the historical active thread threshold data, adjustment is performed according to the threshold adjustment step size to determine the current adjusted active thread threshold data corresponding to the current clock cycle.

5. The thread reorganization method based on GPGPU according to claim 1, characterized in that: Get the pre-generated thread warp reorganization number threshold, including: Get the historical thread warp reorganization number threshold corresponding to the previous time period; Determine the number of memory accesses of the current execution process corresponding to each of the thread warps in the current time period, so as to determine the current average number of memory accesses in the current time period based on the multiple number of memory accesses of the current execution processes; Determine the historical average number of memory accesses in the previous time period according to the number of memory accesses of multiple historical execution processes corresponding to the previous time period; When the current average number of memory accesses is greater than the historical average number of memory accesses, unit quantity reduction is performed on the basis of the historical warp reorganization quantity threshold to determine the warp reorganization quantity threshold.

6. The thread reorganization method based on GPGPU according to claim 1, characterized in that: According to the specified execution performance evaluation factor of each of the first thread warps, a plurality of specified thread warps meeting preset requirements are determined from the plurality of first thread warps to perform thread reorganization, specifically including: Accumulating the number of memory accesses during the current execution process and the number of conflicts in the current execution channels in the current execution performance information corresponding to each first thread warp to determine a designated execution performance evaluation factor for each first thread warp; The plurality of first thread warps are sorted in descending order according to the designated execution performance evaluation factor of each of the first thread warps, and a corresponding number of designated thread warps are determined in sequence according to the thread warp reorganization number threshold to perform thread reorganization.

7. The thread reorganization method based on GPGPU according to claim 1, characterized in that: Performing thread reorganization on multiple specified thread warps according to the active thread state identifier of each thread warp and the PC information of the current thread warp execution, specifically including: Obtaining a PC-Warp lookup table corresponding to the current processing unit, wherein the PC-Warp lookup table includes a warp identification table entry, a warp execution PC table entry, and an active thread state identification table entry; The active thread state identifier of each thread warp and the PC information of the current thread warp execution are used to update the table entry in the PC-Warp lookup table, and the updated PC-Warp lookup table is determined to determine multiple specified thread warps according to the updated PC-Warp lookup table, so as to perform thread reorganization on the multiple specified thread warps.

8. A thread reorganization device based on GPGPU, characterized in that: The device comprises: at least one processor; and, a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can perform the method according to any one of claims 1 to 7.

9. A non-volatile computer storage medium storing computer executable instructions, characterized in that: The computer executable instructions are configured to execute the method according to any one of claims 1 to 7.

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