Data transmission channel switching method, computer equipment, storage medium and program product

Abstract

The present invention relates to the technical field of servers, and discloses a data transmission channel switching method, a computer device, a storage medium and a program product, comprising: when a write request is received in a current bandwidth detection cycle, a write data operation corresponding to the write request is executed in a memory through a first data transmission channel, and the first data transmission channel is a write channel between a data processor and a memory; the operation duration of the write data operation is obtained; the number of write requests whose operation duration is greater than or equal to a first preset threshold value in the current bandwidth detection cycle is counted; according to the number of write requests and the second preset threshold value, it is determined whether to perform a data transmission channel switching operation; when it is determined to perform a channel switching operation, the channel currently occupied by the write data is switched from the first data transmission channel to the second data transmission channel, and the second data transmission channel is a write channel between a data processor and a target memory. The present invention can ensure the quality of image data while ensuring that image data is updated in a timely manner.

Description

Technical Field

[0001] The present invention relates to the technical field of servers, and in particular to a data transmission channel switching method, a computer device, a storage medium and a program product. Background Art

[0002] In the field of server technology, the local display screen of a general server needs to be processed by the internal integrated graphics card of the baseboard management controller (BMC) and output to the display for display.

[0003] Generally, integrated graphics cards use part of the system memory of the BMC system as video memory. However, in the BMC system, the system memory needs to be used as the central processing unit (CPU) for calculation, network, kernel operation, etc. When the BMC system is heavily loaded, insufficient memory bandwidth may occur, resulting in the inability to write image data into the video memory in time, causing abnormal display. In related technologies, the frame rate or resolution of image data is generally reduced to reduce the amount of data to maintain the smoothness of the display screen.

[0004] However, reducing the frame rate or resolution will result in a lower image quality on the displayed picture. Summary of the invention

[0005] In view of this, the present invention provides a data transmission channel switching method, apparatus, computer equipment, storage medium and program product to solve the problem of reduced display effect caused by reducing frame rate or resolution.

[0006] In a first aspect, the present invention provides a data transmission channel switching method, the method is applied to a video memory data reading and writing system, the video memory data reading and writing system comprises a video transmission standard controller and a memory, the video transmission standard controller comprises a data processor and a target memory, the method is executed by the data processor, and the method comprises:

[0007] Whenever a write request is received in the current bandwidth detection cycle, a write data operation corresponding to the write request is performed in the memory through a first data transmission channel, wherein the first data transmission channel is a write channel between the data processor and the memory;

[0008] Obtaining the operation duration of the data writing operation;

[0009] Counting the number of write requests whose operation duration is greater than or equal to a first preset threshold in the current bandwidth detection cycle;

[0010] Determining whether to perform a data transmission channel switching operation according to the number of write requests and a second preset threshold;

[0011] When it is determined to perform a channel switching operation, the channel currently occupied by write data is switched from the first data transmission channel to the second data transmission channel, wherein the second data transmission channel is a write channel between the data processor and the target memory.

[0012] The present invention provides a data transmission channel switching method, which has the following advantages:

[0013] In each bandwidth detection cycle, the data processor can determine whether the bandwidth of the first data transmission channel is sufficient by counting the number of write requests whose operation duration is greater than the first preset threshold and the second preset threshold. If the bandwidth of the first data transmission channel is insufficient, the data processor can switch to the second data transmission channel in time to complete the update of the image data in time. In this way, there is no need to reduce the frame rate or resolution of the image data to ensure the timely update of the image data, that is, while ensuring the timely update of the image data, the image quality of the displayed screen is guaranteed.

[0014] In an optional implementation, when it is determined to perform a channel switching operation, after the channel currently occupied by write data is switched from the first data transmission channel to the second data transmission channel, the method further includes:

[0015] During the data writing operation of the current frame, each time a write request is received, the write request is parsed to obtain position information corresponding to at least one update pixel and image data corresponding to each update pixel;

[0016] Generate flag information corresponding to each of the update pixels, wherein the flag information is used to indicate an operation state of the update pixel;

[0017] According to the position information, the image data and the flag information corresponding to each of the update pixels, the total storage data corresponding to each of the update pixels is formed;

[0018] The total storage data of each of the update pixels is written to the target memory through the second data transmission channel.

[0019] Specifically, the flag information is used to indicate the operation status of the updated pixel, which facilitates the state change of each pixel and ensures that the update is only performed when necessary, thereby saving bandwidth and processing time. In addition, by combining the position information, image data and flag information into the total storage data, the image data can be managed and organized more efficiently, which is convenient for subsequent processing and storage.

[0020] In an optional embodiment, the method further includes:

[0021] After completing the data writing operation of the current frame, obtaining the receiving order and position information of each of the multiple update pixels updated in the current frame;

[0022] Determining the order of each of the update pixels in the plurality of update pixels according to the receiving order and position information of each of the update pixels in the plurality of update pixels;

[0023] Determining a target eliminated pixel according to the ranking of each of the updated pixels among the plurality of updated pixels;

[0024] After completing the display update operation of the current frame, the image data of the target eliminated pixels are written back to the memory.

[0025] Specifically, since the storage space of the target memory is small and the target eliminated pixels may not be updated in the next frame, the image data of the target eliminated pixels can be written back to the memory after the display update operation of the current frame is completed, which can ensure that the image data of the target eliminated pixels is not lost and leave free storage space in the target memory. In addition, after the display update operation of the current frame is completed, the target eliminated pixels are processed to ensure that the display process will not be affected by the memory operation, thereby improving the smoothness and efficiency of the display picture.

[0026] In an optional implementation, determining the order of each of the plurality of update pixels according to the receiving order and position information of each of the plurality of update pixels comprises:

[0027] Selecting a first boundary pixel and a second boundary pixel from the plurality of update pixels according to a receiving order of each of the plurality of update pixels;

[0028] constructing a target straight line according to the position information of the first boundary pixel and the position information of the second boundary pixel;

[0029] Determine a vertical distance from the first update pixel to the target straight line according to position information of the first update pixel and the target straight line, wherein the first update pixel is any one of the plurality of update pixels;

[0030] The order of each of the update pixels is determined according to a vertical distance from each of the update pixels to the target straight line.

[0031] Specifically, since the probability of updating the boundary pixels is low, the target straight line is formed according to the position information of the first boundary pixel and the second boundary pixel selected from the multiple update pixels. The target straight line is the middle line in the area composed of the update pixels. In this way, the update pixels are sorted according to the distance between the update pixels and the target straight line, which can facilitate the selection of pixels with low update probability to write back to the memory, reduce the subsequent access probability to the memory, and save memory bandwidth.

[0032] In an optional embodiment, a vertical distance of a second update pixel is greater than a vertical distance of a third update pixel, and the second update pixel is sorted after the third update pixel, wherein the second update pixel and the third update pixel are both update pixels among the plurality of update pixels.

[0033] Specifically, the larger the vertical distance is, the lower the update probability is. Through the rules of this solution, it is convenient to select pixels with lower update probability and write them back to the memory, thereby reducing the subsequent access probability to the memory, that is, saving memory bandwidth.

[0034] In an optional implementation, after completing the display update operation of the current frame, the method further includes:

[0035] Obtaining a first parameter value, a second parameter value, and a third parameter value, wherein the first parameter value is the number of consecutive times that a write data operation is performed in the target memory, the second parameter value is the number of write requests, and the third parameter value is the number of consecutive times that a write data operation is performed in the memory before switching the write channel;

[0036] Determining a bandwidth index value of the memory according to the first parameter value, the second parameter value and the third parameter value;

[0037] Determining whether to perform a write-back operation according to the bandwidth indicator value and a third preset threshold;

[0038] When it is determined to execute the write-back operation, the image data of the target eliminated pixel is written back to the memory.

[0039] Specifically, the bandwidth index value is calculated according to the first parameter value, the second parameter value and the third parameter value, and further according to the bandwidth index value and the third preset threshold value, it can be determined whether the remaining bandwidth of the memory meets the write-back requirement, and the write-back operation is performed when the write-back requirement is met. In this way, the impact of the write-back operation on other memory services can be avoided.

[0040] In an optional implementation, the bandwidth index value of the memory is determined according to the first parameter value, the second parameter value, and the third parameter value, using the following expression:

[0041]

[0042] Wherein, L is the bandwidth indicator value, M is the first parameter value, N is the second parameter value, and K is the third parameter value.

[0043] In an optional implementation manner, the flag information includes a plurality of bits, and the value of a first bit among the plurality of bits is used to indicate whether the image data in the total storage data in which the first bit is located is written back to the memory;

[0044] After writing the image data of the target eliminated pixels back to the memory, the method further comprises:

[0045] The first bit of the target eliminated pixel is modified from a first value to a second value, wherein the first value is used to indicate that the image data in the total stored data in which it is located has not been written back to the memory, and the second value is used to indicate that the image data in the total stored data in which it is located has been written back to the memory.

[0046] Specifically, the flag bit usually occupies a small space, so using the flag bit to manage the state does not occupy a large amount of memory resources, which is very beneficial when the target memory has a small storage space. In addition, after writing the image data back to the memory, the consistency of the data can be ensured by modifying the corresponding flag bit.

[0047] In an optional implementation, the value of the second bit among the plurality of bits is used to indicate whether the image data in the total stored data in which it is located is the latest image data of the corresponding pixel in the current frame, and the value of the third bit among the plurality of bits is used to indicate whether the image data in the total stored data in which it is located is read;

[0048] After completing the data writing operation of the current frame, the method further includes:

[0049] When receiving a display update request for the current frame, acquiring position information of all pixels constituting an image of the current frame;

[0050] Determining whether the target memory stores target total storage data corresponding to the target pixel according to the position information of the target pixel, wherein the target pixel is any pixel among all pixels constituting the image of the current frame;

[0051] When it is determined that the target total storage data is stored in the target memory, determining whether the value of the second bit in the flag information of the target total storage data is a third value, wherein the third value is used to indicate that the image data in the total storage data where the third value is located is the latest image data of the target pixel in the current frame;

[0052] When it is determined that the value of the second bit in the flag information of the target total storage data is the third value, reading the image data in the target total storage data;

[0053] The third bit in the flag information of the target total storage data is changed from a fourth value to a fifth value, wherein the fourth value is used to indicate that the image data in the total storage data in which it is located has not been read, and the fifth value is used to indicate that the image data in the total storage data in which it is located has been read.

[0054] Specifically, by confirming the latest status of the data through the flag information, it can be ensured that the data read each time is the latest, which helps to maintain data consistency and prevent display errors caused by the use of outdated data.

[0055] In an optional implementation, when it is determined that the target total storage data is not stored in the target memory, or the value of the second bit in the flag information of the target total storage data is not the third value, the method further includes:

[0056] The image data of the target pixel is read from the memory according to the position information of the target pixel.

[0057] Specifically, when the latest image data cannot be read from the target memory, it can be read from the internal memory to ensure the integrity of the displayed image.

[0058] In an optional implementation, determining whether to perform a data transmission channel switching operation according to the number of write requests and a second preset threshold includes:

[0059] Determining whether the number of write requests is greater than or equal to the second preset threshold;

[0060] When it is determined that the number of write requests is greater than or equal to the second preset threshold, determining to perform a data transmission channel switching operation;

[0061] or,

[0062] When it is determined that the number of write requests is less than the second preset threshold, it is determined not to perform the data transmission channel switching operation.

[0063] Specifically, by comparing the number of write requests with the second preset threshold, it can be determined whether the bandwidth of the memory is sufficient. If it is insufficient, the data transmission channel can be switched in time to ensure timely update of the image data.

[0064] In an optional implementation, before writing the total storage data of each update pixel to the target memory through the second data transmission channel, the method further includes:

[0065] Determining whether old storage data corresponding to a fourth update pixel is stored in the target memory according to position information of the fourth update pixel, wherein the fourth update pixel is any update pixel of the at least one update pixel;

[0066] When it is determined that old storage data corresponding to the fourth update pixel is stored in the target memory, the old storage data corresponding to the fourth update pixel in the target memory is deleted.

[0067] Specifically, before writing data each time, old stored data is deleted first, so that storage space can be vacated in the target memory in time to facilitate subsequent data writing operations.

[0068] In a second aspect, the present invention provides a data transmission channel switching device, the device is applied to a video memory data reading and writing system, the video memory data reading and writing system includes a video transmission standard controller and a memory, the video transmission standard controller includes a data processor and a target memory, the device includes:

[0069] a data writing module, configured to execute a data writing operation corresponding to the write request in the memory through a first data transmission channel each time a write request is received in a current bandwidth detection cycle, wherein the first data transmission channel is a write channel between the data processor and the memory;

[0070] An acquisition module, used for acquiring the operation duration of the data writing operation;

[0071] A statistics module, used for counting the number of write requests whose operation duration is greater than or equal to a first preset threshold in the current bandwidth detection cycle;

[0072] A determination module, configured to determine whether to perform a data transmission channel switching operation according to the number of write requests and a second preset threshold;

[0073] A switching module is used to switch the channel currently occupied by write data from the first data transmission channel to the second data transmission channel when it is determined to perform a channel switching operation, wherein the second data transmission channel is a write channel between the data processor and the target memory.

[0074] In a third aspect, the present invention provides a computer device, comprising: a memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, and the processor executing the data transmission channel switching method of the first aspect or any corresponding embodiment thereof by executing the computer instructions.

[0075] In a fourth aspect, the present invention provides a computer-readable storage medium having computer instructions stored thereon, the computer instructions being used to enable a computer to execute the data transmission channel switching method of the first aspect or any corresponding embodiment thereof.

[0076] In a fifth aspect, the present invention provides a computer program product, comprising computer instructions, wherein the computer instructions are used to enable a computer to execute the data transmission channel switching method of the first aspect or any corresponding embodiment thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0077] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the related technologies, the drawings required for use in the specific embodiments or the related technical descriptions will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0078] Figure 1 is a schematic diagram of the architecture of a video memory data reading and writing system according to an embodiment of the present invention;

[0079] Figure 2 is a schematic diagram of the architecture of another video memory data reading and writing system according to an embodiment of the present invention;

[0080] Figure 3 is a schematic flow chart of a data transmission channel switching method according to an embodiment of the present invention;

[0081] Figure 4 is a schematic flow chart of a method for writing data according to an embodiment of the present invention;

[0082] Figure 5 is a schematic structural diagram of total storage data of a pixel according to an embodiment of the present invention;

[0083] Figure 6 is a flow chart of a data write-back method according to an embodiment of the present invention;

[0084] Figure 7 is a schematic diagram of changes in a display screen according to an embodiment of the present invention;

[0085] Figure 8 is a schematic diagram of another display screen change according to an embodiment of the present invention;

[0086] Fig. 9 is a flow chart of a method for reading data according to an embodiment of the present invention;

[0087] Fig.10 is a structural block diagram of a data transmission channel switching device according to an embodiment of the present invention;

[0088] Fig.11 It is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0089] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0090] The embodiment of the present invention provides a video memory data reading and writing system, such as Figure 1 As shown, the video memory data reading and writing system may include a central processing unit (CPU), a video graphics array (VGA) controller and a memory. Among them, the CPU may be the host side, and may send a write request or a read request to the VGA controller. The VGA controller may include a selector, a data processor and a target memory. The selector may be a multiplexer, which may be used to switch data transmission channels. The target memory may be a cache, and the cache may include multiple storage units, and one storage unit may store the total storage data of one or more pixels. The memory may be a double data rate (DDR) memory. The memory may include multiple storage spaces, and the multiple storage spaces include a video memory space for storing image data. The CPU may be connected to the VGA controller, and the VGA controller may be connected to the memory.

[0091] In some optional implementations, the data processor may be composed of modules that perform multiple different functions and multiple data buffers, such as Figure 2As shown, the data processor may specifically include: a control module, a DDR bandwidth monitoring module, a position information matching module, an image data write back module, an eliminated pixel selection module and multiple buffers, etc. Each module may be formed by a corresponding integrated circuit. Multiple buffers may include a write DDR buffer and a read DDR buffer, etc. Among them, the DDR bandwidth monitoring module is used to detect whether the bandwidth of the first data transmission channel is sufficient. The control module can be used to send control instructions to other modules. The selector is used to switch the data transmission channel according to the control instruction of the control module. The position information matching module is used to perform pixel matching operations when updating or reading image data from the memory or the target memory. The image data write back module is used to perform data write back operations according to the order and position information of the pixels in the first-in first-out (FIFO) list. The eliminated pixel selection module is used to determine the eliminated module and add the position information of the eliminated module to the FIFO list.

[0092] The embodiment of the present invention provides a data transmission channel switching method, which ensures that image data is updated in a timely manner without reducing the quality of the image data by timely switching the data transmission channel.

[0093] According to an embodiment of the present invention, an embodiment of a data transmission channel switching method is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0094] In this embodiment, a data transmission channel switching method is provided, which can be executed by a data processor in the above-mentioned video memory data reading and writing system. Figure 3 is a flow chart of a data transmission channel switching method according to an embodiment of the present invention. Figure 3 As shown, the process includes the following steps:

[0095] Step S301: Whenever a write request is received in the current bandwidth detection cycle, a write data operation corresponding to the write request is executed in the memory through the first data transmission channel.

[0096] The first data transmission channel is a write channel between the data processor and the memory, and more specifically, can be considered as a write channel between the selector and the memory. The write request may include position information and image data corresponding to at least one pixel.

[0097] Specifically, when the data processor performs a data write operation in the memory, it can periodically detect whether the bandwidth of the first data transmission channel is sufficient. That is, in each bandwidth detection cycle, when the data processor receives a write request, it can parse the write request, obtain the position information and image data corresponding to the pixel, and write them into the memory through the first data transmission channel.

[0098] Step S302, obtaining the operation duration of the data writing operation.

[0099] Specifically, the data processor may set two counters, namely, a first counter and a second counter. After receiving a write request, the data processor may first send an awvalid signal to the memory and start the first counter to start timing. After the write operation is completed, the data processor may receive a bresp response signal and stop timing the first counter to obtain the timing duration, that is, the operation duration of the write data operation.

[0100] Step S303: Count the number of write requests whose operation duration is greater than or equal to a first preset threshold in the current bandwidth detection cycle.

[0101] Specifically, each time the data processor obtains a timing duration, it can determine whether the timing duration is greater than or equal to the first preset threshold value. If so, it can be considered that the processing of the write request has timed out, and at this time, the count value of the second counter is increased by 1. After the current bandwidth detection cycle ends, the count value of the second counter can represent the number of write requests that have timed out in a bandwidth detection cycle.

[0102] Step S304: determining whether to perform a data transmission channel switching operation according to the number of write requests and a second preset threshold.

[0103] Specifically, the data processor can determine whether the number of write requests is greater than or equal to a second preset threshold. When it is determined that the number of write requests is greater than or equal to the second preset threshold, it indicates that the memory bandwidth is insufficient in the recent period of time and write operations from other components are being performed. At this time, it can be determined to perform a data transmission channel switching operation. Alternatively, when the data processor determines that the number of write requests is less than the second preset threshold, it indicates that the current memory bandwidth is sufficient and there is no need to perform a data transmission channel switching operation.

[0104] Step S305 , when it is determined to perform a channel switching operation, the channel currently occupied by the write data is switched from the first data transmission channel to the second data transmission channel.

[0105] The second data transmission channel is a write channel from the data processor to the target memory, and more specifically, can be considered as a write channel from the selector to the target memory.

[0106] Specifically, when it is determined to perform a channel switching operation, the data processor can transmit a control signal to the selector to close the switch in the selector corresponding to the first data transmission channel and open the switch in the selector corresponding to the second data transmission channel to complete the operation of the data transmission channel.

[0107] In the data transmission channel switching method provided in this embodiment, in each bandwidth detection cycle, the data processor can detect whether the bandwidth of the first data transmission channel is sufficient by counting the number of write requests whose operation duration is greater than the first preset threshold and the second preset threshold. If the bandwidth of the first data transmission channel is insufficient, the data processor can switch to the second data transmission channel in time to complete the update of the image data in time. In this way, there is no need to reduce the frame rate or resolution of the image data to ensure the timely update of the image data, that is, while ensuring the timely update of the image data, the display effect can be guaranteed.

[0108] After the write channel is switched from the first data transmission channel to the second data transmission channel, the data processor can perform a write data operation corresponding to the write request in the target memory according to the received write request. Based on the above embodiments, this embodiment provides a data writing method. Figure 4 is a flow chart of a method for writing data according to an embodiment of the present invention. Figure 4 As shown, the process includes the following steps:

[0109] Step S401 , during the data writing operation of the current frame, each time a write request is received, the write request is parsed to obtain position information corresponding to at least one update pixel and image data corresponding to each update pixel.

[0110] The position information may be coordinate information of the updated pixel in the display screen, the horizontal coordinate in the coordinate information may be used to indicate the row number of the updated pixel, and the vertical coordinate in the coordinate information may be used to indicate the column number of the updated pixel.

[0111] Specifically, during the data writing operation of each frame, the CPU may only update the image data of some pixels. In this way, the data processor may receive one or more write requests from the CPU, and each time a write request is received, the data processor may parse the write request to obtain the position information and image data corresponding to the one or more updated pixels.

[0112] Step S402, generating flag information corresponding to each updated pixel.

[0113] The flag information is used to indicate the operation state of updating the pixel. The flag information may include a first bit, a second bit and a third bit.

[0114] The value of the first bit can be used to indicate whether the image data in the total storage data where it is located is written back to the memory. The value of the first bit can be a first value or a second value, the first value can be used to indicate that the image data in the total storage data where it is located is not written back to the memory, and the second value can be used to indicate that the image data in the total storage data where it is located has been written back to the memory.

[0115] The value of the second bit is used to indicate whether the image data in the total stored data where it is located is the latest image data of the corresponding pixel in the current frame. The value of the second bit can be the third value or the sixth value. The third value can be used to indicate that the image data in the total stored data where it is located is the latest image data of the corresponding pixel in the current frame. The sixth value can be used to indicate that the image data in the total stored data where it is located is not the latest image data of the corresponding pixel in the current frame.

[0116] The value of the third bit can be used to indicate whether the image data in the total storage data where it is located has been read. The value of the third bit can be a fourth value or a fifth value. The fourth value can be used to indicate that the image data in the total storage data where it is located has not been read, and the fifth value can be used to indicate that the image data in the total storage data where it is located has been read.

[0117] For example, the first value, the third value, and the fourth value may all be 0, and the second value, the fifth value, and the sixth value may all be 1.

[0118] In some optional implementations, the values ​​of the bits other than the first bit, the second bit and the third bit in the flag information are used to indicate the number of bytes of the image data in the total stored data.

[0119] Step S403, constructing total storage data corresponding to each updated pixel according to the position information, image data and flag information corresponding to each updated pixel.

[0120] Specifically, for each updated pixel, the data processor may sequentially splice the position information, flag information, and image data of the updated pixel to obtain the total storage data corresponding to the updated pixel.

[0121] like Figure 5As shown, the total stored data can be stored in the following data structure, where the high 32 bits (between 71 and 101 bits) are the pixel location information, the middle 8 bits are the flag information (between 64 and 70 bits), and the other bits are the image data (0 to 63 bits). For example, bit70 can be the first bit mentioned above, bit69 can be the third bit mentioned above, bit69 can be the second bit mentioned above, and the other bits in the flag information can be used to indicate the number of valid bytes of the image data of the pixel, that is, the length of the image data.

[0122] Step S404: writing the total storage data of each updated pixel into the target memory through the second data transmission channel.

[0123] Specifically, the data processor may write the total storage data of each updated pixel in the current frame into the target memory through the second data transmission channel.

[0124] In some optional implementations, before step S404, the data processor may first delete part of the data in the target memory, which may be specifically as follows:

[0125] Step 1: Determine whether old storage data corresponding to the fourth update pixel is stored in the target memory according to the position information of the fourth update pixel.

[0126] The fourth update pixel is any update pixel among the at least one update pixel.

[0127] Step 2: when it is determined that the target memory stores old storage data corresponding to the fourth update pixel, the old storage data corresponding to the fourth update pixel in the target memory is deleted.

[0128] Specifically, since during the data writing operation of each frame, the image data of only some pixels may change, while the image data of some pixels may not change, before each write operation, it can be determined based on the position information of the updated pixel whether the target memory stores old storage data corresponding to the target update pixel. If so, the old storage data can be deleted. If not, the write data operation can be performed directly.

[0129] In some optional embodiments, since the old storage data of the fourth update pixel may be stored in the memory, the data processor may also determine whether there is old storage data corresponding to the fourth update pixel in the memory. If so, the old storage data corresponding to the fourth update pixel in the memory may be deleted.

[0130] In the data writing method provided in this embodiment, the data processor stores pixel-related data according to a certain data structure, including position information, flag information and image data. Through the flag information, the data processor can timely understand the operation status of the corresponding updated pixel according to the flag information and process it in time. That is, the flag information can facilitate the management of the updated pixel.

[0131] Since the storage space of the target memory is limited, if the current frame needs to update a lot of image data, it may not be possible to write the image data into the target memory in time. Therefore, the data processor can write the image data of some pixels back to the memory after completing the display update operation of the current frame, and free up some storage space in the target memory in time. Based on the above embodiment, this embodiment provides a data write-back method. Figure 6 is a flow chart of a data write-back method according to an embodiment of the present invention. Figure 6 As shown, the process includes the following steps:

[0132] Step S601, after completing the data writing operation of the current frame, obtaining the receiving order and position information of each updated pixel among a plurality of updated pixels updated in the current frame.

[0133] Specifically, in general, when the display screen of the display changes between adjacent frames, the image window moves between two adjacent regions of interest (ROI) in a preset moving direction. For example, Figure 7 A moving change of an image window in three adjacent frames is given, that is, the image window moves from ROI1 to ROI3. In the process of changing from the first frame to the second frame, the pixels whose image data changes are the collection of ROI1 and ROI2, and in the process of changing from the second frame to the third frame, the pixels whose image data changes are the collection of ROI2 and ROI3. It can be seen that the pixels in the ROI2 area have changed twice. In other words, the probability of pixels changing in the overlapping area is higher, and the probability of changing in the edge part is lower. Since the storage space of the target memory is small and will soon be full, the data processor can move the image data of pixels with a lower probability of change to the memory.

[0134] Before determining pixels with a lower probability of change, the data processor may first obtain the receiving order and position information of all updated pixels in the current frame.

[0135] Step S602 : determining the order of each update pixel among the multiple update pixels according to the receiving order and position information of each update pixel among the multiple update pixels.

[0136] Specifically, the data processor may determine the order of updating pixels according to the following specific steps:

[0137] Step 1: selecting a first boundary pixel and a second boundary pixel from the plurality of update pixels according to a receiving order of each update pixel from the plurality of update pixels.

[0138] The first boundary pixel is the starting pixel of the region formed by the multiple update pixels in the display screen update direction (ie the above-mentioned preset moving direction), and the second boundary pixel is the ending pixel of the region formed by the multiple update pixels in the display screen update direction.

[0139] Step 2: construct a target straight line according to the position information of the first boundary pixel and the position information of the second boundary pixel.

[0140] Step three: determine the vertical distance from the first update pixel to the target straight line according to the position information of the first update pixel and the target straight line.

[0141] The first update pixel is any update pixel among the multiple update pixels.

[0142] Step 4: Determine the order of each of the multiple update pixels according to the vertical distance from each of the multiple update pixels to the target straight line.

[0143] Specifically, in the data writing operation of the current frame, the data processor may record the receiving order of each updated pixel, determine the updated pixel received first in the current frame as the first boundary pixel, and determine the updated pixel received last in the current frame as the second boundary pixel. Figure 8 As shown, the update direction of the display image is from the lower left corner to the upper right corner, the A pixel is the first boundary pixel, and the B pixel is the second boundary pixel.

[0144] The data processor may determine the target straight line (for example, the function expression y=ax+b corresponding to the target straight line) according to the position information of the first boundary pixel and the second boundary pixel, and further calculate the vertical distance from each update pixel to the target straight line according to the position information of each update pixel and the function expression corresponding to the target straight line. Then, the data processor may sort the update pixels from large to small according to the vertical distance.

[0145] Step S603, determining a target eliminated pixel according to the ranking of each updated pixel among the multiple updated pixels.

[0146] Specifically, the data processor may determine the update pixels ranked before the preset ranking value as the target elimination pixels, that is, determine a preset number of update pixels with a larger vertical distance as the target elimination pixels.

[0147] Step S604, after completing the display update operation of the current frame, writing the image data of the target eliminated pixels back to the memory.

[0148] Specifically, since the update probability of the target eliminated pixel is low, the target eliminated pixel can be written back to the value memory, so that the number of accesses to the memory by the subsequent data processor can be reduced, and the impact on the memory bandwidth can be reduced.

[0149] In some optional implementations, after completing the display update operation of the current frame, the data processor may first determine whether the bandwidth of the memory is sufficient, and then perform the write-back operation if the bandwidth is sufficient. Accordingly, the specific processing may be as follows:

[0150] Step 1: Obtain a first parameter value, a second parameter value, and a third parameter value.

[0151] The first parameter value may be the number of consecutive times that write data operations are performed in the target memory, the second parameter value may be the number of write requests, and the third parameter value may be the number of consecutive times that write data operations are performed in the memory before switching the write channel.

[0152] Step 2: Determine the bandwidth index value of the memory according to the first parameter value, the second parameter value and the third parameter value.

[0153] Step 2 can be expressed as follows:

[0154]

[0155] Wherein, L is the bandwidth index value, M is the first parameter value, N is the second parameter value, and K is the third parameter value.

[0156] Step three: determine whether to perform a write-back operation based on the bandwidth indicator value and a third preset threshold.

[0157] The third preset threshold may be 0.5.

[0158] Specifically, the data processor can determine whether the bandwidth index value is greater than a third preset threshold. When it is determined that the bandwidth index value is greater than the third preset threshold, it can be determined to perform a write-back operation, or, when it is determined that the bandwidth index value is less than or equal to the third preset threshold, it can be determined not to perform a write-back operation.

[0159] Step 4: When it is determined to perform a write-back operation, the image data of the target eliminated pixels is written back to the memory.

[0160] In some optional implementations, after writing the image data of the target eliminated pixel back to the memory, the first bit of the target eliminated pixel is modified from the first value to the second value. In this way, when receiving a new write request, the data processor can overwrite the total stored data of the target eliminated pixel.

[0161] In some optional embodiments, the data processor can generate a FIFO list according to the position information and order of each updated pixel in the multiple updated pixels after determining the order of each updated pixel in the multiple updated pixels. In the process of writing data of the next frame corresponding to the current frame, each time a write request is received, the write request is parsed to obtain the target number of updated pixels included in the write request. Then, according to the target number, the position information corresponding to the target number of pixels in the top order is determined in the FIFO list, and then, the data processor can determine the total storage data corresponding to the target data pixels in the target memory according to the position information corresponding to the target number of pixels, and delete them. In this way, the target memory can be vacated in time, and the image data written back are all pixels with a low probability of updating, which can reduce the subsequent data processor's access to the memory and reduce the impact on the memory bandwidth. In addition, there is no need to wait until the target memory is full to perform the above steps to avoid the problem of image data that cannot be updated to the target memory.

[0162] In the data write-back method provided in this embodiment, the larger the vertical distance is, the lower the update probability is. Through the rules of this scheme, it is convenient to select pixels with lower update probability to write back to the memory, thereby reducing the subsequent access probability to the memory, that is, saving memory bandwidth.

[0163] Based on the above embodiments, this embodiment provides a method for reading data. Fig. 9 is a flow chart of a method for reading data according to an embodiment of the present invention. Fig. 9 As shown, the process includes the following steps:

[0164] Step S901, when a display update request of the current frame is received, the position information of all pixels constituting the image of the current frame is obtained.

[0165] Step S902: Determine whether target total storage data corresponding to the target pixel is stored in the target memory according to the position information of the target pixel.

[0166] The target pixel is any pixel among all pixels constituting the image of the current frame.

[0167] Step S903, when it is determined that the target total storage data is stored in the target memory, determine whether the value of the second bit in the flag information of the target total storage data is a third value.

[0168] Step S904: when it is determined that the value of the second bit in the flag information of the target total storage data is the third value, the image data in the target total storage data is read.

[0169] Step S905: modify the third bit in the flag information of the target total storage data from the fourth value to the fifth value.

[0170] Step S906, when it is determined that the target total storage data is not stored in the target memory, or the value of the second bit in the flag information of the target total storage data is not the third value, read the image data of the target pixel from the memory according to the position information of the target pixel.

[0171] Specifically, the data processor obtains the position information corresponding to all pixels of the image each time a display update request is received. The data processor can traverse each pixel of the image, and each time a pixel is traversed, it determines whether there is total storage data of the pixel in the target memory according to the position information of the pixel. If there is no total storage data of the pixel, the corresponding image data can be read from the video memory. If not, if there is total storage data of the pixel, it can be determined whether the value of the second bit in the flag information of the total storage data is the third value. If it is the third value, the image data in the total storage data can be read. If it is the sixth value, the corresponding image data can be read from the video memory.

[0172] The data reading method provided in this embodiment confirms the latest status of data through flag information, which can ensure that the data read each time is the latest, which helps to maintain data consistency and prevent display errors caused by using outdated data.

[0173] In this embodiment, a data transmission channel switching device is also provided, which is used to implement the above-mentioned embodiments and preferred implementation modes, and the descriptions that have been made will not be repeated. As used below, the term "module" can implement a combination of software and / or hardware of a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.

[0174] This embodiment provides a data transmission channel switching device, such as Fig.10 As shown, including:

[0175] The data writing module 1001 is used to execute a data writing operation corresponding to the write request in the memory through the first data transmission channel every time a write request is received in the current bandwidth detection cycle, wherein the first data transmission channel is a write channel between the data processor and the memory;

[0176] An acquisition module 1002 is used to acquire the operation duration of a data writing operation;

[0177] A statistics module 1003 is used to count the number of write requests whose operation duration is greater than or equal to a first preset threshold in the current bandwidth detection cycle;

[0178] A determination module 1004, configured to determine whether to perform a data transmission channel switching operation according to the number of write requests and a second preset threshold;

[0179] The switching module 1005 is used to switch the channel currently occupied by write data from the first data transmission channel to the second data transmission channel when it is determined to perform a channel switching operation, wherein the second data transmission channel is a write channel between the data processor and the target memory.

[0180] In some optional implementations, the data writing module 1001 is further used to:

[0181] During the data writing operation of the current frame, each time a write request is received, the write request is parsed to obtain position information corresponding to at least one updated pixel and image data corresponding to each updated pixel;

[0182] Generate flag information corresponding to each updated pixel, wherein the flag information is used to indicate an operation state of the updated pixel;

[0183] According to the position information, image data and flag information corresponding to each updated pixel, the total storage data corresponding to each updated pixel is formed;

[0184] The total storage data of each updated pixel is written to the target memory through the second data transmission channel.

[0185] In some optional implementations, the data writing module 1001 is further used to:

[0186] After completing the data writing operation of the current frame, obtaining the receiving order and position information of each updated pixel among the multiple updated pixels updated in the current frame;

[0187] Determining the order of each of the plurality of update pixels according to the order and position information of each of the plurality of update pixels;

[0188] Determining a target elimination pixel according to the ranking of each updated pixel among the plurality of updated pixels;

[0189] After completing the display update operation of the current frame, the image data of the target eliminated pixels are written back to the memory.

[0190] In some optional implementations, the data writing module 1001 is specifically used for:

[0191] Selecting a first boundary pixel and a second boundary pixel from the plurality of update pixels according to a receiving order of each update pixel from the plurality of update pixels;

[0192] According to the position information of the first boundary pixel and the position information of the second boundary pixel, a target straight line is formed;

[0193] Determine a vertical distance from the first update pixel to the target straight line according to position information of the first update pixel and the target straight line, wherein the first update pixel is any one of the plurality of update pixels;

[0194] The order of each of the plurality of update pixels is determined according to a vertical distance from each of the plurality of update pixels to the target straight line.

[0195] In some optional embodiments, the vertical distance of the second update pixel is greater than the vertical distance of the third update pixel, and the second update pixel is sorted after the third update pixel, wherein the second update pixel and the third update pixel are both update pixels among multiple update pixels.

[0196] In some optional implementations, the data writing module 1001 is further used to:

[0197] After completing the display update operation of the current frame, obtaining a first parameter value, a second parameter value, and a third parameter value, wherein the first parameter value is the number of consecutive times of performing a write data operation in the target memory, the second parameter value is the number of write requests, and the third parameter value is the number of consecutive times of performing a write data operation in the memory before switching the write channel;

[0198] Determine a bandwidth index value of the memory according to the first parameter value, the second parameter value and the third parameter value;

[0199] Determining whether to perform a write-back operation according to the bandwidth indicator value and a third preset threshold;

[0200] When it is determined to perform a write-back operation, the image data of the target eliminated pixels is written back to the memory.

[0201] In some optional implementations, the bandwidth index value of the memory is determined according to the first parameter value, the second parameter value, and the third parameter value, using the following expression:

[0202]

[0203] Wherein, L is the bandwidth index value, M is the first parameter value, N is the second parameter value, and K is the third parameter value.

[0204] In some optional implementations, the flag information includes multiple bits, and the value of the first bit among the multiple bits is used to indicate whether the image data in the total storage data where the first bit is located is written back to the memory;

[0205] The apparatus further includes a modification module 1006, configured to:

[0206] The first bit of the target eliminated pixel is modified from a first value to a second value, wherein the first value is used to indicate that the image data in the total stored data in which it is located has not been written back to the memory, and the second value is used to indicate that the image data in the total stored data in which it is located has been written back to the memory.

[0207] In some optional embodiments, the value of the second bit in the plurality of bits is used to indicate whether the image data in the total stored data in which it is located is the latest image data of the corresponding pixel in the current frame, and the value of the third bit in the plurality of bits is used to indicate whether the image data in the total stored data in which it is located is read;

[0208] The device further comprises a reading module 1007, which is used to:

[0209] After completing the data writing operation of the current frame, when receiving a display update request of the current frame, obtaining position information of all pixels constituting the image of the current frame;

[0210] Determining whether target total storage data corresponding to the target pixel is stored in the target memory according to the position information of the target pixel, wherein the target pixel is any pixel among all pixels constituting the image of the current frame;

[0211] When it is determined that the target total storage data is stored in the target memory, determining whether the value of the second bit in the flag information of the target total storage data is a third value, wherein the third value is used to indicate that the image data in the total storage data where the third value is located is the latest image data of the target pixel in the current frame;

[0212] When it is determined that the value of the second bit in the flag information of the target total storage data is the third value, reading the image data in the target total storage data;

[0213] Modification module 1006 is further used for:

[0214] The third bit in the flag information of the target total storage data is changed from the fourth value to the fifth value, wherein the fourth value is used to indicate that the image data in the total storage data where it is located has not been read, and the fifth value is used to indicate that the image data in the total storage data where it is located has been read.

[0215] In some optional implementations, the reading module 1007 is further configured to:

[0216] When it is determined that the target total storage data is not stored in the target memory, or the value of the second bit in the flag information of the target total storage data is not the third value, the image data of the target pixel is read from the memory according to the position information of the target pixel.

[0217] In some optional implementations, the determination module 1004 is specifically configured to:

[0218] Determining whether the number of write requests is greater than or equal to a second preset threshold;

[0219] When it is determined that the number of write requests is greater than or equal to a second preset threshold, determining to perform a data transmission channel switching operation;

[0220] or,

[0221] When it is determined that the number of write requests is less than the second preset threshold, it is determined not to perform the data transmission channel switching operation.

[0222] In some optional implementations, the device further includes a deletion module 1008, configured to:

[0223] Determining whether old storage data corresponding to a fourth update pixel is stored in the target memory according to position information of the fourth update pixel, wherein the fourth update pixel is any update pixel of the at least one update pixel;

[0224] When it is determined that old storage data corresponding to the fourth update pixel is stored in the target memory, the old storage data corresponding to the fourth update pixel in the target memory is deleted.

[0225] The further functional description of each of the above modules and units is the same as that of the above corresponding embodiments and will not be repeated here.

[0226] The data transmission channel switching device in this embodiment is presented in the form of a functional unit, where the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that executes one or more software or fixed programs, and / or other devices that can provide the above functions.

[0227] The embodiment of the present invention also provides a computer device having the above Fig.10 The data transmission channel switching device shown.

[0228] See also Fig.11 , Fig.11 is a schematic diagram of the structure of a computer device provided by an optional embodiment of the present invention, such as Fig.11As shown, the computer device includes: one or more processors 1110, memory 1120, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Each component utilizes different buses to communicate with each other, and can be installed on a common mainboard or installed in other ways as needed. The processor can process the instructions executed in the computer device, including instructions stored in or on the memory to display the graphical information of the GUI on an external input / output device (such as, a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Fig.11 A processor 1110 is taken as an example.

[0229] The processor 1110 may be a central processing unit, a network processor or a combination thereof. The processor 1110 may further include a hardware integrated circuit. The hardware integrated circuit may be a dedicated integrated circuit, a programmable logic device or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable logic gate array, a general purpose array logic or any combination thereof.

[0230] The memory 1120 stores instructions executable by at least one processor 1110, so that the at least one processor 1110 executes the method shown in the above embodiment.

[0231] The memory 1120 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created according to the use of the computer device, etc. In addition, the memory 1120 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 1120 may optionally include a memory remotely arranged relative to the processor 1110, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0232] The memory 1120 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid state drive; the memory 1120 may also include a combination of the above types of memory.

[0233] The computer device also includes a communication interface 1130 for the computer device to communicate with other devices or a communication network.

[0234] The embodiment of the present invention also provides a computer-readable storage medium. The method according to the embodiment of the present invention can be implemented in hardware, firmware, or can be implemented as a computer code that can be recorded in a storage medium, or can be implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and will be stored in a local storage medium through a network download, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state hard disk, etc.; further, the storage medium can also include a combination of the above types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor, or hardware, the method shown in the above embodiment is implemented.

[0235] A part of the present invention may be applied as a computer program product, such as a computer program instruction, which, when executed by a computer, can call or provide the method and / or technical solution according to the present invention through the operation of the computer. Those skilled in the art should understand that the existence of the computer program instruction in a computer-readable medium includes, but is not limited to, a source file, an executable file, an installation package file, etc., and accordingly, the way in which the computer program instruction is executed by the computer includes, but is not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Here, the computer-readable medium may be any available computer-readable storage medium or communication medium accessible to the computer.

[0236] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A data transmission channel switching method, characterized in that: The method is applied to a video memory data reading and writing system, the video memory data reading and writing system comprises a video transmission standard controller and a memory, the video transmission standard controller comprises a data processor and a target memory, the method is executed by the data processor, and the method comprises: Whenever a write request is received in the current bandwidth detection cycle, a write data operation corresponding to the write request is performed in the memory through a first data transmission channel, wherein the first data transmission channel is a write channel between the data processor and the memory; Obtaining the operation duration of the data writing operation; Counting the number of write requests whose operation duration is greater than or equal to a first preset threshold in the current bandwidth detection cycle; Determining whether to perform a data transmission channel switching operation according to the number of write requests and a second preset threshold; When it is determined to perform a channel switching operation, the channel currently occupied by the write data is switched from the first data transmission channel to the second data transmission channel, wherein the second data transmission channel is a write channel between the data processor and the target memory; During the data writing operation of the current frame, each time a write request is received, the write request is parsed to obtain position information corresponding to at least one update pixel and image data corresponding to each update pixel; Generate flag information corresponding to each of the update pixels, wherein the flag information is used to indicate an operation state of the update pixel; According to the position information, the image data and the flag information corresponding to each of the update pixels, the total storage data corresponding to each of the update pixels is formed; The total storage data of each of the update pixels is written to the target memory through the second data transmission channel.

2. The method according to claim 1, characterized in that The method further comprises: After completing the data writing operation of the current frame, obtaining the receiving order and position information of each of the multiple update pixels updated in the current frame; Determining the order of each of the update pixels in the plurality of update pixels according to the receiving order and position information of each of the update pixels in the plurality of update pixels; Determining a target eliminated pixel according to the ranking of each of the updated pixels among the plurality of updated pixels; After completing the display update operation of the current frame, the image data of the target eliminated pixels are written back to the memory.

3. The method according to claim 2, characterized in that The step of determining the order of each of the update pixels according to the receiving order and position information of each of the update pixels comprises: Selecting a first boundary pixel and a second boundary pixel from the plurality of update pixels according to a receiving order of each of the plurality of update pixels; constructing a target straight line according to the position information of the first boundary pixel and the position information of the second boundary pixel; Determine a vertical distance from the first update pixel to the target straight line according to position information of the first update pixel and the target straight line, wherein the first update pixel is any one of the plurality of update pixels; The order of each of the update pixels is determined according to a vertical distance from each of the update pixels to the target straight line.

4. The method according to claim 3, characterized in that A vertical distance of the second update pixel is greater than a vertical distance of the third update pixel, and the second update pixel is arranged after the third update pixel, wherein the second update pixel and the third update pixel are both update pixels among the plurality of update pixels.

5. The method according to claim 2, characterized in that: After completing the display update operation of the current frame, the method further includes: Obtaining a first parameter value, a second parameter value, and a third parameter value, wherein the first parameter value is the number of consecutive times that a write data operation is performed in the target memory, the second parameter value is the number of write requests, and the third parameter value is the number of consecutive times that a write data operation is performed in the memory before switching the write channel; Determining a bandwidth index value of the memory according to the first parameter value, the second parameter value and the third parameter value; Determining whether to perform a write-back operation according to the bandwidth indicator value and a third preset threshold; When it is determined to execute the write-back operation, the image data of the target eliminated pixel is written back to the memory.

6. The method according to claim 5, characterized in that The bandwidth index value of the memory is determined according to the first parameter value, the second parameter value and the third parameter value, using the following expression: Among them, L is the bandwidth indicator value, M is the first parameter value, N is the second parameter value, and K is the third parameter value.

7. The method according to claim 2, characterized in that: The flag information includes a plurality of bits, and the value of the first bit among the plurality of bits is used to indicate whether the image data in the total storage data where the first bit is located is written back to the memory; After writing the image data of the target eliminated pixels back to the memory, the method further comprises: The first bit of the target eliminated pixel is modified from a first value to a second value, wherein the first value is used to indicate that the image data in the total stored data in which it is located has not been written back to the memory, and the second value is used to indicate that the image data in the total stored data in which it is located has been written back to the memory.

8. The method according to claim 7, characterized in that The value of the second bit among the plurality of bits is used to indicate whether the image data in the total stored data in which it is located is the latest image data of the corresponding pixel in the current frame, and the value of the third bit among the plurality of bits is used to indicate whether the image data in the total stored data in which it is located is read; After completing the data writing operation of the current frame, the method further includes: When receiving a display update request for the current frame, acquiring position information of all pixels constituting an image of the current frame; Determining whether the target memory stores target total storage data corresponding to the target pixel according to the position information of the target pixel, wherein the target pixel is any pixel among all pixels constituting the image of the current frame; When it is determined that the target total storage data is stored in the target memory, determining whether the value of the second bit in the flag information of the target total storage data is a third value, wherein the third value is used to indicate that the image data in the total storage data where the third value is located is the latest image data of the target pixel in the current frame; When it is determined that the value of the second bit in the flag information of the target total storage data is the third value, reading the image data in the target total storage data; The third bit in the flag information of the target total storage data is changed from a fourth value to a fifth value, wherein the fourth value is used to indicate that the image data in the total storage data in which it is located has not been read, and the fifth value is used to indicate that the image data in the total storage data in which it is located has been read.

9. The method according to claim 8, characterized in that When it is determined that the target total storage data is not stored in the target memory, or the value of the second bit in the flag information of the target total storage data is not the third value, the method further includes: The image data of the target pixel is read from the memory according to the position information of the target pixel.

10. The method according to any one of claims 1 to 9, characterized in that: The determining whether to perform a data transmission channel switching operation according to the number of write requests and a second preset threshold comprises: Determining whether the number of write requests is greater than or equal to the second preset threshold; When it is determined that the number of write requests is greater than or equal to the second preset threshold, determining to perform a data transmission channel switching operation; or, When it is determined that the number of write requests is less than the second preset threshold, it is determined not to perform the data transmission channel switching operation.

11. The method according to any one of claims 1 to 9, characterized in that: Before writing the total storage data of each updated pixel to the target memory through the second data transmission channel, the method further includes: Determining whether old storage data corresponding to a fourth update pixel is stored in the target memory according to position information of the fourth update pixel, wherein the fourth update pixel is any update pixel of the at least one update pixel; When it is determined that old storage data corresponding to the fourth update pixel is stored in the target memory, the old storage data corresponding to the fourth update pixel in the target memory is deleted.

12. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the data transmission channel switching method described in any one of claims 1 to 11 by executing the computer instructions.

13. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the data transmission channel switching method according to any one of claims 1 to 11.

14. A computer program product, characterized in that The method comprises computer instructions, wherein the computer instructions are used to enable a computer to execute the data transmission channel switching method according to any one of claims 1 to 11.

Images