Chip packaging process

Abstract

The present invention relates to the field of semiconductor packaging technology, and in particular to a chip packaging process. The present invention determines whether there is a risk of solder joints being affected by obtaining the distance between a chip pad and a corresponding substrate pad, determines the moving distance of the lead track in different preset directions through the lead track between the chip pad and the corresponding substrate pad, determines the spacing distance between the chip pad and the last chip pad that completed lead welding, calculates the solder joint affected characterization coefficient of the lead track to determine the affected state of the solder joint, selects the lead bonding adjustment method according to the affected state of the solder joint, and further realizes the calculation and analysis of the lead track of the lead bonding tool required for chips to be packaged with different specifications, the influence of the traction of the lead on the solder joint on the chip pad, and the targeted adjustment of the lead bonding process of the lead bonding tool, thereby improving the quality of lead bonding chip packaging and the connection reliability.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and in particular to a chip packaging process. Background Art

[0002] As the integrated circuit industry is receiving more and more attention from the country, the integration density and production yield of integrated circuits are increasingly attracting the attention of technicians in related fields. Integrated chips of various specifications used in electronic products require general integration requirements. Chips need to be wire bonded to achieve electrical connection and signal communication between the chip and the pins on the substrate. Wire bonding uses metal wires to tightly weld the chip pads to the substrate pads, which has a strong cost advantage in the chip packaging process.

[0003] In the wire bonding process, it is very important to tightly fix the metal lead and the pad at the bonding point. To achieve tight fixation of the metal lead and the pad, it is necessary to control the heating and pressurization of the wire bonding tool. The movement of the wire bonding tool also affects the tightness of the solder joints with different cooling degrees. The improvement of each process link in wire bonding is of great significance to the improvement of chip packaging quality.

[0004] For example, the Chinese patent application: CN116454041A, the invention discloses a wire bonding process chip packaging structure and its preparation method, which relates to the field of semiconductor packaging technology, including a chip, a substrate and a plastic packaging material layer for wrapping the chip, the chip is bonded to the pad of the substrate by a chip mounting adhesive, and also includes a heat dissipation component arranged on the upper surface of the chip, the heat dissipation component is wrapped by the plastic packaging material layer, and its top is exposed outside the plastic packaging material layer. The application has the function of improving the heat dissipation capacity of the chip packaging structure.

[0005] The prior art still has the following problems:

[0006] The prior art does not take into account that in the process of moving the lead from the chip pad to the substrate pad, the traction of the lead by the wire bonding tool causes the loosening of the solder joint between the chip pad and the lead. The prior art cannot calculate and analyze the degree of influence of the traction on the solder joint on the chip pad according to the lead trajectory of the wire bonding tool required for the chips to be packaged with different specifications, and cannot adjust the wire bonding process of the wire bonding tool in a targeted manner, which affects the quality of the wire bonding chip packaging and the connection reliability. Summary of the invention

[0007] To this end, the present invention provides a chip packaging process to overcome the problems in the prior art of being unable to calculate and analyze the degree of influence of the wire traction on the solder joints on the chip pads according to the wire trajectories of the wire bonding tools required for the chips to be packaged with different specifications, and being unable to adjust the wire bonding process of the wire bonding tools in a targeted manner.

[0008] To achieve the above object, the present invention provides a chip packaging process, comprising:

[0009] Step S1, mounting the chip on the substrate;

[0010] Step S2, obtaining the distance between the chip pad on the chip and the corresponding substrate pad to determine whether there is a risk of solder joints being affected between the chip pad and the corresponding substrate pad;

[0011] Step S3, determining the moving distance of the lead track in different preset directions based on the pre-stored lead track between the chip pad and the corresponding substrate pad, and determining the spacing distance between the chip pad and the last chip pad that completed the lead welding, and calculating the affected characterization coefficient of the solder joint of the lead track based on the moving distance and the spacing distance to determine the affected state of the solder joint of the lead track;

[0012] The preset direction includes a first preset direction and a second preset direction, the first preset direction is a direction perpendicular to the plane where the chip is located, and the second preset direction is a direction from the chip pad to the corresponding substrate pad in the plane where the chip is located;

[0013] Step S4, selecting a wire bonding adjustment method based on the affected state of the solder joint;

[0014] The wire bonding adjustment method includes adjusting the interval between wire bonding of the chip pad and the completion of wire bonding of the previous chip pad, or determining a characteristic trajectory point based on the trajectory curvature of the wire trajectory, and determining the pause time of the wire bonding tool at the characteristic trajectory point based on the solder joint influence characterization coefficient;

[0015] Step S5, completing wire bonding.

[0016] Furthermore, the step S2 further includes comparing the distance with a preset distance threshold;

[0017] If the distance is greater than the distance threshold, it is determined that there is a risk of solder joints being affected between the chip pad and the corresponding substrate pad.

[0018] Further, in the step S3, the moving distance of the lead track in different preset directions includes a first moving distance and a second moving distance;

[0019] The first moving distance is a moving distance of the lead track in the first preset direction, and the second moving distance is a moving distance of the lead track in the second preset direction.

[0020] Furthermore, the step S3 further includes calculating the affected characterization coefficient of the solder joint of the lead track according to the following formula;

[0021]

[0022] Wherein, K is the solder joint influence characterization coefficient, D1 is the first moving distance, D2 is the second moving distance, D s is the distance between the chip pad and the last chip pad that has completed wire bonding, D s0 is the preset interval distance reference value, α is the moving distance weight coefficient, and β is the interval distance weight coefficient.

[0023] Furthermore, in step S3, the process of determining the affected state of the solder joint of the lead track is:

[0024] Comparing the solder joint influence characterization coefficient with a preset solder joint influence characterization coefficient comparison value;

[0025] If the solder point influence characterization coefficient is less than or equal to the solder point influence characterization coefficient comparison value, the lead track is determined to be in a solder point affected weak dominant state;

[0026] If the solder point influence characterization coefficient is greater than the solder point influence characterization coefficient comparison value, the lead track is determined to be in a solder point affected dominant state.

[0027] Furthermore, in step S4, the process of selecting the wire bonding adjustment method is as follows:

[0028] If the lead track is in a weak dominant state where the solder joint is affected, adjusting the interval between the lead soldering of the chip pad and the completion of the lead soldering of the previous chip pad;

[0029] If the lead track is in a solder joint affected explicit state, a characteristic track point is determined based on the track curvature of the lead track, and a pause time of the wire bonding tool at the characteristic track point is determined based on the solder joint influence characterization coefficient.

[0030] Furthermore, in the step S4, the interval between wire bonding of the chip pad and wire bonding of the previous chip pad is adjusted based on the solder joint affected characterization coefficient, and the interval is positively correlated with the solder joint affected characterization coefficient.

[0031] Furthermore, the step S4 further includes determining the trajectory curvature of each trajectory point on the lead trajectory, determining the trajectory point corresponding to the maximum value of the trajectory curvature, and determining the trajectory point as the characteristic trajectory point.

[0032] Furthermore, in the step S4, the pause time of the wire bonding tool at the characteristic trajectory point is positively correlated with the affected characterization coefficient of the solder joint.

[0033] Further, in the step S3, the wire trace is a trace for the wire bonding tool to perform wire bonding between the chip pad and the corresponding substrate pad.

[0034] Compared with the prior art, the beneficial effect of the present invention lies in that the present invention determines whether there is a risk of affected solder joints by obtaining the distance between the chip pad and the corresponding substrate pad, determines the moving distance of the lead track in different preset directions through the lead track between the chip pad and the corresponding substrate pad, and determines the spacing distance between the chip pad and the last chip pad that completed lead welding, calculates the solder joint affected characterization coefficient of the lead track to determine the affected state of the solder joint, selects the lead bonding adjustment method according to the affected state of the solder joint, and then realizes the calculation and analysis of the lead track of the lead bonding tool required for the packaged chips of different specifications to determine the degree of influence of the traction of the lead on the solder joints on the chip pad, and the targeted adjustment of the lead bonding process of the lead bonding tool, thereby improving the quality of lead bonding chip packaging and connection reliability.

[0035] In particular, the present invention determines whether there is a risk of solder joints being affected by obtaining the distance between the chip pad and the corresponding substrate pad. Those skilled in the art understand that the greater the distance between the chip pad and the corresponding substrate pad, the longer the lead required, and the longer the time the longer lead is pulled by the wire bonding tool during the welding process, which is more likely to cause the lead at the solder joint on the chip pad to be affected by the traction, causing the solder joint that may not be completely fastened to loosen, causing the risk of cold solder joints. The present invention achieves the screening of lead tracks with the risk of cold solder joints by obtaining the distance between the chip pad and the corresponding substrate pad.

[0036] In particular, the present invention determines the moving distance of the lead track in different preset directions through the lead track. In the actual chip wire bonding process, after the wire bonding tool welds the lead to the chip pad, the metal lead is pulled along the set track toward the substrate pad, so that the metal lead forms an arc lead between the chip pad and the corresponding substrate pad, thereby realizing electrical connection between the chip pad and the corresponding substrate pad. The present invention can obtain the characteristics of the lead track by obtaining the moving distance of the lead track in a direction perpendicular to the plane where the chip is located and the moving distance of the lead track in the direction from the chip pad to the corresponding substrate pad within the plane where the chip is located, thereby facilitating the subsequent analysis of the lead track characteristics.

[0037] In particular, the present invention combines the moving distance of the lead track in different preset directions and the spacing distance between the chip pad and the chip pad of the last chip that has completed lead welding for calculation. In the actual chip lead bonding process, the larger the ratio of the moving distance of the lead track from the chip pad to the corresponding substrate pad in the plane where the chip is located to the moving distance in the direction perpendicular to the plane where the chip is located, the greater the ratio is, the current moving distance of the lead track along the plane where the chip is located is much greater than the moving distance in the direction perpendicular to the plane where the chip is located. It is understood by those skilled in the art that the moving distance along the plane where the chip is located is much greater than the moving distance in the direction perpendicular to the plane where the chip is located. The traction is more likely to cause the lead and the solder joint to be misaligned, so the greater the moving distance of the lead track along the plane where the chip is located, the more easily the solder joint is affected. Similarly, the smaller the spacing between the chip pad and the last chip pad that has completed lead welding, the more easily the solder joint on the current chip pad to be welded is affected by the residual heat of the material around the last chip pad that has completed lead welding, resulting in a decrease in its cooling and tightening rate, which is more likely to cause the lead and the solder joint to be misaligned. The present invention combines the two in calculation, realizes the digital and intuitive representation of the degree of influence of the solder joint on the lead traction, and at the same time, multi-source data avoids the deviation of the calculation results.

[0038] In particular, under the condition that the solder joints are generally affected by the lead pulling, the present invention can adjust the interval between the lead welding of the chip pad and the completion of the lead welding of the previous chip pad, so as to avoid the solder joints being affected by the residual heat in the material around the chip pad of the previous chip that completed the lead welding, thereby achieving targeted adjustment of the wire bonding process of the wire bonding tool and improving the quality of the wire bonding chip package and the connection reliability.

[0039] In particular, in the present invention, when the solder joint is obviously affected by the lead pulling, the wire bonding tool is paused at the characteristic track point of the lead track to avoid the lead and the solder joint being misaligned due to the lead pulling. Those skilled in the art should understand that the position where the track curvature of the lead track of the wire bonding tool is the maximum is the position where the track direction changes the most, and the lead track changes from being perpendicular to the plane where the chip is located to being along the plane where the chip is located. The pause at this position can ensure that the solder joint of the lead at the chip pad has more time to cool and tighten, thereby avoiding the misalignment of the lead and the solder joint caused by the wire bonding tool pulling the metal lead to move along the plane where the chip is located, thereby achieving targeted adjustment of the wire bonding process of the wire bonding tool and improving the quality of the wire bonding chip package and the connection reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 A diagram showing the steps of a chip packaging process according to an embodiment of the present invention;

[0041] Figure 2A logic flow chart for determining whether there is a risk of solder joints being affected between a chip pad and a corresponding substrate pad according to an embodiment of the present invention;

[0042] Figure 3 is a schematic diagram of a first moving distance and a second moving distance according to an embodiment of the present invention;

[0043] Figure 4 A logic flow chart for determining the affected state of a solder joint of a lead track according to an embodiment of the present invention;

[0044] In the figure, 1: chip pad, 2: substrate pad, 3: lead track. DETAILED DESCRIPTION

[0045] In order to make the objects and advantages of the present invention more clearly understood, the present invention is further described below in conjunction with embodiments; it should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0046] The preferred embodiments of the present invention are described below with reference to the accompanying drawings. It should be understood by those skilled in the art that these embodiments are only used to explain the technical principles of the present invention and are not intended to limit the protection scope of the present invention.

[0047] It should be noted that in the description of the present invention, terms such as "upper" and "inner" indicating directions or positional relationships are based on the directions or positional relationships shown in the drawings. This is only for the convenience of description and does not indicate or imply that the device or element must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it cannot be understood as a limitation on the present invention.

[0048] In addition, it should be noted that in the description of the present invention, unless otherwise clearly specified and limited, the term "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For those skilled in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0049] See also Figure 1 As shown, it is a step diagram of a chip packaging process according to an embodiment of the present invention. A chip packaging process according to the present invention includes:

[0050] Step S1, mounting the chip on the substrate;

[0051] Step S2, obtaining the distance between the chip pad 1 on the chip and the corresponding substrate pad 2 to determine whether there is a risk of solder joints being affected between the chip pad 1 and the corresponding substrate pad 2;

[0052] Step S3, based on the pre-stored lead track 3 between the chip pad 1 and the corresponding substrate pad 2, determining the moving distance of the lead track 3 in different preset directions, and determining the spacing distance between the chip pad 1 and the last chip pad that completed the lead welding, and calculating the affected characterization coefficient of the solder joint of the lead track based on the moving distance and the spacing distance to determine the affected state of the solder joint of the lead track;

[0053] The preset direction includes a first preset direction and a second preset direction, the first preset direction is a direction perpendicular to the plane where the chip is located, and the second preset direction is a direction from the chip pad 1 to the corresponding substrate pad 2 in the plane where the chip is located;

[0054] Step S4, selecting a wire bonding adjustment method based on the affected state of the solder joint;

[0055] The wire bonding adjustment method includes adjusting the interval between wire bonding of the chip pad 1 and the completion of wire bonding of the previous chip pad, or determining a characteristic track point based on the track curvature of the wire track 3, and determining the pause time of the wire bonding tool at the characteristic track point based on the solder joint influence characterization coefficient;

[0056] Step S5, completing wire bonding.

[0057] Specifically, the present invention does not limit the method of mounting the chip on the substrate. Preferably, in step S1, the chip can be mounted on the substrate using an SMT surface mounting process, which is a prior art and will not be described in detail here.

[0058] Specifically, the present invention does not limit the method for obtaining the distance between the chip pad 1 and the corresponding substrate pad 2. In an embodiment of the present invention, the acquisition of local images of the chip and the substrate is achieved through image denoising, contrast enhancement, edge detection, etc. The chip pad and the substrate pad in the local image can be extracted by the feature extraction method in image recognition, and the distance between the chip pad and the corresponding substrate pad is calculated. This is a prior art and will not be repeated here.

[0059] Specifically, the present invention does not limit the wire trace 3 between the pre-stored chip pad 1 and the corresponding substrate pad 2. It is well known to those skilled in the art that the wire trace 3 between the chip pad 1 and the corresponding substrate pad 2 is determined by those skilled in the art based on the specific positions of the chip pad 1 and the substrate pad 2. In a general wire bonding process, the position of the chip pad 1 is first located by a visual system, a sensor or predetermined position information, and the wire bonding tool is moved to the chip pad 1 to be welded. A hot pressing wire bonding tool can be used to apply an appropriate heat source and pressure. , fuse one end of the lead and fasten it together with the pad through the solder joint, move the wire bonding tool to pull the lead to the substrate pad 2 corresponding to the chip pad 1, apply heat source and pressure to connect the lead and the substrate pad 2 through the solder joint, and complete the wire bonding step. The running trajectory of the wire bonding tool for wire bonding between the chip pad 1 and the corresponding substrate pad 2 is the lead trajectory 3, which is determined according to the positions of the chip pad 1 and the substrate pad 2. Those skilled in the art can pre-store the lead trajectory 3 for wire bonding corresponding to chip packages of different specifications. This is a prior art and will not be repeated here.

[0060] Specifically, the present invention does not limit the method for determining the spacing distance between the chip pad and the last chip pad that completed lead welding. The chip pad in the local image can be extracted by the feature extraction method in image recognition, and the spacing distance between the chip pad and the last chip pad that completed lead welding can be calculated. This is the prior art and will not be repeated here.

[0061] Specifically, the present invention does not limit the method of determining the trajectory curvature of each trajectory point on the lead trajectory 3. Preferably, a numerical method can be used to approximately calculate the tangent between two adjacent points on the curve, and then calculate the change in direction of the tangent, so as to estimate the curvature of the curve at different positions. This is a prior art and will not be described in detail here.

[0062] Specifically, see Figure 2 As shown, it is a logic flow chart of determining whether there is a risk of solder joints being affected between a chip pad and a corresponding substrate pad according to an embodiment of the present invention, wherein the step S2 further includes comparing the distance S with a preset distance threshold S0;

[0063] If the distance S is less than or equal to the distance threshold S0, it is determined that there is no risk of solder joints being affected between the chip pad 1 and the corresponding substrate pad 2;

[0064] If the distance S is greater than the distance threshold S0, it is determined that there is a risk of solder joints being affected between the chip pad 1 and the corresponding substrate pad 2.

[0065] In the embodiment of the present invention, the value of the distance threshold S0 can be determined based on the chip size, so that D s0 =δ×L0, where δ is the distance threshold value factor, and the value of δ is set by those skilled in the art according to the size of the chip actually produced. Preferably, for small chips, the value range of δ can be [0.01, 0.1], and L0 is the average value of the chip length and width.

[0066] Specifically, the present invention determines whether there is a risk of solder joints being affected by obtaining the distance between the chip pad 1 and the corresponding substrate pad 2. Those skilled in the art understand that the greater the distance between the chip pad 1 and the corresponding substrate pad 2, the longer the lead required, and the longer the time the longer lead is pulled by the wire bonding tool during the welding process, which is more likely to cause the lead at the solder joint on the chip pad 1 to be affected by the traction, causing the solder joint that may not be completely fastened to loosen, causing the risk of cold solder joints. The present invention achieves the screening of lead tracks with the risk of cold solder joints by obtaining the distance between the chip pad 1 and the corresponding substrate pad 2.

[0067] Specifically, see Figure 3 As shown, it is a schematic diagram of the first moving distance and the second moving distance of an embodiment of the present invention. In the step S3, the moving distances of the lead track 3 in different preset directions include a first moving distance D1 and a second moving distance D2;

[0068] The first moving distance D1 is the moving distance of the lead track 3 in the first preset direction, and the second moving distance D2 is the moving distance of the lead track 3 in the second preset direction.

[0069] Specifically, the present invention determines the moving distance of the lead track 3 in different preset directions through the lead track 3. In the actual chip wire bonding process, after the wire bonding tool welds the lead to the chip pad, the metal lead is pulled along the set track toward the substrate pad, so that the metal lead forms an arc lead between the chip pad and the corresponding substrate pad, thereby realizing electrical connection between the chip pad 1 and the corresponding substrate pad 2. The present invention can obtain the characteristics of the lead track by obtaining the moving distance of the lead track 3 in a direction perpendicular to the plane where the chip is located and the moving distance of the lead track 3 in the direction from the chip pad to the corresponding substrate pad within the plane where the chip is located, thereby facilitating the subsequent analysis of the lead track characteristics.

[0070] Specifically, see Figure 4 As shown, it is a logic flow chart for determining the affected state of the solder joints of the lead track according to an embodiment of the present invention. In the step S3, the affected characterization coefficient of the solder joints of the lead track is calculated according to the following formula:

[0071]

[0072] Wherein, K is the solder joint influence characterization coefficient, D1 is the first moving distance, D2 is the second moving distance, D s is the distance between the chip pad and the last chip pad that has completed wire bonding, D s0 is the preset interval distance reference value, α is the moving distance weight coefficient, β is the interval distance weight coefficient, α+β=1.

[0073] In the embodiment of the present invention, the interval distance reference value D s0 The value of can be determined based on the chip size, so that D s0 =γ×L min , where γ is the reference value factor of the spacing distance, and the value of is set by those skilled in the art according to the size of the actual produced chip. Preferably, for small chips, the value range of γ can be [0.01, 0.15], L min is the minimum value between the chip length value and the chip width value. The moving distance weight coefficient α and the spacing distance weight coefficient β are selected by technical personnel in this field according to the influence of the ratio of the second moving distance to the first moving distance in historical data on the calculation result and the influence of the spacing distance between the chip pad and the chip pad of the last chip that has completed lead welding on the calculation result. Preferably, the moving distance weight coefficient α can be set to 0.6 and the spacing distance weight coefficient β can be set to 0.4.

[0074] Specifically, the present invention combines the moving distance of the lead track 3 in different preset directions and the spacing distance between the chip pad 1 and the chip pad of the last chip that has completed the lead bonding to calculate. In the actual chip lead bonding process, the larger the ratio of the moving distance of the lead track 3 from the chip pad to the corresponding substrate pad in the plane where the chip is located to the moving distance in the direction perpendicular to the plane where the chip is located, the greater the ratio is, the current moving distance of the lead track 3 along the plane where the chip is located is much greater than the moving distance in the direction perpendicular to the plane where the chip is located. It is understood by those skilled in the art that the moving distance along the plane where the chip is located is much greater than the moving distance in the direction perpendicular to the plane where the chip is located. The pulling of the plane is more likely to cause the lead and the solder joint to be misaligned, so the greater the moving distance of the lead track 3 along the plane where the chip is located, the more easily the solder joint is affected. Similarly, the smaller the spacing between the chip pad and the last chip pad that has completed lead welding, the more easily the solder joint on the current chip pad to be welded is affected by the residual heat of the material around the last chip pad that has completed lead welding, resulting in a decrease in its cooling and tightening rate, which is more likely to cause the lead and the solder joint to be misaligned. The present invention combines the two in calculation, realizes the digital and intuitive representation of the degree of influence of the solder joint on the lead pulling, and multi-source data avoids the deviation of the calculation results.

[0075] Specifically, in step S3, the process of determining the affected state of the solder joint of the lead track 3 is as follows:

[0076] The solder joint influence characterization coefficient K is compared with the preset solder joint influence characterization coefficient comparison value K c Make a comparison;

[0077] If the solder joint influence characterization coefficient K is less than or equal to the solder joint influence characterization coefficient comparison value K c , it is determined that the lead track is in a weak dominant state where the solder joint is affected;

[0078] If the solder joint influence characterization coefficient K is greater than the solder joint influence characterization coefficient comparison value K c , it is determined that the lead track is in a dominant state where the solder joint is affected.

[0079] Preferably, in the embodiment of the present invention, the solder joint influence characterization coefficient comparison value K c The value range is [2.25,2.3].

[0080] Specifically, in step S4, the process of selecting the wire bonding adjustment method is as follows:

[0081] If the lead track is in a weak dominant state where the solder joint is affected, the interval between the lead soldering of the chip pad 1 and the lead soldering of the previous chip pad is adjusted;

[0082] If the lead track is in a solder joint affected explicit state, a characteristic track point is determined based on the track curvature of the lead track, and a pause time of the wire bonding tool at the characteristic track point is determined based on the solder joint influence characterization coefficient.

[0083] Specifically, in step S4, the interval between wire bonding of the chip pad and wire bonding of the previous chip pad is adjusted based on the solder joint affected coefficient K, and the interval is positively correlated with the solder joint affected coefficient K.

[0084] Specifically, under the condition that the solder joints are generally affected by the wire pulling, the present invention can adjust the interval between the wire welding of the chip pad and the completion of the wire welding of the previous chip pad, so as to avoid the solder joints being affected by the residual heat in the surrounding materials of the chip pad 1 of the previous chip that completed the wire welding, thereby achieving targeted adjustment of the wire bonding process of the wire bonding tool and improving the quality of the wire bonding chip package and the connection reliability.

[0085] Specifically, the step S4 further includes determining the trajectory curvature of each trajectory point on the lead trajectory, determining the trajectory point corresponding to the maximum value of the trajectory curvature, and determining the trajectory point as the characteristic trajectory point.

[0086] Specifically, in step S4, the pause time of the wire bonding tool at the characteristic trajectory point is positively correlated with the affected characterization coefficient K of the solder joint.

[0087] Specifically, in the present invention, when the solder joint is obviously affected by the lead pulling, the wire bonding tool is paused at the characteristic track point of the lead track to avoid the lead and the solder joint being misaligned due to the lead pulling. Those skilled in the art should understand that the position where the track curvature of the lead track of the wire bonding tool is the maximum is the position where the track direction changes the most, and the lead track 3 changes from being perpendicular to the plane where the chip is located to being along the plane where the chip is located. The pause at this position can ensure that the solder joint of the lead at the chip pad 1 has more time to cool and tighten, thereby avoiding the lead and the solder joint being misaligned due to the wire bonding tool pulling the metal lead to move along the plane where the chip is located, thereby achieving targeted adjustment of the wire bonding process of the wire bonding tool and improving the quality of the wire bonding chip package and the connection reliability.

[0088] Specifically, in step S3 , the wire track 3 is a track for the wire bonding tool to perform wire bonding between the chip pad 1 and the corresponding substrate pad 2 .

[0089] So far, the technical solutions of the present invention have been described in conjunction with the preferred embodiments shown in the accompanying drawings. However, it is easy for those skilled in the art to understand that the protection scope of the present invention is obviously not limited to these specific embodiments. Without departing from the principle of the present invention, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will fall within the protection scope of the present invention.

[0090] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A chip packaging process, characterized in that: include: Step S1, mounting the chip on the substrate; Step S2, obtaining the distance between the chip pad on the chip and the corresponding substrate pad to determine whether there is a risk of solder joints being affected between the chip pad and the corresponding substrate pad; Step S3, determining the moving distance of the lead track in different preset directions based on the pre-stored lead track between the chip pad and the corresponding substrate pad, and determining the spacing distance between the chip pad and the last chip pad that completed the lead welding, and calculating the solder joint influence characterization coefficient of the lead track based on the moving distance and the spacing distance to determine the affected state of the solder joint of the lead track; The preset direction includes a first preset direction and a second preset direction, the first preset direction is a direction perpendicular to the plane where the chip is located, and the second preset direction is a direction from the chip pad to the corresponding substrate pad in the plane where the chip is located; The moving distances of the lead track in different preset directions include a first moving distance and a second moving distance; Wherein, the first moving distance is the moving distance of the lead track in the first preset direction, and the second moving distance is the moving distance of the lead track in the second preset direction; The solder joint influence characterization coefficient of the lead track is calculated according to the following formula; Wherein, K is the solder joint influence characterization coefficient, D1 is the first moving distance, D2 is the second moving distance, D s is the distance between the chip pad and the last chip pad that has completed wire bonding, D s0 is the preset interval distance reference value, α is the moving distance weight coefficient, and β is the interval distance weight coefficient; Step S4, selecting a wire bonding adjustment method based on the affected state of the solder joint; The wire bonding adjustment method includes adjusting the interval between wire bonding of the chip pad and the completion of wire bonding of the previous chip pad, or determining a characteristic trajectory point based on the trajectory curvature of the wire trajectory, and determining the pause time of the wire bonding tool at the characteristic trajectory point based on the solder joint influence characterization coefficient; Step S5, completing wire bonding.

2. The chip packaging process according to claim 1, characterized in that: The step S2 further includes comparing the distance with a preset distance threshold; If the distance is greater than the distance threshold, it is determined that there is a risk of solder joints being affected between the chip pad and the corresponding substrate pad.

3. The chip packaging process according to claim 1, characterized in that: In step S3, the process of determining the affected state of the solder joint of the lead track is as follows: Comparing the solder joint influence characterization coefficient with a preset solder joint influence characterization coefficient comparison value; If the solder point influence characterization coefficient is less than or equal to the solder point influence characterization coefficient comparison value, the lead track is determined to be in a solder point affected weak dominant state; If the solder point influence characterization coefficient is greater than the solder point influence characterization coefficient comparison value, the lead track is determined to be in a solder point affected dominant state.

4. The chip packaging process according to claim 3, characterized in that: In step S4, the process of selecting the wire bonding adjustment method is as follows: If the lead track is in a weak dominant state where the solder joint is affected, adjusting the interval between the lead soldering of the chip pad and the lead soldering of the previous chip pad; If the lead track is in a solder joint affected explicit state, a characteristic track point is determined based on the track curvature of the lead track, and a pause time of the wire bonding tool at the characteristic track point is determined based on the solder joint influence characterization coefficient.

5. The chip packaging process according to claim 4, characterized in that: In the step S4, the interval between wire bonding of the chip pad and wire bonding of the previous chip pad is adjusted based on the solder joint influence characterization coefficient, and the interval is positively correlated with the solder joint influence characterization coefficient.

6. The chip packaging process according to claim 4, characterized in that: The step S4 further includes determining the trajectory curvature of each trajectory point on the lead trajectory, determining the trajectory point corresponding to the maximum value of the trajectory curvature, and determining the trajectory point as the characteristic trajectory point.

7. The chip packaging process according to claim 6, characterized in that: In the step S4, the pause time of the wire bonding tool at the characteristic trajectory point is positively correlated with the solder joint influence characterization coefficient.

8. The chip packaging process according to claim 1, characterized in that: In the step S3, the wire trace is a trace for the wire bonding tool to perform wire bonding between the chip pad and the corresponding substrate pad.

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