Semiconductor structure and method of manufacturing the same

Abstract

The present disclosure relates to a semiconductor structure and a method for manufacturing the same. The method comprises: forming a plurality of first trenches in a substrate, the first trenches being arranged in parallel and spaced apart, and extending along a first direction; forming support structures filling the first trenches; forming a mask structure above the substrate, the mask structure comprising a plurality of mask bridges arranged in parallel and spaced apart, the mask bridges extending along a second direction, the second direction intersecting the first direction, a projection of adjacent mask bridges on a surface of the substrate and a corresponding adjacent support structure forming a closed pattern, and a space between the adjacent mask bridges exposing a part of a top surface of the support structures; etching the substrate and the support structures based on the mask structure to form second trenches; removing the support structures to make the first trenches and the second trenches communicate as isolation trenches; and forming isolation structures filling the isolation trenches, the isolation structures separating a plurality of active regions in the substrate. The present disclosure can reduce or eliminate the bridging defects of the active regions, and facilitate improving the production yield and reliability of semiconductor devices.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of semiconductor, and in particular, to a semiconductor structure and a method for manufacturing the same. BACKGROUND

[0002] In the manufacturing process of semiconductor devices such as semiconductor memory, it is often required to define an active region array in a substrate, and then continue to manufacture the corresponding semiconductor device based on the active region array. In the conventional method, a mask defining the pattern of the active region array is usually formed by using a photolithography process, and then the substrate is patterned and etched by a wet etching process based on the mask to obtain the active region array.

[0003] However, as the semiconductor process continues to decrease, the spacing between the active regions also becomes narrower and narrower. Thus, when using a wet process to manufacture an active region array with narrow spacing, the active region bridge defect often occurs. For example, two adjacent active regions are easy to collapse and contact together under the action of unbalanced liquid tension generated by the etching liquid, thereby causing the semiconductor device to fail.

[0004] Therefore, how to reduce or eliminate the active region bridge defect is a problem to be solved. SUMMARY

[0005] Therefore, it is necessary to provide a semiconductor structure and a method for manufacturing the same to reduce or eliminate the active region bridge defect, thereby ensuring the production yield and reliability of the semiconductor device.

[0006] In one aspect, the present disclosure provides a method for manufacturing a semiconductor structure, comprising the following steps.

[0007] Providing a substrate.

[0008] Forming a plurality of first trenches in the substrate, the first trenches being arranged in parallel and spaced apart, and extending along a first direction.

[0009] Forming a support structure filling the first trenches.

[0010] Forming a mask structure above the substrate. The mask structure comprises a plurality of mask bridges arranged in parallel and spaced apart. The mask bridges extend along a second direction, and the second direction intersects the first direction. The orthogonal projection of adjacent mask bridges on the substrate surface and the corresponding adjacent support structures form a closed pattern, and the spacing between the adjacent mask bridges exposes part of the top surface of the support structure.

[0011] Etching the substrate and the support structure based on the mask structure to form second trenches.

[0012] Removing the remaining support structure to make the first trenches and the second trenches communicate as isolation trenches.

[0013] An isolation structure is formed to fill the isolation trench, and the isolation structure separates a plurality of active areas in the substrate.

[0014] In some embodiments, forming a mask structure above a substrate includes the following steps.

[0015] Before forming the first trench, a first sacrificial layer is formed on the substrate; the first sacrificial layer has a first pattern, and the first pattern and the first trench are formed by adopting the same patterning process.

[0016] After forming the support structure, a conformal layer covering the first sacrificial layer and the support structure is formed, and a second sacrificial layer covering the conformal layer is formed.

[0017] The second sacrificial layer, the conformal layer and the first sacrificial layer are patterned to form a mask structure.

[0018] In some embodiments, the material of the conformal layer includes polysilicon.

[0019] In some embodiments, forming a support structure filling the first trench includes: forming a support material layer filling the first trench and covering the first sacrificial layer; etching back the support material layer to retain the portion of the support material layer located in the first trench to form a support structure.

[0020] In some embodiments, after forming the first trench and before forming the support structure, the fabrication method further includes forming a buffer layer covering the first sacrificial layer and the inner wall of the first trench. The support structure is located on a surface of the buffer layer facing away from the substrate. A conformal layer covers the buffer layer.

[0021] The mask structure further includes: a buffer layer which is patterned synchronously with the second sacrificial layer, the conformal layer and the first sacrificial layer and is located on the surface of the first sacrificial layer.

[0022] In some embodiments, the material of the buffer layer is the same as that of the isolation structure.

[0023] In some embodiments, the material of the support structure includes nitride; and the material of the buffer layer includes oxide.

[0024] In some embodiments, forming a second sacrificial layer covering the conformal layer includes: depositing a sacrificial material layer on an upper surface of the conformal layer; and planarizing the upper surface of the sacrificial material layer to form the second sacrificial layer.

[0025] In some embodiments, the materials of the first sacrificial layer and the second sacrificial layer both include oxide.

[0026] In some embodiments, patterning the second sacrificial layer, the conformal layer, and the first sacrificial layer to form the mask structure includes the following steps.

[0027] A hard mask layer having a mask pattern is formed on the second sacrificial layer.

[0028] The second sacrificial layer, the conformal layer, and the first sacrificial layer are etched based on the mask pattern to form a mask structure.

[0029] In some embodiments, the thickness of the hard mask layer is greater than the sum of the height of the mask structure and the height of the active region.

[0030] In some embodiments, the substrate within the closed pattern and the support structures exposed between adjacent mask bridges are etched using a dry etching process to form the second trench; and the support structures remaining after the second trench is formed are removed using a wet etching process.

[0031] In some embodiments, forming an isolation structure filling the isolation trench includes: forming an isolation material layer filling the isolation trench and covering the mask structure; and grinding the isolation material layer to expose the upper surface of the substrate to form the isolation structure.

[0032] In some embodiments, a depth of the first trench is greater than a depth of the second trench.

[0033] On the other hand, embodiments of the present disclosure provide a semiconductor structure that can be prepared using the semiconductor preparation methods described in some of the above embodiments. The semiconductor structure includes: a substrate and an isolation structure. The substrate has an isolation trench. The isolation trench includes: a first trench extending along a first direction, and a second trench connected to the first trench and extending along a second direction; wherein the second direction intersects the first direction. The isolation structure fills the isolation trench and separates a plurality of active regions within the substrate; wherein the orthographic projection shape of the active region on the substrate surface includes a parallelogram.

[0034] In some embodiments, the semiconductor structure further includes a buffer layer, wherein the buffer layer is disposed on a sidewall of the active region extending along the first direction.

[0035] The embodiments of the present disclosure may or may have at least the following advantages:

[0036] In the embodiment of the present disclosure, after forming a first trench in the substrate and filling the first trench to form a support structure, a mask structure can be formed on the substrate. Since the first trench extends along the first direction, the mask structure includes a plurality of mask bridges extending along the second direction, and the first direction and the second direction intersect, the orthographic projections of adjacent mask bridges on the substrate surface and the corresponding adjacent support structures form a closed figure, and the gaps between adjacent mask bridges expose part of the top surface of the support structure. On this basis, the substrate and the support structure are etched based on the mask structure to form a second trench to ensure that the first trench and the second trench are connected to form an isolation trench after the support structure is removed. In this way, an isolation structure filling the isolation trench is formed, and a substrate with multiple active areas can be obtained.

[0037] In the disclosed embodiment, after etching the second trench, the active area is simultaneously formed in the substrate. During the etching process, the support structure filling the first trench remains intact and can connect with the mask bridge above to form a mesh-like structure. Therefore, the support provided by the support and mask structures to the active area effectively prevents the active area from collapsing and bridging due to unbalanced forces on both sides. This reduces or eliminates bridging defects in the active area, ensuring the production yield and reliability of semiconductor devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the following briefly introduces the drawings required for use in the embodiments or the description of the traditional technology. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0039] Figure 1 A schematic diagram of an active area array preparation process provided by some embodiments of the related art;

[0040] Figure 2 A schematic top view of an active area bridging defect provided in some embodiments;

[0041] Figure 3 for Figure 2 A schematic cross-sectional view of an M region in the active region bridging defect is shown;

[0042] Figure 4 A schematic diagram illustrating an analysis of a formation mechanism of an active region bridging defect provided in some embodiments;

[0043] Figure 5 A schematic flow chart of a method for preparing a semiconductor structure provided in some embodiments;

[0044] Figure 6 A schematic flow chart of a method for forming a mask structure provided in some embodiments;

[0045] Figure 7 A schematic flow chart of another method for forming a mask structure provided in some embodiments;

[0046] Figure 8 A schematic flow chart of a method for forming a support structure provided in some embodiments;

[0047] Figure 9 A schematic flow chart of a method for forming an isolation structure provided in some embodiments;

[0048] Figure 10is a schematic diagram of a structure obtained after forming a first trench provided in some embodiments;

[0049] Figure 11 for Figure 10 A schematic cross-sectional view of the structure shown along the RR direction;

[0050] Figure 12 is a schematic diagram of a structure obtained after forming a first hard mask layer provided in some embodiments;

[0051] Figure 13 for Figure 12 A schematic cross-sectional view of the structure shown along the RR direction;

[0052] Figure 14 is a schematic cross-sectional view along the RR direction of a structure obtained after forming a photoresist layer provided in some embodiments;

[0053] Figure 15 is a schematic cross-sectional view along the RR direction of a structure obtained after forming a buffer layer provided in some embodiments;

[0054] Figure 16 is a schematic cross-sectional view along the RR direction of a structure obtained after forming a support material layer provided in some embodiments;

[0055] Figure 17 is a schematic cross-sectional view of a structure obtained after forming a support structure along the RR direction provided in some embodiments;

[0056] Figure 18 is a schematic cross-sectional view along the RR direction of a structure obtained after forming a conformal layer provided in some embodiments;

[0057] Figure 19 is a schematic cross-sectional view along the RR direction of a structure obtained after forming a sacrificial material layer provided in some embodiments;

[0058] Figure 20 is a schematic cross-sectional view along the RR direction of a structure obtained after forming a second sacrificial layer provided in some embodiments;

[0059] Figure 21 is a schematic diagram of a structure obtained after forming a second hard mask layer provided in some embodiments;

[0060] Figure 22 for Figure 21 A schematic cross-sectional view of the structure shown along the RR direction;

[0061] Figure 23 A schematic diagram of a structure obtained after forming a mask structure provided in some embodiments;

[0062] Figure 24 for Figure 23 A schematic cross-sectional view of the structure shown along the RR direction;

[0063] Figure 25 is a schematic cross-sectional view along the RR direction of a structure obtained after forming a second trench provided in some embodiments;

[0064] Figure 26 for Figure 25 A schematic cross-sectional view of the structure shown along the CC direction;

[0065] Figure 27 for Figure 25 A schematic cross-sectional view of the structure shown along the DD direction;

[0066] Figure 28 is a schematic cross-sectional view along the RR direction of a structure obtained after forming an isolation trench provided in some embodiments;

[0067] Figure 29 for Figure 28 A schematic cross-sectional view of the structure shown along the PP direction;

[0068] Figure 30 for Figure 28 A schematic cross-sectional view of the structure shown along the QQ direction;

[0069] Figure 31 is a schematic cross-sectional view along the RR direction of a structure obtained after forming an isolation material layer provided in some embodiments;

[0070] Figure 32 A schematic diagram of a structure obtained after forming an isolation structure provided in some embodiments;

[0071] Figure 33 for Figure 32 The structure shown is a schematic cross-sectional view along the RR direction.

[0072] Description of reference numerals:

[0073] 1-Substrate, AA-Active region, 01-First sacrificial layer, 02-First hard mask layer, G1'-First linear groove, G2'-Second linear groove, ES-Etchant, F1-First force, F2-Second force, a-Contact angle, 03-Second hard mask layer, G1-First trench, G2-Second trench, G-Isolation trench, YM1-First spin-on mask layer, ARC1-First anti-reflective layer, YM2-Second spin-on mask layer, ARC2-Second anti-reflective layer, PR-Photoresist layer, 11-Buffer layer, 2-Support structure, 20-Support material layer, 3-Conformal layer, 4-Second sacrificial layer, 40-Second sacrificial material layer, 5-Mask structure, 51-Mask bridge, 511-First sub-portion, 512-Second sub-portion, 513-Third sub-portion, 514-Fourth sub-portion, P-Blocking pattern, 6-Isolation structure, 60-Isolation material layer. DETAILED DESCRIPTION

[0074] For the purpose of the present disclosure, the following description will be made with reference to the accompanying drawings. Embodiments of the present disclosure are illustrated in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, the purpose of providing these embodiments is to make the disclosure of the present disclosure more thorough and comprehensive.

[0075] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. The terminology used in the description of the present disclosure herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure.

[0076] It should be noted that when an element is considered to be "connected" to another element, it can be directly connected to the other element or connected to the other element through an intermediate element. In addition, "connected" in the following embodiments should be understood as "electrically connected", "communicatively connected", etc. if there is transmission of electrical signals or data between the connected objects.

[0077] As used herein, the singular forms "a", "an" and "the" can include plural forms unless the context clearly indicates otherwise. It should also be understood that the term "comprise / comprises" or "has / have" specifies the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but does not exclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. At the same time, the term "and / or" used in the specification includes any and all combinations of the related listed items.

[0078] Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present disclosure, and variations from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Accordingly, embodiments of the present disclosure should not be limited to the specific shapes of regions illustrated herein, but rather include deviations in shapes due to, for example, manufacturing techniques. The regions shown in the figures are schematic in nature, and their shapes do not represent the actual shapes of regions of a device and do not limit the scope of the present disclosure.

[0079] In the process of preparing semiconductor devices such as semiconductor memories, it is often necessary to define an active area array in a substrate, and then to continue to prepare corresponding semiconductor devices based on the active area array. In traditional methods, it is usually necessary to use a photolithography process to form a mask that defines the active area array pattern, and then use a wet etching process to pattern the substrate based on the mask to obtain the active area array. However, as the semiconductor process continues to decrease, the spacing between active areas is becoming narrower and narrower. As a result, when using a wet process to prepare an active area array with a narrow spacing, active area bridging defects often occur. For example, two adjacent active areas are easily collapsed and contacted together under the action of the unbalanced liquid tension generated by the etching solution, thereby causing the semiconductor device to fail.

[0080] Figure 1 The figure shows a process for preparing an active area array in the related art. Figure 1 In some embodiments, as Figure 1 As shown in FIG. (a), a first sacrificial layer 01 and a first hard mask layer 02 are sequentially formed on the substrate. The first hard mask layer 02 has a plurality of first linear grooves G1', and the extension direction of the first linear grooves G1' intersects both the X direction and the Y direction. Then, as shown in FIG. Figure 1 As shown in FIG. (b), a plurality of second linear grooves G2' are formed in the first hard mask layer 02. The second linear grooves G2' extend, for example, along the X direction. In this way, the first linear grooves G1' and the second linear grooves G2' intersect, and a plurality of mask patterns arranged in an array can be separated in the first hard mask layer 02 to define an active area array. Figure 1 As shown in FIG. 5( c ), the first sacrificial layer 01 and the substrate 1 are etched based on the mask pattern in the first hard mask layer 02 , so that a pattern can be formed in the first sacrificial layer 01 and an initial active area can be obtained in the substrate 1 . Finally, as shown in FIG. Figure 1 As shown in FIG. 5( d ), the first sacrificial layer 01 is removed to obtain a substrate 1 having an array of active areas AA.

[0081] Figure 2 and Figure 3 Figure 2 shows an active area bridging defect in an active area array. Figure 2 and Figure 3As shown in the M region in FIG, during the process of etching the first sacrificial layer 01 and the substrate 1 to form the active area AA array, some adjacent active areas are easily collapsed and contacted together under the action of the unbalanced liquid tension generated by the etching solution, resulting in a bridging defect. Figure 4 The force analysis of the active area AA shown in FIG can help us understand the formation mechanism of the above-mentioned active area AA bridging defect.

[0082] See also Figure 4 When etching the first sacrificial layer 01 and the substrate 1 based on the mask pattern in the first hard mask layer 02, due to the surface tension of the etching solution ES, the surface of the etching solution ES in the grooves on both sides of the active area AA forms a contact angle α with the edge of the corresponding groove. Assuming that the contact angle α does not change with the change of the process critical dimension, the first force F1 and the second force F2 acting on the sidewalls of the active area AA are both horizontal tensile forces, and this horizontal tensile force is proportional to the surface tension coefficient γ of the etching solution ES and inversely proportional to the curvature radius R of the sidewall morphology of the active area AA. In this way, assuming that other conditions remain unchanged, as the process critical dimension is miniaturized, the curvature radius R of the sidewall morphology of the active area AA decreases, and assuming that the curvature radii of the sidewall morphology on both sides of the active area AA are R and R+ΔR respectively, then the unbalanced force ΔF acting on the active area AA satisfies the following formula:

[0083] ΔR can be used to characterize the imbalance state of the active area AA process.

[0084] Therefore, under the same process environment, as the critical dimension of the process shrinks, the smaller the curvature radius R of the sidewall morphology of the active area AA, the greater the unbalanced force ΔF on the active area AA, which is likely to cause bridging defects in the active area AA.

[0085] Based on this, some embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, which can reduce or eliminate bridging defects in the active region, thereby ensuring the production yield and reliability of semiconductor devices.

[0086] See also Figure 5 , the preparation method of the semiconductor structure includes the following steps.

[0087] S100 , providing a substrate.

[0088] S200 , forming a plurality of first trenches in parallel and spaced apart from each other in a substrate; the first trenches extend along a first direction.

[0089] S300 , forming a support structure filling the first trench.

[0090] S400, forming a mask structure above the substrate; the mask structure includes a plurality of mask bridges arranged in parallel and spaced apart; the mask bridges extend along a second direction, and the second direction intersects the first direction; the orthographic projections of adjacent mask bridges on the substrate surface and the corresponding adjacent support structures form a closed figure, and the intervals between adjacent mask bridges expose a portion of the top surface of the support structure.

[0091] S500 , etching the substrate and the support structure based on the mask structure to form a second trench.

[0092] S600 , removing the remaining support structure to connect the first trench and the second trench to form an isolation trench.

[0093] S700 , forming an isolation structure filling the isolation trench, wherein the isolation structure separates a plurality of active regions in the substrate.

[0094] In the embodiment of the present disclosure, after forming a first trench in the substrate and filling the first trench to form a support structure, a mask structure can be formed on the substrate. Since the first trench extends along the first direction, the mask structure includes a plurality of mask bridges extending along the second direction, and the first direction and the second direction intersect, the orthographic projections of adjacent mask bridges on the substrate surface and the corresponding adjacent support structures form a closed figure, and the gaps between adjacent mask bridges expose part of the top surface of the support structure. On this basis, the substrate and the support structure are etched based on the mask structure to form a second trench to ensure that the first trench and the second trench are connected to form an isolation trench after the support structure is removed. In this way, an isolation structure filling the isolation trench is formed, and a substrate with multiple active areas can be obtained.

[0095] In the disclosed embodiment, after etching the second trench, the active area is simultaneously formed in the substrate. During the etching process, the support structure filling the first trench remains intact and can connect with the mask bridge above to form a mesh-like structure. Therefore, the support provided by the support and mask structures to the active area effectively prevents the active area from collapsing and bridging due to unbalanced forces on both sides. This reduces or eliminates bridging defects in the active area, ensuring the production yield and reliability of semiconductor devices.

[0096] It is worth mentioning that, in some embodiments, the depth of the first trench is greater than the depth of the second trench.

[0097] In some embodiments, a size of the active region in the third direction is the same as a size of the mask bridge in the third direction; wherein the third direction is perpendicular to the second direction in an intersection plane of the first direction and the second direction.

[0098] In some embodiments, see Figure 6 , step S400 forms a mask structure above the substrate, which may include steps S150 to S430.

[0099] S150 , before forming the first trench, forming a first sacrificial layer on the substrate; the first sacrificial layer has a first pattern, and the first pattern and the first trench are formed by the same patterning process.

[0100] S410 , after forming the support structure, forming a conformal layer covering the first sacrificial layer and the support structure.

[0101] S420 , forming a second sacrificial layer covering the conformal layer.

[0102] S430 , patterning the second sacrificial layer, the conformal layer, and the first sacrificial layer to form a mask structure.

[0103] For example, the conformal layer is made of polysilicon. Polysilicon is dense, stable, and has excellent mechanical properties. This allows the conformal layer to maintain its structural stability during subsequent etching steps and provide support for adjacent layers.

[0104] For example, the conformal layer is formed by an atomic layer deposition process, which is conducive to controlling the film thickness of the conformal layer.

[0105] In some embodiments, see Figure 7 Step S420 forms a second sacrificial layer covering the conformal layer, which may include steps S421 to S422.

[0106] S421 , depositing a sacrificial material layer on the upper surface of the conformal layer.

[0107] S422 , planarizing the upper surface of the sacrificial material layer to form a second sacrificial layer.

[0108] For example, the materials of both the first and second sacrificial layers include oxide. This facilitates patterning and removal processes on the first and second sacrificial layers. Furthermore, oxides are stable and are less likely to react with other film layers and generate unnecessary impurities.

[0109] For example, the planarization process of the sacrificial material layer includes but is not limited to chemical mechanical polishing (CMP).

[0110] Accordingly, please continue to see Figure 7 In step S430 , patterning the second sacrificial layer, the conformal layer, and the first sacrificial layer to form a mask structure may include steps S431 to S432 .

[0111] S431 , forming a hard mask layer having a mask pattern on the second sacrificial layer.

[0112] S432 , etching the second sacrificial layer, the conformal layer, and the first sacrificial layer based on the mask pattern to form a mask structure.

[0113] Illustratively, the thickness of the hard mask layer is greater than the sum of the height of the mask structure and the height of the active region.

[0114] For example, the mask structure may be formed by a dry etching process.

[0115] For example, after forming the second trench, the hard mask layer remaining on the mask structure may be removed by a wet etching process.

[0116] In some embodiments, see Figure 8 , step S300 forms a support structure filling the first trench, which may include steps S310 and S320.

[0117] S310 , forming a support material layer filling the first trench and covering the first sacrificial layer.

[0118] S320 , etching back the support material layer to retain a portion of the support material layer located in the first trench to form a support structure.

[0119] In some embodiments, after forming the first trench and before forming the support structure, the fabrication method further includes forming a buffer layer covering the first sacrificial layer and the inner wall of the first trench. The support structure is located on a surface of the buffer layer facing away from the substrate. A conformal layer covers the buffer layer. The mask structure further includes a buffer layer located on the surface of the first sacrificial layer after being patterned simultaneously with the second sacrificial layer, the conformal layer, and the first sacrificial layer.

[0120] Illustratively, the material of the buffer layer is the same as that of the isolation structure.

[0121] Illustratively, the material of the support structure includes nitride; and the material of the buffer layer includes oxide.

[0122] In some embodiments, etching the substrate and the support structure based on the mask structure to form a second trench in step S500 includes: etching the substrate within the closed pattern and the support structure exposed between adjacent mask bridges using a dry etching process to form the second trench.

[0123] In some embodiments, removing the remaining support structure in step S600 so that the first trench and the second trench are connected to form an isolation trench includes: using a wet etching process to remove the remaining support structure after forming the second trench.

[0124] In some embodiments, see Figure 9 The step S700 of forming an isolation structure filling the isolation trench may include steps S710 and S720.

[0125] S710 , forming an isolation material layer that fills the isolation trench and covers the mask structure.

[0126] S720 , grinding the isolation material layer until the upper surface of the substrate is exposed to form an isolation structure.

[0127] It should be understood that although Figures 5 to 9 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. In addition, Figures 5 to 9 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The order of execution of these steps or stages is not necessarily one by one, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0128] In order to more clearly illustrate the method for preparing the semiconductor structure in some of the above embodiments, the following embodiments exemplarily give some possible implementations of the preparation method and describe them in detail. Figures 10 to 33 Understand.

[0129] In steps S100 and S200, please refer to Figure 10 and Figure 11 A substrate 1 is provided, and a plurality of first trenches G1 arranged in parallel and spaced apart are formed in the substrate 1; the first trenches G1 extend along a first direction (eg, X direction).

[0130] For example, the substrate 1 may be made of a semiconductor material, an insulating material, a conductive material, or any combination thereof. For example, the substrate 1 may be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates.

[0131] Illustratively, the substrate 1 includes but is not limited to a silicon substrate or a silicon-based substrate.

[0132] For example, please continue to see Figure 10 and Figure 11 In step S150 , before forming the first trench G1 , a first sacrificial layer 01 is formed on the substrate 1 ; the first sacrificial layer 01 has a first pattern, and the first pattern and the first trench G1 are formed using the same patterning process.

[0133] Here, it can be understood that the first pattern and the first trench G1 in the first sacrificial layer 01 can be formed by etching based on the mask pattern of the hard mask layer.

[0134] For example, see Figure 12 and Figure 13 Before forming the first trench G1, a first sacrificial layer 01 and a first hard mask layer 02 may be stacked on the surface of the substrate 1. The first hard mask layer 02 has a first mask pattern for defining the first trench G1.

[0135] The first sacrificial layer 01 can be formed using a deposition process, and the thickness of the first sacrificial layer 01 can be set as needed, so that after forming the first trench G1, a first sacrificial layer 01 of a target thickness is still present above the substrate 1. Furthermore, the deposition processes mentioned herein and below include, but are not limited to, atomic layer deposition (ALD), chemical vapor deposition (CVD), and molecular layer deposition (MLD).

[0136] For example, the material of the first sacrificial layer 01 includes, but is not limited to, oxide, such as silicon oxide. Oxide materials have good etching resistance and can maintain the shape stability of the etched pattern during the etching process to form the first trench G1. This facilitates obtaining the first trench G1 with good morphological accuracy.

[0137] By way of example, the material of the first hard mask layer 02 includes, but is not limited to, polysilicon.

[0138] For example, the first groove G1 extends along a first direction (eg, X direction), and the first groove G1 may be a linear groove.

[0139] It should be added that the first mask pattern in the first hard mask layer 02 can be formed using a self-aligned double patterning (SADP) process or a patterning process with higher precision, such as a self-aligned quadruple patterning (SAQP) process.

[0140] For example, see Figure 14, the first mask pattern in the first hard mask layer 02 is formed using a SADP process. Before forming the first mask pattern in the first hard mask layer 02, a first spin-on mask layer YM1, a first anti-reflective layer ARC1, a second spin-on mask layer YM2, a second anti-reflective layer ARC2, and a photoresist layer PR can be stacked on the surface of the first hard mask layer 02. In this way, after the photoresist layer PR is exposed, developed, and etched, the pattern in the photoresist layer PR can be transferred in sequence through the pattern alignment of the second spin-on mask layer YM2 and the first spin-on mask layer YM1, thereby forming the first mask pattern in the first hard mask layer 02, as shown in FIG. Figure 12 As shown in .

[0141] For example, the first spin-on mask layer YM1 and the second spin-on mask layer YM2 are spin-on hard masks (SOH), including but not limited to spin-on carbon hard masks (SOC).

[0142] Illustratively, the first anti-reflection layer ARC1 and the second anti-reflection layer ARC2 include, but are not limited to, a silicon oxynitride (SiON) layer.

[0143] In order to more clearly illustrate the structural changes brought about by each process step in the embodiment of the present application, the following figures are Figure 10 The local structure in the N region is used as an example. It is understood that the same process steps can be performed simultaneously in other regions adjacent to the N region. This application does not limit this.

[0144] In some embodiments, see Figure 15 After forming the first trench and before forming the support structure, the preparation method further includes: forming a buffer layer 11 covering the first sacrificial layer 01 and the inner wall of the first trench G1.

[0145] By way of example, the material of the buffer layer 11 includes but is not limited to oxide, such as silicon oxide.

[0146] For example, the buffer layer 11 is formed by an atomic layer deposition process, and the buffer layer 11 conformally covers the inner wall of the first trench G1 and the exposed surface of the first sacrificial layer 01. The inner wall of the first trench G1 includes a bottom wall and side walls.

[0147] In step S300, refer to Figure 16 and Figure 17 , forming a support structure 2 filling the first trench G1.

[0148] In step S310, Figure 16 As shown in FIG, a support material layer 20 is formed to fill the first trench G1 and cover the first sacrificial layer 01 .

[0149] For example, the material of the support material layer 20 is different from that of the first sacrificial layer 01 , so as to facilitate selective etching of the support material layer 20 .

[0150] For example, the material of the support material layer 20 includes, but is not limited to, nitride, such as silicon nitride. The support material layer 20 can be formed by a deposition process.

[0151] In step S320, Figure 17 As shown in , the support material layer 20 is etched back to retain the portion of the support material layer 20 located in the first trench G1 to form the support structure 2 .

[0152] For example, Figure 17 As shown in , the top surface of the support structure 2 is flush or substantially flush with the upper surface of the substrate 1. Alternatively, it is also permissible that the top surface of the support structure 2 is lower than the upper surface of the substrate 1.

[0153] In some embodiments, please refer to Figure 17 The support structure 2 is formed on the surface of the buffer layer 11 facing away from the substrate 1. In this way, the buffer layer 11 can be used to improve the adhesion between the support structure 2 and the inner wall of the first trench G1, thereby ensuring the film quality of the support structure 2. In addition, the buffer layer 11 can also serve as an etch-stop layer in the subsequent step of etching back the support material layer 20.

[0154] For example, the dry etching process can be used to etch back the support material layer 20. In this way, the height of the obtained support structure 2 can be adjusted by controlling the direction and duration of the dry etching.

[0155] In step S400, refer to Figures 18 to 24 A mask structure 5 is formed above the substrate 1. The mask structure 5 includes a plurality of mask bridges 51 arranged in parallel and spaced apart. The mask bridges 51 extend along a second direction (e.g., an X1 direction that intersects both the X and Y directions), where the second direction (e.g., the X1 direction) intersects the first direction (e.g., the X direction). The orthographic projections of adjacent mask bridges 51 on the surface of the substrate 1 and the corresponding adjacent support structures 2 form a closed pattern P, and the spaces between adjacent mask bridges 51 expose portions of the top surface of the support structure 2.

[0156] For example, the shape of the closed figure P includes but is not limited to a parallelogram.

[0157] For example, step S400 may include S410 to S430.

[0158] In step S410, refer to Figure 18 After forming the support structure 2 , a conformal layer 3 covering the first sacrificial layer 01 and the support structure 2 is formed.

[0159] For example, Figure 18As shown in FIG. 1, the support structure 2 is formed on the surface of the buffer layer 11, and the surface of the first sacrificial layer 01 is covered with the buffer layer 11. Accordingly, the conformal layer 3 covers the top surface of the support structure 2 and the surface of the buffer layer 11 facing away from the first sacrificial layer 01.

[0160] For example, the material of the conformal layer 3 includes but is not limited to polysilicon.

[0161] For example, the conformal layer 3 is formed by an atomic layer deposition process.

[0162] In step S420, referring to Figure 19 and Figure 20 , a second sacrificial layer 4 covering the conformal layer 3 is formed.

[0163] For example, step S420 can include steps S421 and S422. In step S421, as shown in Figure 19 , a sacrificial material layer 40 is deposited on the upper surface of the conformal layer 3. In step S422, as shown in Figure 20 , the upper surface of the sacrificial material layer 40 is planarized to form the second sacrificial layer 4.

[0164] For example, the material of the sacrificial material layer 40 includes but is not limited to oxide, such as silicon oxide.

[0165] In step S430, referring to Figures 21 to 24 , the second sacrificial layer 4, the conformal layer 3 and the first sacrificial layer 01 are patterned to form a mask structure 5.

[0166] Here, it can be understood that in the example where the buffer layer 11 is formed, the mask structure 5 further includes the buffer layer 11 located on the surface of the first sacrificial layer 01 after being patterned synchronously with the second sacrificial layer 4, the conformal layer 3 and the first sacrificial layer 01.

[0167] For example, step S430 can include steps S431 and S432.

[0168] In step S431, as shown in Figure 21 and Figure 22 , a second hard mask layer 03 having a second mask pattern is formed on the second sacrificial layer 4.

[0169] Here, the second mask pattern in the second hard mask layer 03 is used to define second trenches to ensure that the second trenches can intersect and communicate with the first trenches G1 and separate a plurality of active areas AA in the substrate 1. The second mask pattern may, for example, be a plurality of linear patterns arranged in parallel and spaced apart, and the linear patterns extend along an X1 direction intersecting both the X direction and the Y direction.

[0170] In some examples, the material of the second hard mask layer 03 includes, but is not limited to, polysilicon. Furthermore, the second mask pattern in the second hard mask layer 03 can be formed using a self-aligned double patterning (SADP) process or a patterning process with higher precision, such as a self-aligned quadruple patterning (SAQP) process.

[0171] In step S432, if Figure 23 and Figure 24 As shown, the second sacrificial layer 4, the conformal layer 3, and the first sacrificial layer 01 are etched based on the second mask pattern to form a mask structure 5. Thus, the mask bridge 51 in the mask structure 5 includes: a first sub-portion 511 retained after the second sacrificial layer 4 is patterned; a second sub-portion 512 retained after the conformal layer 3 is patterned; and a third sub-portion 513 retained after the first sacrificial layer 01 is patterned. Furthermore, it will be understood that in the example where a buffer layer 11 is formed, the mask bridge 51 in the mask structure 5 also includes: a fourth sub-portion 514 located on the surface of the first sacrificial layer 01 after the buffer layer 11 is patterned.

[0172] From the above, after the mask structure 5 is formed, the orthographic projections of the adjacent mask bridges 51 on the surface of the substrate 1 and the corresponding adjacent support structures 2 form a closed pattern P, for example Figure 23 As shown in .

[0173] In step S500, refer to Figures 25 to 27 , the substrate 1 and the support structure 2 are etched based on the mask structure 5 to form a second trench G2.

[0174] For example, a dry etching process is used to etch the substrate 1 within the closed pattern P and the exposed support structures 2 between adjacent mask bridges 51 to form the second trench G2.

[0175] Here, it can be understood that after forming the mask bridge 51, as shown in FIG. Figure 26 As shown in , part of the top surface of the same support structure 2 is exposed within the spaces between adjacent mask bridges 51. Furthermore, the orthographic projection of the second trench G2 on the substrate 1 coincides with the orthographic projection of the spaces between adjacent mask bridges 51 on the substrate 1 in a one-to-one correspondence. That is, during step S500, the structure within the spaces between adjacent mask bridges 51 (including the substrate 1, support structure 2, and buffer layer 11) can be simultaneously etched downward, for example, using a dry etching process, thereby forming the second trench G2.

[0176] It should be noted that, in this step, after etching the substrate 1 and forming the second trench G2 based on the self-alignment of the mask bridge 51 and the support structure 2 , the protruding portion of the substrate 1 constitutes the active area AA referred to in this application.

[0177] In some embodiments, please combine Figures 22 to 25 It is understood that the thickness T1 of the second hard mask layer 03 is greater than the sum of the thickness T2 of the mask structure 5 and the height T3 of the active area AA.

[0178] Here, the thickness T1 of the second hard mask layer 03 is greater than the sum of the thickness T2 of the mask structure 5 and the height T3 of the active area AA. This ensures that after the second hard mask layer 03 is used as a mask for etching to obtain the mask bridge 51 and the active area AA, a certain thickness of the second hard mask layer 03 remains above the top of the mask bridge 51. Thus, during step S500, the second hard mask layer 03 can protect the top of the mask bridge 51 from etching damage.

[0179] In some examples, the remaining portion of the second hard mask layer 03 can be removed by a wet etching process after the second trench G2 is formed. Alternatively, it can be removed along with other structures in subsequent process steps. This application does not limit this.

[0180] For example, the depth of the second trench G2 may be less than that of the first trench G1. Thus, after the second trench G2 is formed, the support structure 2 retained in the substrate 1 below the second trench G2 can be used to balance the etching stress during the formation of the second trench G2.

[0181] In step S600, refer to Figure 28 、 Figure 29 and Figure 30 , remove the retained support structure 2 so that the first trench G1 and the second trench G2 are connected to form an isolation trench G.

[0182] For example, the support structure 2 remaining after the second trench G2 is formed can be removed by a wet etching process, thereby reducing the difficulty of removing the support structure 2 and improving production efficiency.

[0183] Here, it can be understood that the material of the buffer layer 11 is different from the material of the support structure 2. After the support structure 2 is removed by the wet etching process, the buffer layer 11 that is not removed by etching when the second trench G2 is formed can remain in the substrate 1, for example Figure 30 As shown in .

[0184] In some embodiments, please combine Figure 29 and Figure 30It is understood that the dimension D2 of the active area AA in the third direction (e.g., X2 direction) is the same as the dimension D1 of the mask bridge 51 in the third direction (e.g., X2 direction); wherein the third direction (e.g., X2 direction) is perpendicular to the second direction (e.g., X1 direction) within the intersection plane of the first direction (e.g., X direction) and the second direction (e.g., X1 direction).

[0185] It can be understood that the active area AA is obtained by etching the substrate 1 in a self-aligned manner using the mask bridge 51 and the support structure 2. Thus, in a specific direction (defined as the third direction X2 in the disclosed embodiment), the size of the active area AA is the same as the size of the corresponding mask bridge 51. Based on this, by controlling the size of the mask bridge 51 in the third direction, the size of the active area AA in the third direction can be controlled. This helps reduce the difficulty of preparing the active area AA.

[0186] In step S700, refer to Figure 31 、 Figure 32 and Figure 33 , forming an isolation structure 6 filling the isolation trench G, and separating a plurality of active areas AA in the substrate 1 from the isolation structure 6 .

[0187] For example, step S700 may include S710 and S720.

[0188] In step S710, Figure 31 As shown, an isolation material layer 60 is formed to fill the isolation trench G and cover the mask structure 5 .

[0189] For example, the material of the isolation material layer 60 is the same as that of the buffer layer 11. In this way, the isolation material layer 60 and the buffer layer 11 remaining in the substrate 1 can be in good contact and fused into one.

[0190] By way of example, the material of the isolation material layer 60 includes but is not limited to oxide, such as silicon oxide.

[0191] In step S720, if Figure 32 and Figure 33 As shown, the isolation material layer 60 is ground until the upper surface of the substrate 1 is exposed, thereby forming an isolation structure 6 .

[0192] By way of example, the grinding process of the isolation material layer 60 includes, but is not limited to, CMP.

[0193] Here, part of the second hard mask layer 03 retained in the above steps may also be removed.

[0194] In addition, it can be understood that after forming the above-mentioned isolation structure 6 and active area AA, subsequent processes can be performed on the surface of the substrate 1, such as preparing a gate, source and drain above the active area to prepare a semiconductor device based on the active area.

[0195] The present disclosure also provides a semiconductor structure that can be manufactured using the semiconductor manufacturing methods described in some of the above embodiments. The semiconductor structure also possesses the technical advantages of the aforementioned semiconductor manufacturing methods, which will not be further elaborated here.

[0196] See also Figure 28 、 Figure 30 、 Figure 32 and Figure 33 The semiconductor structure includes a substrate 1 and an isolation structure 6. The substrate 1 has an isolation trench G. The isolation trench G includes a first trench G1 extending along a first direction (e.g., the X direction), and a second trench G2 communicating with the first trench G1 and extending along a second direction (e.g., the X direction). The second direction (e.g., the X direction) intersects the first direction (e.g., the X direction). The isolation structure 6 fills the isolation trench G and separates a plurality of active areas AA within the substrate 1. The orthographic projection of the active areas AA on the surface of the substrate 1 comprises a parallelogram.

[0197] For example, the depth of the first trench G1 is greater than the depth of the second trench G2.

[0198] Illustratively, the depth of the second trench G2 is the same as the dimension of the active area AA in the same direction.

[0199] In some embodiments, as Figure 33 As shown in , the semiconductor structure further includes a buffer layer 11. The buffer layer 11 is disposed on the sidewalls of the active area AA extending along the first direction (eg, the X direction).

[0200] For example, the material of the buffer layer 11 is the same as that of the isolation structure 6 , and the material includes but is not limited to oxide, such as silicon oxide.

[0201] Throughout this specification, references to terms such as "some embodiments," "other embodiments," and "desired embodiments" indicate that a particular feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. Although these terms are used interchangeably throughout this specification, they do not necessarily refer to the same embodiment or example.

[0202] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0203] The above-described embodiments merely represent several implementation methods of the present disclosure. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person of ordinary skill in the art could make various modifications and improvements without departing from the spirit of the present disclosure, all of which fall within the scope of protection of the present disclosure. Therefore, the scope of protection of the present patent shall be determined by the appended claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: providing a substrate; forming a plurality of first trenches arranged in parallel and spaced apart in the substrate; The first groove extends along a first direction; forming a support structure filling the first trench; forming a mask structure above the substrate; The mask structure includes a plurality of mask bridges arranged in parallel and spaced apart; The mask bridge extends along a second direction, and the second direction intersects the first direction; The orthographic projections of adjacent mask bridges on the substrate surface and the corresponding adjacent support structures form a closed pattern, and the spaces between adjacent mask bridges expose a portion of the top surface of the support structure; etching the substrate and the support structure based on the mask structure to form a second trench; removing the remaining support structure so that the first trench and the second trench are connected to form an isolation trench; An isolation structure is formed to fill the isolation trench, wherein the isolation structure separates a plurality of active regions in the substrate.

2. The method for preparing a semiconductor structure according to claim 1, wherein: The step of forming a mask structure above the substrate includes: Before forming the first trench, forming a first sacrificial layer on the substrate; the first sacrificial layer has a first pattern, and the first pattern and the first trench are formed by the same patterning process; After forming the support structure, forming a conformal layer covering the first sacrificial layer and the support structure, and forming a second sacrificial layer covering the conformal layer; And, patterning the second sacrificial layer, the conformal layer and the first sacrificial layer to form the mask structure.

3. The method for preparing a semiconductor structure according to claim 2, wherein: The conformal layer is made of polysilicon.

4. The method for preparing a semiconductor structure according to claim 2, wherein: The forming of the support structure filling the first trench comprises: forming a support material layer filling the first trench and covering the first sacrificial layer; The support material layer is etched back to retain a portion of the support material layer located in the first trench to form the support structure.

5. The method for preparing a semiconductor structure according to claim 2, wherein: After forming the first groove and before forming the support structure, the preparation method further includes: forming a buffer layer covering the first sacrificial layer and the inner wall of the first trench; Among them, the support structure is also located on the surface of the buffer layer away from the substrate; the conformal layer covers the buffer layer; the mask structure also includes: a buffer layer located on the surface of the first sacrificial layer after being synchronously patterned with the second sacrificial layer, the conformal layer, and the first sacrificial layer.

6. The method for preparing a semiconductor structure according to claim 5, wherein: The material of the buffer layer is the same as that of the isolation structure.

7. The method for preparing a semiconductor structure according to claim 5, wherein: The material of the support structure includes nitride; the material of the buffer layer includes oxide.

8. The method for preparing a semiconductor structure according to claim 2, wherein: The forming of a second sacrificial layer covering the conformal layer comprises: depositing a sacrificial material layer on the upper surface of the conformal layer; The upper surface of the sacrificial material layer is planarized to form the second sacrificial layer.

9. The method for preparing a semiconductor structure according to claim 2, wherein: Materials of the first sacrificial layer and the second sacrificial layer both include oxide.

10. The method for preparing a semiconductor structure according to claim 2, wherein: The patterning of the second sacrificial layer, the conformal layer, and the first sacrificial layer to form the mask structure includes: forming a hard mask layer having a mask pattern on the second sacrificial layer; The second sacrificial layer, the conformal layer, and the first sacrificial layer are etched based on the mask pattern to form the mask structure.

11. The method for preparing a semiconductor structure according to claim 10, wherein: The thickness of the hard mask layer is greater than the sum of the height of the mask structure and the height of the active region.

12. The method for preparing a semiconductor structure according to claim 1, wherein: The substrate in the closed pattern and the support structures exposed between adjacent mask bridges are etched using a dry etching process to form the second trench; The support structure remaining after forming the second trench is removed by a wet etching process.

13. The method for preparing a semiconductor structure according to claim 1, wherein: The forming of the isolation structure filling the isolation trench includes: forming an isolation material layer filling the isolation trench and covering the mask structure; The isolation material layer is ground until the upper surface of the substrate is exposed to form the isolation structure.

14. The method for preparing a semiconductor structure according to any one of claims 1 to 13, wherein: The depth of the first trench is greater than the depth of the second trench.

15. A semiconductor structure formed by the method according to any one of claims 1 to 14, characterized in that: include: A substrate having an isolation trench; the isolation trench comprises: a first trench extending along a first direction, and a second trench connected to the first trench and extending along a second direction; the second direction intersects the first direction; an isolation structure, filling the isolation trench and separating a plurality of active areas in the substrate; a buffer layer, disposed on a sidewall of the active area extending along the first direction; The orthographic projection shape of the active region on the substrate surface includes a parallelogram.

Images