Semiconductor structure and manufacturing method thereof, and electronic device

Abstract

A semiconductor structure, a manufacturing method thereof, and an electronic device. The semiconductor structure includes a substrate and a stacked structure located on the substrate, wherein the stacked structure includes, from top to bottom, M conductive segment groups, the M conductive segment groups being stacked sequentially, each of the M conductive segment groups including two conductive segments located on the same straight line extending along a first horizontal direction and spaced apart from each other, the region between the two conductive segments in the 2i-th conductive segment group serving as a first spacing region, and the region between the two conductive segments in the 2i-th conductive segment group serving as a second spacing region, the plurality of first spacing regions being distributed substantially in a step-like manner, and the plurality of second spacing regions being distributed substantially in a step-like manner, wherein M is a positive integer greater than or equal to 2, and i is a positive integer, i=1, 2, 3, ..., M / 2. The semiconductor structure can optimize wiring arrangements in three-dimensional stacked semiconductor devices and improve the uniformity of winding extension lengths.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a semiconductor structure, a manufacturing method thereof, and an electronic device. Background Art

[0002] To improve the performance and device density of semiconductor devices, three-dimensional stacked semiconductor devices have been developed. For example, in a three-dimensional stacked semiconductor device, two or more transistors can be stacked vertically, two or more capacitors can be stacked vertically, and transistors and capacitors located on the same level can be coupled to each other to form a memory cell.

[0003] However, in the manufacture of three-dimensional stacked semiconductor devices, vertically stacked wires and corresponding connection / contact structures are often required to achieve the necessary electrical connections while reducing the occupied area. In three-dimensional stacked semiconductor devices, the vertically stacked wires often have different extension lengths, resulting in significant differences in their electrical parameters (such as transmission resistance), which is not conducive to improving semiconductor device performance. Summary of the Invention

[0004] According to a first aspect of an embodiment of the present disclosure, a method for manufacturing a semiconductor structure is provided, comprising: providing an initial semiconductor structure, wherein the initial semiconductor structure comprises a substrate and an initial stacking structure located on the substrate, the initial stacking structure comprising M levels from top to bottom, each level comprising a first layer and a second layer stacked in sequence; etching the initial stacking structure located in a first region to form a stepped structure extending along a first horizontal direction, wherein M sacrificial patterns are provided in the stepped structure, the 2i-1th sacrificial pattern of the M sacrificial patterns being located at a first end of a first layer in a 2i-1th level of the M levels, the 2ith sacrificial pattern of the M sacrificial patterns being located at a second end of a first layer in a 2i-1th level of the M levels, the multiple sacrificial patterns located in odd-numbered levels being distributed in a substantially stepped manner, and the multiple sacrificial patterns located in even-numbered levels being distributed in a substantially stepped manner; etching the initial stacking structure located in a second region The first layer of the M levels in the structure is replaced with M conductive lines, wherein the M conductive lines are respectively in contact with the M sacrificial patterns, and the second region is located on one side of the first region in a second horizontal direction, and the second horizontal direction is perpendicular to the first horizontal direction; the M sacrificial patterns are removed to form M horizontal openings, wherein the M horizontal openings respectively expose parts of the M conductive lines; the M conductive lines are laterally etched through the M horizontal openings to divide each of the M conductive lines into two conductive segments, the spacing region between the two conductive segments in the odd-numbered levels is used as a first spacing region, and the spacing region between the two conductive segments in the even-numbered levels is used as a second spacing region, a plurality of the first spacing regions are basically distributed in a step-like manner, and a plurality of the second spacing regions are basically distributed in a step-like manner; wherein M is a positive integer and a multiple of 2, and i is a positive integer, i=1, 2, 3, ..., M / 2.

[0005] In some embodiments, etching the initial stacking structure located in the first region to form the stepped structure extending along the first horizontal direction includes: etching the initial stacking structure located in the first region to form an initial stepped structure, wherein the initial stepped structure includes M initial step portions, the 2i-1th initial step portion among the M initial step portions includes the 2i-1th level, and the 2ith initial step portion among the M initial step portions includes the 2i level; forming a first isolation pattern, wherein the first isolation pattern covers the side walls of the initial stepped structure; etching the M initial step portions to expose the side walls of the first layer in each of the M initial step portions; laterally etching to remove a portion of the first layer in each of the M initial step portions to form a first horizontal opening; and forming the M sacrificial patterns filling the first horizontal opening.

[0006] In some embodiments, in the step of etching the M initial step portions, the sidewalls at the first end of the first layer in the 2i-1th initial step portion and the sidewalls at the second end of the first layer in the 2ith initial step portion among the M initial step portions are exposed.

[0007] In some embodiments, M is a multiple of 4, and etching the initial stacked structure in the first region to form the stepped structure extending along the first horizontal direction includes: etching the initial stacked structure in the first region to form an initial stepped structure, wherein the initial stepped structure includes M / 2 initial step portions, the 2j-1 initial step portion of the M / 2 initial step portions includes the 4j-3 to 4j-1 levels, and the 2j-2 initial step portion of the M / 2 initial step portions includes the 4j-2 to 4j levels; forming a first isolation pattern , wherein the first isolation pattern covers the sidewalls of the initial stepped structure; etching the M / 2 initial step portions to expose the sidewalls of the first layer in the 4j-3 level in the 2j-1 initial step portion and the sidewalls of the first layer in the 4j-2 level in the 2j initial step portion; laterally etching away a portion of the first layer in the 4j-3 level in the 2j-1 initial step portion and a portion of the first layer in the 4j-2 level in the 2j initial step portion to form a second horizontal opening; forming a first sacrificial pattern filling the second horizontal opening ; Continue etching the M / 2 initial step portions to expose the sidewall of the first layer in the 4j-2 level in the 2j-1 th initial step portion and the sidewall of the first layer in the 4j-1 th level in the 2j th initial step portion; Laterally etch away a portion of the first layer in the 4j-2 level in the 2j-1 th initial step portion and a portion of the first layer in the 4j-1 th level in the 2j th initial step portion to form a third horizontal opening; Form an insulating pattern filling the third horizontal opening; Continue etching the M / 2 initial step portions to expose the sidewall of the first layer in the 4j-2 level in the 2j-1 th initial step portion and the sidewall of the first layer in the 4j-1 th level in the 2j th initial step portion; Laterally etch away a portion of the first layer in the 4j-2 level in the 2j-1 th initial step portion and the sidewall ... -1 initial step portion and the side wall of the first layer in the 4j-1 level in the 2j-1 initial step portion and the side wall of the first layer in the 4j level in the 2j-1 initial step portion; laterally etching away a portion of the first layer in the 4j-1 level in the 2j-1 initial step portion and a portion of the first layer in the 4j level in the 2j initial step portion to form a fourth horizontal opening; forming a second sacrificial pattern filling the fourth horizontal opening; wherein the M sacrificial patterns include the first sacrificial pattern and the second sacrificial pattern, j is a positive integer, j=1, 2, 3, ..., M / 4.

[0008] In some embodiments, in the step of etching the M / 2 initial step portions, the side walls at the first end of the first layer in the 4j-3 level in the 2j-1 initial step portion and the side walls at the second end of the first layer in the 4j-2 level in the 2j initial step portion are exposed.

[0009] In some embodiments, replacing the first layer of the M levels in the initial stacked structure located in the second region with the M conductive lines includes: etching the initial stacked structure located in the third region to expose the side walls of the M levels in the initial stacked structure located in the second region, wherein the third region is located on a side of the second region away from the first region in the second horizontal direction; laterally etching away the first layer of the M levels in the initial stacked structure located in the second region to form M fifth horizontal openings; and forming the M conductive lines that respectively fill the M fifth horizontal openings.

[0010] In some embodiments, the M conductive lines extend along the first horizontal direction, and each of the M conductive lines includes a lateral recess contacting the corresponding sacrificial pattern.

[0011] In some embodiments, removing the M sacrificial patterns to form the M horizontal openings includes: etching the initial stacked structure located in the fourth region to expose the side walls of the M sacrificial patterns, wherein the fourth region is located on a side of the first region away from the second region in the second horizontal direction; and laterally etching to remove the M sacrificial patterns.

[0012] According to a second aspect of an embodiment of the present disclosure, a semiconductor structure is provided, comprising: a substrate; a stacked structure located on the substrate, wherein the stacked structure comprises M conductive segment groups from top to bottom, the M conductive segment groups being stacked in sequence, each of the M conductive segment groups comprising two conductive segments located on the same straight line extending along a first horizontal direction and spaced apart from each other, a spacing region between the two conductive segments in a 2i-1th conductive segment group among the M conductive segment groups serving as a first spacing region, and a spacing region between the two conductive segments in a 2ith conductive segment group among the M conductive segment groups serving as a second spacing region, a plurality of the first spacing regions being distributed substantially in a step-like manner, and a plurality of the second spacing regions being distributed substantially in a step-like manner, wherein M is a positive integer greater than or equal to 2, i is a positive integer, i=1, 2, 3, ..., M / 2.

[0013] In some embodiments, an area of ​​an overlapping portion of an orthographic projection of the first spacing region in the 2i-1th conductive segment group on the substrate and an orthographic projection of the first spacing region in the 2i+1th conductive segment group on the substrate is less than or equal to 20% of an area of ​​an orthographic projection of the first spacing region in the 2i-1th conductive segment group on the substrate, and an area of ​​an overlapping portion of an orthographic projection of the second spacing region in the 2ith conductive segment group on the substrate and an orthographic projection of the second spacing region in the 2i+2th conductive segment group on the substrate is less than or equal to 20% of an area of ​​an orthographic projection of the second spacing region in the 2i+2th conductive segment group on the substrate.

[0014] In some embodiments, M is a multiple of 4, the area of ​​the overlapping portion of the orthographic projection of the first spacing region in the 4j-3th conductive segment group and the orthographic projection of the first spacing region in the 4j-1th conductive segment group on the substrate is greater than or equal to 80% of the area of ​​the orthographic projection of the first spacing region in the 4j-3th conductive segment group on the substrate, and the area of ​​the overlapping portion of the orthographic projection of the second spacing region in the 4j-2th conductive segment group and the orthographic projection of the second spacing region in the 4jth conductive segment group on the substrate is greater than or equal to 80% of the area of ​​the orthographic projection of the second spacing region in the 4jth conductive segment group on the substrate, where j is a positive integer, j=1, 2, 3, ..., M / 4.

[0015] In some embodiments, one of the two conductive segments in the 4j-2th conductive segment group has a first lateral recess, and the first lateral recess is located between the first spacing region in the 4j-3th conductive segment group and the first spacing region in the 4j-1th conductive segment group; one of the two conductive segments in the 4j-3th conductive segment group has a second lateral recess, and the second lateral recess is located between the second spacing region in the 4j-2th conductive segment group and the second spacing region in the 4jth conductive segment group.

[0016] In some embodiments, the stack structure further includes at least one of a first air gap and a second air gap, wherein the first air gap is at least partially located in the first spacing region, and the second air gap is at least partially located in the second spacing region.

[0017] In some embodiments, the semiconductor structure further includes M / 2 sense amplifier structures from top to bottom, the M / 2 sense amplifier structures being stacked in sequence, each sense amplifier structure including a first P-type transistor and a second P-type transistor stacked in sequence and a first N-type transistor and a second N-type transistor stacked in sequence, one of the two conductive segments in the 2i-1th conductive segment group being coupled to the gates of the first P-type transistor and the first N-type transistor in the i-th sense amplifier structure, the other of the two conductive segments in the 2i-1th conductive segment group being coupled to the source and drain of the first P-type transistor and the first N-type transistor in the i-th sense amplifier structure, and the two conductive segments in the 2i-1th conductive segment group being coupled to the source and drain of the first P-type transistor and the first N-type transistor in the i-th sense amplifier structure. One of the conductive segments is coupled to the source and drain of the second P-type transistor and the second N-type transistor in the i-th sense amplifier structure, which are close to each other, and the other of the two conductive segments in the 2i-th conductive segment group is coupled to the gate of the second P-type transistor and the second N-type transistor in the i-th sense amplifier structure; each sense amplifier structure further includes a first connection structure and a second connection structure, the first connection structure is coupled to one of the two conductive segments in the 2i-1th conductive segment group and one of the two conductive segments in the 2i-th conductive segment group, and the second connection structure is coupled to the other of the two conductive segments in the 2i-1th conductive segment group and the other of the two conductive segments in the 2i-th conductive segment group.

[0018] According to a third aspect of an embodiment of the present disclosure, an electronic device is provided, comprising a processor and a memory. The memory is coupled to the processor and comprises the semiconductor structure provided by any embodiment of the present disclosure.

[0019] In the embodiments of the present disclosure, by providing sacrificial patterns that are substantially distributed in a step-like manner to achieve the cutting of vertically stacked conductive lines, the wiring arrangement in a three-dimensional stacked semiconductor device can be optimized and the uniformity of the winding extension length can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a schematic diagram of a partial cross-sectional structure of a semiconductor structure;

[0021] Figure 2 A schematic flow chart of a method for manufacturing a semiconductor structure provided in some embodiments of the present disclosure;

[0022] Figure 3A A schematic top view of a structure obtained according to step S100 provided in some embodiments of the present disclosure;

[0023] Figure 3B For the Figure 3A Schematic diagram of the cross section taken along line K1-K2;

[0024] Figures 4A-4D A schematic diagram of a cross-sectional structure of various stages of forming an initial stepped structure provided by some embodiments of the present disclosure;

[0025] Figure 5A A schematic top view of a structure obtained according to step S201 provided in some embodiments of the present disclosure;

[0026] Figure 5B For the Figure 5A A schematic cross-sectional view taken along line A1-A2 in FIG.

[0027] Figure 5C For the Figure 5A A schematic cross-sectional view taken along line B1-B2 in FIG.

[0028] Figure 6A and Figure 6B A schematic cross-sectional view of a structure obtained according to step S202 provided in some embodiments of the present disclosure;

[0029] Figure 7A and Figure 7B A schematic cross-sectional view of a structure obtained according to step S203 provided in some embodiments of the present disclosure;

[0030] Figure 8A and Figure 8B A schematic cross-sectional view of a structure obtained according to step S204 provided in some embodiments of the present disclosure;

[0031] Figure 9A and Figure 9B A schematic cross-sectional view of a structure obtained according to step S205 provided in some embodiments of the present disclosure;

[0032] Figures 10A-10C A schematic diagram of a cross-sectional structure of various stages of forming an initial stepped structure provided in some other embodiments of the present disclosure;

[0033] Figure 11A A schematic top view of a structure obtained according to step S211 provided in some embodiments of the present disclosure;

[0034] Figure 11B For the Figure 11A A schematic cross-sectional view taken along line A1-A2 in FIG.

[0035] Figure 11C For the Figure 11A A schematic cross-sectional view taken along line B1-B2 in FIG.

[0036] Figure 12A and Figure 12B A schematic cross-sectional view of a structure obtained according to step S212 provided in some embodiments of the present disclosure;

[0037] Figure 13A and Figure 13B A schematic cross-sectional view of a structure obtained according to steps S213 to S215 provided in some embodiments of the present disclosure;

[0038] Figure 14A and Figure 14B A schematic cross-sectional view of a structure obtained according to steps S216 to S218 provided in some embodiments of the present disclosure;

[0039] Figure 15A and Figure 15B A schematic cross-sectional view of a structure obtained according to steps S219 to S221 in some embodiments of the present disclosure;

[0040] Figure 16A A schematic top view of a structure obtained after forming a planarization layer according to some embodiments of the present disclosure;

[0041] Figure 16B and Figure 16C A schematic cross-sectional view of a structure obtained after forming a planarization layer according to some embodiments of the present disclosure;

[0042] Figure 16D and Figure 16E Schematic cross-sectional view of a structure obtained after forming a planarization layer according to other embodiments of the present disclosure;

[0043] Figure 17A A schematic top view of a structure obtained according to step S301 provided in some embodiments of the present disclosure;

[0044] Figure 17B A schematic cross-sectional view of a structure obtained according to step S301 provided in some embodiments of the present disclosure;

[0045] Figure 17C A schematic cross-sectional view of a structure obtained according to step S301 provided in some other embodiments of the present disclosure;

[0046] Figure 18A A schematic cross-sectional view of a structure obtained according to step S302 and step S303 provided in some embodiments of the present disclosure;

[0047] Figure 18B for Figure 18A A schematic top view of the conductive line 200 and the sacrificial pattern SQ located at the same level in the structure shown;

[0048] Figure 18C Schematic cross-sectional view of the structure obtained according to step S302 and step S303 provided in some other embodiments of the present disclosure;

[0049] Figure 18D for Figure 18CA schematic top view of the conductive line 200, the sacrificial pattern SQ and the insulating pattern IL located at the same level in the structure shown;

[0050] Figure 19A A schematic top view of a structure obtained according to step S401 provided in some embodiments of the present disclosure;

[0051] Figure 19B A schematic cross-sectional view of a structure obtained according to step S401 provided in some embodiments of the present disclosure;

[0052] Figure 19C for Figure 18B A schematic top view of the conductive line 200 and the sacrificial pattern SQ located at the same level in the structure shown;

[0053] Figure 19D A schematic cross-sectional view of a structure obtained according to step S401 provided in some other embodiments of the present disclosure;

[0054] Figure 19E for Figure 18D A schematic top view of the conductive line 200, the sacrificial pattern SQ and the insulating pattern IL located at the same level in the structure shown;

[0055] Figure 20A A schematic cross-sectional view of a structure obtained according to step S402 provided in some embodiments of the present disclosure;

[0056] Figure 20B Shown Figure 19C Schematic diagram of the sacrificial pattern SQ being completely removed;

[0057] Figure 20C Shown Figure 19C Schematic diagram of a sacrificial pattern SQ being partially removed;

[0058] Figure 20D A schematic cross-sectional view of a structure obtained according to step S402 provided in some other embodiments of the present disclosure;

[0059] Figure 20E Shown Figure 19E Schematic diagram of the sacrificial pattern SQ being completely removed;

[0060] Figure 20F Shown Figure 19E Schematic diagram of a sacrificial pattern SQ being partially removed;

[0061] Figure 21A A schematic cross-sectional view of a structure obtained according to step S500 provided in some embodiments of the present disclosure;

[0062] Figure 21B For the Figure 21AA schematic cross-sectional view taken along the vertical dashed line in FIG.

[0063] Figure 21C for Figure 21B A schematic top view of two conductive segments located at the same level in FIG;

[0064] Figure 21D A schematic cross-sectional view of a structure obtained according to step S500 provided in some other embodiments of the present disclosure;

[0065] Figure 21E For the Figure 21D A schematic cross-sectional view taken along the vertical dashed line in FIG.

[0066] Figure 21F for Figure 21E A schematic top view of two conductive segments located at the same level in FIG;

[0067] Figure 22A Schematic diagram of a circuit structure of a sense amplifier structure;

[0068] Figure 22B and Figure 22C A schematic diagram of a partial planar structure of two levels of a sense amplifier structure in a semiconductor structure provided by some embodiments of the present disclosure;

[0069] Figure 22D A schematic diagram of a plurality of connection structures stacked in sequence according to some embodiments of the present disclosure;

[0070] Figure 23 A schematic block diagram of the structure of an electronic device provided in some embodiments of the present disclosure. DETAILED DESCRIPTION

[0071] The technical solutions of the present disclosure will be further described in detail below with reference to the accompanying drawings and examples. Although the accompanying drawings illustrate exemplary implementations of the present disclosure, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0072] The following paragraphs describe the present disclosure in more detail by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become more apparent from the following description and claims. It should be noted that the drawings are highly simplified and not to exact scale, and are intended solely to facilitate and clearly illustrate the embodiments of the present disclosure.

[0073] It will be understood that the meanings of “on,” “over,” and “over” throughout this disclosure should be interpreted in the broadest manner, such that “on” not only means being “on” something with no intervening features or layers (i.e., directly on something), but also includes being “on” something with intervening features or layers.

[0074] In the embodiments of the present disclosure, the terms "first," "second," "third," etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0075] In the embodiments of the present disclosure, the term "layer" refers to a portion of a material including an area having a thickness. A layer may extend over the entirety of a lower or upper structure, or may have an extent that is smaller than the extent of the lower or upper structure. In addition, a layer may be an area of ​​a homogeneous or inhomogeneous continuous structure having a thickness that is smaller than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be between any horizontal faces at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.

[0076] In the embodiments of the present disclosure, the term "coupling" refers to two (or more) conductive structures being operably connected to each other. Depending on actual needs, it may include but is not limited to the following situations: 1) the two conductive structures are directly electrically connected; 2) the two conductive structures are indirectly electrically connected (through other conductive structures); 3) although the two conductive structures are not electrically connected (for example, an insulating layer is provided between the two), one of the two conductive structures can control the electrical properties of the other of the two conductive structures in response to an electrical signal, for example, the gate (or word line) is coupled with the active area (or channel area).

[0077] It should be noted that the technical solutions and technical features described in the embodiments of the present disclosure can be arbitrarily combined without conflict.

[0078] Figure 1 This is a schematic diagram of a partial cross-sectional structure of a semiconductor structure, which can be used as a part of a three-dimensional stacked semiconductor device to achieve the necessary electrical connections in the three-dimensional stacked semiconductor device. Figure 1As shown, the semiconductor structure includes a plurality of conductive layers CL1-CL8 stacked on a substrate 100, and the ends of the plurality of conductive layers CL1-CL8 are formed into a stepped structure; through the conductive layers CL1-CL8 and the conductive plugs CP1-CP8 located on the ends of the conductive layers CL1-CL8, the mutual electrical connection between the transistors and / or other components in the three-dimensional stacked semiconductor device and the electrical connection between the transistors and / or other components in the three-dimensional stacked semiconductor device and the external circuit can be achieved. In other words, in order to achieve the above-mentioned electrical connection, it is usually necessary to set up a stepped structure, conductive plugs and external windings. Figure 1 It can be seen that the extension lengths of the conductive layers CL1-CL8 are different, among which the extension length of the conductive layer CL1 is the shortest and the extension length of the conductive layer CL8 is the longest; similarly, the extension lengths of the conductive plugs CP1-CP8 are different, among which the extension length of the conductive plug CP1 is the shortest and the extension length of the conductive plug CP8 is the longest; thus, there is a large difference between the transmission resistance of the transmission path formed by the conductive layer CL1 and the conductive plug CP1 and the transmission resistance of the transmission path formed by the conductive layer CL8 and the conductive plug CP8, which is not conducive to improving the performance of the semiconductor device.

[0079] It should be noted that Figure 1 The number of conductive layers and the number of conductive plugs are exemplary; in addition, it can be understood that Figure 1 The unmarked layers are dielectric layers and / or insulating layers.

[0080] At least some embodiments of the present disclosure provide a method for manufacturing a semiconductor structure. The manufacturing method includes: providing an initial semiconductor structure, wherein the initial semiconductor structure includes a substrate and an initial stacking structure located on the substrate, the initial stacking structure including M levels from top to bottom, each level including a first layer and a second layer stacked in sequence; etching the initial stacking structure located in a first region to form a stepped structure extending along a first horizontal direction, wherein the stepped structure is provided with M sacrificial patterns, the 2i-1th sacrificial pattern of the M sacrificial patterns is located at the first end of the first layer of the 2i-1th level of the M levels, the 2ith sacrificial pattern of the M sacrificial patterns is located at the second end of the first layer of the 2ith level of the M levels, the multiple sacrificial patterns located in the odd levels are basically distributed in a stepped manner, and the multiple sacrificial patterns located in the even levels are basically distributed in a stepped manner; the M sacrificial patterns in the initial stacking structure located in the second region are etched. The first layer in the layers is replaced with M conductive lines, wherein the M conductive lines are in contact with M sacrificial patterns respectively, and the second region is located on one side of the first region in a second horizontal direction, and the second horizontal direction is perpendicular to the first horizontal direction; the M sacrificial patterns are removed to form M horizontal openings, wherein the M horizontal openings respectively expose parts of the M conductive lines; the M conductive lines are laterally etched from the M horizontal openings to divide each of the M conductive lines into two conductive segments, the region between the two conductive segments in the odd layers is used as a first spacing region, and the spacing between the two conductive segments in the even layers is used as a second spacing region, the multiple first spacing regions are basically distributed in a step-like manner, and the multiple second spacing regions are basically distributed in a step-like manner; wherein M is a positive integer and a multiple of 2, and i is a positive integer, i=1, 2, 3, ..., M / 2.

[0081] In the manufacturing method provided in the embodiment of the present disclosure, by setting a sacrificial pattern with a basically stepped distribution to achieve the cutting of the vertically stacked conductive wires, the wiring setting in the three-dimensional stacked semiconductor device can be optimized and the uniformity of the winding extension length can be improved.

[0082] Figure 2 A schematic flow chart of a method for manufacturing a semiconductor structure provided in some embodiments of the present disclosure. Figure 2 As shown, the manufacturing method may include the following steps S100 to S500.

[0083] S100: Provide an initial semiconductor structure, wherein the initial semiconductor structure includes a substrate and an initial stacking structure located on the substrate, the initial stacking structure includes M levels from top to bottom, each level includes a first layer and a second layer stacked in sequence, and M is a positive integer and a multiple of 2.

[0084] For example, the initial stacking structure may include multiple levels, and the M levels may be part or all of the multiple levels.

[0085] Figure 3A A schematic top view of a structure obtained according to step S100 provided in some embodiments of the present disclosure; Figure 3B For the Figure 3A A schematic cross-sectional view of the K1-K2 line in FIG. Figure 3A and Figure 3B As shown, step S100 may include: sequentially forming an etch stop layer 105, an alternating first layer 110 and a second layer 120, and a hard mask layer 125 on a substrate 100. For example, the initial stacked structure includes the etch stop layer 105, the alternating first layer 110 and the second layer 120, and the hard mask layer 125. For example, the substrate 100 may include, but is not limited to, a silicon substrate, a silicon-on-insulator substrate, etc. For example, the material of the etch stop layer 105 may include, but is not limited to, silicon carbide (SiC) or silicon carbon nitride (SiCN). For example, the first layer 110 may be a dielectric layer, and its material may include, but is not limited to, silicon oxide (SiO2), silicon nitride (SiN), or silicon oxynitride (SiON). The material of the first layer 110 may also include, but is not limited to, polycrystalline silicon, amorphous silicon, etc. For example, the second layer 120 may be a dielectric layer, and its material may include, but is not limited to, silicon oxide (SiO2), silicon nitride (SiN), or silicon oxynitride (SiON). For example, the material of the hard mask layer 125 may include, but is not limited to, silicon nitride (SiN), silicon carbide (SiC), silicon carbon nitride (SiCN), amorphous carbon, etc. It is understood that the materials of the first layer 110, the second layer 120, and the hard mask layer 130 are usually different from each other, and usually have a certain etching selectivity ratio between them.

[0086] For example, Figure 3B As shown, each level includes a first layer 110 and a second layer 120 located on and adjacent to the first layer 110. Eight levels T1-T8 (ie, M=8) are shown in the figure, but this should not be considered as a limitation to the present disclosure.

[0087] S200: Etching the initial stacked structure located in the first area to form a stepped structure extending along the first horizontal direction, wherein M sacrificial patterns are provided in the stepped structure, the 2i-1th sacrificial pattern among the M sacrificial patterns is located at the first end of the first layer in the 2i-1th level of the M levels, the 2ith sacrificial pattern among the M sacrificial patterns is located at the second end of the first layer in the 2ith level of the M levels, the multiple sacrificial patterns located in the odd levels are basically distributed in a stepped shape, and the multiple sacrificial patterns located in the even levels are basically distributed in a stepped shape, i is a positive integer, i=1, 2, 3, ..., M / 2.

[0088] For example, in some embodiments, step S200 may include the following steps S201 to S205.

[0089] S201: etching an initial stacked structure in the first region to form an initial stepped structure, wherein the initial stepped structure includes M initial stepped portions, a 2i-1th initial stepped portion among the M initial stepped portions includes a 2i-1th level, and a 2ith initial stepped portion among the M initial stepped portions includes a 2ith level;

[0090] S202: forming a first isolation pattern, wherein the first isolation pattern covers a sidewall of the initial stepped structure;

[0091] S203: etching M initial step portions to expose a sidewall of the first layer in each of the M initial step portions;

[0092] S204: Laterally etching and removing a portion of the first layer in each of the M initial step portions to form a first horizontal opening;

[0093] S205 : forming M sacrificial patterns filling the first horizontal opening.

[0094] Figures 4A-4D A schematic diagram of a cross-sectional structure of various stages of forming an initial staircase structure according to some embodiments of the present disclosure. For example, in step S201, a photoresist layer PR1 with an opening may be formed on the initial stacked structure, and the photoresist layer PR1 may be used as a mask to etch the hard mask layer 125 and one level to obtain the following: Figure 4A Then, the photoresist layer PR1 is removed to form a photoresist layer PR2 having an opening, and the current photoresist layer PR2 is used as a mask to etch the hard mask layer 125 and two levels to obtain a Figure 4B Afterwards, the photoresist layer PR2 may be processed so that the photoresist layer PR2 shrinks inwardly, and using the current photoresist layer PR2 as a mask, the hard mask layer 125 and the two levels are etched to obtain a Figure 4C Then, the above steps can be repeated (ie, the photoresist layer PR2 is processed so that the photoresist layer PR2 shrinks inward, and the current photoresist layer PR2 is used as a mask to etch the hard mask layer 125 and the two-level step) until the desired initial step structure (ie, as shown) is obtained. Figure 4D finally, the remaining photoresist layer PR2 may be removed, or the hard mask layer 125 may be etched to a target state (see related description below) and then the remaining photoresist layer PR2 may be removed.

[0095] Figure 5A A schematic top view of a structure obtained according to step S201 provided in some embodiments of the present disclosure; Figure 5B For the Figure 5AA schematic cross-sectional view taken along line A1-A2 in FIG. Figure 5C For the Figure 5A Schematic diagram of the cross section taken along line B1-B2 in ( Figure 5B The vertical dashed line in the figure is located within the section. For example, Figures 5A-5C As shown, in Figure 3A and Figure 3B Based on the structure shown, you can refer to Figures 4A-4D The method for forming the initial staircase structure shown in FIG. 1 is to etch the initial stacked structure in the first region R1 to form an initial staircase structure extending along the first horizontal direction X. For example, Figure 5B As shown, the initial step structure includes 8 initial step portions ST1-ST8; among the 8 initial step portions ST1-ST8, the first initial step portion ST1 includes the first level T1, the second initial step portion ST2 includes the second level T2, the third initial step portion ST3 includes the third level T3, the fourth initial step portion ST4 includes the fourth level T4, the fifth initial step portion ST5 includes the fifth level T5, the sixth initial step portion ST6 includes the sixth level T6, the seventh initial step portion ST7 includes the seventh level T7, and the eighth initial step portion ST8 includes the eighth level T8.

[0096] Figure 6A and Figure 6B Schematic diagram of a cross section of the structure obtained according to step S202 provided in some embodiments of the present disclosure. Figure 6A and Figure 6B As shown, in Figures 5A-5C Based on the structure shown, the hard mask layer 125 can be first etched to expose a portion of the top surface of the initial stepped portion ST1 (i.e., the hard mask layer 125 is etched to a target state); then, a first isolation material layer is conformally deposited and etched back to remove the portions of the first isolation material layer located on the top surfaces of the initial stepped structure (including the top surface of the hard mask layer 125, the exposed top surfaces of the initial stepped portions ST1-ST8, and the exposed top surface of the etch-stop layer 105). The portions of the first isolation material layer remaining on the sidewalls of the initial stepped structure serve as the first isolation pattern SP1. For example, the material of the first isolation material layer can be different from the material of any of the etch-stop layer 105, the first layer 110, the second layer 120, and the hard mask layer 125.

[0097] Figure 7A and Figure 7B Schematic diagram of the cross section of the structure obtained according to step S203 provided in some embodiments of the present disclosure. Figure 7A and Figure 7B As shown, in Figure 6A and Figure 6BBased on the structure shown in FIG. 1 , the initial step portions ST1-ST8 can be etched simultaneously to expose the sidewall of the first layer 110 in each of the initial step portions ST1-ST8. For example, after etching the initial step portions ST1-ST8, the first end of the first layer 110 in the initial step portions ST1, ST3, ST5, and ST7 is exposed (e.g., Figure 7A The side wall of the first layer 110 in the initial step portions ST2, ST4, ST6, and ST8 (such as the right end) and the second end of the first layer 110 in the initial step portions ST2, ST4, ST6, and ST8 (such as Figure 7A That is, in step S203, after etching the M initial step portions, the sidewall of the first end of the first layer in the 2i-1th initial step portion and the sidewall of the second end of the first layer in the 2ith initial step portion are exposed.

[0098] Figure 8A and Figure 8B Schematic diagram of a cross section of the structure obtained according to step S204 provided in some embodiments of the present disclosure. Figure 8A and Figure 8B As shown, in Figure 7A and Figure 7B Based on the structure shown in FIG. 1 , the first layer 110 in the initial step portions ST1 - ST8 can be removed by synchronous lateral etching to form corresponding first horizontal openings HP1. Figure 8B As shown, the first horizontal opening HP1 may extend beyond the first region R1 ; of course, the first horizontal opening may also be located only within the first region R1 .

[0099] Figure 9A and Figure 9B Schematic diagram of a cross section of the structure obtained according to step S205 provided in some embodiments of the present disclosure. Figure 9A and Figure 9B As shown, in Figure 8A and Figure 8B Based on the structure shown, a sacrificial material layer can be conformally deposited to fill the first horizontal opening HP1, and the portion of the sacrificial material layer outside the first horizontal opening HP1 can be etched away. The portion of the sacrificial material layer remaining in the first horizontal opening HP1 serves as the sacrificial pattern SQ. For example, the material of the sacrificial material layer can be different from the material of any of the etch stop layer 105, the first layer 110, the second layer 120, and the first isolation pattern SP1. It is understood that the planar shape of the sacrificial pattern SQ can be a "U" shape. For example, as shown in FIG. Figure 9AAs shown, the multiple sacrificial patterns in the odd-numbered levels T1, T3, T5, and T7 are generally arranged in a stair-like pattern (one of the two adjacent sacrificial patterns is offset relative to the other in both the horizontal and vertical directions), while the multiple sacrificial patterns in the even-numbered levels T2, T4, T6, and T8 are generally arranged in a stair-like pattern. For example, the remaining portion of the initial stair-like structure can be used as a stair-like structure.

[0100] For example, in some embodiments, Figure 9A and Figure 9B Based on the structure shown in FIG. 1 , a planarization layer covering the step structure can be formed by a spin coating process (see the planarization layer 135 described below). Figure 9A and Figure 9B Based on the structure shown, the first isolation pattern SP1 can be selectively etched to remove part or all of the first isolation pattern SP1, and then a planarization layer covering the stepped structure can be formed by spin coating, thereby helping to improve the quality of the planarization layer. For example, the material of the planarization layer can be different from the material of the sacrificial pattern SQ. For example, the material of the planarization layer can be the same as the material of either the second layer 120 or the first isolation pattern SP1, but is not limited thereto.

[0101] For example, in some other embodiments, M is a multiple of 4. In this case, step S200 may include the following steps S211 to S221.

[0102] S211: etching the initial stacked structure in the first region to form an initial stepped structure, wherein the initial stepped structure includes M / 2 initial step portions, the 2j-1th initial step portion of the M / 2 initial step portions includes the 4j-3th to 4j-1th levels, and the 2jth initial step portion of the M / 2 initial step portions includes the 4j-2th to 4jth levels, where j is a positive integer, j=1, 2, 3, ..., M / 4;

[0103] S212: forming a first isolation pattern, wherein the first isolation pattern covers a sidewall of the initial stepped structure;

[0104] S213: etching M / 2 initial step portions to expose the sidewall of the first layer in the 4j-3th level in the 2j-1th initial step portion and the sidewall of the first layer in the 4j-2th level in the 2jth initial step portion;

[0105] S214: Laterally etching and removing a portion of the first layer in the 4j-3th level in the 2j-1th initial step portion and a portion of the first layer in the 4j-2th level in the 2jth initial step portion to form a second horizontal opening;

[0106] S215: forming a first sacrificial pattern filling the second horizontal opening;

[0107] S216: Continue etching M / 2 initial step portions to expose the sidewall of the first layer in the 4j-2th level in the 2j-1th initial step portion and the sidewall of the first layer in the 4j-1th level in the 2jth initial step portion;

[0108] S217: Laterally etching and removing a portion of the first layer in the 4j-2th level in the 2j-1th initial step portion and a portion of the first layer in the 4j-1th level in the 2jth initial step portion to form a third horizontal opening;

[0109] S218: forming an insulating pattern filling the third horizontal opening;

[0110] S219: Continue etching M / 2 initial step portions to expose the sidewall of the first layer in the 4j-1th level in the 2j-1th initial step portion and the sidewall of the first layer in the 4jth level in the 2jth initial step portion;

[0111] S220 : Laterally etching and removing a portion of the first layer in the 4j-1th level in the 2j-1th initial step portion and a portion of the first layer in the 4jth level in the 2jth initial step portion to form a fourth horizontal opening;

[0112] S221 : forming a second sacrificial pattern filling the fourth horizontal opening.

[0113] Figures 10A-10C Schematic diagram of a cross-sectional structure of each stage of forming an initial step structure provided by another embodiment of the present disclosure. For example, in step S211, a photoresist layer PR1 with an opening can be formed on the initial stacked structure, and the photoresist layer PR1 is used as a mask to etch the hard mask layer 125 and one level to obtain the following: Figure 10A then, removing the photoresist layer PR1, forming a photoresist layer PR2 having an opening, and using the current photoresist layer PR2 as a mask, etching the hard mask layer 125 and the four levels to obtain as shown Figure 10B Afterwards, the photoresist layer PR2 may be processed so that the photoresist layer PR2 shrinks inwardly, and using the current photoresist layer PR2 as a mask, the hard mask layer 125 and the four levels are etched to obtain a Figure 10C Then, if necessary (for example, M is large), the above steps (i.e., processing the photoresist layer PR2 so that the photoresist layer PR2 shrinks inward, and using the current photoresist layer PR2 as a mask, etching the hard mask layer 125 and the four-level step) can be repeated until the desired initial step structure (i.e., as shown) is obtained. Figure 4Dfinally, the remaining photoresist layer PR2 may be removed, or the hard mask layer 125 may be etched to a target state (see related description below) and then the remaining photoresist layer PR2 may be removed.

[0114] Figure 11A A schematic top view of a structure obtained according to step S211 provided in some embodiments of the present disclosure; Figure 11B For the Figure 11A A schematic cross-sectional view taken along line A1-A2 in FIG. Figure 11C For the Figure 11A Schematic diagram of the cross section taken along line B1-B2 in ( Figure 11B The vertical dashed line in the figure is located within the section. For example, Figures 11A-11C As shown, in Figure 3A and Figure 3B Based on the structure shown, you can refer to Figures 10A-10C The method for forming the initial staircase structure shown in FIG. 1 is to etch the initial stacked structure in the first region R1 to form an initial staircase structure extending along the first horizontal direction X. For example, Figure 11B As shown, the initial step structure includes four initial step portions SC1-SC4; among the four initial step portions SC1-SC4, the first initial step portion SC1 includes the first level T1 to the third level T3, the second initial step portion SC2 includes the second level T2 to the fourth level T4, the third initial step portion SC3 includes the fifth level T5 to the seventh level T7, and the fourth initial step portion SC4 includes the sixth level T6 to the eighth level T8.

[0115] Figure 12A and Figure 12B Schematic diagram of a cross section of the structure obtained according to step S212 provided in some embodiments of the present disclosure. Figure 12A and Figure 12B As shown, in Figures 11A-11C Based on the structure shown, the hard mask layer 125 can be first etched to expose a portion of the top surface of the initial stepped portion SC1 (i.e., the hard mask layer 125 is etched to a target state). Then, a first isolation material layer is conformally deposited and etched back to remove the portions of the first isolation material layer located on the top surfaces of the initial stepped structure (including the top surface of the hard mask layer 125, the exposed top surfaces of the initial stepped portions SC1-SC4, and the exposed top surface of the etch-stop layer 105). The portions of the first isolation material layer remaining on the sidewalls of the initial stepped structure serve as the first isolation pattern SP1. For example, the material of the first isolation material layer can be different from the material of any of the etch-stop layer 105, the first layer 110, the second layer 120, and the hard mask layer 125.

[0116] Figure 13A and Figure 13BSchematic cross-sectional view of the structure obtained according to steps S213 to S215 provided in some embodiments of the present disclosure. Figure 13A and Figure 13B As shown, in Figure 6A and Figure 6B Based on the structure shown, first, the initial step portions SC1-SC4 can be etched synchronously to expose the sidewalls of the first layer 110 in the 1st level T1 in the initial step portion SC1, the sidewalls of the first layer 110 in the 2nd level T2 in the initial step portion SC2, the sidewalls of the first layer 110 in the 5th level T5 in the initial step portion SC3, and the sidewalls of the first layer 110 in the 6th level T6 in the initial step portion SC4. It can be understood that in step S213, after etching M / 2 initial step portions, the first end of the first layer in the 4j-3th level in the 2j-1th initial step portion is exposed (as shown in FIG. Figure 11A The side wall of the right end in FIG) and the second end of the first layer in the 4j-2th level in the 2jth initial step portion (as shown in FIG). Figure 11A The sidewalls of the first layer 110 in the first level T1 of the initial step SC1, the first layer 110 in the second level T2 of the initial step SC2, the first layer 110 in the fifth level T5 of the initial step SC3, and the first layer 110 in the sixth level T6 of the initial step SC4 can then be simultaneously removed by lateral etching to form corresponding second horizontal openings. It will be appreciated that, similar to the aforementioned first horizontal openings, the second horizontal openings can extend beyond the first region R1; of course, the second horizontal openings can also be located solely within the first region R1. A first sacrificial material layer can then be conformally deposited to fill the second horizontal openings, and the portion of the first sacrificial material layer located outside the second horizontal openings can be etched away. The portion of the first sacrificial material layer remaining in the second horizontal openings serves as the first sacrificial pattern SQ1. For example, the material of the first sacrificial material layer can be different from the material of any of the etch-stop layer 105, the first layer 110, the second layer 120, and the first isolation pattern SP1. It is understood that the planar shape of the first sacrificial pattern SQ1 may be a “U” shape.

[0117] It is understandable that at least some implementation details of steps S213 to S215 can be referred to the relevant descriptions of steps S203 to S205 and will not be repeated here.

[0118] Figure 14A and Figure 14B The cross-sectional view of the structure obtained according to steps S216 to S218 is provided in some embodiments of the present disclosure. Figure 14A and Figure 14B As shown, in Figure 13A and Figure 13BBased on the structure shown, the initial step portions SC1-SC4 can first be simultaneously etched to expose the sidewalls of the first layer 110 in the second level T2 of the initial step portion SC1, the sidewalls of the first layer 110 in the third level T3 of the initial step portion SC2, the sidewalls of the first layer 110 in the sixth level T6 of the initial step portion SC3, and the sidewalls of the first layer 110 in the seventh level T7 of the initial step portion SC4. Subsequently, portions of the first layer 110 in the second level T2 of the initial step portion SC1, the first layer 110 in the third level T3 of the initial step portion SC2, the first layer 110 in the sixth level T6 of the initial step portion SC3, and the first layer 110 in the seventh level T7 of the initial step portion SC4 can be simultaneously removed by lateral etching to form a corresponding third horizontal opening. It will be appreciated that, similar to the aforementioned first horizontal opening, the third horizontal opening can extend beyond the first region R1; however, the third horizontal opening can also be located solely within the first region R1. Afterwards, an insulating material layer may be conformally deposited to fill the third horizontal opening, and the portion of the insulating material layer outside the third horizontal opening may be etched away. The portion of the insulating material layer remaining within the third horizontal opening serves as the insulating pattern IL. For example, the insulating pattern IL may be made of a material different from that of the first sacrificial pattern SQ1. For example, the insulating pattern IL may be made of the same material as, but is not limited to, the second layer 120 and the first isolation pattern SP1. It is understood that the insulating pattern IL may have a U-shaped plan view.

[0119] Figure 15A and Figure 15B Schematic cross-sectional view of the structure obtained according to steps S219 to S221 in some embodiments of the present disclosure. Figure 15A and Figure 15B As shown, in Figure 14A and Figure 14BBased on the structure shown, the initial step portions SC1-SC4 can first be simultaneously etched to expose the sidewalls of the first layer 110 in the third level T3 of the initial step portion SC1, the sidewalls of the first layer 110 in the fourth level T4 of the initial step portion SC2, the sidewalls of the first layer 110 in the seventh level T7 of the initial step portion SC3, and the sidewalls of the first layer 110 in the eighth level T8 of the initial step portion SC4. Subsequently, portions of the first layer 110 in the third level T3 of the initial step portion SC1, the first layer 110 in the fourth level T4 of the initial step portion SC2, the first layer 110 in the seventh level T7 of the initial step portion SC3, and the first layer 110 in the eighth level T8 of the initial step portion SC4 can be simultaneously removed by lateral etching to form a corresponding fourth horizontal opening. It will be appreciated that, similar to the aforementioned first horizontal opening, the fourth horizontal opening can extend beyond the first region R1; however, the fourth horizontal opening can also be located solely within the first region R1. Thereafter, a second sacrificial material layer may be conformally deposited to fill the fourth horizontal opening, and the portion of the second sacrificial material layer outside the fourth horizontal opening may be etched away. The portion of the second sacrificial material layer remaining within the fourth horizontal opening serves as the second sacrificial pattern SQ2. For example, the material of the second sacrificial pattern SQ2 may be different from the material of the insulating pattern IL. For example, the material of the second sacrificial pattern SQ2 may be the same as that of the first sacrificial pattern SQ1. It will be appreciated that the planar shape of the second sacrificial pattern SQ2 may be a "U" shape.

[0120] It is understandable that at least some implementation details of steps S219 to S221 can be referred to the relevant descriptions of steps S203 to S205 and will not be repeated here.

[0121] It is understood that the M sacrificial patterns include a first sacrificial pattern SQ1 and a second sacrificial pattern SQ2. Figure 15A As shown, the multiple sacrificial patterns located in the odd-numbered levels T1, T3, T5, and T7 are basically distributed in a stair-like manner (the sacrificial patterns SQ1 and SQ2 located in the levels T1 and T3 can be regarded as one overall structure, and the sacrificial patterns SQ1 and SQ2 located in the levels T5 and T7 can be regarded as another overall structure, and the two overall structures are distributed in a stair-like manner). The multiple sacrificial patterns located in the even-numbered levels T2, T4, T6, and T8 are basically distributed in a stair-like manner (the sacrificial patterns SQ1 and SQ2 located in the levels T2 and T4 can be regarded as one overall structure, and the sacrificial patterns SQ1 and SQ2 located in the levels T6 and T8 can be regarded as another overall structure, and the two overall structures are distributed in a stair-like manner). For example, the remaining portion of the initial stair-like structure can be used as a stair-like structure.

[0122] It can be understood that, compared with the embodiment described in steps S201 to S205 , the embodiment described in steps S211 to S221 can reduce the number of steps in the stepped structure, thereby reducing the occupied area of ​​the stepped structure.

[0123] For example, in some embodiments, Figure 15A and Figure 15B Based on the structure shown in FIG. 1 , a planarization layer covering the step structure can be formed by a spin coating process (see the planarization layer 135 described below). Figure 15A and Figure 15B Based on the structure shown, the first isolation pattern SP1 can be selectively etched to remove part or all of the first isolation pattern SP1, and then a planarization layer covering the stepped structure can be formed by spin coating, thereby helping to improve the quality of the planarization layer. For example, the material of the planarization layer can be different from the material of the sacrificial patterns SQ1 and SQ2 (collectively referred to as sacrificial patterns SQ). For example, the material of the planarization layer can be the same as the material of either the second layer 120 or the first isolation pattern SP1, but is not limited thereto.

[0124] Figure 16A A schematic top view of a structure obtained after forming a planarization layer according to some embodiments of the present disclosure; Figure 16B and Figure 16C A schematic cross-sectional view of a structure obtained after forming a planarization layer according to some embodiments of the present disclosure; Figure 16D and Figure 16E Schematic cross-sectional view of the structure obtained after forming the planarization layer according to some other embodiments of the present disclosure. For example, in some embodiments, Figure 9A and Figure 9B Based on the structure shown, a planarization layer 135 covering the stepped structure is formed to obtain Figures 16A-16C The structure shown in FIG. 1 is shown in FIG. 1 (herein, the first isolation pattern SP1 and the planarization layer 135 are not distinguished, or the first isolation pattern SP1 is completely removed). For example, in some other embodiments, Figure 15A and Figure 15B Based on the structure shown, a planarization layer 135 covering the stepped structure is formed to obtain Figure 16A 、 Figure 16D and Figure 16E The structure shown (herein, the first isolation pattern SP1 and the planarization layer 135 are not distinguished, or the first isolation pattern SP1 is completely removed).

[0125] S300: replacing the first layer of the M levels in the initial stacking structure located in the second region with M conductive lines, wherein the M conductive lines are in contact with the M sacrificial patterns respectively, and the second region is located on one side of the first region in the second horizontal direction, and the second horizontal direction is perpendicular to the first horizontal direction.

[0126] For example, in some embodiments, step S300 may include the following steps S301 to S303.

[0127] S301: etching the initial stacked structure in the third region to expose sidewalls of M levels of the initial stacked structure in the second region, wherein the third region is located on a side of the second region away from the first region in the second horizontal direction;

[0128] S302: Laterally etching and removing the first layer of the M levels in the initial stacked structure in the second region to form M fifth horizontal openings;

[0129] S303 : forming M conductive lines respectively filling the M fifth horizontal openings.

[0130] Figure 17A A schematic top view of a structure obtained according to step S301 provided in some embodiments of the present disclosure; Figure 17B A schematic cross-sectional view of a structure obtained according to step S301 provided in some embodiments of the present disclosure; Figure 17C Schematic cross-sectional view of the structure obtained according to step S301 is provided for other embodiments of the present disclosure. For example, in some embodiments, Figure 17A and Figure 17B As shown, in Figures 16A-16C Based on the structure shown in FIG. 1 , the initial stacked structure in the third region R3 can be etched to expose the sidewalls of the layers T1-T8 in the initial stacked structure in the second region R2, wherein the third region R3 is located on a side of the second region R2 away from the first region R1 in the second horizontal direction Y. For example, the second horizontal direction Y is perpendicular to the first horizontal direction X. For example, in some other embodiments, as Figure 17A and Figure 17C As shown, in Figure 16A 、 Figure 16D and Figure 16E Based on the structure shown, the initial stacked structure in the third region R3 may be etched to expose sidewalls of the levels T1 - T8 in the initial stacked structure in the second region R2 .

[0131] Figure 18A A schematic cross-sectional view of a structure obtained according to step S302 and step S303 provided in some embodiments of the present disclosure; Figure 18B for Figure 18AFIG. 1 is a top view of the conductive line 200 and the sacrificial pattern SQ located at the same level in the structure shown. For example, in some embodiments, as Figure 18A and Figure 18B As shown, in Figure 17A and Figure 17B Based on the structure shown, the first layer 110 in the layers T1-T8 in the initial stacked structure in the second region R2 can be laterally etched away to form eight corresponding fifth-level openings; then, a conductive material layer is conformally deposited to fill the eight fifth-level openings, and the portion of the conductive material layer outside the fifth-level openings is etched away, with the portion of the conductive material layer remaining in the fifth-level openings serving as the conductive wire 200. For example, the material of the conductive wire 200 can include, but is not limited to, titanium nitride and / or tungsten. For example, in some examples, such as Figure 18B As shown, conductive line 200 includes a lateral recess LR1 that contacts the corresponding sacrificial pattern SQ. In a subsequent step S500, conductive line 200 can be etched from lateral recess LR1 to remove the portion of conductive line 200 located in region CR, thereby dividing conductive line 200 into two conductive segments. Region CR is referred to as the separation region below. It should be understood that the shape of region CR is schematic and, in actual applications, the shape of region CR can be irregular.

[0132] Figure 18C Schematic cross-sectional view of the structure obtained according to step S302 and step S303 provided in some other embodiments of the present disclosure; Figure 18D for Figure 18C FIG. 2 is a top view of the conductive line 200, the sacrificial pattern SQ and the insulating pattern IL located at the same level in the structure shown in FIG. Figure 18C and Figure 18D As shown, in Figure 17A and Figure 17C Based on the structure shown, the first layer 110 in the layers T1-T8 in the initial stacked structure in the second region R2 can be laterally etched away to form eight corresponding fifth-level openings; then, a conductive material layer is conformally deposited to fill the eight fifth-level openings, and the portion of the conductive material layer outside the fifth-level openings is etched away, and the portion of the conductive material layer remaining in the fifth-level openings serves as the conductive line 200. For example, in some examples, such as Figure 18DAs shown, the conductive line 200 includes a lateral recess LR1 that contacts the corresponding sacrificial pattern SQ and a lateral recess LR2 that contacts the corresponding insulating pattern IL. In a subsequent step S500, the conductive line 200 can be etched from the lateral recess LR1 to remove the portion of the conductive line 200 located in the region CR, thereby dividing the conductive line 200 into two conductive segments. The region CR is referred to as the separation region below. It should be understood that the shape of the region CR is schematic and, in actual applications, the shape of the region CR can be irregular.

[0133] For example, in some embodiments, step S300 may further include: forming a first filling layer (see FIG. 1 ) filling the third region R3 after forming M conductive lines. Figures 19A-19C For example, the material of the first filling layer 145 may be the same as that of the planarization layer 135, but is not limited thereto.

[0134] S400 : removing the M sacrificial patterns to form M horizontal openings, wherein the M horizontal openings respectively expose portions of the M conductive lines.

[0135] For example, in some embodiments, step S400 may include the following steps S401 and S402.

[0136] S401: etching the initial stacked structure in the fourth region to expose sidewalls of the M sacrificial patterns, wherein the fourth region is located on a side of the first region away from the second region in the second horizontal direction;

[0137] S402: Laterally etching and removing the M sacrificial patterns.

[0138] Figure 19A A schematic top view of a structure obtained according to step S401 provided in some embodiments of the present disclosure; Figure 19B A schematic cross-sectional view of a structure obtained according to step S401 provided in some embodiments of the present disclosure; Figure 19C for Figure 18B A schematic top view of the conductive line 200 and the sacrificial pattern SQ located at the same level in the structure shown; Figure 19D A schematic cross-sectional view of a structure obtained according to step S401 provided in some other embodiments of the present disclosure; Figure 19E for Figure 18D FIG. 1 is a top view of the conductive line 200 , the sacrificial pattern SQ and the insulating pattern IL located at the same level in the structure shown.

[0139] For example, in some embodiments, Figures 19A-19C As shown, in Figure 18A and Figure 18BBased on the structure shown in FIG. 1 , the initial stacked structure in the fourth region R4 can be etched to expose the sidewalls of each sacrificial pattern SQ, wherein the fourth region R4 is located on a side of the first region R1 away from the second region R2 in the second horizontal direction Y. In this case, a portion of the sacrificial pattern SQ (such as Figure 19C (as shown in the dashed box SQR1).

[0140] For example, in other embodiments, Figure 19A 、 Figure 19D and Figure 19E As shown, in Figure 18C and Figure 18D Based on the structure shown in FIG. 1 , the initial stacked structure in the fourth region R4 can be etched to expose the sidewalls of each sacrificial pattern SQ (i.e., the first sacrificial pattern SQ1 and the second sacrificial pattern SQ2), wherein the fourth region R4 is located on a side of the first region R1 away from the second region R2 in the second horizontal direction Y. In this case, a portion of the sacrificial pattern SQ (e.g., Figure 19E as shown in the dashed box SQR1) and a portion of the insulating pattern IL (as shown in Figure 19E (shown in the dashed box ILR1).

[0141] Figure 20A A schematic cross-sectional view of a structure obtained according to step S402 provided in some embodiments of the present disclosure; Figure 20B Shown Figure 19C Schematic diagram of the sacrificial pattern SQ being completely removed; Figure 20C Shown Figure 19C Schematic diagram of a sacrificial pattern SQ in FIG. 1 being partially removed. For example, in some embodiments, as Figures 20A-20C As shown, in Figures 19A-19C Based on the structure shown in FIG, all or part of each sacrificial pattern SQ can be removed by lateral etching to form a corresponding horizontal opening HO. Figure 20B As shown, the entirety of the sacrificial pattern SQ may be removed (e.g., Figure 20B ); for example, in other examples, such as Figure 20C As shown, a portion of the sacrificial pattern SQ may be removed (eg, Figure 20C The remaining portion SQR3 of the “U”-shaped sacrificial pattern SQ is located at one end of the “U”-shape.

[0142] Figure 20D A schematic cross-sectional view of a structure obtained according to step S402 provided in some other embodiments of the present disclosure; Figure 20E Shown Figure 19E Schematic diagram of the sacrificial pattern SQ being completely removed; Figure 20F ShownFigure 19E Schematic diagram of a sacrificial pattern SQ in FIG. 1 being partially removed. For example, in some embodiments, as Figures 20D-20F As shown, in Figure 19A 、 Figure 19D and Figure 19E Based on the structure shown in FIG, all or part of each sacrificial pattern SQ (ie, the first sacrificial pattern SQ1 and the second sacrificial pattern SQ2) can be removed by lateral etching to form a corresponding horizontal opening HO. Figure 20E As shown, the entirety of the sacrificial pattern SQ may be removed (e.g., Figure 20E ); for example, in other examples, such as Figure 20C As shown, a portion of the sacrificial pattern SQ may be removed (eg, Figure 20F The remaining portion SQR3 of the “U”-shaped sacrificial pattern SQ is located at one end of the “U”-shape.

[0143] S500: Laterally etching M conductive lines from M horizontal openings to divide each of the M conductive lines into two conductive segments, with the spacing region between two conductive segments in odd-numbered levels serving as a first spacing region, and the spacing region between two conductive segments in even-numbered levels serving as a second spacing region. The plurality of first spacing regions are substantially distributed in a stepped manner, and the plurality of second spacing regions are substantially distributed in a stepped manner.

[0144] Figure 21A A schematic cross-sectional view of a structure obtained according to step S500 provided in some embodiments of the present disclosure; Figure 21B For the Figure 21A A schematic cross-sectional view taken along the vertical dashed line in FIG. Figure 21C for Figure 21B For example, in some embodiments, as shown in FIG. Figures 21A-21C As shown, in Figures 20A-20C Based on the structure shown, the corresponding conductive line 200 can be etched from the horizontal opening HO to divide the conductive line 200 into two conductive segments and form an interval region IR (i.e., interval region IR1 / IR2) located between the two conductive segments. Figure 21B As shown, the spacing area between two conductive segments in the odd-numbered levels T1, T3, T5, and T7 is used as the first spacing area IR1, and the multiple first spacing areas IR1 are basically distributed in a stepped manner; the spacing area between two conductive segments in the even-numbered levels T2, T4, T6, and T8 is used as the second spacing area IR2, and the multiple second spacing areas IR2 are basically distributed in a stepped manner.

[0145] Figure 21D A schematic cross-sectional view of a structure obtained according to step S500 provided in some other embodiments of the present disclosure; Figure 21E For the Figure 21D A schematic cross-sectional view taken along the vertical dashed line in FIG. Figure 21F for Figure 21E For example, in some embodiments, as shown in FIG. Figures 21D-21F As shown, in Figures 20D-20F Based on the structure shown, the corresponding conductive line 200 can be etched from the horizontal opening HO to divide the conductive line 200 into two conductive segments and form an interval region IR (i.e., interval region IR1 / IR2) located between the two conductive segments. Figure 21E As shown, the spacing area between two conductive segments in the odd-numbered levels T1, T3, T5, and T7 is used as the first spacing area IR1, and the multiple first spacing areas IR1 are basically distributed in a stepped manner; the spacing area between two conductive segments in the even-numbered levels T2, T4, T6, and T8 is used as the second spacing area IR2, and the multiple second spacing areas IR2 are basically distributed in a stepped manner.

[0146] For example, in some embodiments, after each of the M conductive lines is divided into two conductive segments, a second filling layer (not shown) may be formed to fill the fourth region R4. It is understandable that the second filling layer may not be able to completely fill the aforementioned spacing region and the portion of the horizontal opening HO near the spacing region. Therefore, an air gap is typically formed at least partially within the spacing region. This air gap is beneficial for reducing parasitic capacitance between the two conductive segments.

[0147] It should be noted that one or more steps of the above-mentioned manufacturing method may include multiple sub-steps, and these sub-steps may be executed sequentially or in parallel according to actual needs; in addition, according to actual needs, the sub-steps in different steps may be executed sequentially, in parallel or alternately.

[0148] At least some embodiments of the present disclosure further provide a semiconductor structure. For example, the semiconductor structure can be obtained by the above-mentioned manufacturing method, but is not limited thereto. For example, Figure 21B or Figure 21EAs shown, the semiconductor structure includes a substrate 100 and a stacked structure on the substrate 100. The stacked structure includes M conductive segment groups stacked sequentially from top to bottom. Each of the M conductive segment groups includes two conductive segments located on the same straight line extending along a first horizontal direction X and spaced apart from each other. The spacing region between the two conductive segments in the 2i-1th conductive segment group (i.e., the two conductive segments in the 2i-1th level) among the M conductive segment groups serves as a first spacing region IR1, and the spacing region between the two conductive segments in the 2ith conductive segment group (i.e., the two conductive segments in the 2ith level) among the M conductive segment groups serves as a second spacing region IR2. The plurality of first spacing regions IR1 are substantially distributed in a stair-like manner, and the plurality of second spacing regions IR2 are substantially distributed in a stair-like manner. Wherein, M is a positive integer greater than or equal to 2, and i is a positive integer, i=1, 2, 3, ..., M / 2. Figure 21B and Figure 21E The case of M=8 is schematically shown, but should not be considered as limiting the present disclosure.

[0149] For example, in some embodiments, Figure 21B As shown, the area of ​​the overlapping portion of the orthographic projection of the first spacing region IR1 in the 2i-1th conductive segment group on the substrate 100 and the orthographic projection of the first spacing region IR1 in the 2i+1th conductive segment group on the substrate 100 is less than or equal to 20% of the area of ​​the orthographic projection of the first spacing region IR1 in the 2i-1th conductive segment group on the substrate 100, and the area of ​​the overlapping portion of the orthographic projection of the second spacing region IR2 in the 2ith conductive segment group on the substrate 100 and the orthographic projection of the second spacing region IR2 in the 2i+2th conductive segment group on the substrate 100 is less than or equal to 20% of the area of ​​the orthographic projection of the second spacing region IR2 in the 2i+2th conductive segment group on the substrate 100.

[0150] For example, in other embodiments, Figure 21E As shown, M is a multiple of 4, the area of ​​an overlapping portion of the orthographic projection of the first spacing region IR1 in the 4j-3 th conductive segment group and the orthographic projection of the first spacing region IR1 in the 4j-1 th conductive segment group on the substrate 100 is greater than or equal to 80% of the area of ​​the orthographic projection of the first spacing region IR1 in the 4j-3 th conductive segment group on the substrate 100, and the area of ​​an overlapping portion of the orthographic projection of the second spacing region IR2 in the 4j-2 th conductive segment group and the orthographic projection of the second spacing region IR2 in the 4j th conductive segment group on the substrate 100 is greater than or equal to 80% of the area of ​​the orthographic projection of the second spacing region IR2 in the 4j th conductive segment group on the substrate 100, wherein j is a positive integer, j=1, 2, 3, ..., M / 4.

[0151] For example, in some embodiments, in combination Figures 21D-21F As shown, one of the two conductive segments in the 4j-2 conductive segment group has a first lateral recess (see Figure 21F The first lateral recess is located between the first spacing region IR1 in the 4j-3 conductive segment group and the first spacing region IR1 in the 4j-1 conductive segment group; one of the two conductive segments in the 4j-3 conductive segment group has a second lateral recess (see Figure 21F The second lateral recess is located between the second spacing region IR2 in the 4j-2 th conductive segment group and the second spacing region IR2 in the 4j th conductive segment group.

[0152] For example, in some embodiments, the stacked structure may also include at least one of a first air gap and a second air gap, wherein the first air gap is at least partially located in the first spacing region IR1 and the second air gap is at least partially located in the second spacing region IR2 (refer to the description of the air gap in the above method embodiment).

[0153] For example, in some embodiments, the semiconductor structure may further include a plurality of vertically stacked sense amplifier (SA) structures, where the plurality of sense amplifier structures include M / 2 sense amplifier structures from top to bottom. Figure 22A Schematic diagram of a circuit structure of a sense amplifier structure; Figure 22B and Figure 22C A partial planar structural diagram of two levels of a sense amplifier structure in a semiconductor structure provided by some embodiments of the present disclosure.

[0154] For example, Figures 22A-22C As shown, each sense amplifier structure includes a first P-type transistor P1 and a second P-type transistor P2 stacked in sequence and a first N-type transistor N1 and a second N-type transistor N2 stacked in sequence. For example, one of the two conductive segments in the 2i-1th conductive segment group (see Figure 22B The conductive segment on the left side in the dotted box DF1 or the conductive segment on the left side in the dotted box DF2) is coupled to the gates of the first P-type transistor P1 and the first N-type transistor N1 in the i-th sense amplifier structure, and the other of the two conductive segments in the 2i-1-th conductive segment group (see Figure 22B The conductive segment on the right side in the dotted box DF1 or the conductive segment on the right side in the dotted box DF2) is coupled to the source and drain of the first P-type transistor P1 and the first N-type transistor N1 in the i-th sense amplifier structure, and one of the two conductive segments in the 2i-th conductive segment group (see Figure 22CThe conductive segment on the right side in the dotted box DF1 or the conductive segment on the right side in the dotted box DF2) is coupled to the source and drain of the second P-type transistor P2 and the second N-type transistor N2 in the i-th sense amplifier structure, and the other of the two conductive segments in the 2i-th conductive segment group (see Figure 22C The conductive segment on the left side in the dotted box DF1 or the conductive segment on the left side in the dotted box DF2) is coupled to the gates of the second P-type transistor P1 and the second N-type transistor P2 in the i-th sense amplifier structure.

[0155] For example, Figure 22B and Figure 22C As shown, each sense amplifier further includes a first connection structure CC1 and a second connection structure CC2, wherein the first connection structure CC1 couples one of the two conductive segments in the 2i-1th conductive segment group and one of the two conductive segments in the 2i-th conductive segment group, and the second connection structure CC2 couples the other of the two conductive segments in the 2i-1th conductive segment group and the other of the two conductive segments in the 2i-th conductive segment group. Figure 22B and Figure 22C As shown, each sense amplifier further includes a third connection structure CC3 and a fourth connection structure CC4, wherein the third connection structure CC3 couples the source and drain of the first N-type transistor N1 and the second N-type transistor N2, and the fourth connection structure CC4 couples the source and drain of the first P-type transistor P1 and the second P-type transistor P2.

[0156] It should be noted that the vertically stacked annular windings can be cut off by setting sacrificial patterns that are basically distributed in a step-like manner (sacrificial patterns are set on opposite sides of the annular windings), thereby obtaining Figure 22B and Figure 22C The conductive segment shown in .

[0157] Figure 22D A schematic diagram of a plurality of connection structures stacked in sequence provided in some embodiments of the present disclosure. For example, Figure 22D As shown, each connection structure includes a first connection part CC in a "C" shape and two second strip-shaped connection parts CS electrically connected to the first connection part CC; multiple connection structures are stacked in sequence along the vertical direction Z, where the vertical direction Z is perpendicular to the first horizontal direction X and the second horizontal direction Y; each connection structure is electrically connected to the corresponding two windings CW. It can be understood that Figure 22D The connection structure in may be any one of the first connection structure CC1, the second connection structure CC2, the third connection structure CC3 and the fourth connection structure CC4.

[0158] For example, transistors P1, N1, P2, and N2 can all be configured as wrap-around gate transistors, i.e., gate G1 of transistor N1 wraps around its active area A1, gate G2 of transistor P1 wraps around its active area A2, gate G3 of transistor N2 wraps around its active area A3, and gate G4 of transistor P2 wraps around its active area A4. Embodiments of the present disclosure include but are not limited to this.

[0159] For example, in some embodiments, the semiconductor structure may further include a vertically stacked memory array coupled to the plurality of sense amplifier structures. In other words, the semiconductor structure may be formed as a DRAM, for example.

[0160] For more details and technical effects of the semiconductor structure provided by the embodiments of the present disclosure, reference can be made to the relevant description in the embodiments of the above-mentioned manufacturing method, which will not be repeated here.

[0161] At least some embodiments of the present disclosure also provide an electronic device. Figure 23 This is a schematic block diagram of the structure of an electronic device provided in some embodiments of the present disclosure. As shown in FIG13 , the electronic device 1 includes a processor 20 and a memory 10 coupled to each other, wherein the memory 10 includes a semiconductor structure provided in any of the aforementioned embodiments.

[0162] For example, the processor 20 may include, but is not limited to, a central processing unit (CPU), a graphics processing unit (GPU), etc. The memory 10 may be configured to store data to be processed by the processor 20 and / or data processed by the processor.

[0163] For example, the electronic device 1 includes but is not limited to mobile phones, tablet computers, smart bracelets, wearable electronic devices, virtual reality devices, augmented reality devices, vehicle-mounted devices, servers, workstations, etc.

[0164] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: Providing an initial semiconductor structure, wherein the initial semiconductor structure includes a substrate and an initial stacked structure located on the substrate, the initial stacked structure includes M levels from top to bottom, and each level includes a first layer and a second layer stacked in sequence; Etching the initial stacked structure in the first region to form a staircase structure extending along a first horizontal direction, wherein the staircase structure is provided with M sacrificial patterns, a 2i-1th sacrificial pattern among the M sacrificial patterns is located at a first end of a first layer in a 2i-1th level of the M levels, a 2ith sacrificial pattern among the M sacrificial patterns is located at a second end of the first layer in a 2ith level of the M levels, the plurality of sacrificial patterns located in odd-numbered levels are substantially distributed in a staircase shape, and the plurality of sacrificial patterns located in even-numbered levels are substantially distributed in a staircase shape; replacing a first layer of the M levels in the initial stacked structure located in a second region with M conductive lines, wherein the M conductive lines are in contact with the M sacrificial patterns respectively, wherein the second region is located on one side of the first region in a second horizontal direction, and the second horizontal direction is perpendicular to the first horizontal direction; removing the M sacrificial patterns to form M horizontal openings, wherein the M horizontal openings respectively expose portions of the M conductive lines; Laterally etching the M conductive lines from the M horizontal openings to divide each of the M conductive lines into two conductive segments, wherein a spacing region between the two conductive segments in odd-numbered levels serves as a first spacing region, and a spacing region between the two conductive segments in even-numbered levels serves as a second spacing region, wherein a plurality of the first spacing regions are substantially distributed in a stair-like manner, and a plurality of the second spacing regions are substantially distributed in a stair-like manner; Wherein, M is a positive integer and a multiple of 2, i is a positive integer, i=1, 2, 3,…, M / 2.

2. The manufacturing method according to claim 1, characterized in that Etching the initial stacked structure in the first region to form the stepped structure extending along the first horizontal direction, comprising: Etching the initial stacked structure in the first region to form an initial stepped structure, wherein the initial stepped structure includes M initial stepped portions, a 2i-1th initial stepped portion among the M initial stepped portions includes a 2i-1th level, and a 2ith initial stepped portion among the M initial stepped portions includes a 2ith level; forming a first isolation pattern, wherein the first isolation pattern covers a sidewall of the initial stepped structure; Etching the M initial step portions to expose a sidewall of the first layer in each of the M initial step portions; Laterally etching and removing a portion of the first layer in each of the M initial step portions to form a first horizontal opening; The M sacrificial patterns filling the first horizontal opening are formed.

3. The manufacturing method according to claim 2, characterized in that In the step of etching the M initial step portions, a sidewall of the first end of the first layer in the 2i-1th initial step portion and a sidewall of the second end of the first layer in the 2ith initial step portion are exposed.

4. The manufacturing method according to claim 1, characterized in that M is a multiple of 4, Etching the initial stacked structure in the first region to form the stepped structure extending along the first horizontal direction, comprising: Etching the initial stacked structure in the first region to form an initial stepped structure, wherein the initial stepped structure includes M / 2 initial stepped portions, the 2j-1th initial stepped portion among the M / 2 initial stepped portions includes the 4j-3th to 4j-1th levels, and the 2jth initial stepped portion among the M / 2 initial stepped portions includes the 4j-2th to 4jth levels; forming a first isolation pattern, wherein the first isolation pattern covers a sidewall of the initial stepped structure; Etching the M / 2 initial step portions to expose a sidewall of the first layer in the 4j-3th level in the 2j-1th initial step portion and a sidewall of the first layer in the 4j-2th level in the 2jth initial step portion; Laterally etching and removing a portion of the first layer in the 4j-3th level in the 2j-1th initial step portion and a portion of the first layer in the 4j-2th level in the 2jth initial step portion to form a second horizontal opening; forming a first sacrificial pattern filling the second horizontal opening; Continue etching the M / 2 initial step portions to expose the sidewall of the first layer in the 4j-2th level in the 2j-1th initial step portion and the sidewall of the first layer in the 4j-1th level in the 2jth initial step portion; Laterally etching and removing a portion of the first layer in the 4j-2th level in the 2j-1th initial step portion and a portion of the first layer in the 4j-1th level in the 2jth initial step portion to form a third horizontal opening; forming an insulating pattern filling the third horizontal opening; Continue etching the M / 2 initial step portions to expose the sidewall of the first layer in the 4j-1th level in the 2j-1th initial step portion and the sidewall of the first layer in the 4jth level in the 2jth initial step portion; Laterally etching and removing a portion of the first layer in the 4j-1th level in the 2j-1th initial step portion and a portion of the first layer in the 4jth level in the 2jth initial step portion to form a fourth horizontal opening; forming a second sacrificial pattern filling the fourth horizontal opening; The M sacrificial patterns include the first sacrificial pattern and the second sacrificial pattern, j is a positive integer, j=1, 2, 3, ..., M / 4.

5. The manufacturing method according to claim 4, characterized in that In the step of etching the M / 2 initial step portions, the side wall at the first end of the first layer in the 4j-3 level in the 2j-1 initial step portion and the side wall at the second end of the first layer in the 4j-2 level in the 2j initial step portion are exposed.

6. The manufacturing method according to any one of claims 1 to 5, characterized in that: Replacing a first layer of the M levels in the initial stacked structure in the second region with the M conductive lines comprises: Etching the initial stacked structure in a third region to expose sidewalls of the M levels in the initial stacked structure in the second region, wherein the third region is located on a side of the second region away from the first region in the second horizontal direction; Laterally etching away the first layer of the M levels in the initial stacked structure in the second region to form M fifth horizontal openings; The M conductive lines are formed to respectively fill the M fifth horizontal openings.

7. The manufacturing method according to claim 6, characterized in that The M conductive lines extend along the first horizontal direction, and each of the M conductive lines includes a lateral recess contacting the corresponding sacrificial pattern.

8. The manufacturing method according to any one of claims 1 to 5, characterized in that: Removing the M sacrificial patterns to form the M horizontal openings includes: Etching the initial stack structure in a fourth region to expose sidewalls of the M sacrificial patterns, wherein the fourth region is located on a side of the first region away from the second region in the second horizontal direction; The M sacrificial patterns are removed by laterally etching.

9. A semiconductor structure, characterized in that include: substrate; A stacked structure on the substrate, wherein the stacked structure comprises M conductive segment groups from top to bottom, the M conductive segment groups are stacked in sequence, and each of the M conductive segment groups comprises two conductive segments located on the same straight line extending along a first horizontal direction and spaced apart from each other, The spacing region between the two conductive segments in the 2i-1th conductive segment group among the M conductive segment groups is used as a first spacing region, and the spacing region between the two conductive segments in the 2ith conductive segment group among the M conductive segment groups is used as a second spacing region, a plurality of the first spacing regions are substantially distributed in a step-like manner, and a plurality of the second spacing regions are substantially distributed in a step-like manner. Wherein, M is a positive integer greater than or equal to 2, i is a positive integer, i=1, 2, 3, ..., M / 2; The semiconductor structure further includes: M / 2 sense amplifier structures from top to bottom, wherein the M / 2 sense amplifier structures are stacked sequentially, and each sense amplifier structure includes a first P-type transistor and a second P-type transistor stacked sequentially, and a first N-type transistor and a second N-type transistor stacked sequentially, One of the two conductive segments in the 2i-1th conductive segment group is coupled to gates of a first P-type transistor and a first N-type transistor in an i-th sense amplifier structure, the other of the two conductive segments in the 2i-1th conductive segment group is coupled to adjacent sources and drains of the first P-type transistor and the first N-type transistor in the i-th sense amplifier structure, one of the two conductive segments in the 2i conductive segment group is coupled to adjacent sources and drains of a second P-type transistor and a second N-type transistor in the i-th sense amplifier structure, and the other of the two conductive segments in the 2i conductive segment group is coupled to gates of a second P-type transistor and a second N-type transistor in the i-th sense amplifier structure; Each sense amplifier structure further includes a first connection structure and a second connection structure, wherein the first connection structure couples one of the two conductive segments in the 2i-1th conductive segment group and one of the two conductive segments in the 2ith conductive segment group, and the second connection structure couples the other of the two conductive segments in the 2i-1th conductive segment group and the other of the two conductive segments in the 2ith conductive segment group.

10. The semiconductor structure according to claim 9, wherein: An area of ​​an overlapping portion of an orthographic projection of the first spacing region in the 2i-1th conductive segment group on the substrate and an orthographic projection of the first spacing region in the 2i+1th conductive segment group on the substrate is less than or equal to 20% of an area of ​​an orthographic projection of the first spacing region in the 2i-1th conductive segment group on the substrate, and an area of ​​an overlapping portion of an orthographic projection of the second spacing region in the 2ith conductive segment group on the substrate and an orthographic projection of the second spacing region in the 2i+2th conductive segment group on the substrate is less than or equal to 20% of an area of ​​an orthographic projection of the second spacing region in the 2i+2th conductive segment group on the substrate.

11. The semiconductor structure according to claim 9, wherein: M is a multiple of 4, an overlapping area of ​​an orthographic projection of the first spacing region in the 4j-3rd conductive segment group on the substrate and an orthographic projection of the first spacing region in the 4j-1st conductive segment group on the substrate is greater than or equal to 80% of an orthographic projection of the first spacing region in the 4j-3rd conductive segment group on the substrate, an overlapping area of ​​an orthographic projection of the second spacing region in the 4j-2nd conductive segment group on the substrate and an orthographic projection of the second spacing region in the 4jth conductive segment group on the substrate is greater than or equal to 80% of an orthographic projection of the second spacing region in the 4jth conductive segment group on the substrate, Wherein, j is a positive integer, j=1, 2, 3,…, M / 4.

12. The semiconductor structure according to claim 11, wherein: One of the two conductive segments in the 4j-2 th conductive segment group has a first lateral recess, wherein the first lateral recess is located between the first spacing region in the 4j-3 th conductive segment group and the first spacing region in the 4j-1 th conductive segment group; One of the two conductive segments in the 4j-3 th conductive segment group has a second lateral recess, and the second lateral recess is located between the second spacing region in the 4j-2 th conductive segment group and the second spacing region in the 4j th conductive segment group.

13. The semiconductor structure according to any one of claims 9 to 12, characterized in that: The stack structure further includes at least one of a first air gap and a second air gap, wherein the first air gap is at least partially located in the first spacing region, and the second air gap is at least partially located in the second spacing region.

14. An electronic device, characterized in that: include: processor; as well as A memory, wherein the memory is coupled to the processor, and the memory comprises the semiconductor structure according to any one of claims 9 to 13.

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