Semiconductor device and preparation method thereof, chip, and electronic device

Abstract

The present disclosure provides a semiconductor device and a preparation method thereof, a chip, and an electronic device, which relate to the field of semiconductor technology and are intended to improve the power density and response speed of semiconductor devices and enhance the performance of semiconductor devices. The semiconductor device includes a substrate, a channel layer, a first adjustment layer, a gate layer, a source electrode, and a drain electrode. The channel layer is arranged on one side of the substrate, and the first adjustment layer is stacked on the side of the channel layer away from the substrate. The channel layer generates biaxial tensile strain under the action of the first adjustment layer. The gate layer is stacked on the side of the first adjustment layer away from the substrate, and the source electrode and the drain electrode are located on opposite sides of the gate layer along a first direction. The above-mentioned semiconductor device is applied to a chip.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, a chip, and an electronic device. Background Art

[0002] Gallium nitride (GaN) semiconductor materials are called third-generation semiconductor materials. Compared with the first-generation semiconductor materials represented by silicon (Si), they have higher bandgap width, critical breakdown field strength, and electron saturation drift velocity. They have significant advantages in high frequency, high voltage resistance, high power, and low on-resistance. They can be used as core components in various power conversion systems and have broad prospects in consumer electronics, 5G RF, servers, and telecommunications applications. Summary of the invention

[0003] Embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same, a chip, and an electronic device, aiming to increase the power density and response speed of the semiconductor device and enhance the performance of the semiconductor device.

[0004] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0005] In one aspect, a semiconductor device is provided. The semiconductor device comprises a substrate, a channel layer, a first adjustment layer, a gate layer, a source electrode and a drain electrode. The channel layer is arranged on one side of the substrate. The first adjustment layer is stacked on the side of the channel layer away from the substrate, and the channel layer generates biaxial tensile strain under the action of the first adjustment layer. The gate layer is stacked on the side of the first adjustment layer away from the substrate. The source electrode and the drain electrode are located on opposite sides of the gate layer along a first direction.

[0006] The semiconductor device provided by the above-mentioned embodiments of the present disclosure can change the energy band structure of the channel layer by setting a first adjustment layer in the semiconductor device. The first adjustment layer is stacked on the side of the channel layer away from the substrate, and the channel layer generates biaxial tensile strain under the action of the first adjustment layer, so that the energy band structure of the channel layer can be changed, and the valence band energy band structure of the channel layer can be modulated.

[0007] Specifically, by causing the channel layer to generate biaxial tensile strain under the action of the first adjustment layer, the crystal field splitting band caused by the spin-orbit coupling effect in the channel layer can be moved upward, and the heavy hole band and the light hole band can be moved downward accordingly, thereby reducing the effective mass of the holes in the channel layer. The holes in the channel layer are more easily accelerated and moved under the action of the electric field, which is beneficial to improving the mobility of the holes in the channel layer, and thus is beneficial to improving the power density and response speed of the semiconductor device, and improving the performance of the semiconductor device.

[0008] In some embodiments, a lattice constant of a material of the first adjustment layer is greater than a lattice constant of a material of the channel layer.

[0009] In some embodiments, a material of the channel layer includes gallium nitride, and a material of the first adjustment layer includes indium gallium nitride.

[0010] In some embodiments, the first adjustment layer includes a P-type doped semiconductor material. The first adjustment layer includes a first portion and a second portion, and in an orthographic projection onto the substrate, the first portion of the first adjustment layer overlaps with the gate layer, and the second portion of the first adjustment layer does not overlap with the gate layer. The thickness of the first portion of the first adjustment layer is less than the thickness of the second portion of the first adjustment layer.

[0011] In some embodiments, a thickness of the first portion of the first adjustment layer is less than or equal to 2 nm, and a thickness of the second portion of the first adjustment layer is greater than or equal to 5 nm and less than or equal to 200 nm.

[0012] In some embodiments, the first adjustment layer comprises an undoped semiconductor material and has a uniform thickness.

[0013] In some embodiments, the thickness of the first adjustment layer is greater than or equal to 5 nm and less than or equal to 200 nm.

[0014] In some embodiments, a size of the first adjustment layer along the first direction is equal to a size of the channel layer along the first direction.

[0015] In some embodiments, the channel layer includes a first portion, the first portion of the channel layer is located on a side of the first adjustment layer close to the substrate. The semiconductor device further includes a second adjustment layer, the second adjustment layer is located on opposite sides of the first portion of the channel layer along the first direction. The channel layer generates a compressive strain along the first direction under the action of the second adjustment layer.

[0016] In some embodiments, a lattice constant of a material of the second adjustment layer is greater than a lattice constant of a material of the channel layer.

[0017] In some embodiments, the channel layer further includes a second portion, the second portion of the channel layer is located on a side of the second adjustment layer close to the substrate, and is located on opposite sides of the first portion of the channel layer along the first direction. The second portion of the channel layer is connected to the first portion of the channel layer, and a thickness of the second portion of the channel layer is less than a thickness of the first portion of the channel layer.

[0018] In some embodiments, a material of the channel layer includes gallium nitride, and a material of the second adjustment layer includes P-type doped indium gallium nitride.

[0019] In some embodiments, the semiconductor device further includes a back barrier layer, the back barrier layer being located on a side of the channel layer and the second adjustment layer close to the substrate, and the back barrier layer is in contact with the second adjustment layer.

[0020] In some embodiments, the material of the back barrier layer includes aluminum gallium nitride, and the material of the second adjustment layer includes P-type doped indium gallium nitride.

[0021] In some embodiments, the semiconductor device further includes a gate dielectric layer, wherein the gate dielectric layer is located between the gate layer and the first adjustment layer, between the source and the gate layer, and between the drain and the gate layer.

[0022] In some embodiments, the semiconductor device further comprises an insulating layer, wherein the insulating layer covers the source electrode and the drain electrode, and the gate dielectric layer covers the insulating layer.

[0023] In another aspect, a method for preparing a semiconductor device is provided. The method for preparing a semiconductor device comprises:

[0024] A channel layer is formed on one side of the substrate.

[0025] A first adjustment layer is formed on a side of the channel layer away from the substrate, and the channel layer generates biaxial tensile strain under the action of the first adjustment layer.

[0026] A source and a drain are formed.

[0027] A gate layer is formed on a side of the first adjustment layer away from the substrate, and the gate layer is located between the source and the drain.

[0028] In some embodiments, the channel layer includes a first portion located on a side of the first adjustment layer close to the substrate. After forming the first adjustment layer on a side of the channel layer away from the substrate and before forming the source and the drain, the method for preparing the semiconductor device further includes:

[0029] A second adjustment layer is formed, and the second adjustment layer is located on two opposite sides of the first part of the channel layer along a first direction, and the first direction is parallel to the arrangement direction of the source and the drain. The channel layer generates compressive strain along the first direction under the action of the second adjustment layer.

[0030] In another aspect, a chip is provided, wherein the chip includes the semiconductor device described in any one of the above embodiments.

[0031] In another aspect, an electronic device is provided, wherein the electronic device comprises a circuit board and the chip as described above, wherein the chip is electrically connected to the circuit board.

[0032] It can be understood that the beneficial effects that can be achieved by the semiconductor device manufacturing method, chip and electronic device provided by the above embodiments of the present disclosure can refer to the beneficial effects of the semiconductor device mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0034] Figure 1 FIG. 1 is a schematic diagram of a structure of an electronic device according to some embodiments Figure 1 ;

[0035] Figure 2 FIG. 1 is a schematic diagram of a structure of an electronic device according to some embodiments Figure 2 ;

[0036] Figure 3 is a schematic diagram of a three-dimensional structure of a chip according to some embodiments;

[0037] Figure 4 is a cross-sectional schematic diagram of a chip according to some embodiments;

[0038] Figure 5 A cross-sectional view of a semiconductor device according to some embodiments Figure 1 ;

[0039] Figure 6 A cross-sectional view of a semiconductor device according to some embodiments Figure 2 ;

[0040] Figure 7 is a schematic structural diagram of a first adjustment layer and a channel layer according to some embodiments;

[0041] Figure 8 A cross-sectional view of a semiconductor device according to some embodiments Figure 3 ;

[0042] Fig. 9 A cross-sectional view of a semiconductor device according to some embodiments Figure 4 ;

[0043] Fig.10 is a schematic structural diagram of a first adjustment layer, a channel layer, and a second adjustment layer according to some embodiments;

[0044] Fig.11is a flow chart of a method for preparing a semiconductor device according to some embodiments;

[0045] Fig.12 for Fig.11 A schematic structural diagram of a semiconductor device corresponding to step S1 in the flowchart of the method for preparing a semiconductor device in FIG. 1 ;

[0046] Fig.13 for Fig.11 The structure of the semiconductor device corresponding to step S2 in the flowchart of the method for preparing the semiconductor device in FIG. Figure 1 ;

[0047] Fig.14 for Fig.11 A schematic structural diagram of a semiconductor device corresponding to step S3 in the flowchart of the method for preparing a semiconductor device in FIG. 1 ;

[0048] Fig.15 for Fig.11 A schematic structural diagram of a semiconductor device corresponding to step S4 in the flowchart of the method for preparing a semiconductor device in FIG.

[0049] Fig.16 for Fig.11 A schematic structural diagram of a semiconductor device corresponding to step S5 in the flowchart of the method for preparing a semiconductor device in FIG. 1 ;

[0050] Fig.17 for Fig.11 The structure of the semiconductor device corresponding to step S2 in the flowchart of the method for preparing the semiconductor device in FIG. Figure 2 .

[0051] Reference numerals:

[0052] 1000-electronic device; 100-chip; 200-circuit board; 10-semiconductor device; c-substrate; 1-buffer layer; 2-back barrier layer; 3-channel layer; 3a-first part of the channel layer; 3b-second part of the channel layer; 4-hole supply layer; 5-gate dielectric layer; 61-first adjustment layer; 61a-first part of the first adjustment layer; 61b-second part of the first adjustment layer; 62-second adjustment layer; 7-insulating layer; G-gate layer; S-source; D-drain. DETAILED DESCRIPTION

[0053] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0054] In the description of the present disclosure, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0055] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0056] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0057] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0058] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0059] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0060] The use of "adapted to" or "configured to" herein is meant to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0061] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0062] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of variation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0063] In the context of the present disclosure, the meanings of “on,” “over,” and “over” should be interpreted in the broadest manner, so that “on” means not only “directly on something,” but also includes the meaning of “on something” with intervening features or layers therebetween, and “over” or “above” means not only “above” or “over” something, but also includes the meaning of “above” or “over” something without intervening features or layers therebetween (i.e., directly on something).

[0064] The words "exemplary" or "for example" are used herein to indicate examples, illustrations, or descriptions. Any embodiment or design described in this application as "exemplary" or "for example" should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a specific way.

[0065] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0066] For the convenience of the following description, an XYZ coordinate system is established. The third direction Z is a direction perpendicular to the substrate, the XY plane is perpendicular to the third direction Z, and the first direction X intersects the second direction Y. For example, the first direction X and the second direction Y are perpendicular to each other.

[0067] like Figure 1 As shown, an embodiment of the present application provides an electronic device 1000. The electronic device 1000 may include a mobile phone, a tablet computer (pad), a smart wearable product (e.g., a smart watch, a smart bracelet), a virtual reality (VR) device, an augmented reality (AR) device, etc. The embodiment of the present application does not impose any special restrictions on the specific form of the above electronic device 1000. Figure 1 In the figure, the electronic device 1000 is taken as a mobile phone as an example for illustration.

[0068] In some embodiments, Figure 2 As shown, Figure 2 1 is a schematic diagram of the structure of an electronic device 1000 according to some embodiments. The electronic device 1000 includes a chip 100 and a circuit board 200. The chip 100 and the circuit board 200 are electrically connected.

[0069] Exemplarily, the circuit board 200 may include a printed circuit board (PCB) or the like.

[0070] For example, the circuit board 200 may include a plurality of conductive layers. The plurality of conductive layers within the circuit board 200 may be separated from each other by a dielectric layer.

[0071] The chip 100 is described in detail below.

[0072] In some embodiments, Figure 3 and Figure 4 As shown, Figure 3 is a schematic diagram of a three-dimensional structure of a chip 100 according to some embodiments, Figure 4 FIG. 1 is a schematic cross-sectional view of a chip 100 according to some embodiments. The chip 100 includes a semiconductor device 10 .

[0073] Exemplarily, the chip 100 may include a processor chip. For example, the processor chip may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0074] The semiconductor device 10 described above will be described in detail below.

[0075] In some embodiments, please refer to Figure 3 and Figure 4 , the semiconductor device 10 may include a substrate c.

[0076] By way of example, the material of the substrate c in the semiconductor device 10 may include one of silicon (Si), sapphire, silicon carbide (SiC), gallium nitride (GaN), and the like.

[0077] In some embodiments, please refer to Figure 3 and Figure 4 The semiconductor device 10 may further include a buffer layer 1. The buffer layer 1 may be stacked on one side of the substrate c.

[0078] By setting a buffer layer 1 in the semiconductor device 10, and the buffer layer 1 is stacked on one side of the substrate c, other film layer structures stacked on the side of the buffer layer 1 in the semiconductor device 10 away from the substrate c can be bonded, and the substrate c can be protected to prevent the substrate c from being invaded by some metal ions.

[0079] For example, the material of the buffer layer 1 may include a plurality of nitride Al x In y Ga (1-x-y) At least one of N, (0≤x, y≤1).

[0080] For example, the material of the buffer layer 1 may include a plurality of nitride Al x In y Ga (1-x-y) N, one of (0≤x,y≤1).

[0081] For example, the material of the buffer layer 1 may include a plurality of nitride Al x In y Ga (1-x-y) Multiple types in N, (0≤x,y≤1).

[0082] For example, the buffer layer 1 may be formed by a metal-organic chemical vapor deposition (MOCVD) process, a molecular beam epitaxy (MBE) process, or a physical vapor deposition (PVD) process.

[0083] Exemplarily, the buffer layer 1 may be a single-layer structure, that is, along the third direction (ie, the direction perpendicular to the substrate c) Z, the buffer layer 1 includes a film layer structure.

[0084] Alternatively, the buffer layer 1 may be a multi-layer structure, that is, along the third direction (i.e., the direction perpendicular to the substrate c) Z, the buffer layer 1 includes a multi-layer film structure.

[0085] For example, please refer to Figure 4 The thickness h1 of the buffer layer 1 may be 0.1 μm-50 μm.

[0086] It should be noted that the above-mentioned "thickness of the buffer layer 1" refers to the dimension of the buffer layer 1 along the third direction (i.e., the direction perpendicular to the substrate c) Z. The following description of the "thickness of the buffer layer 1" also follows this description and will not be repeated.

[0087] For example, see Figure 4 , the thickness of the buffer layer 1 (i.e., the size of the buffer layer 1 along the third direction Z) h1 can be 0.1μm, 0.5μm, 1μm, 3μm, 6μm, 8μm, 10μm, 12μm, 15μm, 18μm, 20μm, 23μm, 25μm, 28μm, 30μm, 33μm, 35μm, 38μm, 40μm, 43μm, 45μm, 48μm or 50μm, etc.

[0088] In some embodiments, please refer to Figure 3 and Figure 4 The semiconductor device 10 may further include a back barrier layer 2. The back barrier layer 2 may be stacked on one side of the substrate c.

[0089] For example, please refer to Figure 3 and Figure 4, when the semiconductor device 10 includes a buffer layer 1, the back barrier layer 2 can be stacked on the side of the buffer layer 1 away from the substrate c. That is, the buffer layer 1 is located between the back barrier layer 2 and the substrate c.

[0090] Exemplarily, the material of the back barrier layer 2 may include nitrides of various different components such as Al x In y Ga (1-x-y) N, at least one of (0 < x ≤ 1, 0 ≤ y ≤ 1).

[0091] For example, the material of the back barrier layer 2 may include a nitride of various different components such as Al x In y Ga (1-x-y) N, one of (0 < x ≤ 1, 0 ≤ y ≤ 1).

[0092] Again, for example, the material of the back barrier layer 2 may include nitrides of various different components such as Al x In y Ga (1-x-y) N, multiple of (0 < x ≤ 1, 0 ≤ y ≤ 1).

[0093] Exemplarily, the back barrier layer 2 can be formed by processes such as Metal-organic Chemical Vapor Deposition (MOCVD), Molecular Beam Epitaxy (MBE), or Physical Vapor Deposition (PVD).

[0094] Exemplarily, please continue to refer to Figure 4 , the thickness h2 of the back barrier layer 2 can be 10 nm - 5 μm.

[0095] It should be noted that the above "thickness of the back barrier layer 2" refers to the dimension of the back barrier layer 2 along the third direction (i.e., the direction perpendicular to the substrate c) Z. The following descriptions of the "thickness of the back barrier layer 2" also follow this explanation and will not be repeated.

[0096] For example, please continue to refer to Figure 4, the thickness of the back barrier layer 2 (i.e., the dimension of the back barrier layer 2 along the third direction Z) h2 can be 10 nm, 50 nm, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 350 nm, 400 nm, 450 nm, 500 nm, 550 nm, 600 nm, 650 nm, 700 nm, 750 nm, 800 nm, 850 nm, 900 nm, 950 nm, 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm, 4.5 μm, or 5 μm, etc.

[0097] In some embodiments, please continue to refer to Figure 3 and Figure 4 , the semiconductor device 10 may further include a channel layer 3. The channel layer 3 may be stacked on one side of the substrate c.

[0098] Exemplarily, please continue to refer to Figure 3 and Figure 4 , in the case where the semiconductor device 10 includes the back barrier layer 2, the channel layer 3 may be stacked on the side of the back barrier layer 2 away from the substrate c.

[0099] Exemplarily, the material of the channel layer 3 may include gallium nitride (GaN).

[0100] When there is an elemental composition difference between the material used to form the channel layer 3 (e.g., GaN) and the material used to form the back barrier layer 2 (e.g., Al x In y Ga (1-x-y) N, (0 < x ≤ 1, 0 ≤ y ≤ 1)), the channel layer 3 and the back barrier layer 2 can jointly form a heterojunction structure, generating a polarization effect. Since all III-nitride materials are polar materials, here it refers to metal polarity, then a two-dimensional hole gas (2DHG) is induced to form near the connection interface between the channel layer 3 and the back barrier layer 2, which is beneficial to improving the carrier mobility (i.e., hole mobility) and enhancing the performance of the semiconductor device 10.

[0101] Exemplarily, the channel layer 3 can be formed by processes such as metal-organic chemical vapor deposition (MOCVD) process, molecular beam epitaxy (MBE) process, or physical vapor deposition (PVD) process.

[0102] Exemplarily, please continue to refer to Figure 4, the thickness h3 of the channel layer 3 can be 2nm-50nm.

[0103] It should be noted that the above “thickness of the channel layer 3 ” refers to the dimension of the channel layer 3 along the third direction (ie, the direction perpendicular to the substrate c) Z. The following description of “thickness of the channel layer 3 ” also follows this description and will not be repeated.

[0104] For example, see Figure 4 The thickness of the channel layer 3 (i.e., the dimension of the channel layer 3 along the third direction Z) h3 can be 2nm, 3nm, 6nm, 8nm, 10nm, 12nm, 15nm, 18nm, 20nm, 23nm, 25nm, 28nm, 30nm, 33nm, 35nm, 38nm, 40nm, 43nm, 45nm, 48nm or 50nm, etc.

[0105] In some embodiments, please refer to Figure 3 and Figure 4 The semiconductor device 10 may further include a hole supply layer 4. The hole supply layer 4 may be stacked on a side of the channel layer 3 away from the substrate c.

[0106] For example, the material of the hole supply layer 4 may include P-type gallium nitride (GaN). P-type gallium nitride (GaN) may be formed by doping elements such as iron (Fe) and magnesium (Mg) into the gallium nitride (GaN) material.

[0107] For example, when doping elements such as iron (Fe) and magnesium (Mg) into gallium nitride (GaN) materials to form P-type gallium nitride (GaN), a vapor phase doping process or an ion implantation process can be used.

[0108] When the material of the hole supply layer 4 includes P-type gallium nitride (GaN), the doping concentration of elements such as iron (Fe) and magnesium (Mg) in the P-type gallium nitride (GaN) may be 1E17 cm -3 -2E20 cm -3 .

[0109] For example, please refer to Figure 4 The hole-providing layer 4 may be a multi-layer structure. That is, along the third direction (ie, the direction perpendicular to the substrate c) Z, the hole-providing layer 4 includes a multi-layer film structure.

[0110] For example, when the hole supply layer 4 is a multi-layer structure and the material of the hole supply layer 4 includes P-type gallium nitride (GaN), the doping concentrations of elements such as iron (Fe) and magnesium (Mg) in different film layer structures within the hole supply layer 4 may be different.

[0111] For example, the hole supply layer 4 can be formed by a process such as a metal-organic chemical vapor deposition (MOCVD) process, a molecular beam epitaxy (MBE) process or a physical vapor deposition (PVD) process.

[0112] For example, please refer to Figure 4 , the thickness h4 of the hole supply layer 4 can be 5nm-200nm.

[0113] It should be noted that the above “thickness of the hole supply layer 4 ” refers to the dimension of the hole supply layer 4 along the third direction (ie, the direction perpendicular to the substrate c) Z. The following description of “thickness of the hole supply layer 4 ” also follows this description and will not be repeated.

[0114] For example, see Figure 4 , the thickness h4 of the hole-supplying layer 4 can be 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, 55 nm, 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, 85 nm, 90 nm, 95 nm, 100 nm, 105 nm, 110 nm, 115 nm, 120 nm, 125 nm, 130 nm, 135 nm, 140 nm, 145 nm, 150 nm, 155 nm, 160 nm, 165 nm, 170 nm, 175 nm, 180 nm, 185 nm, 190 nm, 195 nm or 200 nm, etc.

[0115] In some embodiments, please refer to Figure 3 and Figure 4 The semiconductor device 10 may further include a gate layer G. The gate layer G may be stacked on a side of the channel layer 3 away from the substrate c.

[0116] The gate layer G is a key electrode for controlling the conductivity of the semiconductor device 10 . The gate layer G does not directly participate in the conduction of current, but controls the carrier concentration in the channel layer 3 through the electric field effect, thereby controlling the current in the semiconductor device 10 .

[0117] By way of example, the material of the gate layer G may include conductive materials such as nickel (Ni), gold (Au), titanium (Ti), and titanium nitride.

[0118] In some embodiments, please refer to Figure 3 and Figure 4 The semiconductor device 10 may further include a gate dielectric layer 5 . The gate dielectric layer 5 is located between the gate layer G and the channel layer 3 .

[0119] Exemplarily, the material of the gate dielectric layer 5 may include at least one of silicon dioxide (SiO 2 ), aluminum oxide (Al 2 O 3 ), and hafnium dioxide (HfO 2 ).

[0120] For example, the material of the gate dielectric layer 5 may include one of silicon dioxide (SiO 2 ), aluminum oxide (Al 2 O 3 ), and hafnium dioxide (HfO 2 ).

[0121] For another example, the material of the gate dielectric layer 5 may include multiple materials such as silicon dioxide (SiO 2 ), aluminum oxide (Al 2 O 3 ), and hafnium dioxide (HfO 2 ).

[0122] Exemplarily, the gate dielectric layer 5 may be formed by at least one of a chemical vapor deposition (CVD) process and a physical vapor deposition (PVD) process.

[0123] For example, the gate dielectric layer 5 may be formed by a process selected from the group consisting of a chemical vapor deposition (CVD) process and a physical vapor deposition (PVD) process.

[0124] For another example, the gate dielectric layer 5 may be formed by a variety of processes such as a chemical vapor deposition (CVD) process and a physical vapor deposition (PVD) process.

[0125] In some embodiments, please refer to Figure 3 and Figure 4 The semiconductor device 10 may further include a source electrode S and a drain electrode D. The source electrode S and the drain electrode D are located at opposite sides of the gate layer G along the first direction X.

[0126] The effective mass of the holes in the channel layer 3 of the semiconductor device 10 is relatively high. The effective mass of the holes is a physical quantity that describes the response of the holes to the external electric field when they move in the energy band. It is not equivalent to the real mass of the holes, but it can reflect the difficulty of the holes moving in the semiconductor. The high effective mass of the holes in the channel layer 3 means that the holes are more easily scattered and blocked when they move in the channel layer 3, which makes the mobility of the holes in the channel layer 3 lower, and thus makes the power density and response speed of the semiconductor device 10 lower, and the performance of the semiconductor device 10 is poor.

[0127] In particular, when the material of the channel layer 3 in the semiconductor device 10 includes gallium nitride (GaN), the mobility of holes in the channel layer 3 is only about 10 cm 2 / V·S, which makes the power density and response speed of the semiconductor device 10 low, and the performance of the semiconductor device 10 is poor.

[0128] Based on this, in some embodiments, Figure 5 , Figure 6 and Figure 7 As shown, Figure 5 and Figure 6 are schematic cross-sectional views of a semiconductor device 10 according to some embodiments, Figure 7 Schematic diagram of the structure of the first adjustment layer 61 and the channel layer 3 according to some embodiments. The semiconductor device 10 may further include a first adjustment layer 61. The first adjustment layer 61 is stacked on a side of the channel layer 3 away from the substrate c, and the channel layer 3 generates biaxial tensile strain under the action of the first adjustment layer 61.

[0129] Please continue reading Figure 5 , Figure 6 and Figure 7 By setting a first adjustment layer 61 in the semiconductor device 10, the first adjustment layer 61 is stacked on the side of the channel layer 3 away from the substrate c, and the channel layer 3 generates a biaxial tensile strain under the action of the first adjustment layer 61, so that the band structure of the channel layer 3 (for example, the gallium nitride (GaN) layer) can be changed, and the valence band structure of the channel layer 3 (for example, the gallium nitride (GaN) layer) can be modulated.

[0130] Specifically, by causing the channel layer 3 to generate biaxial tensile strain under the action of the first adjustment layer 61, the crystal field splitting band caused by the spin-orbit coupling effect in the channel layer 3 (for example, the gallium nitride (GaN) layer) can be moved upward, and the heavy hole band and the light hole band can be moved downward accordingly, thereby reducing the effective mass of the holes in the channel layer 3 (for example, the gallium nitride (GaN) layer), and the holes in the channel layer 3 (for example, the gallium nitride (GaN) layer) are more easily accelerated and moved under the action of the electric field, which is beneficial to improving the mobility of the holes in the channel layer 3 (for example, the gallium nitride (GaN) layer), thereby facilitating improving the power density and response speed of the semiconductor device 10, and improving the performance of the semiconductor device 10.

[0131] For example, please refer to Figure 5 and Figure 6 , the lattice constant of the material of the first adjustment layer 61 in the semiconductor device 10 is greater than the lattice constant of the material of the channel layer 3 in the semiconductor device 10 .

[0132] It should be noted that the lattice constant (also called unit cell parameter or lattice constant) is a basic parameter that describes the crystal structure. It defines the periodicity of the spatial arrangement of atoms, ions or molecules in the crystal. In three-dimensional space, the lattice constant usually includes the lengths in three directions and the angles between them. The three lengths correspond to the periodic lengths of the three basic crystal directions in the crystal, while the three angles describe the relative directions between these crystal directions.

[0133] When the lattice constant of the material of the first adjustment layer 61 in the semiconductor device 10 is different from the lattice constant of the material of the channel layer 3, there will be a lattice mismatch between the first adjustment layer 61 and the channel layer 3, and stress will be applied to each other between the first adjustment layer 61 and the channel layer 3. By making the lattice constant of the material of the first adjustment layer 61 in the semiconductor device 10 greater than the lattice constant of the material of the channel layer 3 in the semiconductor device 10, the first adjustment layer 61 can be subjected to compressive stress, while the channel layer 3 is subjected to tensile stress, and biaxial tensile strain is generated, thereby changing the energy band structure of the channel layer 3, thereby reducing the effective mass of the holes in the channel layer 3, and the holes in the channel layer 3 are more easily accelerated and moved under the action of the electric field, which is beneficial to improving the mobility of the holes in the channel layer 3, thereby improving the power density and response speed of the semiconductor device 10, and improving the performance of the semiconductor device 10.

[0134] For example, the material of the channel layer 3 in the semiconductor device 10 may include gallium nitride (GaN), and the material of the first adjustment layer 61 in the semiconductor device 10 may include indium gallium nitride (InGaN), and the lattice constant of indium gallium nitride (InGaN) is greater than that of gallium nitride (GaN).

[0135] For example, the first adjustment layer 61 may be formed by a metal-organic chemical vapor deposition (MOCVD) process, a molecular beam epitaxy (MBE) process, or a physical vapor deposition (PVD) process.

[0136] For example, please refer to Figure 5 and Figure 6 , a dimension L61 of the first adjustment layer 61 in the semiconductor device 10 along the first direction X (the first direction X is parallel to the arrangement direction of the source S and the drain D) is equal to a dimension L3 of the channel layer 3 in the semiconductor device 10 along the first direction X (the first direction X is parallel to the arrangement direction of the source S and the drain D).

[0137] For example, please refer to Figure 5 and Figure 6 In the case where the semiconductor device 10 includes the first adjustment layer 61, the gate layer G in the semiconductor device 10 can be stacked on the side of the first adjustment layer 61 away from the substrate c. Since the first adjustment layer 61 is stacked on the side of the channel layer 3 away from the substrate c, the first adjustment layer 61 is located between the channel layer 3 and the gate layer G.

[0138] For example, please refer to Figure 5 and Figure 6 In the case where the semiconductor device 10 includes the first adjustment layer 61 , the gate dielectric layer 5 in the semiconductor device 10 may be located between the gate layer G and the first adjustment layer 61 , between the source S and the gate layer G, and between the drain D and the gate layer G.

[0139] In some embodiments, please refer to Figure 5 , the first adjustment layer 61 in the semiconductor device 10 may include a P-type doped semiconductor material.

[0140] When the first adjustment layer 61 in the semiconductor device 10 includes a P-type doped semiconductor material, the first adjustment layer 61 can be used to provide holes to the heterojunction structure formed by the channel layer 3 and the back barrier layer 2 in the semiconductor device 10, which is beneficial to inducing the formation of two-dimensional hole gas (Two-dimensionalhole gas, 2DHG) near the connection interface between the channel layer 3 and the back barrier layer 2, thereby facilitating the improvement of carrier mobility (i.e., hole mobility) and enhancing the performance of the semiconductor device 10.

[0141] For example, the material of the first adjustment layer 61 may include P-type indium gallium nitride (InGaN). P-type indium gallium nitride (InGaN) may be formed by doping the indium gallium nitride (InGaN) material with elements such as iron (Fe) and magnesium (Mg).

[0142] For example, when doping elements such as iron (Fe) and magnesium (Mg) into indium gallium nitride (InGaN) material to form P-type indium gallium nitride (InGaN), a vapor phase doping process or an ion implantation process can be used.

[0143] When the material of the first adjustment layer 61 includes P-type indium gallium nitride (InGaN), the doping concentration of elements such as iron (Fe) and magnesium (Mg) in the P-type indium gallium nitride (InGaN) may be 1E17 cm -3 -2E20 cm -3 .

[0144] For example, please refer to Figure 5 and Figure 6 The first adjustment layer 61 may be a single-layer structure. That is, along the third direction Z (ie, the direction perpendicular to the substrate c), the first adjustment layer 61 includes only one film layer structure.

[0145] Alternatively, the first adjustment layer 61 may also be a multi-layer structure, that is, along the third direction (ie, the direction perpendicular to the substrate c) Z, the first adjustment layer 61 includes a multi-layer film structure.

[0146] For example, when the first adjustment layer 61 is a multi-layer structure and the material of the first adjustment layer 61 includes a P-type doped semiconductor material, the doping concentrations of elements such as iron (Fe) and magnesium (Mg) in different film structures in the first adjustment layer 61 may be different.

[0147] Please continue reading Figure 5 In the case where the first adjustment layer 61 in the semiconductor device 10 includes a P-type doped semiconductor material, the first adjustment layer 61 may include a first portion 61a of the first adjustment layer and a second portion 61b of the first adjustment layer. In the orthographic projection onto the substrate c, the first portion 61a of the first adjustment layer overlaps with the gate layer G, and the second portion 61b of the first adjustment layer does not overlap with the gate layer G. The thickness h61a of the first portion 61a of the first adjustment layer is less than the thickness h61b of the second portion 61b of the first adjustment layer.

[0148] It should be noted that the above “thickness of the first portion 61a of the first adjustment layer” refers to the size of the first portion 61a of the first adjustment layer along the third direction (i.e., the direction perpendicular to the substrate c) Z. The above “thickness of the second portion 61b of the first adjustment layer” refers to the size of the second portion 61b of the first adjustment layer along the third direction (i.e., the direction perpendicular to the substrate c) Z. The following descriptions of “thickness of the first portion 61a of the first adjustment layer” and “thickness of the second portion 61b of the first adjustment layer” also follow this description and will not be repeated.

[0149] In the case where the first adjustment layer 61 in the semiconductor device 10 includes a P-type doped semiconductor material, by making the thickness h61a of the first portion 61a of the first adjustment layer (i.e., the portion where the first adjustment layer 61 and the gate layer G overlap in the orthographic projection onto the substrate c) smaller than the thickness h61b of the second portion 61b of the first adjustment layer (i.e., the portion where the first adjustment layer 61 and the gate layer G do not overlap in the orthographic projection onto the substrate c), the number of holes injected into the heterojunction structure formed by the channel layer 3 and the back barrier layer 2 in the semiconductor device 10 by the first portion 61a of the first adjustment layer (i.e., the portion where the first adjustment layer 61 and the gate layer G overlap in the orthographic projection onto the substrate c) can be reduced, which is beneficial to achieving the depletion of two-dimensional hole gas (2DHG) in the semiconductor device 10, and further beneficial to the semiconductor device 10 to achieve an enhanced operating mode (i.e., the semiconductor device 10 is in an off state at zero gate voltage or a low gate voltage).

[0150] For example, please refer to Figure 5 , a thickness h61a of the first portion 61a of the first adjustment layer is less than or equal to 2 nm, and a thickness h61b of the second portion 61b of the first adjustment layer is greater than or equal to 5 nm and less than or equal to 200 nm.

[0151] For example, see Figure 5 , the thickness h61a of the first portion 61a of the first adjustment layer can be 0.1 nm, 0.2 nm, 0.3 nm, 0.4 nm, 0.5 nm, 0.6 nm, 0.7 nm, 0.8 nm, 0.9 nm, 1 nm, 1.1 nm, 1.2 nm, 1.3 nm, 1.4 nm, 1.5 nm, 1.6 nm, 1.7 nm, 1.8 nm, 1.9 nm or 2 nm, etc.

[0152] The thickness h61b of the second portion 61b of the first adjustment layer may be 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, 55 nm, 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, 85 nm, 90 nm, 95 nm, 100 nm, 105 nm, 110 nm, 115 nm, 120 nm, 125 nm, 130 nm, 135 nm, 140 nm, 145 nm, 150 nm, 155 nm, 160 nm, 165 nm, 170 nm, 175 nm, 180 nm, 185 nm, 190 nm, 195 nm or 200 nm, etc.

[0153] In other embodiments, please refer to Figure 6 , the first adjustment layer 61 in the semiconductor device 10 may include an undoped semiconductor material.

[0154] In the case where the first adjustment layer 61 in the semiconductor device 10 includes an undoped semiconductor material, the thickness h61 of the first adjustment layer 61 is uniform.

[0155] It should be noted that the above “thickness of the first adjustment layer 61 ” refers to the dimension of the first adjustment layer 61 along the third direction (ie, the direction perpendicular to the substrate c) Z. The following description of “thickness of the first adjustment layer 61 ” also follows this description and will not be repeated.

[0156] The above “the thickness h61 of the first adjustment layer 61 is uniform” means that the difference between the thicknesses h61 at multiple positions of the first adjustment layer 61 (i.e., the size of the first adjustment layer 61 along the third direction Z) is within a preset threshold range. The threshold range is a relatively small numerical range, for example, the threshold range can be a process accuracy range when forming the first adjustment layer 61 with uniform thickness.

[0157] For example, please refer to Figure 6 , a thickness h61 of the first adjustment layer 61 in the semiconductor device 10 is greater than or equal to 5 nm and less than or equal to 200 nm.

[0158] For example, see Figure 6, the thickness h61 of the first adjustment layer 61 can be 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, 55 nm, 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, 85 nm, 90 nm, 95 nm, 100 nm, 105 nm, 110 nm, 115 nm, 120 nm, 125 nm, 130 nm, 135 nm, 140 nm, 145 nm, 150 nm, 155 nm, 160 nm, 165 nm, 170 nm, 175 nm, 180 nm, 185 nm, 190 nm, 195 nm or 200 nm, etc.

[0159] In some embodiments, please refer to Figure 5 and Figure 6 , and combined with Figure 8 , Fig. 9 and Fig.10 , Figure 8 and Fig. 9 are schematic cross-sectional views of a semiconductor device 10 according to some embodiments, Fig.10 Schematic diagram of the structure of the first adjustment layer 61, the channel layer 3 and the second adjustment layer 62 according to some embodiments. The channel layer 3 in the semiconductor device 10 includes a first portion 3a of the channel layer. The first portion 3a of the channel layer is located on a side of the first adjustment layer 61 close to the substrate c.

[0160] The semiconductor device 10 further includes a second adjustment layer 62, which is located on opposite sides of the first portion 3a of the channel layer along a first direction X (the first direction X is parallel to the arrangement direction of the source electrode S and the drain electrode D). Under the action of the second adjustment layer 62, the channel layer 3 generates a compressive strain along the first direction X (the first direction X is parallel to the arrangement direction of the source electrode S and the drain electrode D). Specifically, under the action of the second adjustment layer 62, the first portion 3a of the channel layer generates a compressive strain along the first direction X (the first direction X is parallel to the arrangement direction of the source electrode S and the drain electrode D).

[0161] Please continue reading Figure 5 , Figure 6 , Figure 8 , Fig. 9 and Fig.10By disposing a second adjustment layer 62 in the semiconductor device 10, the second adjustment layer 62 is located on opposite sides of the first portion 3a of the channel layer along a first direction X (the first direction X is parallel to the arrangement direction of the source electrode S and the drain electrode D), and the channel layer 3 generates a compressive strain along the first direction X (the first direction X is parallel to the arrangement direction of the source electrode S and the drain electrode D) under the action of the second adjustment layer 62, which can destroy the six-fold symmetry of the crystal in the channel layer 3, so that the band structure of the channel layer 3 (for example, the gallium nitride (GaN) layer) changes. That is, by causing the channel layer 3 (e.g., gallium nitride (GaN) layer) to generate compressive strain along the first direction X (the first direction X is parallel to the arrangement direction of the source S and the drain D) under the action of the second adjustment layer 62, the valence band energy band structure of the channel layer 3 (e.g., gallium nitride (GaN) layer) can be modulated, so that the effective mass of holes in the channel layer 3 (e.g., gallium nitride (GaN) layer) decreases, and the holes in the channel layer 3 (e.g., gallium nitride (GaN) layer) are more easily accelerated and moved under the action of the electric field, which is beneficial to improving the mobility of holes in the channel layer 3 (e.g., gallium nitride (GaN) layer), thereby facilitating improving the power density and response speed of the semiconductor device 10, and improving the performance of the semiconductor device 10.

[0162] It can be understood that, in the case where the semiconductor device 10 includes both the first adjustment layer 61 and the second adjustment layer 62, the channel layer 3 (for example, the gallium nitride (GaN) layer) in the semiconductor device 10 generates biaxial tensile strain under the action of the first adjustment layer 61, and generates compressive strain along the first direction X (the first direction X is parallel to the arrangement direction of the source S and the drain D) under the action of the second adjustment layer 62, which can further reduce the effective mass of the holes in the channel layer 3 (for example, the gallium nitride (GaN) layer), and the holes in the channel layer 3 (for example, the gallium nitride (GaN) layer) are more easily accelerated and moved under the action of the electric field, which is beneficial to further improve the mobility of the holes in the channel layer 3 (for example, the gallium nitride (GaN) layer), thereby further improving the power density and response speed of the semiconductor device 10, and further improving the performance of the semiconductor device 10.

[0163] For example, please refer to Figure 5 , Figure 6 , Figure 8 and Fig. 9 , the lattice constant of the material of the second adjustment layer 62 in the semiconductor device 10 is greater than the lattice constant of the material of the channel layer 3 in the semiconductor device 10 .

[0164] In the case where the lattice constant of the material of the second adjustment layer 62 in the semiconductor device 10 is different from the lattice constant of the material of the channel layer 3, there will be a lattice mismatch between the second adjustment layer 62 and the channel layer 3, and stress will be applied to each other between the second adjustment layer 62 and the channel layer 3. By making the lattice constant of the material of the second adjustment layer 62 in the semiconductor device 10 greater than the lattice constant of the material of the channel layer 3 in the semiconductor device 10, the second adjustment layer 62 can squeeze the channel layer 3, and the channel layer 3 can generate a compressive strain along the first direction X (the first direction X is parallel to the arrangement direction of the source S and the drain D), thereby destroying the six-fold symmetry of the crystal in the channel layer 3, changing the energy band structure of the channel layer 3, thereby reducing the effective mass of the holes in the channel layer 3, and the holes in the channel layer 3 are more easily accelerated and moved under the action of the electric field, which is beneficial to improving the mobility of the holes in the channel layer 3, thereby improving the power density and response speed of the semiconductor device 10, and improving the performance of the semiconductor device 10.

[0165] For example, the material of the channel layer 3 in the semiconductor device 10 may include gallium nitride (GaN), and the material of the second adjustment layer 62 in the semiconductor device 10 may include indium gallium nitride (InGaN), and the lattice constant of indium gallium nitride (InGaN) is greater than that of gallium nitride (GaN).

[0166] For example, the second adjustment layer 62 may be formed by a metal-organic chemical vapor deposition (MOCVD) process, a molecular beam epitaxy (MBE) process, or a physical vapor deposition (PVD) process.

[0167] For example, please refer to Figure 5 , Figure 6 , Figure 8 and Fig. 9 , a thickness h62 of the second adjustment layer 62 is greater than or equal to 5 nm and less than or equal to 200 nm.

[0168] It should be noted that the above “thickness of the second adjustment layer 62 ” refers to the dimension of the second adjustment layer 62 along the third direction (ie, the direction perpendicular to the substrate c) Z. The following description of “thickness of the second adjustment layer 62 ” also follows this description and will not be repeated.

[0169] For example, see Figure 5, the thickness h62 of the second adjustment layer 62 can be 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, 55 nm, 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, 85 nm, 90 nm, 95 nm, 100 nm, 105 nm, 110 nm, 115 nm, 120 nm, 125 nm, 130 nm, 135 nm, 140 nm, 145 nm, 150 nm, 155 nm, 160 nm, 165 nm, 170 nm, 175 nm, 180 nm, 185 nm, 190 nm, 195 nm or 200 nm, etc.

[0170] In some embodiments, please refer to Figure 5 and Figure 6 In the case where the semiconductor device 10 includes the back barrier layer 2 and the second adjustment layer 62 , the back barrier layer 2 may be located on a side of the channel layer 3 and the second adjustment layer 62 close to the substrate c. The back barrier layer 2 and the second adjustment layer 62 are in contact.

[0171] When the back barrier layer 2 is in contact with the second adjustment layer 62, a piezoelectric polarization effect is easily generated between the back barrier layer 2 and the second adjustment layer 62. The piezoelectric polarization effect causes the energy band of the second adjustment layer 62 to tilt and forms an extremely narrow triangular potential well on the semiconductor side of the metal-semiconductor contact, which can increase the probability of hole tunneling and is conducive to forming a better ohmic contact.

[0172] For example, please refer to Figure 5 and Figure 6 , the material of the back barrier layer 2 in the semiconductor device 10 may include aluminum gallium nitride, and the material of the second adjustment layer 62 in the semiconductor device 10 may include p-type doped indium gallium nitride. In the case where the material of the back barrier layer 2 in the semiconductor device 10 includes aluminum gallium nitride, and the material of the second adjustment layer 62 in the semiconductor device 10 includes p-type doped indium gallium nitride, since the material of the back barrier layer 2 is different from the material of the second adjustment layer 62, there is a lattice mismatch between the material of the back barrier layer 2 and the material of the second adjustment layer 62. When the second adjustment layer 62 whose lattice constant does not match the back barrier layer 2 is epitaxially grown on the side of the back barrier layer 2 away from the substrate c, due to the difference in lattice constants between the material of the back barrier layer 2 and the material of the second adjustment layer 62, strain is easily generated in the second adjustment layer 62, and then a piezoelectric polarization effect is generated between the back barrier layer 2 and the second adjustment layer 62. The piezoelectric polarization effect causes the energy band of the second adjustment layer 62 to tilt, and forms an extremely narrow triangular potential well on the semiconductor side of the metal-semiconductor contact, which can increase the probability of hole tunneling and is conducive to forming a better ohmic contact.

[0173] In other embodiments, please refer to Figure 8 and Fig. 9 The channel layer 3 further includes a second portion 3b of the channel layer. The second portion 3b of the channel layer is located on a side of the second adjustment layer 62 close to the substrate c, and is located on opposite sides of the first portion 3a of the channel layer along a first direction X (the first direction X is parallel to the arrangement direction of the source S and the drain D).

[0174] It can be understood that, in the case where the channel layer 3 includes the second portion 3b of the channel layer, the second adjustment layer 62 is in contact with the second portion 3b of the channel layer. A piezoelectric polarization effect is easily generated between the second portion 3b of the channel layer and the second adjustment layer 62. The piezoelectric polarization effect causes the energy band of the second adjustment layer 62 to tilt and forms an extremely narrow triangular potential well on the semiconductor side of the metal-semiconductor contact, which can increase the probability of hole tunneling and is conducive to forming a better ohmic contact.

[0175] For example, please refer to Figure 8 and Fig. 9 , the material of the second portion 3b of the channel layer in the semiconductor device 10 may include gallium nitride, and the material of the second adjustment layer 62 in the semiconductor device 10 may include P-type doped indium gallium nitride. In the case where the material of the second portion 3b of the channel layer in the semiconductor device 10 includes gallium nitride, and the material of the second adjustment layer 62 in the semiconductor device 10 includes P-type doped indium gallium nitride, since the material of the second portion 3b of the channel layer is different from the material of the second adjustment layer 62, there is a lattice mismatch between the material of the second portion 3b of the channel layer and the material of the second adjustment layer 62. When the second adjustment layer 62 whose lattice constant does not match the second portion 3b of the channel layer is epitaxially grown on the side of the second portion 3b of the channel layer away from the substrate c, due to the difference in lattice constants between the material of the second portion 3b of the channel layer and the material of the second adjustment layer 62, strain is easily generated in the second adjustment layer 62, thereby generating a piezoelectric polarization effect between the second portion 3b of the channel layer and the second adjustment layer 62. The piezoelectric polarization effect causes the energy band of the second adjustment layer 62 to tilt and forms an extremely narrow triangular potential well on the semiconductor side of the metal-semiconductor contact, which can increase the probability of hole tunneling and is conducive to forming a better ohmic contact.

[0176] For example, please refer to Figure 8 and Fig. 9 , the second portion 3b of the channel layer may be connected to the first portion 3a of the channel layer, and a thickness h3b of the second portion 3b of the channel layer is less than a thickness h3a of the first portion 3a of the channel layer.

[0177] It should be noted that the above “thickness of the first portion 3a of the channel layer” refers to the dimension of the first portion 3a of the channel layer along the third direction (i.e., the direction perpendicular to the substrate c) Z. The above “thickness of the second portion 3b of the channel layer” refers to the dimension of the second portion 3b of the channel layer along the third direction (i.e., the direction perpendicular to the substrate c) Z. The following descriptions of “thickness of the first portion 3a of the channel layer” and “thickness of the second portion 3b of the channel layer” also follow this description and will not be repeated.

[0178] In some embodiments, please refer to Figure 5 , Figure 6 , Figure 8 and Fig. 9 The semiconductor device 10 further includes an insulating layer 7 . The insulating layer 7 covers the source S and the drain D in the semiconductor device 10 . The gate dielectric layer 5 in the semiconductor device 10 covers the insulating layer 7 .

[0179] The method for manufacturing the semiconductor device 10 is described in detail below.

[0180] In some embodiments, Fig.11 As shown, Fig.11 FIG. 1 is a flow chart of a method for preparing a semiconductor device 10 according to some embodiments. It should be noted that: Fig.11 The method for preparing the semiconductor device 10 shown in FIG. 1 is not exclusive and may also be Fig.11 Other steps are performed before, after or between any steps in the method for manufacturing the semiconductor device 10. The method for manufacturing the semiconductor device 10 includes steps S1 to S4.

[0181] S1: Fig.12 As shown, Fig.12 for Fig.11 A schematic structural diagram of the semiconductor device 10 corresponding to step S1 in the flowchart of the method for preparing the semiconductor device 10 in FIG.

[0182] For example, the channel layer 3 may be formed on one side of the substrate c by a metal-organic chemical vapor deposition (MOCVD) process, a molecular beam epitaxy (MBE) process, or a physical vapor deposition (PVD) process.

[0183] S2: Fig.13 As shown, Fig.13 for Fig.11A schematic structural diagram of the semiconductor device 10 corresponding to step S2 in the flowchart of the method for preparing the semiconductor device 10 in FIG. A first adjustment layer 61 is formed on a side of the channel layer 3 away from the substrate c, and the channel layer 3 generates biaxial tensile strain under the action of the first adjustment layer 61.

[0184] For example, the first adjustment layer 61 may be formed on a side of the channel layer 3 away from the substrate c by a metal-organic chemical vapor deposition (MOCVD) process, a molecular beam epitaxy (MBE) process, or a physical vapor deposition (PVD) process.

[0185] S3: Fig.14 As shown, Fig.14 for Fig.11 The structure diagram of the semiconductor device 10 corresponding to step S3 in the flowchart of the method for preparing the semiconductor device 10 in FIG.

[0186] S4: Fig.15 As shown, Fig.15 for Fig.11 A schematic structural diagram of the semiconductor device 10 corresponding to step S4 in the flowchart of the method for preparing the semiconductor device 10 in FIG. A gate layer G is formed on a side of the first adjustment layer 61 away from the substrate c, and the gate layer G is located between the source electrode S and the drain electrode D.

[0187] By setting a first adjustment layer 61 in the semiconductor device 10, the first adjustment layer 61 is stacked on the side of the channel layer 3 away from the substrate c, and the channel layer 3 generates biaxial tensile strain under the action of the first adjustment layer 61, so that the band structure of the channel layer 3 (for example, the gallium nitride (GaN) layer) can be changed, and the valence band structure of the channel layer 3 (for example, the gallium nitride (GaN) layer) can be modulated.

[0188] Specifically, by causing the channel layer 3 to generate biaxial tensile strain under the action of the first adjustment layer 61, the crystal field splitting band caused by the spin-orbit coupling effect in the channel layer 3 (for example, the gallium nitride (GaN) layer) can be moved upward, and the heavy hole band and the light hole band can be moved downward accordingly, thereby reducing the effective mass of the holes in the channel layer 3 (for example, the gallium nitride (GaN) layer), and the holes in the channel layer 3 (for example, the gallium nitride (GaN) layer) are more easily accelerated and moved under the action of the electric field, which is beneficial to improving the mobility of the holes in the channel layer 3 (for example, the gallium nitride (GaN) layer), thereby facilitating improving the power density and response speed of the semiconductor device 10, and improving the performance of the semiconductor device 10.

[0189] In some embodiments, please refer to Fig.11 , and combined with Fig.13 , the channel layer 3 in the semiconductor device 10 includes a first portion 3a of the channel layer located on a side of the first adjustment layer 61 close to the substrate c. After forming the first adjustment layer 61 on a side of the channel layer 3 away from the substrate c and before forming the source S and the drain D, the method for preparing the semiconductor device 10 may further include step S5.

[0190] S5: Fig.16 As shown, Fig.16 for Fig.11 A schematic diagram of the structure of the semiconductor device 10 corresponding to step S5 in the flowchart of the method for preparing the semiconductor device 10 in FIG. A second adjustment layer 62 is formed, and the second adjustment layer 62 is located on opposite sides of the first portion 3a of the channel layer along a first direction X, and the first direction X is parallel to the arrangement direction of the source S and the drain D. Under the action of the second adjustment layer 62, the channel layer 3 generates a compressive strain along the first direction X.

[0191] By disposing the second adjustment layer 62 in the semiconductor device 10, the second adjustment layer 62 is located on opposite sides of the first part 3a of the channel layer along the first direction X (the first direction X is parallel to the arrangement direction of the source electrode S and the drain electrode D), and the channel layer 3 generates compressive strain along the first direction X (the first direction X is parallel to the arrangement direction of the source electrode S and the drain electrode D) under the action of the second adjustment layer 62, which can destroy the six-fold symmetry of the crystal in the channel layer 3, so that the band structure of the channel layer 3 (for example, gallium nitride (GaN) layer) changes. That is, by causing the channel layer 3 (e.g., gallium nitride (GaN) layer) to generate compressive strain along the first direction X (the first direction X is parallel to the arrangement direction of the source S and the drain D) under the action of the second adjustment layer 62, the valence band energy band structure of the channel layer 3 (e.g., gallium nitride (GaN) layer) can be modulated, so that the effective mass of holes in the channel layer 3 (e.g., gallium nitride (GaN) layer) decreases, and the holes in the channel layer 3 (e.g., gallium nitride (GaN) layer) are more easily accelerated and moved under the action of the electric field, which is beneficial to improving the mobility of holes in the channel layer 3 (e.g., gallium nitride (GaN) layer), thereby facilitating improving the power density and response speed of the semiconductor device 10, and improving the performance of the semiconductor device 10.

[0192] It can be understood that, in the case where the semiconductor device 10 includes both the first adjustment layer 61 and the second adjustment layer 62, the channel layer 3 (for example, the gallium nitride (GaN) layer) in the semiconductor device 10 generates biaxial tensile strain under the action of the first adjustment layer 61, and generates compressive strain along the first direction X (the first direction X is parallel to the arrangement direction of the source S and the drain D) under the action of the second adjustment layer 62, which can further reduce the effective mass of the holes in the channel layer 3 (for example, the gallium nitride (GaN) layer), and the holes in the channel layer 3 (for example, the gallium nitride (GaN) layer) are more easily accelerated and moved under the action of the electric field, which is beneficial to further improve the mobility of the holes in the channel layer 3 (for example, the gallium nitride (GaN) layer), thereby further improving the power density and response speed of the semiconductor device 10, and further improving the performance of the semiconductor device 10.

[0193] For example, the second adjustment layer 62 may be formed on opposite sides of the first portion 3a of the channel layer along a first direction X (the first direction X is parallel to the arrangement direction of the source S and the drain D) by a metal-organic chemical vapor deposition (MOCVD) process, a molecular beam epitaxy (MBE) process, or a physical vapor deposition (PVD) process.

[0194] For example, Fig.17 As shown, combined with Fig.16 , Fig.17 for Fig.11 Schematic diagram of the structure of the semiconductor device 10 corresponding to step S2 in the flowchart of the method for preparing the semiconductor device 10 in FIG. When the second adjustment layer 62 is formed after the first adjustment layer 61 is formed on the side of the channel layer 3 away from the substrate c, a mask layer Q may be provided on the side of the first adjustment layer 61 away from the channel layer 3 to prevent the material for forming the second adjustment layer 62 from being deposited on the side of the first adjustment layer 61 away from the channel layer 3 when the second adjustment layer 62 is formed.

[0195] For example, the material of the mask layer Q may include silicon dioxide or silicon nitride.

[0196] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A semiconductor device, characterized in that: include: substrate; A channel layer is disposed on one side of the substrate; A first adjustment layer is stacked on a side of the channel layer away from the substrate; the lattice constant of the material of the first adjustment layer is greater than the lattice constant of the material of the channel layer; the channel layer includes a first portion, which is located on a side of the first adjustment layer close to the substrate; the channel layer generates a biaxial tensile strain under the action of the first adjustment layer; a second adjustment layer, located at two opposite sides of the first portion of the channel layer along a first direction; the channel layer generates a compressive strain along the first direction under the action of the second adjustment layer; A gate layer, stacked on a side of the first adjustment layer away from the substrate; The source electrode and the drain electrode are located at opposite sides of the gate layer along the first direction.

2. The semiconductor device according to claim 1, wherein: The material of the channel layer includes gallium nitride, and the material of the first adjustment layer includes indium gallium nitride.

3. The semiconductor device according to claim 1, wherein: The first adjustment layer includes a P-type doped semiconductor material; The first adjustment layer comprises a first part and a second part, in an orthographic projection onto the substrate, the first part of the first adjustment layer overlaps with the gate layer, and the second part of the first adjustment layer does not overlap with the gate layer; The thickness of the first portion of the first adjustment layer is smaller than the thickness of the second portion of the first adjustment layer.

4. The semiconductor device according to claim 3, characterized in that The thickness of the first portion of the first adjustment layer is less than or equal to 2 nm, and the thickness of the second portion of the first adjustment layer is greater than or equal to 5 nm and less than or equal to 200 nm.

5. The semiconductor device according to claim 1, wherein: The first adjustment layer comprises an undoped semiconductor material; The first adjustment layer has a uniform thickness.

6. The semiconductor device according to claim 5, characterized in that The thickness of the first adjustment layer is greater than or equal to 5 nm and less than or equal to 200 nm.

7. The semiconductor device according to claim 5, characterized in that A size of the first adjustment layer along the first direction is equal to a size of the channel layer along the first direction.

8. The semiconductor device according to claim 1, wherein: The lattice constant of the material of the second adjustment layer is greater than the lattice constant of the material of the channel layer.

9. The semiconductor device according to claim 1, wherein: The channel layer also includes a second portion, which is located on a side of the second adjustment layer close to the substrate and on opposite sides of the first portion of the channel layer along the first direction; the second portion of the channel layer is connected to the first portion of the channel layer, and a thickness of the second portion of the channel layer is less than a thickness of the first portion of the channel layer.

10. The semiconductor device according to claim 9, characterized in that The material of the channel layer includes gallium nitride, and the material of the second adjustment layer includes P-type doped indium gallium nitride.

11. The semiconductor device according to claim 1, wherein: The semiconductor device further comprises a back barrier layer located on a side of the channel layer and the second adjustment layer close to the substrate; The back barrier layer is in contact with the second adjusting layer.

12. The semiconductor device according to claim 11, characterized in that The material of the back barrier layer includes aluminum gallium nitride, and the material of the second adjustment layer includes P-type doped indium gallium nitride.

13. The semiconductor device according to any one of claims 1 to 12, characterized in that: The semiconductor device further includes a gate dielectric layer located between the gate layer and the first adjustment layer, between the source electrode and the gate layer, and between the drain electrode and the gate layer.

14. The semiconductor device according to claim 13, characterized in that The semiconductor device further comprises an insulating layer covering the source and the drain; the gate dielectric layer covers the insulating layer.

15. A method for preparing a semiconductor device, characterized in that: include: forming a channel layer on one side of the substrate; A first adjustment layer is formed on a side of the channel layer away from the substrate; the channel layer includes a first portion located on a side of the first adjustment layer close to the substrate; a lattice constant of a material of the first adjustment layer is greater than a lattice constant of a material of the channel layer; and the channel layer generates a biaxial tensile strain under the action of the first adjustment layer; forming a second adjustment layer, wherein the second adjustment layer is located at two opposite sides of the first portion of the channel layer along a first direction; the channel layer generates a compressive strain along the first direction under the action of the second adjustment layer; forming a source electrode and a drain electrode; the first direction is parallel to the arrangement direction of the source electrode and the drain electrode; A gate layer is formed on a side of the first adjustment layer away from the substrate, and the gate layer is located between the source and the drain.

16. A chip, characterized in that: Comprising the semiconductor device according to any one of claims 1 to 14.

17. An electronic device, characterized in that: include: Circuit boards; The chip as claimed in claim 16, wherein the chip is electrically connected to the circuit board.

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