A time-to-digital converter based on interpolating differential ring delay chain

Abstract

This invention relates to a time-to-digital converter based on an interpolation differential ring delay chain, comprising: a controller, a delay chain, and an encoder; the controller is electrically connected to both the delay chain and the encoder; the delay chain is also connected to the encoder; the controller receives the pulse signal to be measured and the system clock and generates control signals for the delay chain and the encoder; the delay chain includes a fine counting module and a coarse counting module; the fine counting module includes 11 stages of differential amplifiers connected in an interleaved manner, each stage of which is connected to a 6-stage interpolation circuit; each stage of the interpolation circuit is simultaneously sampled by 6 D flip-flops; the fine counting module measures the pulse signal to be measured and outputs a fine count value; the coarse counting module records the oscillation period of the fine counting module and outputs a coarse count value. This invention utilizes a 55 nm CMOS process to fabricate a time-to-digital converter with an interpolation differential ring delay chain, achieving a time resolution of less than 13 ps and a time measurement accuracy of no more than 10 ps.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits and relates to a time-to-digital converter based on an interpolation differential ring delay chain. Background Art

[0002] Positron emission tomography (PET) is an important nuclear medicine imaging technology. Researchers have added time-of-flight (TOF) technology to the PET system to obtain photon flight time information, thereby effectively narrowing the image reconstruction range, reducing invalid information and improving the signal-to-noise ratio of the reconstructed image.

[0003] The TOF-PET detection system adds the measurement of time information on the basis of traditional PET technology. TOF-PET tracks the distribution of radioactive tracers in the body, monitors cell activity and its metabolic processes to perform complex three-dimensional imaging. It is a high-end medical imaging device that can monitor organisms at the molecular level. It is also an indispensable key diagnostic equipment in the fields of nuclear medicine clinical disease diagnosis, pathological research, and drug development.

[0004] In a TOF-PET instrument, it is necessary to read out the PMT (Photomultiplier Tube) array with thousands of channels. The specific process is as follows: PMT collects the current pulses generated by the photons transmitted by the scintillator, and the current pulses are subjected to constant fraction discriminator (CFD) by the analog front-end circuit to generate rectangular pulses. The TDC (Time to Digital Converter) is based on the flight time of the photons collected by the rectangular pulses.

[0005] For TOF-PET that uses scintillators and PMT as conversion devices, the time resolution of TDC in the readout chip directly affects the positioning accuracy and imaging quality of TOF-PET. The higher the time resolution of TDC, the higher the positioning accuracy of TOF-PET and the better the quality of the imaging picture. Studies have found that in order to ensure the photon measurement performance of PMT, the time resolution of the TDC readout circuit needs to meet the minimum value of the transit time distribution of PMT (15 ps). However, the existing TDC designs at home and abroad are complex in design, and most TDC designs cannot overcome the limitation of the minimum gate delay of the process. Summary of the invention

[0006] To solve the above-mentioned problems in the prior art, the present invention provides a time-to-digital converter based on an interpolated differential ring delay chain.

[0007] In order to achieve the above object, the technical solution adopted by the present invention is:

[0008] In the first aspect, the present application provides a time-to-digital converter based on an interpolation differential ring delay chain, comprising: a controller, a delay chain and an encoder; the controller is electrically connected to the delay chain and the encoder respectively; the delay chain is also electrically connected to the encoder; the controller is used to receive a pulse signal to be measured and a system clock, and generate control signals for the delay chain and the encoder; the delay chain comprises a fine counting module and a coarse counting module; the fine counting module comprises 11 levels of differential amplifiers connected end to end in an interleaved manner, and each level of differential amplifier is connected to a 6-level interpolation circuit; each level of interpolation circuit is sampled simultaneously by 6 D flip-flops; the fine counting module is used to measure the pulse signal to be measured and output a fine count value; the coarse counting module is used to record the oscillation period of the fine counting module and output a coarse count value; the encoder is used to convert the fine count value and the coarse count value into binary numbers.

[0009] Optionally, for any one of the 11 differential amplifiers connected end to end in an alternating manner, the connection relationship includes: the non-inverting input terminal of the differential amplifier is connected to the inverting output terminal of the previous differential amplifier; the inverting input terminal of the differential amplifier is connected to the non-inverting output terminal of the previous differential amplifier; the non-inverting output terminal of the differential amplifier is connected to the inverting input terminal of the next differential amplifier; and the inverting output terminal of the differential amplifier is connected to the non-inverting input terminal of the next differential amplifier.

[0010] Optionally, for any one of the 11 differential amplifiers connected end to end in an alternating manner, the connection relationship also includes: the differential amplifier is connected to the corresponding 6-stage interpolation circuit through an input buffer and an output buffer; wherein the non-phase input of the input buffer is connected to the non-phase input of the differential amplifier; the inverting input of the input buffer is connected to the inverting input of the differential amplifier; the output of the input buffer is connected to the first input of the 6-stage interpolation circuit; the non-phase input of the output buffer is connected to the non-phase output of the differential amplifier; the inverting input of the output buffer is connected to the inverting output of the differential amplifier; and the output of the output buffer is connected to the second input of the 6-stage interpolation circuit.

[0011] Optionally, for any one of the 6-level interpolation circuits, it includes: a first sub-input buffer, a second sub-input buffer, a first sub-output buffer, a second sub-output buffer, a third sub-output buffer, a fourth sub-output buffer, a fifth sub-output buffer, a sixth sub-output buffer, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor and a seventh resistor; the first resistor is connected in series between the output end of the first sub-input buffer and the input end of the first sub-output buffer; the seventh resistor is connected in series between the output end of the second sub-input buffer and the input end of the sixth sub-output buffer; the second resistor, the third resistor, the fourth resistor, the fifth resistor and the sixth resistor are also connected in series in sequence between the output end of the first sub-input buffer and the output end of the second sub-input buffer; the input end of the second sub-output buffer is connected between the second resistor and the third resistor; the input end of the third sub-output buffer is connected between the third resistor and the fourth resistor; the input end of the fourth sub-output buffer is connected between the fourth resistor and the fifth resistor; the input end of the fifth sub-output buffer is connected between the fifth resistor and the sixth resistor.

[0012] Optionally, the driving clock of the coarse counting module comes from the last interpolation output in the last stage of interpolation circuit in the fine counting module.

[0013] Optionally, the coarse counting module includes two groups of 5-bit ripple counters; wherein the first group of 5-bit ripple counters is driven by the rising edge of the last interpolation output in the last stage interpolation circuit in the fine counting module; and the second group of 5-bit ripple counters is driven by the falling edge of the last interpolation output in the last stage interpolation circuit in the fine counting module.

[0014] Optionally, the encoder includes: a fifo module, an encoding logic module and an output latch module; the fifo module is used to cache the fine count value and the coarse count value output by the delay chain; the encoding logic module is used to convert the fine count value and the coarse count value into corresponding binary values; and the output latch module is used to output the binary value.

[0015] Optionally, the output latch module is further used to output a check signal; wherein the check signal is used to indicate whether the output binary of the time-to-digital converter is valid.

[0016] Optionally, the pulse signal to be measured comes from an analog front-end circuit between a photomultiplier tube and the time-to-digital converter.

[0017] Optionally, the system clock of the time-to-digital converter is 40 MHz.

[0018] The beneficial effects of this application include:

[0019] The embodiment of the present application develops a time-to-digital converter with an interpolated differential ring delay chain based on a 55 nm CMOS process, which can obtain a time resolution of less than 13 ps and a time measurement accuracy of no more than 10 ps. The time-to-digital converter can meet the application of high time resolution PMT in TOF-PET system. In view of the limitation of the minimum gate delay of the 55 nm CMOS process, an interpolated differential ring delay chain structure TDC is proposed, so that its time resolution is less than the minimum gate delay of the process. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A module block diagram of a time-to-digital converter based on an interpolated differential ring delay chain provided by an embodiment of the present invention;

[0021] Figure 2 A schematic diagram of a first delay chain provided by an embodiment of the present invention;

[0022] Figure 3 A schematic diagram of a second delay chain provided by an embodiment of the present invention;

[0023] Figure 4 A schematic diagram of a third delay chain provided by an embodiment of the present invention;

[0024] Figure 5 A circuit diagram of an interpolation circuit provided by an embodiment of the present invention;

[0025] Figure 6 A schematic diagram of a coarse counting module provided in an embodiment of the present invention;

[0026] Figure 7 A schematic diagram of an encoder provided by an embodiment of the present invention;

[0027] Figure 8 A schematic diagram of encoding logic of an encoder provided by an embodiment of the present invention;

[0028] Fig. 9 A control relationship diagram of a time-to-digital converter provided by an embodiment of the present invention;

[0029] Fig.10 A timing control diagram of a controller provided in an embodiment of the present invention.

[0030] Figure numerals: 100 - time-to-digital converter; 10 - controller; 20 - delay chain; 201 - fine counting module; 202 - coarse counting module; 30 - encoder; 301 - fifo module; 302 - encoding logic module; 303 - output latch module. DETAILED DESCRIPTION

[0031] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0032] For TOF-PET that uses scintillators and PMT as conversion devices, the time resolution of TDC in the readout chip directly affects the positioning accuracy and imaging quality of TOF-PET. The higher the time resolution of TDC, the higher the positioning accuracy of TOF-PET and the better the quality of the imaging picture. Studies have found that in order to ensure the photon measurement performance of PMT, the time resolution of the TDC readout circuit should meet the minimum value of the transit time distribution of PMT (15ps). However, the existing TDC designs at home and abroad are complex in design, and most TDC designs cannot overcome the limitation of the minimum gate delay of the process.

[0033] In view of the above problems, the present application provides the following embodiments to solve them:

[0034] See also Figure 1 An embodiment of the present application provides a time-to-digital converter 100 based on an interpolation differential ring delay chain, comprising: a controller 10 , a delay chain 20 and an encoder 30 .

[0035] The controller 10 is electrically connected to the delay chain 20 and the encoder 30 . The delay chain 20 is also electrically connected to the encoder 30 .

[0036] The controller 10 is used to receive the pulse signal to be measured and the system clock, and generate control signals for the delay chain 20 and the encoder 30 .

[0037] The pulse signal to be measured may come from an analog front-end circuit between the photomultiplier tube and the time-to-digital converter.

[0038] See also Figure 2 The delay chain 20 may include a fine counting module 201 and a coarse counting module 202 ; the fine counting module 201 and the coarse counting module 202 are electrically connected.

[0039] In the embodiment of the present application, the fine counting module 201 is used to measure the pulse signal to be measured and output the fine counting value. The coarse counting module 202 is used to record the vibration period of the fine counting module and output the coarse counting value. Both are controlled by the control signal generated by the controller 10.

[0040] See also Figure 3The fine counting module 201 includes 11 levels of differential amplifiers connected end to end in an alternating manner, and each level of differential amplifier is connected to a 6-level interpolation circuit; each level of interpolation circuit is sampled simultaneously by 6 D flip-flops.

[0041] It should be noted that the six D flip-flops are grouped together, and each group of D flip-flops shares a latch clock latch_clk.

[0042] The encoder 30 is used to convert the fine count value and the coarse count value into binary numbers.

[0043] It should be noted that the ASIC of the time-to-digital converter 100 based on the interpolated differential ring delay chain provided in the embodiment of the present application is implemented on a 55 nm CMOS (Complementary Metal-Oxide-Semiconductor) process. The minimum gate delay of the 55 nm CMOS process is about 18 ps, which is comparable to the transit time distribution of the PMT, and the tape-out cost is relatively low and the process stability is good.

[0044] Through post-simulation verification, the differential ring delay chain is composed of 11 differential amplifiers connected end to end to form a ring oscillator. Through post-simulation, the delay of each differential amplifier is about 78 ps. The interpolation circuit uses 6-level resistor interpolation. After interpolation, the 11-level differential amplifier obtains 66 levels of interpolation output (d0~d65), and the average delay of each interpolation is about 13 ps (78ps / 6).

[0045] It can be seen that the time-to-digital converter of the interpolated differential ring delay chain developed in the embodiment of the present application based on the 55 nm CMOS process can obtain a time resolution of less than 13 ps and a time measurement accuracy of no more than 10 ps. The time-to-digital converter can meet the application of high time resolution PMT in TOF-PET system. In addition, in view of the limitation of the minimum gate delay of the 55 nm CMOS process, an interpolated differential ring delay chain structure TDC is proposed to make its time resolution less than the minimum gate delay of the process.

[0046] That is, at the physical level, this application proposes to use a dedicated integrated circuit to implement a TDC readout circuit for a high time-resolution PMT to meet its application requirements in a TOF-PET system, further reduce the TOF-PET's time resolution, and thus improve the image quality of TOF-PET imaging.

[0047] On the technical level, in response to the limitation of the minimum gate delay of the 55 nm CMOS process, a TDC with an interpolated differential ring delay chain structure is proposed to make its time resolution smaller than the minimum gate delay of the process.

[0048] In summary, the TDC provided in the embodiments of the present application can greatly promote the potential of high time resolution PMT to achieve breakthrough discoveries in the fields of nuclear medicine and high energy physics, and has important scientific significance in physics and important practical value in technology.

[0049] Of course, the time-to-digital converter 100 based on the interpolation differential ring delay chain provided in the embodiment of the present application can also be applied to other processes, such as 45 nm COMS process, which is not limited in the present application.

[0050] The specific structure of the delay chain provided in the embodiment of the present application is described below:

[0051] See also Figure 4 Optionally, for any one of the 11 differential amplifiers connected end to end in an alternating manner, the connection relationship includes: the non-inverting input terminal of the differential amplifier is connected to the inverting output terminal of the previous differential amplifier; the inverting input terminal of the differential amplifier is connected to the non-inverting output terminal of the previous differential amplifier; the non-inverting output terminal of the differential amplifier is connected to the inverting input terminal of the next differential amplifier; the inverting output terminal of the differential amplifier is connected to the non-inverting input terminal of the next differential amplifier.

[0052] That is, the differential ring delay chain is composed of 11 differential amplifiers (Delay Cell, DC) connected end to end to form a ring oscillator. The differential ring delay chain includes 11 differential amplifiers D0~D10.

[0053] Taking the differential amplifier D1 as an example, the non-inverting input terminal of the differential amplifier D1 is connected to the inverting output terminal of the previous differential amplifier D0; the inverting input terminal of the differential amplifier D1 is connected to the non-inverting output terminal of the previous differential amplifier D0; the non-inverting output terminal of the differential amplifier D1 is connected to the inverting input terminal of the next differential amplifier D2 (not shown in the figure); the inverting output terminal of the differential amplifier D1 is connected to the non-inverting input terminal of the next differential amplifier D2.

[0054] Optionally, for any one of the 11 differential amplifiers connected end to end in an alternating manner, the connection relationship also includes: the differential amplifier is connected to the corresponding 6-stage interpolation circuit through an input buffer and an output buffer; wherein the non-inverting input of the input buffer is connected to the non-inverting input of the differential amplifier; the inverting input of the input buffer is connected to the inverting input of the differential amplifier; the output of the input buffer is connected to the first input of the 6-stage interpolation circuit; the non-inverting input of the output buffer is connected to the non-inverting output of the differential amplifier; the inverting input of the output buffer is connected to the inverting output of the differential amplifier; and the output of the output buffer is connected to the second input of the 6-stage interpolation circuit.

[0055] Please continue reading Figure 4 Taking the differential amplifier D1 as an example, an input buffer D101 and an output buffer D102 are provided between the differential amplifier D1 and the interpolation circuit.

[0056] Among them, the non-inverting input terminal of the input buffer D101 is connected to the non-inverting input terminal of the differential amplifier D1; the inverting input terminal of the input buffer D101 is connected to the inverting input terminal of the differential amplifier D1; the output terminal of the input buffer D101 is connected to the first input terminal of the corresponding 6-level interpolation circuit; the non-inverting input terminal of the output buffer D102 is connected to the non-inverting output terminal of the differential amplifier D1; the inverting input terminal of the output buffer D102 is connected to the inverting output terminal of the differential amplifier D1; the output terminal of the output buffer D102 is connected to the second input terminal of the 6-level interpolation circuit.

[0057] It should be noted that the above buffer may specifically be a differential-to-single-ended buffer.

[0058] See also Figure 5 Optionally, for any one of the 6-level interpolation circuits, it includes: a first sub-input buffer U1, a second sub-input buffer U1, a first sub-output buffer U01, a second sub-output buffer U02, a third sub-output buffer U03, a fourth sub-output buffer U04, a fifth sub-output buffer U05, a sixth sub-output buffer U06, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6 and a seventh resistor R7.

[0059] The above buffer may specifically be a differential-to-single-ended buffer.

[0060] The input end of the first sub-input buffer U1 can be used as the first input end of the 6-level interpolation circuit; the input end of the second sub-input buffer U2 can be used as the second input end of the 6-level interpolation circuit. A first resistor R1 is connected in series between the output end of the first sub-input buffer U1 and the input end of the first sub-output buffer U01. A seventh resistor R7 is connected in series between the output end of the second sub-input buffer U2 and the input end of the sixth sub-output buffer U06.

[0061] A second resistor R2 , a third resistor R3 , a fourth resistor R4 , a fifth resistor R5 and a sixth resistor R6 are sequentially connected in series between the output end of the first sub-input buffer U1 and the output end of the second sub-input buffer U2 .

[0062] The input end of the second sub-output buffer U02 is connected between the second resistor R2 and the third resistor R3; the input end of the third sub-output buffer U03 is connected between the third resistor R3 and the fourth resistor R4; the input end of the fourth sub-output buffer U04 is connected between the fourth resistor R4 and the fifth resistor R5; and the input end of the fifth sub-output buffer U05 is connected between the fifth resistor R5 and the sixth resistor R6.

[0063] It should be noted that the above structure can be applied to any interpolation circuit.

[0064] The coarse counting module 202 is electrically connected to the fine counting module 201, and the driving clock of the coarse counting module 202 comes from the last interpolation output of the last interpolation circuit in the fine counting module 201. That is, the interpolation circuit output d65 (the 66-level interpolation output, including d0-d65, is obtained after the 11-level differential amplifier is interpolated) is used as the driving clock of the coarse counting module 202.

[0065] It should be noted that, in the embodiment of the present application, the dynamic range of the time-to-digital converter is expanded by combining the fine counting module 201 and the coarse counting module 202 .

[0066] See also Figure 6 Optionally, the coarse counting module 202 includes two groups of 5-bit ripple counters.

[0067] The first group of 5-bit ripple counters is driven by the rising edge of the last interpolation output in the last stage of interpolation circuit in the fine counting module 201 .

[0068] The second group of 5-bit ripple counters is driven by the falling edge of the last interpolation output in the last stage of interpolation circuit in the fine counting module 201 .

[0069] exist Figure 6 In the example, signal Clk_CNT represents the driving clock (provided by interpolation output D65). cnt_enable represents the clock enable signal of the coarse counting module 202, which is valid at a high level; when no pulse (pulse signal to be measured) is generated, the coarse counting module 202 is in a static state to save power consumption. cnt_rstn represents the reset signal of the coarse counting module 202, which is valid at a low level. When a pulse measurement is restarted, the cnt_rstn signal will clear the coarse count value. CA<0:4> and CB<0:4> are two sets of output values ​​of the coarse counting circuit.

[0070] It should be noted that the coarse counting module 202 is composed of two groups of ripple counters, which are driven by the rising edge and falling edge of the Clk_CNT clock respectively. In this way, the problem of unstable output data caused by the metastable state of the ripple counter can be overcome, that is, it can be determined later which group of ripple counters has valid values.

[0071] The principles of the fine counting module 201 and the coarse counting module 202 provided in the embodiment of the present application are described below:

[0072] Combined with the requirement for TDC time resolution (less than 13 ps) and the limitation of the minimum gate delay of 55 nm CMOS process (about 18 ps), it is proposed to use an interpolated differential ring delay structure to implement the delay chain, which can overcome the limitation of the minimum gate delay of the process and enable TDC to obtain a smaller time resolution. At the same time, in order to balance the relationship between the delay chain layout area, the delay chain power consumption and the dynamic range of TDC measurement, the time interval measurement is achieved by combining fine counting with coarse counting.

[0073] The principle of the fine counting module 201 can be combined with Figure 4~Figure 5 As shown in the figure, it is mainly composed of three parts: differential ring delay chain, interpolation circuit and D flip-flop. The differential ring delay chain is composed of 11 differential amplifiers connected end to end to form a ring oscillator. Through post-simulation, the delay of each differential amplifier is about 78 ps. The interpolation circuit (Interpolator) uses 6-level resistor interpolation. After the 11-level differential amplifier is interpolated, 66 levels of interpolation output (d0~d65) are obtained. Therefore, the average delay of each level of interpolation is about 13 ps (78 ps / 6). The interpolation output d65 is used as the driving clock (Clk_CNT) of the coarse counting module 202. The clock period of Clk_CNT is calculated to be about 1.716 ns (2*11*78ps). From the above analysis, we can know that the measurement range of the interpolated differential ring delay chain, i.e., the fine count, is 0~1.716ns, while the measurement dynamic range of TDC is 0.5 ns~24.5ns. In order to meet the maximum measurement range of TDC (24.5 ns), the fine count module 201 and the coarse count module 202 are combined to expand its measurement dynamic range. The driving clock of the coarse count module 202 comes from the delay chain interpolation output terminal D65 (Clk_CNT). According to calculations, the bit width of the coarse count module 202 should be no less than 4 bits. Considering the influence of PVT, the bit width of the coarse count module 202 is expanded to 5 bits. Therefore, the measurement dynamic range of TDC is 54.912 ns (2 5 *1.716 ns). The schematic diagram of the coarse counting module 202 is as follows Figure 6As shown, the coarse counting module 202 is composed of two groups of ripple counters, and the two groups of ripple counters are driven by the rising edge and the falling edge of the Clk_CNT clock respectively, so as to overcome the problem of unstable output data caused by the metastable state of the ripple counter.

[0074] See also Figure 7 Optionally, the encoder 30 includes: a fifo module 301 , an encoding logic module 302 and an output latch module 303 .

[0075] The fifo module 301 is used to cache the fine count value and the coarse count value output by the delay chain. Specifically, the fifo module 301 is used to cache the fine count value (D[65:0]) and the coarse count value (CA / B[4:0]) output by the delay chain.

[0076] The encoding logic module 302 is used to convert the fine count value and the coarse count value into corresponding binary values.

[0077] The output latch module 303 is used to output the binary value. Specifically, the output latch circuit outputs the encoded binary value at the rising edge of encdatawrtclk.

[0078] See also Figure 8 , Figure 8 To encode the logic for the detailed count value, the specific process includes:

[0079] Figure 8 The detailed count values ​​of two cases are listed in (case 1: 0-1 or 1-0 jump occurs within a group, case 2: 0-1 or 1-0 jump occurs between groups, where a group is defined as 6 data separated by the first-level differential amplifier in the delay chain through the interpolation circuit). When 0-1 or 1-0 appears within a group, such as Figure 8 As shown in the coding logic in the upper middle part, the 6 data in the same group are "AND" and "OR" at the same time, and the values ​​after "AND" and "OR" are "XORed". When the value after "XOR" is 1, the 0-1 or 1-0 jump is located in the group. For the first case, after determining the group number, the specific position of the 0-1 or 1-0 jump in the group is obtained by performing "XOR" calculation on adjacent bits. When 0-1 or 1-0 appears between groups, such as Figure 8 As shown in the coding logic in the lower middle part, the 6 data in the same group are "AND" and "OR" at the same time, and the values ​​after "AND" and "OR" are "AND" calculated again, and the values ​​after "AND" calculation are cyclically "XOR"ed. When the value after "XOR" is 1, the 0-1 or 1-0 jump is between this group and the previous group.

[0080] Optionally, the output latch module 303 is further used to output an indication signal; wherein the indication signal is used to indicate whether the output binary of the time-to-digital converter is valid.

[0081] Specifically, the encoder 30 encodes the original numerical value output by the delay chain into a binary value (TOA_code[11:0], TOT_code[7:0], CAL_code[10:0]) and generates a Hit_flag signal. The Hit_flag signal is used to indicate whether the TDC output binary is valid, a high level is valid, and a low level is invalid.

[0082] Optionally, the system clock of the time-to-digital converter is 40 MHz.

[0083] The time-to-digital converter based on the interpolation differential ring delay chain provided in the embodiment of the present application is described below from the perspective of signal control:

[0084] See also Fig. 9 According to the functions, TDC can be divided into controller, delay chain and encoder. The encoder includes fifo module, encoding logic module and output latch module. Among them, the fifo module includes tot fifo module and toa fifo module.

[0085] The controller receives the pulse signal (Pulse), 40MHz system clock (Clk40M) and related control signals (Ctrl_bits) output by the analog front-end circuit, and generates related control signals for the delay chain and encoder (latch_clk, tot_clk, cnt_enable, cnt_rstn, totfifowriteclk, fifowriteclk, fiforeadclk, encdatawrtclk); the delay chain converts the leading edge position and width of the pulse (Pulse) into the corresponding original digital values ​​(tot finedata[65:0], counterA / B[4:0]; toa finedata[65:0], counterA / B[4:0]); the encoder encodes the original numerical value output by the delay chain into a binary value (TOA_code[11:0], TOT_code[7:0], CAL_code[10:0]) and generates a Hit_flag signal. The Hit_flag signal is used to indicate whether the TDC output binary is valid. A high level is valid and a low level is invalid.

[0086] The typical timing diagram of the controller is as follows: Fig.10 As shown in the figure, the gray area is a measurement window, that is, a cycle of 40MHz clock (Clk40M) is 25ns. When the rising edge of the pulse appears in the measurement window, the TDC starts a measurement, and the pulse signal and the Clk40M clock generate related control signals. Fig. 9 and Fig.10 The relevant signals are described as follows:

[0087] Clk40M: 40MHz system clock.

[0088] Pulse: The pulse being measured comes from the output signal of the front-end comparator.

[0089] cnt_enable: coarse counting module clock enable signal, high level is valid.

[0090] cnt_rstn: reset signal of coarse counting module, low level is valid.

[0091] latch_clk: delay chain fine count and coarse count latch signal, rising edge is valid.

[0092] tot_clk: used to latch the fine count value and coarse count value corresponding to the falling edge of the measured pulse Pulse;

[0093] fifowriteclk: encoder fifo write clock, which is generated by delayed and inverted latch_clk, and the rising edge is valid.

[0094] totfifowriteclk: writes the fine count value and coarse count value corresponding to the falling edge of the measured pulse Pulse into the tot fifo module.

[0095] fiforeadclk: encoder fifo read clock, triggered by the Clk40M clock to generate four continuous pulses.

[0096] encdatawrtclk: Encoder data output clock signal, generated by the Clk40M clock trigger.

[0097] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0098] References to "one embodiment" or "some embodiments" etc. described in the specification of this application mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0099] In the description of the embodiments of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "install", "connect", "connect", and "assemble" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0100] In the description of the embodiments of the present invention, specific features, structures, materials or characteristics may be combined in a suitable manner in any one or more embodiments or examples.

[0101] In the description of the embodiments of the present invention, it should be understood that "-" and "~" represent the range between two values, and the range includes the endpoints. For example, "AB" represents a range greater than or equal to A and less than or equal to B. "A~B" represents a range greater than or equal to A and less than or equal to B.

[0102] In the description of the embodiments of the present invention, the term "and / or" herein is merely a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " herein generally indicates that the associated objects before and after are in an "or" relationship.

[0103] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A time-to-digital converter based on an interpolating differential ring delay chain, characterized in that: include: Controllers, delay chains and encoders; The controller is electrically connected to the delay chain and the encoder respectively; the delay chain is also electrically connected to the encoder; The controller is used to receive the pulse signal to be measured and the system clock, and generate control signals for the delay chain and the encoder; The delay chain includes a fine counting module and a coarse counting module; the fine counting module includes 11 levels of differential amplifiers connected end to end, each level of differential amplifier is connected to a 6-level interpolation circuit; each level of interpolation circuit is sampled simultaneously by 6 D flip-flops; the fine counting module is used to measure the pulse signal to be measured and output a fine counting value; the coarse counting module is used to record the oscillation period of the fine counting module and output a coarse counting value; The encoder is used to convert the fine count value and the coarse count value into binary numbers; Among them, for any differential amplifier in the 11 stages of differential amplifiers connected end to end in an alternating manner, the connection relationship includes: the non-inverting input terminal of the differential amplifier is connected to the inverting output terminal of the previous stage differential amplifier; the inverting input terminal of the differential amplifier is connected to the non-inverting output terminal of the previous stage differential amplifier; the non-inverting output terminal of the differential amplifier is connected to the inverting input terminal of the next stage differential amplifier; the inverting output terminal of the differential amplifier is connected to the non-inverting input terminal of the next stage differential amplifier; For any differential amplifier among the 11 differential amplifiers connected end to end in an alternating manner, the connection relationship further includes: the differential amplifier is connected to the corresponding 6-stage interpolation circuit through an input buffer and an output buffer; wherein the non-inverting input of the input buffer is connected to the non-inverting input of the differential amplifier; the inverting input of the input buffer is connected to the inverting input of the differential amplifier; the output of the input buffer is connected to the first input of the 6-stage interpolation circuit; the non-inverting input of the output buffer is connected to the non-inverting output of the differential amplifier; the inverting input of the output buffer is connected to the inverting output of the differential amplifier; and the output of the output buffer is connected to the second input of the 6-stage interpolation circuit; Any one of the six-level interpolation circuits comprises: a first sub-input buffer, a second sub-input buffer, a first sub-output buffer, a second sub-output buffer, a third sub-output buffer, a fourth sub-output buffer, a fifth sub-output buffer, a sixth sub-output buffer, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor and a seventh resistor; the first resistor is connected in series between the output end of the first sub-input buffer and the input end of the first sub-output buffer; the seventh resistor is connected in series between the output end of the second sub-input buffer and the input end of the sixth sub-output buffer; the second resistor, the third resistor, the fourth resistor, the fifth resistor and the sixth resistor are connected in series in sequence between the output end of the first sub-input buffer and the output end of the second sub-input buffer; the second resistor and the The input end of the second sub-output buffer is connected between the third resistor; the input end of the third sub-output buffer is connected between the third resistor and the fourth resistor; the input end of the fourth sub-output buffer is connected between the fourth resistor and the fifth resistor; the input end of the fifth sub-output buffer is connected between the fifth resistor and the sixth resistor; the input end of the first sub-input buffer serves as the first input end of the 6-level interpolation circuit; the input end of the second sub-input buffer serves as the second input end of the 6-level interpolation circuit; the output end of the first sub-output buffer, the output end of the second sub-output buffer, the output end of the third sub-output buffer, the output end of the fourth sub-output buffer, the output end of the fifth sub-output buffer and the output end of the sixth sub-output buffer serve as the output end of the 6-level interpolation circuit and are connected to the corresponding D flip-flops.

2. The time-to-digital converter based on interpolation differential ring delay chain according to claim 1, characterized in that: The driving clock of the coarse counting module comes from the last interpolation output of the last-stage interpolation circuit in the fine counting module.

3. The time-to-digital converter based on interpolation differential ring delay chain according to claim 2, characterized in that: The coarse counting module includes two groups of 5-bit ripple counters; The first group of 5-bit ripple counters is driven by the rising edge of the last interpolation output in the last interpolation circuit in the fine counting module; The second group of 5-bit ripple counters is driven by the falling edge of the last interpolation output in the last stage interpolation circuit in the fine counting module.

4. The time-to-digital converter based on interpolation differential ring delay chain according to claim 2, characterized in that: The encoder comprises: a fifo module, an encoding logic module and an output latch module; The fifo module is used to cache the fine count value and the coarse count value output by the delay chain; The encoding logic module is used to convert the fine count value and the coarse count value into corresponding binary values; The output latch module is used to output a binary value.

5. The time-to-digital converter based on interpolation differential ring delay chain according to claim 4, characterized in that: The output latch module is further used to output a check signal; wherein the check signal is used to indicate whether the output binary of the time-to-digital converter is valid.

6. The time-to-digital converter based on interpolation differential ring delay chain according to claim 1, characterized in that: The pulse signal to be measured comes from an analog front-end circuit between a photomultiplier tube and the time-to-digital converter.

7. The time-to-digital converter based on interpolation differential ring delay chain according to claim 1, characterized in that: The system clock of the time-to-digital converter is 40 MHz.

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