Method for forming semiconductor structure
By using tilted and cross-arranged multi-step mask patterns and flip-adjusted mask template technology, the high cost and low efficiency problems caused by multiple masks in the existing technology are solved, and the cost of semiconductor structures is reduced and the performance is improved.
Patent Information
- Application Number
- CN202310371405.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-04-04
- Publication Date
- 2025-09-19
- Estimated Expiration
- 2043-04-04
AI Technical Summary
The prior art requires multiple masks and double patterning when forming small-sized transistors, resulting in high manufacturing costs and low manufacturing efficiency for semiconductor structures.
A mask plate with multi-step mask patterns arranged obliquely and crosswise is used. The positions of the mask patterns and the mask layer are adjusted by flipping, the number of mask plates is reduced, and multiple etching patterns are used to jointly etch the substrate to form an active area.
The manufacturing cost of the semiconductor structure is reduced, the manufacturing process is simplified, the manufacturing efficiency is improved, and the performance of the semiconductor structure is enhanced.
Smart Images
Figure CN118829190B_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor manufacturing technology, and in particular to a method for forming a semiconductor structure. Background Art
[0002] Dynamic Random Access Memory (DRAM) is a semiconductor device commonly used in electronic devices such as computers. It consists of multiple memory cells, each of which typically includes a transistor and a capacitor. The gate of the transistor is electrically connected to a word line, the source is electrically connected to a bit line, and the drain is electrically connected to a capacitor. The word line voltage on the word line can control the on and off of the transistor, thereby allowing data stored in the capacitor to be read or written through the bit line.
[0003] As the size of semiconductor structures like DRAM continues to shrink and their storage density continues to increase, the manufacturing difficulty of small-sized transistors is gradually increasing. Currently, four different masks are often used in conjunction with double patterning technology to form the active area of small-sized transistors. This not only significantly increases the manufacturing cost of semiconductor structures, but also reduces their manufacturing efficiency.
[0004] Therefore, how to reduce the manufacturing cost of semiconductor structures, simplify the manufacturing process of semiconductor structures, and improve the performance of semiconductor structures is a technical problem that needs to be solved urgently. Summary of the Invention
[0005] Some embodiments of the present disclosure provide methods for forming a semiconductor structure, which are used to reduce the manufacturing cost of the semiconductor structure, simplify the manufacturing process of the semiconductor structure, and improve the performance of the semiconductor structure.
[0006] According to some embodiments, the present disclosure provides a method for forming a semiconductor structure, comprising the following steps:
[0007] Providing a mask plate, wherein the mask plate includes a plurality of mask patterns arranged at intervals along a first direction, the mask patterns include a plurality of steps arranged along a second direction, and the first direction and the second direction obliquely intersect;
[0008] forming a mask layer on the top surface of the substrate;
[0009] placing the mask plate above the mask layer and etching the mask layer along the mask pattern to form a first etching pattern in the mask layer;
[0010] Turning over the mask plate to adjust the relative position between the mask pattern and the mask layer;
[0011] Etching the mask layer along the mask pattern in the flipped mask plate to form a second etched pattern in the mask layer;
[0012] The substrate is etched along the first etch pattern and the second etch pattern to form a plurality of active regions in the substrate.
[0013] In some embodiments, the widths of the multiple steps in the mask pattern along the first direction are the same, and two adjacent steps in the mask pattern along the second direction are partially staggered along the first direction.
[0014] In some embodiments, the specific steps of forming the first etch pattern in the mask layer include:
[0015] forming a first photoresist layer above the mask layer;
[0016] placing the mask plate above the mask layer, and etching the first photoresist layer along the mask pattern to form a first window in the first photoresist layer;
[0017] The mask layer is etched along the first window to form the first etched pattern in the mask layer.
[0018] In some embodiments, the specific steps of forming the first etching pattern in the mask layer include:
[0019] forming a first sidewall covering the sidewall of the first window;
[0020] The mask layer is etched along the first window covered with the first sidewall to form the first etched pattern in the mask layer.
[0021] In some embodiments, before flipping the mask, the following steps are further included:
[0022] translating the mask plate along the first direction to adjust the relative position between the mask pattern and the mask layer;
[0023] The mask layer is etched along the mask pattern in the shifted mask plate to form a third etched pattern in the mask layer.
[0024] In some embodiments, the specific steps of etching the mask layer along the mask pattern in the translated mask plate to form a third etched pattern in the mask layer include:
[0025] backfilling the first etching pattern to form a first filling layer covering the mask layer;
[0026] forming a second photoresist layer on the first filling layer;
[0027] Etching the second photoresist layer along the mask pattern in the translated mask plate to form a second window in the second photoresist layer;
[0028] The mask layer is etched along the second window to form the third etched pattern in the mask layer.
[0029] In some embodiments, the specific steps of etching the mask layer along the second window to form the third etched pattern in the mask layer include:
[0030] forming a second sidewall covering the sidewall of the second window;
[0031] The mask layer is etched along the second window covered with the second sidewall to form the third etched pattern in the mask layer.
[0032] In some embodiments, etching the mask layer along the mask pattern in the flipped mask plate to form a second etched pattern in the mask layer includes:
[0033] backfilling the third etch pattern to form a second filling layer covering the mask layer;
[0034] forming a third photoresist layer on the second filling layer;
[0035] Etching the third photoresist layer along the mask pattern in the flipped mask plate to form a third window in the third photoresist layer;
[0036] The mask layer is etched along the third window to form a second etched pattern in the mask layer.
[0037] In some embodiments, the specific steps of etching the mask layer along the third window to form a second etched pattern in the mask layer include:
[0038] forming a third sidewall covering the sidewall of the third window;
[0039] The mask layer is etched along the third window covered with the third sidewall spacer to form the second etched pattern in the mask layer.
[0040] In some embodiments, after forming the second etching pattern in the mask layer, the method further includes the following steps:
[0041] The mask plate is translated along the first direction, and the mask layer is etched along the mask pattern in the translated mask plate to form a fourth etched pattern in the mask layer.
[0042] In some embodiments, etching the substrate along the first etching pattern and the second etching pattern to form a plurality of active regions in the substrate includes:
[0043] The substrate is etched along the first etch pattern, the second etch pattern, the third etch pattern, and the fourth etch pattern to form a plurality of active regions in the substrate.
[0044] Some embodiments of the present disclosure provide a method for forming a semiconductor structure, by forming a mask plate including a plurality of mask patterns arranged at intervals along a first direction, and the mask pattern including a plurality of steps arranged along a second direction, the first direction and the second direction intersect at an angle, so that the first etching pattern and the second etching pattern can be formed in the mask layer by flipping the mask plate, and the first etching pattern and the second etching pattern are used together as mask patterns to etch the substrate to form an active area, thereby reducing the number of mask plates, reducing the manufacturing cost of the semiconductor structure, and improving the manufacturing efficiency of the semiconductor structure, simplifying the manufacturing process of the semiconductor structure, and improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0045] Attachment Figure 1 is a flow chart of a method for forming a semiconductor structure in a specific embodiment of the present disclosure;
[0046] Attachment Figure 2 -Attached Figure 21 It is a schematic diagram of the main process structure in the process of forming a semiconductor structure according to a specific embodiment of the present disclosure. DETAILED DESCRIPTION
[0047] The specific implementation of the method for forming a semiconductor structure provided by the present disclosure is described in detail below with reference to the accompanying drawings.
[0048] This embodiment provides a method for forming a semiconductor structure. Figure 1 is a flow chart of a method for forming a semiconductor structure in a specific embodiment of the present disclosure, Figure 2 -Attached Figure 21 This is a schematic diagram of the main process structure in the process of forming a semiconductor structure in the specific embodiment of the present disclosure. Figures 1-21 As shown, the method for forming the semiconductor structure includes the following steps:
[0049] Step S11, providing a mask plate 20, wherein the mask plate 20 includes a plurality of mask patterns 21 arranged at intervals along a first direction D1, and the mask pattern 21 includes a plurality of steps 211 arranged along a second direction D2, wherein the first direction D1 and the second direction D2 intersect obliquely, as shown in FIG. Figure 2 As shown;
[0050] Step S12, forming a mask layer 33 on the top surface of the substrate 30, as shown in FIG. Figure 3 As shown;
[0051] In step S13, the mask plate 20 is placed on the mask layer 33, and the mask layer 33 is etched along the mask pattern 21 to form a first etching pattern 60 in the mask layer 33. Figure 6 As shown;
[0052] Step S14, turning over the mask plate 20 to adjust the relative position between the mask pattern 21 and the mask layer 33;
[0053] Step S15, etching the mask layer 33 along the mask pattern 21 in the flipped mask plate 20 to form a second etching pattern 140 in the mask layer 33. Figure 14 As shown;
[0054] Step S16: etching the substrate 30 along the first etching pattern 60 and the second etching pattern 140 to form a plurality of active regions 210 in the substrate 30. Figure 21 shown.
[0055] The semiconductor structure described in this embodiment may be, but is not limited to, a DRAM. The following description uses a DRAM as an example. The substrate 30 may be, but is not limited to, a silicon substrate. This embodiment uses a silicon substrate as an example. In other embodiments, the substrate 30 may also be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide, or SOI. The substrate 30 is used to support the device structure above it. By forming the mask patterns 21 in the mask plate 20, extending along the second direction D2 and spaced apart along the first direction D1, with the first direction D1 and the second direction D2 intersecting at an angle, the relative positional relationship between the mask patterns 21 in the mask plate 20 and the mask layer 33 on the substrate 30 can be adjusted by flipping the mask plate 20. This allows the position and / or shape of the projections of the multiple mask patterns 21 in the mask plate 20 onto the mask layer 33 along the third direction D3 to be adjusted. This eliminates the need for multiple mask plates, reduces the number of mask plates used to form the active area, lowers the manufacturing cost of the semiconductor structure, improves the manufacturing efficiency of the semiconductor structure, simplifies the manufacturing process of the semiconductor structure, and improves the performance of the semiconductor structure. The third direction D3 is perpendicular to the top surface of the substrate 30. In one example, both the first direction D1 and the second direction D2 are parallel to the top surface of the substrate 30.
[0056] In some embodiments, the widths of the multiple steps 211 in the mask pattern 21 along the first direction D1 are the same, and two adjacent steps 211 in the mask pattern 21 along the second direction D2 are partially staggered along the first direction D1.
[0057] Specifically, if Figure 2 As shown, the mask plate 20 includes a plurality of mask patterns 21 spaced apart along the first direction D1, each mask pattern 21 extending along the second direction D2. The mask pattern 21 includes a plurality of steps 211 arranged along the second direction D2. In one example, all of the steps 211 in the mask pattern 21 have the same shape and size. Two adjacent steps 211 in the mask pattern 21 along the second direction D2 are partially staggered along the first direction D1, meaning that, for two adjacent steps 211 in the mask pattern 21 along the second direction D2, one step 211 protrudes from the other step 211 along the first direction D1. In this specific embodiment, any two adjacent steps 211 in the mask pattern 21 are partially staggered along the first direction D1, thereby giving the mask pattern 21 an overall zigzag shape. This, on the one hand, increases the pattern arrangement density, thereby increasing the arrangement density of the active area 210 subsequently formed within the substrate 30, thereby increasing the storage density of the semiconductor structure. On the other hand, it also simplifies the subsequent operation of adjusting the relative position between the mask pattern 21 and the mask layer 33 by flipping the mask plate 20, thereby further simplifying the semiconductor structure manufacturing process and improving the manufacturing efficiency of the semiconductor structure. Flipping the mask plate 20 can be done horizontally or vertically.
[0058] This embodiment is described using an inverted L-shaped step 211 (i.e., the step 211 includes a first portion extending along the first direction D1 and a second portion perpendicular to the end of the first portion) as an example to further reduce the size of the subsequently formed active area 210, thereby facilitating further miniaturization of the semiconductor structure. In other embodiments, the step 211 may also have other shapes, such as a regular quadrilateral, and those skilled in the art may adjust the shape and size of the active area 210 to meet specific needs, such as the shape and size of the active area 210 to be formed.
[0059] In order to further ensure the morphology of the first etched pattern 60 , in some embodiments, the specific steps of forming the first etched pattern 60 in the mask layer 33 include:
[0060] A first photoresist layer 36 is formed on the mask layer 33, as shown in FIG. Figure 3 As shown;
[0061] The mask plate 20 is placed on the mask layer 33, and the first photoresist layer 36 is etched along the mask pattern 21 to form a first window 40 in the first photoresist layer 36. Figure 4 As shown;
[0062] The mask layer 33 is etched along the first window 40 to form the first etched pattern 60 in the mask layer 33. Figure 6 shown.
[0063] In order to further reduce the size of the subsequently formed active area 210, in some embodiments, the specific steps of forming the first etching pattern in the mask layer include:
[0064] A first sidewall 50 is formed to cover the sidewall of the first window 40. Figure 5 As shown;
[0065] The mask layer 33 is etched along the first window 40 covered with the first sidewall spacer 50 to form the first etched pattern 60 in the mask layer 33 .
[0066] For example, to avoid damaging the substrate 30, before forming the mask layer 33, a first protective layer 31 and a second protective layer 32 located on the first protective layer 31 are sequentially formed on the top surface of the substrate 30. In one example, the material of the first protective layer 31 can be an organic mask material, such as carbon; the material of the second protective layer 32 can be a hard mask material, such as silicon nitride or silicon oxynitride. The mask layer 33 is formed on the top surface of the second protective layer 32. Thereafter, a first capping layer 34, a second capping layer 35 located on the first capping layer 34, and the first photoresist layer 36 located on the second capping layer 35 are formed on the top surface of the mask layer 33. In one example, the material of the first capping layer 34 can be an organic mask material, such as carbon; and the material of the second capping layer 35 can be a hard mask material, such as silicon nitride or silicon oxynitride. Then, the mask plate 20 is placed on the mask layer 33, and the first photoresist layer 36 is etched along the mask pattern 21 to form a first window 40 in the first photoresist layer 36 that passes through the first photoresist layer 36 along the third direction D3. Figure 4 As shown, Figure 4 (b) is a schematic top view of the semiconductor structure after the first window 40 is formed. Figure 4 (a) in Figure 4 (b) is a cross-sectional view at position AA. Next, an atomic layer deposition process may be used to deposit oxide (e.g., silicon dioxide) on the inner wall of the first window 40 (including the sidewalls of the first window 40 and the bottom wall of the first window 40) and the first sidewall 50 on the top surface of the remaining first photoresist layer 36, as shown in FIG. Figure 5 As shown, Figure 5(b) is a schematic top view of the semiconductor structure after the first spacer 50 is formed. Figure 5 (a) in Figure 5 (b) is a cross-sectional schematic diagram at position AA. Then, a dry etching process can be used to remove the first sidewall 50 covering the bottom wall of the first window 40 and the top surface of the first photoresist layer 36, and only the first sidewall 50 covering the sidewall of the first window 40 is retained to further reduce the width of the first window 40 (for example, the width of the first window 40 along the first direction D1), so as to further reduce the size of the subsequently formed active area 210. Next, the second covering layer 35, the first covering layer 34 and the mask layer 33 are etched downward along the first window 40 whose sidewall is covered with the first sidewall 50, and the first etching pattern 60 penetrating the mask layer 33 along the third direction D3 is formed in the mask layer 33. After removing the first photoresist layer 36, the second covering layer 35 and the first covering layer 34, the following is obtained. Figure 6 The structure shown, wherein Figure 6 (b) is a schematic top view of the semiconductor structure after the first etching pattern 60 is formed. Figure 6 (a) in Figure 6 (b) Schematic diagram of the cross section at position AA.
[0067] Those skilled in the art can flexibly adjust the characteristic size of the first etched pattern (e.g., the width of the first etched pattern along the first direction D1) by adjusting the thickness of the first sidewall 50. In one example, the width of the first sidewall 50 along the first direction D1 (i.e., the thickness of the first sidewall 50) is 10 nm.
[0068] In some embodiments, before flipping the mask 20, the following steps are further included:
[0069] The mask plate 20 is translated along the first direction D1 to adjust the relative position between the mask pattern 21 and the mask layer 33, as shown in FIG. Figure 7 As shown in (b);
[0070] The mask layer 33 is etched along the mask pattern 21 in the shifted mask plate 20 to form a third etched pattern 100 in the mask layer. Figure 10 shown.
[0071] In order to further ensure the morphology of the third etched pattern 100, in some embodiments, the mask layer 33 is etched along the mask pattern 21 in the translated mask plate 20. The specific steps of forming the third etched pattern 100 in the mask layer include:
[0072] The first etching pattern 60 is backfilled to form a first filling layer 70 covering the mask layer 33. Figure 7 As shown in (a);
[0073] A second photoresist layer 72 is formed on the first filling layer 70, as shown in FIG. Figure 7 As shown in (a);
[0074] The second photoresist layer 72 is etched along the mask pattern 21 in the shifted mask plate 20 to form a second window 80 in the second photoresist layer 72. Figure 8 As shown;
[0075] The mask layer 33 is etched along the second window 80 to form the third etched pattern 100 in the mask layer 33. Figure 10 shown.
[0076] In order to further reduce the size of the subsequently formed active area 210 , in some embodiments, the mask layer 33 is etched along the second window 80 to form the third etched pattern 100 in the mask layer 33 . Specifically, the steps include:
[0077] A second sidewall 90 is formed to cover the sidewall of the second window 80, such as Figure 9 As shown;
[0078] The mask layer 33 is etched along the second window 80 covered with the second sidewall 90 to form the third etched pattern 100 in the mask layer 33. Figure 10 shown.
[0079] For example, a spin coating process may be used to form the first filling layer 70 that fills the first etching pattern 60 and covers the remaining top surface of the mask layer 33, as shown in FIG. Figure 7 As shown in (a) of FIG. Next, a hard mask material such as silicon nitride or silicon oxynitride is deposited on the first filling layer 70 to form a third covering layer 71, and the second photoresist layer 72 is formed on the third covering layer 71. Then, the second photoresist layer 72 is etched along the mask pattern 21 in the translated mask plate 20 to form the second window 80 penetrating the second photoresist layer 72 along the third direction D3 in the second photoresist layer 72, as shown in FIG. Figure 8 As shown, Figure 8 (b) is a schematic top view of the semiconductor structure after the second window 80 is formed. Figure 8 (a) in Figure 8(b) is a cross-sectional view at position AA. Next, an atomic layer deposition process may be used to deposit oxide (e.g., silicon dioxide) on the inner wall of the second window 80 (including the sidewall of the second window 80 and the bottom wall of the second window 80) and the second sidewall 90 on the top surface of the remaining second photoresist layer 72, as shown in FIG. Figure 9 As shown, Figure 9 (b) is a schematic top view of the semiconductor structure after the second sidewall spacer 90 is formed. Figure 9 (a) in Figure 9 (b) is a cross-sectional schematic diagram at position AA. Then, a dry etching process can be used to remove the second sidewall 90 covering the bottom wall of the second window 80 and the top surface of the second photoresist layer 72, and only the second sidewall 90 covering the sidewall of the second window 80 is retained to further reduce the width of the second window 80 (for example, the width of the second window 80 along the first direction D1), so as to further reduce the size of the active area 210 formed subsequently. Next, the third covering layer 71, the first filling layer 70 and the mask layer 33 are etched downward along the second window 80 covered with the second sidewall 90, and the third etching pattern 100 is formed in the mask layer 33 along the third direction D3 and penetrates the mask layer 33. After removing the second photoresist layer 72 and the third covering layer 71, the following is obtained. Figure 10 The structure shown, wherein Figure 10 (b) is a schematic top view of the semiconductor structure after forming the third etching pattern 100. Figure 10 (a) in Figure 10 (b) Schematic diagram of the cross section at position AA.
[0080] In order to further reduce the size of the subsequently formed active area 210 and further increase the storage density of the subsequently formed semiconductor structure, in some embodiments, the mask layer 33 is etched along the mask pattern 21 in the flipped mask plate 20 to form the second etched pattern 140 in the mask layer 33, specifically comprising the following steps:
[0081] The third etching pattern 100 is backfilled to form a second filling layer 110 covering the mask layer 33. Figure 11 As shown;
[0082] A third photoresist layer 112 is formed on the second filling layer 110, as shown in FIG. Figure 11 As shown;
[0083] The third photoresist layer 112 is etched along the mask pattern 21 in the flipped mask plate 20 to form a third window 120 in the third photoresist layer 112. Figure 12 As shown;
[0084] The mask layer 33 is etched along the third window 120 to form a second etched pattern 140 in the mask layer 33. Figure 14 shown.
[0085] In some embodiments, the specific steps of etching the mask layer 33 along the third window 120 to form the second etched pattern 140 in the mask layer 33 include:
[0086] A third sidewall 130 is formed to cover the sidewall of the third window 120. Figure 13 As shown;
[0087] The mask layer 33 is etched along the third window 120 covered with the third sidewall 130 to form the second etched pattern 140 in the mask layer 33. Figure 14 shown.
[0088] For example, a spin coating process may be used to form the second filling layer 110 that fills the third etched pattern 100 and covers the remaining top surface of the mask layer 33, as shown in FIG. Figure 11 Next, a hard mask material such as silicon nitride or silicon oxynitride is deposited on the second filling layer 110 to form a fourth covering layer 111, and the third photoresist layer 112 is formed on the fourth covering layer 111. The schematic diagram of the mask plate 20 after horizontal flipping is shown as follows: Figure 11 The third photoresist layer 112 is etched along the mask pattern 21 in the horizontally flipped mask plate 20 to form the third window 120 penetrating the third photoresist layer 112 along the third direction D3 in the third photoresist layer 112. Figure 12 As shown, Figure 12 (b) is a schematic top view of the semiconductor structure after the third window 120 is formed. Figure 12 (a) in Figure 12 (b) is a cross-sectional view at position AA. Next, an atomic layer deposition process may be used to deposit oxide (e.g., silicon dioxide) on the inner wall of the third window 120 (including the sidewalls of the third window 120 and the bottom wall of the third window 120) and the third sidewall 130 on the top surface of the remaining third photoresist layer 112, as shown in FIG. Figure 13 As shown, Figure 13 (b) is a schematic top view of the semiconductor structure after the third spacer 130 is formed. Figure 13 (a) in Figure 13(b) is a cross-sectional view at position BB in FIG. A dry etching process can then be used to remove the third spacer 130 covering the bottom wall of the third window 120 and the top surface of the third photoresist layer 112, leaving only the third spacer 130 covering the sidewalls of the third window 120. This further reduces the width of the third window 120 (e.g., the width of the third window 120 along the first direction D1), thereby further reducing the size of the subsequently formed active area 210. Next, the fourth covering layer 111, the second filling layer 110, the first filling layer 70 and the mask layer 33 are etched downward along the third window 120 whose sidewall is covered with the third spacer 130, and the second etching pattern 140 penetrating the mask layer 33 along the third direction D3 is formed in the mask layer 33. The remaining first filling layer 70 and the second filling layer 110 are used together as a backfill layer 141. After removing the third photoresist layer 112 and the fourth covering layer 111, the following is obtained. Figure 14 The structure shown, wherein Figure 14 (b) is a schematic top view of the semiconductor structure after the second etching pattern 140 is formed. Figure 14 (a) in Figure 14 (b) Schematic diagram of the cross section at the BB position.
[0089] In some embodiments, after forming the second etch pattern 140 in the mask layer 33, the following steps are further included:
[0090] The mask plate 20 is translated along the first direction D1, and the mask layer 33 is etched along the mask pattern 21 in the translated mask plate 20 to form a fourth etching pattern 180 in the mask layer 33. Figure 18 shown.
[0091] For example, the first etching pattern 60, the third etching pattern 100 and the second etching pattern 140 are backfilled again to form a third filling layer 150. A fifth covering layer 151 and a fourth photoresist layer 152 are sequentially formed on the third filling layer 150. Figure 15 Then, the mask plate 20 is translated along the first direction D1. The schematic diagram of the mask plate 20 after translation is as shown in FIG. Figure 15 The fourth photoresist layer 152 is etched along the mask pattern 21 in the mask plate 20 after translation, and a fourth window 160 is formed in the fourth photoresist layer 152 along the third direction D3 and through the fourth photoresist layer 152, as shown in FIG. Figure 16 As shown, Figure 16 (b) is a schematic top view of the semiconductor structure after the fourth window 160 is formed. Figure 16 (a) in Figure 16 (b) is a cross-sectional view at position BB. Afterwards, a fourth sidewall 170 is formed to cover the inner wall of the fourth window 160 and the top surface of the remaining fourth photoresist layer 152, as shown in FIG. Figure 17 As shown, Figure 17 (b) is a schematic top view of the semiconductor structure after the fourth sidewall spacer 170 is formed. Figure 17 (a) in Figure 17 (b) is a cross-sectional view at position BB. After removing the fourth sidewall spacer 170 covering the top surface of the fourth photoresist layer 152 and the bottom wall of the fourth window 160, the fifth covering layer 151, the third filling layer 150, the backfill layer 141 and the mask layer 33 are etched along the fourth window 160 to form a fourth etched pattern 180 that penetrates the mask layer 33 along the third direction D3, wherein: Figure 18 (b) is a schematic top view of the semiconductor structure after forming the fourth etching pattern 180. Figure 18 (a) in Figure 18 (b) Schematic diagram of the cross section at the BB position.
[0092] In some embodiments, the specific steps of etching the substrate 30 along the first etch pattern 60 and the second etch pattern 140 to form a plurality of active regions 210 in the substrate 30 include:
[0093] The substrate 30 is etched along the first etch pattern 60, the second etch pattern 140, the third etch pattern 100 and the fourth etch pattern 180 to form a plurality of active regions 210 in the substrate 30. Figure 21 shown.
[0094] Specifically, during the process of forming the mask plate 20, the size and spacing of the mask pattern 21 in the mask plate 20 can be adjusted as needed, thereby adjusting the size of the active area 210 finally obtained. For example, the spacing L3 between two adjacent mask patterns 21 along the first direction D1 is 80nm, the staggered width L2 between two adjacent steps 211 in the mask pattern 21 is 40nm, the distance L1 between two opposite steps in two adjacent mask patterns 21 along the fourth direction (the fourth direction is perpendicular to the first direction D1) is 140nm, and the distance L4 between two adjacent steps in two adjacent mask patterns 21 along the first direction D1 is 40nm; the first etching pattern 60, the second etching pattern 140, the third etching pattern 100 and the fourth etching pattern 180 separate the mask layer 33 into a plurality of sub-masks 200 (such as Figure 20 (as shown), the length H1 of the sub-mask 200 along the fourth direction is 120 nm, and the distance H2 between two adjacent sub-masks 200 along the fourth direction is 40 nm. A plurality of the sub-masks 200 form a plurality of mask rows arranged along the fourth direction. Each mask row includes a plurality of sub-masks 200 spaced apart along the first direction D1, and the sub-masks 200 in two adjacent mask rows are staggered. The distance D2 between two adjacent sub-masks 200 in the same mask row is 60 nm, and the distance D3 between adjacent sub-masks 200 in two adjacent mask rows along the first direction D1 is 20 nm. The above dimensions L1, L2, L3, and L4 are for illustrative purposes only, and those skilled in the art may adjust them according to actual needs, for example, according to the size and arrangement density of the active area to be ultimately formed. In other examples, under the premise that the size and spacing distance (including specific values of L1, L2, L3 and L4) of the mask pattern 21 in the mask template 20 are fixed, the size and arrangement density of the active area to be finally formed can also be adjusted by adjusting the thickness of any one or more of the first side wall 50, the second side wall 90, the third side wall 130, and the fourth side wall 170.
[0095] Some embodiments of this specific embodiment provide a method for forming a semiconductor structure, by forming a mask plate including a plurality of mask patterns arranged at intervals along a first direction, and the mask pattern including a plurality of steps arranged along a second direction, the first direction and the second direction are obliquely intersected, so that the first etching pattern and the second etching pattern can be formed in the mask layer by flipping the mask plate, and the first etching pattern and the second etching pattern are used together as mask patterns to etch the substrate to form an active area, thereby reducing the number of mask plates, reducing the manufacturing cost of the semiconductor structure, and improving the manufacturing efficiency of the semiconductor structure, simplifying the manufacturing process of the semiconductor structure, and improving the performance of the semiconductor structure.
[0096] The above is only a preferred embodiment of the present disclosure. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principles of the present disclosure. These improvements and modifications should also be regarded as within the scope of protection of the present disclosure.
Claims
1. A method for forming a semiconductor structure, characterized in that: The steps include: Providing a mask plate, wherein the mask plate includes a plurality of mask patterns arranged at intervals along a first direction, the mask patterns include a plurality of steps arranged along a second direction, and the first direction and the second direction obliquely intersect; forming a mask layer on the top surface of the substrate; placing the mask plate above the mask layer and etching the mask layer along the mask pattern to form a first etching pattern in the mask layer; Turning over the mask plate to adjust the relative position between the mask pattern and the mask layer; Etching the mask layer along the mask pattern in the flipped mask plate to form a second etched pattern in the mask layer; The substrate is etched along the first etch pattern and the second etch pattern to form a plurality of active regions in the substrate.
2. The method for forming a semiconductor structure according to claim 1, wherein: The widths of the multiple steps in the mask pattern along the first direction are the same, and two adjacent steps in the mask pattern along the second direction are partially staggered along the first direction.
3. The method for forming a semiconductor structure according to claim 1, wherein: The specific steps of forming a first etching pattern in the mask layer include: forming a first photoresist layer above the mask layer; placing the mask plate above the mask layer, and etching the first photoresist layer along the mask pattern to form a first window in the first photoresist layer; The mask layer is etched along the first window to form the first etched pattern in the mask layer.
4. The method for forming a semiconductor structure according to claim 1, wherein: Before flipping the mask, the following steps are also included: translating the mask plate along the first direction to adjust the relative position between the mask pattern and the mask layer; The mask layer is etched along the mask pattern in the shifted mask plate to form a third etched pattern in the mask layer.
5. The method for forming a semiconductor structure according to claim 4, wherein: The specific steps of etching the mask layer along the mask pattern in the translated mask plate to form a third etching pattern in the mask layer include: backfilling the first etching pattern to form a first filling layer covering the mask layer; forming a second photoresist layer on the first filling layer; Etching the second photoresist layer along the mask pattern in the translated mask plate to form a second window in the second photoresist layer; The mask layer is etched along the second window to form the third etched pattern in the mask layer.
6. The method for forming a semiconductor structure according to claim 5, wherein: The specific steps of etching the mask layer along the second window to form the third etched pattern in the mask layer include: forming a second sidewall covering the sidewall of the second window; The mask layer is etched along the second window covered with the second sidewall to form the third etched pattern in the mask layer.
7. The method for forming a semiconductor structure according to claim 4, wherein: The specific steps of etching the mask layer along the mask pattern in the flipped mask plate to form a second etching pattern in the mask layer include: backfilling the third etch pattern to form a second filling layer covering the mask layer; forming a third photoresist layer on the second filling layer; Etching the third photoresist layer along the mask pattern in the flipped mask plate to form a third window in the third photoresist layer; The mask layer is etched along the third window to form a second etched pattern in the mask layer.
8. The method for forming a semiconductor structure according to claim 7, wherein: The specific steps of etching the mask layer along the third window to form a second etched pattern in the mask layer include: forming a third sidewall spacer covering the sidewall of the third window; The mask layer is etched along the third window covered with the third sidewall spacer to form the second etched pattern in the mask layer.
9. The method for forming a semiconductor structure according to claim 7, wherein: After forming the second etching pattern in the mask layer, the method further includes the following steps: The mask plate is translated along the first direction, and the mask layer is etched along the mask pattern in the translated mask plate to form a fourth etched pattern in the mask layer.
10. The method for forming a semiconductor structure according to claim 9, wherein: The specific steps of etching the substrate along the first etching pattern and the second etching pattern to form a plurality of active areas in the substrate include: The substrate is etched along the first etch pattern, the second etch pattern, the third etch pattern, and the fourth etch pattern to form a plurality of active regions in the substrate.
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