An impedance self-matching three-channel cable fault detection system

Abstract

The application discloses a kind of impedance self-matching three-channel cable fault detection systems, the impedance of each phase of three-phase cable is directly measured by impedance measurement module, when carrying out fault test, according to the impedance of each phase measured, initiative adjustment control module is carried out to reach the expected isolation effect, avoid repeated measurement, improve the accuracy and efficiency of three-phase cable fault test;Channel of three-channel switching module is controlled using FPGA, so that SSTDR signal in analog signal can be transmitted to corresponding cable phase in turn, and the reflection signal of corresponding phase is transmitted to host computer for related processing, realize one-time acquisition of three-phase cable fault detection information, the whole process does not need manual intervention, so as to improve the fault detection efficiency of three-phase cable;The cross-correlation result of each phase is used as a reference to each other, so as to judge the fault information of each phase, which can effectively reduce the misjudgment rate of cable fault information.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of three-phase cable fault detection, and particularly relates to a three-channel cable fault detection system with impedance self-matching. BACKGROUND

[0002] With the expansion of the city scale and the development of urbanization construction in China, underground laid cables are widely replaced by overhead cables due to the advantages of not occupying ground space, improving the urban environment and high power supply reliability. However, since the cables are laid underground, they have poor visibility, and it is difficult to quickly and effectively find the fault position of the underground laid cables once a fault occurs.

[0003] At present, the methods for cable fault positioning at home and abroad mainly include impedance method (bridge method), traveling wave method, acoustic magnetic method and reflection method. The reflection method is widely used, and the spread spectrum time domain reflectometry (SSTDR) has good signal noise immunity and positioning accuracy, and has developed rapidly. However, the existing SSTDR equipment can only detect the fault of a single-phase cable at a time, and cannot simultaneously detect the fault of a three-phase cable. For impedance self-matching of an isolator, some scholars use resistance scanning to determine the matching resistance, detect the received signal by changing the matching resistance from small to large, calculate the leakage of the interference signal power of the isolator, and the best matching resistance is when the power leakage is the least. Since the input impedance of the cable is affected by many factors such as frequency and length, resistance scanning is required for each detection, and a lot of repeated calculations are performed, which reduces the detection efficiency.

[0004] In summary, the existing SSTDR fault detection equipment has the following problems: each detection can only detect the fault of a single-phase cable at a time, if the fault of a three-phase cable needs to be detected, the cable phase connected by the equipment needs to be manually switched, which is not automated, reduces the fault detection efficiency of the three-phase cable, and the best matching resistance is obtained by a large number of repeated calculations through resistance scanning, which increases the fault detection time and reduces the fault detection efficiency. SUMMARY

[0005] In order to solve the above problems in the prior art, the application provides a three-channel cable fault detection system with impedance self-matching. The technical problems to be solved by the application are solved by the following technical scheme:

[0006] The application provides a three-channel cable fault detection system with impedance self-matching, which comprises an upper computer, an FPGA, a digital-to-analog conversion module, a control module, a three-channel switching module, an impedance measurement module, a reflection input module, a signal processing module and an analog-to-digital conversion module.

[0007] The host computer is configured to control the FPGA to output a corresponding digital signal.

[0008] The digital-to-analog conversion module is configured to output an SSTDR signal or a sine signal according to the digital signal.

[0009] The control module is configured to, under the control of the FPGA, cause the detection system to work in a fault detection mode or an impedance measurement mode, and transmit the SSTDR signal or the sine signal to the three-channel switching module.

[0010] The three-channel switching module is configured to, in the impedance measurement mode, switch the cable phase corresponding to the impedance measurement module to achieve measurement of the impedance of each cable phase by the impedance measurement module; and in the fault detection mode, sequentially transmit the SSTDR signal to each cable phase to output a reflection signal of the corresponding phase.

[0011] The control module is further configured to, in the fault detection mode, send the reflection signal to the reflection input module and avoid interference between the reflection signal and the SSTDR signal output by the control module.

[0012] The reflection input module is configured to, in the fault detection mode, amplify the reflection signal.

[0013] The signal processing module is configured to, in the impedance measurement mode, process voltage signals of two points of each phase of the cable corresponding to the impedance measurement module and output processed signals.

[0014] The analog-to-digital conversion module is configured to, in the fault detection mode, output reflection signal conversion data according to the amplified reflection signal; and in the impedance measurement mode, output impedance measurement conversion data according to the processed signals.

[0015] The FPGA is configured to store the reflection signal conversion data and the impedance measurement conversion data and send them to the host computer.

[0016] The host computer is further configured to, in the impedance measurement mode, obtain impedances of each phase of the cable by using a preset program based on the impedance measurement conversion data and store the impedances; in the fault detection mode, adjust the impedance of the impedance matching network in the control module based on the stored impedances; and obtain a fault detection result of the cable based on the reflection signal conversion data corresponding to each phase and a reference signal corresponding to the host computer.

[0017] In an embodiment of the present application, the process in which the host computer controls the FPGA to output a corresponding digital signal includes:

[0018] The host computer outputs a control frame.

[0019] The FPGA outputs a corresponding digital signal according to the control frame.

[0020] The control frame comprises a three-phase impedance measurement control frame or a three-phase fault detection frame.

[0021] The three-phase impedance measurement control frame comprises:

[0022] a frame header, a system working mode, a signal frequency and a frame tail.

[0023] The three-phase fault detection frame comprises:

[0024] a frame header, a system working mode, a signal frequency, impedance matching network control information of A / B / C three-phase impedance and a frame tail.

[0025] In an embodiment of the present application, the process that the digital-to-analog conversion module outputs an SSTDR signal or a sinusoidal signal according to the digital signal comprises:

[0026] The FPGA outputs a corresponding digital signal according to the three-phase impedance measurement control frame, and the digital-to-analog conversion module outputs the sinusoidal signal according to the received digital signal.

[0027] The FPGA outputs a corresponding digital signal according to the three-phase fault detection frame, and the digital-to-analog conversion module outputs the SSTDR signal according to the received digital signal.

[0028] In an embodiment of the present application, the control module comprises:

[0029] a relay S1, a relay S2 and an isolator; wherein,

[0030] The moving contact of the relay S1 is connected with the digital-to-analog conversion module, the first stationary contact is connected with the impedance measurement module, and the second stationary contact is connected with the isolator.

[0031] The moving contact of the relay S2 is connected with the three-channel switching module, the first stationary contact is connected with the impedance measurement module, and the second stationary contact is connected with the isolator.

[0032] The isolator is connected with the reflected input module.

[0033] In an embodiment of the present application, the process that the control module controls the detection system to work in a fault detection mode or an impedance measurement mode comprises:

[0034] The relay S1 and the relay S2 are switched to the impedance measurement module, so that the detection system works in the impedance measurement mode.

[0035] The relays S1 and S2 are switched to the isolator, so that the detection system works in a fault detection mode;

[0036] The isolator is used to separate the SSTDR signal and the reflected signal output by the control module, so as to avoid interference between the SSTDR signal and the reflected signal output by the control module.

[0037] In an embodiment of the present application, the impedance matching network comprises:

[0038] Eight single-pole single-throw normally open signal relays and a plurality of resistors;

[0039] For each single-pole single-throw normally open signal relay, the single-pole single-throw normally open signal relay and the resistor constitute a parallel module;

[0040] Each parallel module is connected in series between the remaining resistors.

[0041] In an embodiment of the present application, the three-channel switching module comprises:

[0042] Channel A double-pole double-throw signal relay, channel B double-pole double-throw signal relay and channel C double-pole double-throw signal relay; wherein,

[0043] The moving contacts of each channel double-pole double-throw signal relay are connected to a common terminal and are connected to the moving contacts of the relay S2, and a group of stationary contacts of each channel double-pole double-throw signal relay is connected to the corresponding cable.

[0044] In an embodiment of the present application, the impedance measurement module is composed of an automatic balancing bridge.

[0045] In an embodiment of the present application, the process of adjusting the impedance of the impedance matching network in the control module based on the stored impedance by the upper computer comprises:

[0046] The upper computer controls the FPGA to adjust the impedance of the impedance matching network in the control module to match the impedance of the corresponding phase of the cable based on the stored impedance of each phase of the cable.

[0047] In an embodiment of the present application, the fault detection result of the cable is obtained based on the corresponding reflection signal conversion data of each phase and the corresponding reference signal of the upper computer, comprising:

[0048] The cross-correlation calculation is performed on the corresponding reflection signal conversion data of each phase and the reference signal of the corresponding frequency of the upper computer to obtain the time delay of each phase.

[0049] The fault distance of each phase is obtained based on the corresponding time delay and the propagation speed of the SSTDR signal in the cable by using a preset formula.

[0050] The fault information of each phase is obtained according to the fault distances of all phases as the fault detection result of the cable.

[0051] The present application has the following advantages:

[0052] In the scheme, the impedance of each phase of the three-phase cable is directly measured by the impedance measurement module, and when the fault test is performed, the control module is actively adjusted according to the measured impedance of each phase to achieve the expected isolation effect, thereby avoiding repeated measurement and improving the accuracy and efficiency of the three-phase cable fault test; the pass of the three-channel switching module is controlled by the FPGA, so that the SSTDR signal can be transmitted to the corresponding cable phase in turn, and the reflection signal of the corresponding phase is transmitted to the upper computer for related processing, so that the three-phase fault detection information of the cable is obtained at one time, and the whole process does not need manual intervention, thereby improving the fault detection efficiency of the three-phase cable; the cross-correlation results of each phase are used as a reference to each other, so that the fault information of each phase is judged, and the misjudgment rate of the cable fault information can be effectively reduced. BRIEF DESCRIPTION OF DRAWINGS

[0053] Figure 1 A schematic diagram of an impedance self-matching three-channel cable fault detection system provided by an embodiment of the present application;

[0054] Figure 2 A structural schematic diagram of an impedance self-matching three-channel cable fault detection system provided by an embodiment of the present application;

[0055] Figure 3 A structural schematic diagram of an impedance matching network in a control module provided by an embodiment of the present application;

[0056] Figure 4 A structural schematic diagram of a three-channel switching module provided by an embodiment of the present application;

[0057] Figure 5 A structural schematic diagram of an impedance measurement module provided by an embodiment of the present application;

[0058] Figure 6 A flowchart of an impedance measurement mode provided by an embodiment of the present application;

[0059] Figure 7 A flowchart of a fault detection mode provided by an embodiment of the present application.

[0060] REFERENCE NUMERALS

[0061] 1-upper computer, 2-FPGA, 3-digital-to-analog conversion module, 4-control module, 5-three-channel switching module, 6-impedance measurement module, 7-reflection input module, 8-signal processing module, 9-analog-to-digital conversion module. DETAILED DESCRIPTION

[0062] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings of the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of the present application.

[0063] The embodiments of the present application provide a three-channel cable fault detection system with impedance self-matching, which can include: Figure 1

[0064] The host computer 1, the FPGA 2, the digital-to-analog conversion module 3, the control module 4, the three-channel switching module 5, the impedance measurement module 6, the reflection input module 7, the signal processing module 8, and the analog-to-digital conversion module 9; wherein,

[0065] The host computer 1 is configured to control the FPGA 2 to output a corresponding digital signal.

[0066] The digital-to-analog conversion module 3 is configured to output an SSTDR signal or a sine signal according to the digital signal.

[0067] The control module 4 is configured to control the detection system to work in a fault detection mode or an impedance measurement mode, and transmit the SSTDR signal or the sine signal to the three-channel switching module 5.

[0068] The three-channel switching module 5 is configured to switch the cable phase corresponding to the impedance measurement module 6 to realize impedance measurement of each cable phase by the impedance measurement module 6 in the impedance measurement mode, and transmit the SSTDR signal to each cable phase in sequence to output a reflection signal of a corresponding phase in the fault detection mode.

[0069] The control module 4 is further configured to send the reflection signal to the reflection input module 7 and avoid interference between the reflection signal and the SSTDR signal output by the control module 4 in the fault detection mode.

[0070] The reflection input module 7 is configured to amplify the reflection signal in the fault detection mode.

[0071] The signal processing module 8 is configured to process voltage signals of two points of each phase of the cable corresponding to the impedance measurement module 6 and output a processed signal in the impedance measurement mode.

[0072] The analog-to-digital conversion module 9 is configured to output reflection signal conversion data according to the amplified reflection signal in the fault detection mode, and output impedance measurement conversion data according to the processed signal in the impedance measurement mode.

[0073] ​FPGA2, used for storing the reflection signal conversion data and the impedance measurement conversion data, and sending to the host computer 1;

[0074] The host computer 1 is further used for obtaining the impedance of each phase of the cable based on the impedance measurement conversion data by using a preset program and storing in the impedance measurement mode, adjusting the impedance of the impedance matching network in the control module 4 based on the stored impedance in the fault detection mode, and obtaining the fault detection result of the cable based on the reflection signal conversion data corresponding to each phase and the reference signal corresponding to the host computer 1.

[0075] The embodiment of the present application directly measures the impedance of each phase of the three-phase cable through the impedance measurement module 6, actively adjusts the control module 4 according to the measured impedance of each phase when performing fault testing, so as to achieve the best isolation effect and avoid repeated measurement, and improves the accuracy and efficiency of the three-phase cable fault testing; the FPGA 2 is used for controlling the channel of the three-channel switching module 5, so that the amplified SSTDR signal can be transmitted to the corresponding cable phase in turn, and the reflection signal of the corresponding phase is transmitted to the host computer 1 for related processing, so as to realize one-time acquisition of the fault detection information of all three phases of the cable, and the whole process does not need manual intervention, thereby improving the fault detection efficiency of the three-phase cable.

[0076] The structural diagram of the three-channel cable fault detection system provided by the embodiment of the present application is shown in Figure 2 In order to facilitate understanding, the following will be introduced in combination with Figure 2 The various modules of the three-channel cable fault detection system proposed by the embodiment of the present application will be introduced respectively.

[0077] The host computer

[0078] The host computer 1 can output a control frame; in the impedance measurement mode, the impedance of each phase of the cable is obtained based on the impedance measurement conversion data by using a preset program and stored; in the fault detection mode, the impedance of the impedance matching network in the control module 4 is adjusted based on the stored impedance; and the fault detection result of the cable is obtained based on the reflection signal conversion data corresponding to each phase and the reference signal corresponding to the host computer 1. Among them,

[0079] The process that the host computer 1 adjusts the impedance of the impedance matching network in the control module 4 based on the stored impedance can include:

[0080] The host computer 1 controls the FPGA 2 to adjust the impedance of the impedance matching network in the control module 4 to match the impedance of the corresponding cable phase based on the stored impedance of each phase of the cable. It can be understood that the impedance of the impedance matching network matches the impedance of the corresponding cable phase, which can include that the impedance of the two is equal or close.

[0081] Based on each corresponding reflection signal conversion data and the reference signal corresponding to the host computer 1, the fault detection result of the cable can be obtained, which can include:

[0082] The cross-correlation calculation is performed on each corresponding reflection signal conversion data and the reference signal corresponding to the frequency of the host computer 1, and the time delay of each phase is obtained.

[0083] Based on each corresponding time delay and the propagation speed of the SSTDR signal in the cable, the fault distance of each phase is obtained by using a preset formula; wherein the preset formula is as follows:

[0084]

[0085] It can be understood that in the preset formula, d represents the fault distance, v represents the propagation speed of the SSTDR signal in the cable, and t represents the time delay corresponding to each phase; based on the preset formula, the corresponding fault distance can be obtained.

[0086] According to the fault distance of all phases, the fault information of each phase is obtained as the fault detection result of the cable.

[0087] The three-channel cable fault detection system proposed in the embodiment of the application uses the cross-correlation results of each phase as a reference to each other, thereby judging the fault information of each phase, which can effectively reduce the misjudgment rate of the cable fault information.

[0088] Specifically, the process of the host computer 1 controlling the FPGA 2 to output the corresponding digital signal can include:

[0089] The host computer 1 outputs a control frame;

[0090] The FPGA 2 outputs the corresponding digital signal according to the control frame; wherein,

[0091] The control frame can include a three-phase impedance measurement control frame or a three-phase fault detection frame;

[0092] The three-phase impedance measurement control frame can include:

[0093] Frame header, system working mode, signal frequency and frame tail;

[0094] The format of the three-phase impedance measurement control frame can be:

[0095] Frame header 1 byte, system working mode and signal frequency 1 byte, wherein the highest bit of the byte represents the system working mode, and the remaining bits represent the signal frequency, frame tail 1 byte.

[0096] The three-phase fault detection frame can include:

[0097] Frame header, system working mode, signal frequency, A / B / C three-phase impedance matching network control information and frame tail.

[0098] The format of the three-phase fault detection frame can be:

[0099] 1 byte of frame header, 1 byte of system operation mode and signal frequency, 1 byte of A-phase impedance, 1 byte of B-phase impedance, 1 byte of C-phase impedance, and 1 byte of frame tail.

[0100] It can be understood that the host computer 1 can select a Linux host computer, which can specifically select a freescale i.MX6D processor core board and its peripheral circuit to constitute. The processor runs a Linux system, and the running frequency of the processor is as high as 1.2 GHz, which can meet the demand of operation. The Qt program for cable fault positioning can run on the Linux host computer to realize sending the control frame to the FPGA, receiving and processing the two kinds of signal data received by the FPGA, and displaying the fault detection result of the cable on the screen.

[0101] FPGA

[0102] The FPGA 2 is used to output corresponding digital signals according to the control frame, and store the reflection signal conversion data or impedance measurement conversion data and send them to the host computer 1.

[0103] Six FIFOs with a depth of 1024 can be created in the FPGA 2 to accept two-point voltage signals for measuring the impedances of the A / B / C three-phase cables, and three FIFOs with a depth of 2048 can be created to receive the corresponding reflection signals from the A / B / C three-phase cables respectively.

[0104] The FPGA can be selected from the Intel Cyclone 10LP series 10CL040YU484I7G. This FPGA provides a rich standard of pin I / O and a large number of pins, which can meet the requirements of design connection. The internal clock of this FPGA is as high as 450 MHz, which can quickly receive and process the required data. The host computer and the FPGA communicate through a serial port. It can be understood that FIFO (First-In-First-Out) in FPGA (Field-Programmable Gate Array) usually refers to a cache or buffer structure, which plays a role in buffering, storing and managing data flow in data transmission. FIFO can effectively solve common problems in data transmission, such as data being too fast or too slow, data interface mismatch, data concurrency problem, etc.

[0105] In FPGA design, FIFO usually has the following key characteristics:

[0106] Data Storage: FIFOs can store a certain amount of data, providing a buffer for data flow when needed, preventing data loss or blocking of data transmission.

[0107] Sequential Access: FIFOs follow the First-In-First-Out principle, meaning that the data that enters the FIFO first will be taken out first.

[0108] Configurability: In FPGAs, parameters such as the size, depth (amount of stored data), and read-write speed of FIFOs can be configured to adapt to different data processing needs.

[0109] Asynchronous and Synchronous Operations: FIFOs can support asynchronous and synchronous read-write operations, often having multiple read-write ports that allow simultaneous reading from multiple sources or writing to multiple destinations.

[0110] Error Detection and Recovery: Advanced FIFOs may also include error detection and recovery mechanisms to ensure data accuracy and integrity.

[0111] The benefits of using FIFOs in FPGA design are as follows:

[0112] Simplify Data Flow Management: FIFOs can simplify the management and control of complex data flows, reducing the complexity of hardware design.

[0113] Improve Performance: Through data buffering, FIFOs can help optimize data processing processes and improve overall system performance.

[0114] Enhance Flexibility: By configuring FIFO parameters, designers can adjust data processing strategies according to specific application needs.

[0115] Digital-to-Analog Conversion Module

[0116] As shown in Figure 2 , the digital-to-analog conversion module 3 can include a digital-to-analog converter DAC and an amplification sub-module; wherein,

[0117] The digital-to-analog converter DAC is used to convert the received digital signal into a corresponding analog signal; the amplification sub-module is used to amplify and output the received analog signal. When the detection system works in the fault detection mode, the analog signal is the SSTDR signal, and in the impedance measurement mode, the analog signal is the sine signal.

[0118] Specifically, the analog signal can include: a sine signal or an SSTDR signal.

[0119] The process of the digital-to-analog conversion module outputting the SSTDR signal or the sine signal according to the digital signal includes:

[0120] The FPGA 2 outputs corresponding digital signals according to the three-phase impedance measurement control frame, and the digital-to-analog conversion module 3 outputs a sinusoidal signal according to the received digital signals.

[0121] The FPGA 2 outputs corresponding digital signals according to the three-phase fault detection frame, and the digital-to-analog conversion module 3 outputs an SSTDR signal according to the received digital signals.

[0122] It can be understood that the SSTDR signal can be a signal generated by modulating a PN sequence with a sinusoidal wave. In the fault detection mode, the signal is used as a test signal for the detection system, and the test signal has a white noise characteristic with a mean value of zero, thereby having good anti-noise ability.

[0123] The control module

[0124] The control module 4 is configured to control the detection system to work in the fault detection mode or the impedance measurement mode under the control of the FPGA 2, and transmit the SSTDR signal or the sinusoidal signal to the three-channel switching module 5.

[0125] As shown in Figure 2 , the control module 4 can include:

[0126] The relay S1, the relay S2 and the isolator; wherein,

[0127] The moving contact of the relay S1 is connected with the digital-to-analog conversion module 3, the first stationary contact is connected with the impedance measurement module 6, and the second stationary contact is connected with the isolator;

[0128] The moving contact of the relay S2 is connected with the three-channel switching module 5, the first stationary contact is connected with the impedance measurement module 6, and the second stationary contact is connected with the isolator;

[0129] The isolator is connected with the reflected input module 7.

[0130] Specifically, the working process of the control module 4 for controlling the detection system to work in the fault detection mode or the impedance measurement mode can include:

[0131] The relays S1 and S2 are switched to the impedance measurement module 6, so that the detection system works in the impedance measurement mode;

[0132] The relays S1 and S2 are switched to the isolator, so that the detection system works in the fault detection mode;

[0133] The isolator is configured to separate the SSTDR signal and the reflected signal output by the control module 4, so as to avoid interference between the SSTDR signal and the reflected signal output by the control module 4. The isolator can include an impedance matching network; wherein,

[0134] The impedance matching network, as Figure 3As shown, can include:

[0135] eight single-pole single-throw normally open signal relays and a plurality of resistors;

[0136] For each single-pole single-throw normally open signal relay, the single-pole single-throw normally open signal relay and the resistor constitute a parallel module.

[0137] Each parallel module is connected in series between the rest of the resistors.

[0138] The resistance range of each resistor in the impedance matching network can be [20Ω, 100.08Ω]. Each signal relay in the impedance matching network is controlled by 1 pin of FPGA 2, so the impedance matching network needs FPGA 2 to provide 8 pin controls, and the control signals of the 8 pins can exactly constitute 1 byte of data. After the host computer 1 calculates the impedance of the corresponding cable phase, 3 bytes of impedance network control information corresponding to A / B / C three cable phases can be added on the subsequent three-phase fault detection frame.

[0139] Three-channel switching module

[0140] The three-channel switching module 5 is used to switch the cable phase corresponding to the impedance measurement module 6 in the impedance measurement mode, so as to realize the measurement of the impedance of each cable phase by the impedance measurement module 6; in the fault detection mode, the SSTDR signal is transmitted to each cable phase in turn, and the reflection signal of the corresponding phase is output.

[0141] Specifically, the three-channel switching module 5, as shown in Figure 4 can include:

[0142] Channel A double-pole double-throw signal relay, channel B double-pole double-throw signal relay and channel C double-pole double-throw signal relay; wherein,

[0143] The moving contacts of each channel double-pole double-throw signal relay are connected to a common terminal and are connected to the moving contact of the relay S2, and one group of static contacts of each channel double-pole double-throw signal relay is connected to the corresponding cable phase.

[0144] It can be understood that one set of static contacts of each channel double-pole double-throw signal relay is connected with three phases of the cable in turn, and the other set of static contacts is not connected with any phase, at this time, each channel double-pole double-throw signal relay can be regarded as a double-pole single-throw relay, when the relay switches to the side connected with the phase of the cable, it is regarded as closed, otherwise, it is regarded as open. All the signal relays proposed in the embodiment of the application are controlled by the pins of the FPGA 2 one by one, the action time of all the signal relays, that is, the time required from the start of the coil power supply to the time when all the contacts reach the working state, can be 3 ms, the release time, that is, the time required from the start of the coil power supply to the time when all the contacts reach the reset state, can be 3 ms, and the switch jitter time can be 5 ms.

[0145] Impedance measurement module

[0146] The impedance measurement module 6 is used for measuring the impedance of the cable phase switched by the three-channel switching module 5.

[0147] Specifically, as shown in Figure 5 The impedance measurement module 6 is composed of an automatic balancing bridge.

[0148] In the specific measurement, only the voltage amplitude ratio and the phase difference of the m and n points are known, the unknown impedance can be calculated by using the first formula, and the expression of the first formula is as follows:

[0149] Among them,

[0150] Z X represents the unknown impedance, u m represents the voltage signal of the m point, which includes the amplitude and phase information of the m point, u n represents the voltage signal of the n point, which includes the amplitude and phase information of the n point, and R1 represents the resistance value of the standard resistance.

[0151] Reflection input module

[0152] The reflection input module 7 is used for amplifying the reflection signal in the fault detection mode, and sending the amplified reflection signal to the analog-digital conversion module 9.

[0153] Signal processing module

[0154] The signal processing module 8 is used for processing the voltage signals of the m and n points of each phase of the cable corresponding to the impedance measurement module 6 in the impedance measurement mode, and outputting the processed signals.

[0155] Specifically, the signal processing module 8 can include:

[0156] A first point signal processing sub-module and a second point signal processing sub-module.

[0157] The first point signal processing sub-module is configured to process the voltage signal of the n points, and the second point signal processing sub-module is configured to process the voltage signal of the m points.

[0158] Analog-to-digital conversion module

[0159] The analog-to-digital conversion module 9 is configured to, in the fault detection mode, enter the single-channel mode, perform analog-to-digital conversion on the amplified reflected signal, and output reflected signal conversion data; and in the impedance measurement mode, enter the double-channel mode, perform analog-to-digital conversion on the processed signal, and output impedance measurement conversion data.

[0160] Specifically, the analog-to-digital conversion module 9 can include an analog-to-digital converter ADC.

[0161] The ADC can be HMCAD1511, which has four input channels to receive data, can adjust the function through SPI communication, and has three working modes, namely, the single-channel mode, the double-channel mode and the four-channel mode. The embodiment of the present application can only select the first two working modes, the single-channel mode is to collect data of a selected input channel, and the double-channel mode is to collect data of two selected input channels at the same time, which can meet the requirement of the embodiment of the present application for collecting two kinds of data.

[0162] The converted conversion result is processed by the FPGA 2 and the host computer 1, and then the fault detection result of the cable is output.

[0163] In order to facilitate understanding, the two working modes of the three-channel cable fault detection system proposed in the embodiment of the present application will be introduced in detail below.

[0164] The working process of the detection system in the impedance measurement mode is shown in FIG. 4, and the specific impedance measurement steps are as follows: Figure 6

[0165] The FPGA 2 controls the relays S1 and S2 to switch to the impedance measurement module 6 under the command of the host computer 1, so that the detection system enters the impedance measurement mode, the FPGA 2 controls the digital-to-analog conversion module 3 to generate continuous sine signals of corresponding frequencies, and controls the analog-to-digital conversion module 9 to work in the double-channel mode.

[0166] The FPGA 2 controls the A-phase cable corresponding channel A double-pole double-throw signal relay to close, and after T1 which is the sum of the maximum action time and the maximum jitter time of the relay, the voltage data of the m and n points corresponding to the A phase are acquired, the FIFO in the FPGA 2 starts to receive the corresponding data, and when the FIFO is full, the writing of data is stopped, and the data is transmitted to the host computer 1 through the serial port.

[0167] ​When the channel A double-pole double-throw signal relay corresponding to the A-phase cable starts to close for a fixed time T2, the channel B double-pole double-throw signal relay corresponding to the B-phase closes, and after more than time T3, the voltage data of the m and n points corresponding to the B-phase are acquired, the FIFO starts to receive the corresponding data, and when the FIFO is full, the writing of data is stopped, and the data is transmitted to the host computer 1 through the serial port; wherein T3 can be the larger one of the sum of the maximum release time and the maximum jitter time of the channel A double-pole double-throw signal relay and the sum of the maximum action time and the maximum jitter time of the channel B double-pole double-throw signal relay.

[0168] The voltage data processing process of the m and n points corresponding to the C-phase is the same as that of the A-phase and the B-phase, and during the process, after the host computer 1 receives the data corresponding to each phase, the program in the host computer 1 starts to calculate the impedance corresponding to the phase, and stores the impedance corresponding to each phase for subsequent three-fault detection links;

[0169] When the channel C double-pole double-throw signal relay corresponding to the C-phase cable closes for a fixed time T2, that is, after the data acquisition of all phases is completed, the FPGA 2 controls all the relays in the three-channel switching module 5 to be opened to complete the impedance measurement process.

[0170] The working process of the detection system in the fault detection mode is as shown in Figure 7 The specific fault detection steps are as follows:

[0171] Under the command of the host computer 1, the FPGA 2 controls the relays S1 and S2 to switch to the isolator, so that the detection system enters the fault detection mode, the FPGA 2 controls the digital-to-analog conversion module 3 to generate continuous SSTDR signals with a corresponding frequency, and controls the analog-to-digital conversion module 9 to work in a single-channel mode;

[0172] The FPGA 2 controls the channel A double-pole double-throw signal relay corresponding to the A-phase cable to close, and adjusts the impedance matching network in the isolator to match the measured A-phase impedance, and after T1, the reflection data of the A-phase are acquired, the FIFO starts to receive the corresponding data, and when the FIFO is full, the writing of data is stopped, and the data is transmitted to the host computer 1 through the serial port;

[0173] When the channel A double-pole double-throw signal relay corresponding to the A-phase cable starts to close for a fixed time T2, the channel B double-pole double-throw signal relay corresponding to the B-phase closes, and adjusts the impedance matching network in the isolator to match the measured B-phase impedance, and after more than time T3, the reflection data of the B-phase are acquired, the FIFO starts to receive the corresponding data, and when the FIFO is full, the writing of data is stopped, and the data is transmitted to the host computer 1 through the serial port;

[0174] The C-phase reflection data processing process is same as the A-phase and B-phase processing processes, during which the host computer 1 performs cross-correlation calculation with the reference signal of the corresponding frequency stored in the host computer 1 after receiving the data of each phase, to obtain the corresponding time delay, and obtain the fault distance of each phase based on the time delay of each phase and the propagation speed of the SSTDR signal in the cable by using a preset formula; the fault information of each phase is obtained according to the fault distances of all phases as the fault detection result of the cable, and the corresponding fault detection result can be drawn according to the fault distances of each phase by using a preset drawing program and displayed on the screen; wherein, the preset program can be selected according to the specific type of the host computer, for example, the host computer is a Linux host computer, and the cable fault positioning program is Qt program, and the preset drawing program can be QCustomPlot.

[0175] When the channel C double-pole double-throw signal relay of the C-phase cable is closed for a fixed time T2, the data acquisition of all phases is completed, and the FPGA 2 controls all the relays in the three-channel switching module 5 to be opened to complete the fault detection process.

[0176] It can be understood that the values of T1 and T3 can be obtained by the user according to the corresponding relays, and T2 can be selected by the user according to the requirements of the two working modes, in an embodiment of the present application, the detection system can take 10 ms greater than T1, 20 ms equal to T2, and 10 ms greater than T3 as the processing time corresponding to each processing process when the detection system is in the impedance measurement mode and the fault detection mode.

[0177] It can be understood that when the selected host computer is not Linux but another type of host computer, the selected cable fault positioning program and the preset drawing program will also change accordingly.

[0178] The three-channel cable fault detection system provided in the embodiment of the present application directly measures the impedance of each phase of the three-phase cable through the impedance measurement module, actively adjusts the control module according to the measured impedance of each phase when performing fault testing, to achieve the expected isolation effect and avoid repeated measurement, thereby improving the accuracy and efficiency of the three-phase cable fault testing; the FPGA controls the path of the three-channel switching module, so that the SSTDR signal can be transmitted to the corresponding cable phase in turn, and the reflection signal of the corresponding phase is transmitted to the host computer for related processing, to realize one-time acquisition of all the fault detection information of the three-phase cable, and the whole process does not need manual intervention, thereby improving the fault detection efficiency of the three-phase cable; the cross-correlation results of each phase are used as references to each other, to determine the fault information of each phase, which can effectively reduce the misjudgment rate of the cable fault information.

[0179] It should be noted that in the description of the present application, it should be understood that the terms "first", "second" are only used for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can be explicitly or implicitly included one or more of the features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise specifically limited.

[0180] The above only describes the preferred embodiments of the present application, and is not used to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. An impedance self-matching three-channel cable fault detection system, characterized by, The device comprises an upper computer (1), an FPGA (2), a digital-to-analog conversion module (3), a control module (4), a three-channel switching module (5), an impedance measurement module (6), a reflected input module (7), a signal processing module (8) and an analog-to-digital conversion module (9); wherein, the upper computer (1) is configured to control the FPGA (2) to output a corresponding digital signal; the digital-to-analog conversion module (3) is configured to output an SSTDR signal or a sine signal according to the digital signal; the control module (4) is configured to, under the control of the FPGA (2), make the detection system work in a fault detection mode or an impedance measurement mode, and transmit the SSTDR signal or the sine signal to the three-channel switching module (5); the three-channel switching module (5) is configured to, in the impedance measurement mode, switch the cable phase corresponding to the impedance measurement module (6) to realize the measurement of the impedance of each cable phase by the impedance measurement module (6); and in the fault detection mode, sequentially transmit the SSTDR signal to each cable phase to output a reflected signal of the corresponding phase; the control module (4) is further configured to, in the fault detection mode, send the reflected signal to the reflected input module (7) and avoid interference between the reflected signal and the SSTDR signal output by the control module (4); the reflected input module (7) is configured to amplify the reflected signal in the fault detection mode; the signal processing module (8) is configured to, in the impedance measurement mode, process the voltage signals of two points of each phase of the cable corresponding to the impedance measurement module (6) and output a processed signal; the analog-to-digital conversion module (9) is configured to, in the fault detection mode, output reflected signal conversion data according to the amplified reflected signal; and in the impedance measurement mode, output impedance measurement conversion data according to the processed signal; the FPGA (2) is configured to store the reflected signal conversion data and the impedance measurement conversion data and send them to the upper computer (1); the upper computer (1) is further configured to, in the impedance measurement mode, obtain the impedance of each phase of the cable by using a preset program based on the impedance measurement conversion data and store the impedance; in the fault detection mode, adjust the impedance of an impedance matching network in the control module (4) based on the stored impedance; and obtain a fault detection result of the cable based on the reflected signal conversion data corresponding to each phase and a reference signal corresponding to the upper computer (1). The process in which the upper computer (1) controls the FPGA (2) to output a corresponding digital signal comprises:

2. An impedance self-matching, three-channel cable fault detection system according to claim 1, wherein, the upper computer (1) outputs a control frame; the FPGA (2) outputs a corresponding digital signal according to the control frame; wherein, the control frame comprises a three-phase impedance measurement control frame or a three-phase fault detection frame; the three-phase impedance measurement control frame comprises: a frame header, a system working mode, a signal frequency and a frame tail; the three-phase fault detection frame comprises: a frame header, a system working mode, a signal frequency, impedance matching network control information of A / B / C three-phase impedance and a frame tail. ​ 3. An impedance self-matching, three-channel cable fault detection system according to claim 2, wherein, The process of outputting SSTDR signal or sinusoidal signal by the digital-to-analog conversion module according to the digital signal comprises: The FPGA (2) outputs corresponding digital signal according to the three-phase impedance measurement control frame, and the digital-to-analog conversion module (3) outputs the sinusoidal signal according to the received digital signal; The FPGA (2) outputs corresponding digital signal according to the three-phase fault detection frame, and the digital-to-analog conversion module (3) outputs the SSTDR signal according to the received digital signal.

4. The impedance self-matching, three-channel cable fault detection system of claim 1, wherein, The control module (4) comprises: The relay S1, the relay S2 and the isolator; wherein, The moving contact of the relay S1 is connected with the digital-to-analog conversion module (3), the first stationary contact is connected with the impedance measurement module (6), and the second stationary contact is connected with the isolator; The moving contact of the relay S2 is connected with the three-channel switching module (5), the first stationary contact is connected with the impedance measurement module (6), and the second stationary contact is connected with the isolator; The isolator is connected with the reflected input module (7).

5. An impedance self-matching, three-channel cable fault detection system according to claim 4, wherein, The process that the control module (4) controls the detection system to work in the fault detection mode or the impedance measurement mode comprises: The relay S1 and the relay S2 are switched to the impedance measurement module (6), so that the detection system works in the impedance measurement mode; The relay S1 and the relay S2 are switched to the isolator, so that the detection system works in the fault detection mode; The isolator is used for separating the SSTDR signal and the reflected signal output by the control module (4), so as to avoid the interference between the SSTDR signal and the reflected signal output by the control module (4).

6. An impedance self-matching, three-channel cable fault detection system according to claim 1, wherein, The impedance matching network comprises: Eight single-pole single-throw normally open signal relays and a plurality of resistors; For each single-pole single-throw normally open signal relay, the single-pole single-throw normally open signal relay and the resistor constitute a parallel module; Each parallel module is connected in series between the remaining resistors.

7. An impedance self-matching, three-channel cable fault detection system according to claim 4, wherein, The three-channel switching module (5) comprises: Channel A double-pole double-throw signal relay, channel B double-pole double-throw signal relay and channel C double-pole double-throw signal relay; wherein, The moving contacts of each channel double-pole double-throw signal relay are connected into a common terminal and are connected with the moving contact of the relay S2, and a group of stationary contacts of each channel double-pole double-throw signal relay is connected with the corresponding cable.

8. The impedance self-matching, three-channel cable fault detection system of claim 1, wherein, The impedance measurement module (6) is composed of an automatic balance bridge.

9. The impedance self-matching, three-channel cable fault detection system of claim 1, wherein, The process that the host computer (1) adjusts the impedance of the impedance matching network in the control module (4) based on the stored impedance comprises: The host computer (1) controls the FPGA (2) to adjust the impedance of the impedance matching network in the control module (4) to match the impedance of the corresponding cable phase based on the stored impedance of each phase of the cable.

10. The impedance self-matching, three-channel cable fault detection system of claim 1, wherein, The process of obtaining the fault detection result of the cable based on the corresponding reflection signal conversion data of each phase and the corresponding reference signal of the host computer (1) comprises: The corresponding reflection signal conversion data of each phase and the reference signal of the corresponding frequency of the host computer (1) are cross-correlated to obtain the time delay of each phase. The fault distance of each phase is obtained by using a preset formula based on the corresponding time delay and the propagation speed of the SSTDR signal in the cable. The fault information of each phase is obtained according to the fault distance of all phases, as the fault detection result of the cable.

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