A method for realizing voltage parallel switching based on FPGA

Abstract

The present invention belongs to the technical field of voltage paralleling switching, and particularly relates to a method for realizing voltage paralleling switching based on FPGA. An AD data configuration area, an SV received data configuration area, and a paralleling switching configuration area are set in a preset configuration register of the FPGA; and information of each area is configured in the configuration register of the FPGA; the FPGA is used to calculate and process the AD data and the SV received data respectively, and save the processed data to a preset data buffer area of the FPGA; the CPU monitors the status of the telecontrol signal data in real time and makes a status judgment, and the CPU updates the result of the logical judgment to a preset status register of the FPGA in real time; the FPGA selects corresponding transmission data as SV transmission data from the preset data buffer area of the FPGA according to the content of the status register and the configuration register. The present invention makes full use of FPGA resources and effectively reduces the operating load of the CPU.

Description

Technical Field

[0001] The present invention belongs to the technical field of voltage paralleling switching, and particularly relates to a method for realizing voltage paralleling switching based on FPGA. Background Art

[0002] Embedded intelligent devices in substations are core devices of the power system. Intelligent process layer devices such as merging units, integrated merging and intelligent units, and acquisition and execution units are core devices of intelligent substations and new-generation highly reliable substations, and are important units to ensure stable and reliable acquisition and control of data sources. Their functions of the original voltage paralleling switching device are realized by software to meet the requirements of real-time paralleling and switching of voltages.

[0003] The logic judgment of the voltage paralleling switching function is complex. Since the result of the device to complete the logic is reflected by converting the analog quantity data collected into the transmitted message of SV (Sampled Values), and the message is provided for protection and measurement and control devices to use, it is necessary to ensure the stability of the SV transmitted message interval, and the paralleling and switching processes are real-time, reliable, and have high data consistency.

[0004] Currently, the implementation of this function mainly relies on CPU software, and the participation of FPGA is relatively small. Due to the complexity of the entire judgment and processing process, it poses a great test to the real-time performance, stability, and reliability of the CPU operating system. When the device CPU is running at a high load, each sampling period requires the acquisition and processing of analog quantities and the framing and sending of SV, etc. The judgment logic of voltage paralleling and switching may lag, resulting in problems such as delayed sending of sampling messages, large dispersion, and even packet loss. Summary of the Invention

[0005] In order to overcome the problems in the prior art, the present invention proposes a method for realizing voltage paralleling switching based on FPGA.

[0006] The technical solution of the present invention to solve the above technical problems is as follows:

[0007] The present invention provides a method for realizing voltage paralleling switching based on FPGA, including the following steps:

[0008] Step 100: Set an AD data configuration area, an SV received data configuration area, and a paralleling switching configuration area in the FPGA; and configure the information of each area in the configuration register of the FPGA;

[0009] Step 200: The FPGA collects AD data and SV received data, uses the FPGA to calculate and process the AD data and SV received data, and saves the processed data to a preset data buffer area of the FPGA;

[0010] Step 300: The CPU monitors the status of the telecontrol signal data in real time, uses the binary judgment method for status judgment, and the CPU updates the result of the logical judgment to the status register preset in the FPGA in real time;

[0011] Step 400: The FPGA selects the corresponding transmission data as the SV transmission data from the data buffer preset in the FPGA according to the content of the status register and the configuration register.

[0012] Further, in the step 100, it includes: configuring the configuration register of the FPGA, including SV received data or AD data mapping and parallel switching mapping, where the low byte of the parallel switching mapping is used to identify the classification, and the high byte is used to represent the serial number of this data in this classification.

[0013] Further, in the step 100, it includes: judging whether the analog quantity is AD conventional data or SV received data:

[0014] Initialize the analog quantity parameters of the parallel switching module; check whether all the analog quantity parameters are repeated; if all the analog quantity parameters are repeated, the analog quantity data check fails; if all the analog quantity parameters are not repeated, check whether the number of data in each group is the same; if the number of data in each group is not the same, the analog quantity data check fails; if the number of data in each group is the same, check whether the data sources in each group are consistent, if not, the analog quantity data check fails; if the data sources in each group are consistent, detect the attribution of the data source; judge whether it is AD data, if it is AD data, the analog quantity data check is successful; if it is not AD data, check whether it is SV data, if so, the analog quantity data check is successful, if not, the analog quantity data check fails.

[0015] Further, in the step 200, after the FPGA acquires the AD data and the SV received data, time stamps are added to the AD data and the SV data.

[0016] Further, in the step 200, the FPGA performs calculation and processing on the SV received data, specifically including:

[0017] When the FPGA receives a message, it first parses whether it is an SV message. If so, it checks whether it is a subscribed message according to the destination MAC address, APPID, and SVID checksum in the SV received control block configuration information parsed during initialization, and directly discards the non-subscribed message;

[0018] While discarding the non-subscribed message, the FPGA also performs storm message detection to obtain the preliminarily screened message;

[0019] Based on the preliminarily screened message, it is compared with other configuration information in the control block. If the preliminarily screened message does not match the information in the control block, a configuration error alarm will be issued;

[0020] The FPGA uses the time stamp information recorded in the message to monitor whether the sampling interval is normal. If an abnormal sampling interval is detected, the FPGA will trigger the corresponding alarm.

[0021] If the FPGA does not receive a message within the preset time, it is determined that the communication link is interrupted, and a link interruption alarm is triggered.

[0022] After interpolation synchronization processing, if the FPGA detects the loss of one frame of SV message, the data of the lost frame is fitted based on the data of the previous and next frames for supplementation; if multiple frames of messages are lost, the FPGA will clear the data corresponding to the lost frames and mark their quality as invalid.

[0023] Further, in step 200, the FPGA is used to calculate and process the AD data, specifically including: performing interpolation synchronization processing on the AD data, and the interpolation synchronization processing is the Lagrange cubic interpolation algorithm implemented by the FPGA. The moment corresponding to the sampling point in the Lagrange cubic interpolation algorithm is the time stamp marked during sampling.

[0024] Further, in step 300, the binary judgment method is used for status judgment, specifically including:

[0025] Voltage paralleling is judged by the binary number formed by the handle state and the bus coupler position.

[0026] Voltage switching is judged by the binary number formed by the PT disconnecting switches.

[0027] Further, voltage paralleling in step 400 includes:

[0028] The FPGA receives the judgment result from the CPU, and the judgment result includes the paralleling relationship between the bus voltages and the voltages of the buses.

[0029] The FPGA analyzes the judgment result of the CPU.

[0030] The FPGA selects the corresponding bus voltage sampling data according to the parsed output state and fills it into the corresponding data area of the SV transmission message; if a certain bus is configured to output the voltage of another bus, the FPGA will read the sampling data of the voltage from the corresponding data cache.

[0031] Further, voltage switching in step 400 includes:

[0032] The FPGA receives the judgment result from the CPU, and the judgment result includes the SV cascade data switching method and the bus switching method.

[0033] The FPGA analyzes the judgment result of the CPU.

[0034] The FPGA selects the bus voltage sampling data from the data cache according to the parsed switching method; if the set A SV cascade data is selected and the I bus is selected, the FPGA will select the voltage sampling data of the I bus from the set A data cache.

[0035] Compared with the prior art, the present invention has the following technical effects:

[0036] The present invention can make full use of FPGA resources, effectively reduce the CPU operation load; the voltage paralleling switching logic judgment can reduce the judgment process through the binary judgment method; simplify the interaction process between the CPU and the FPGA, and reduce the probability of data interaction and transmission errors; the entire sampling process and the SV sending message framing process do not involve the CPU; improve the timeliness of the SV sending message and reduce the dispersion value. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions and advantages in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required to be used in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0038] Figure 1 It is a schematic flowchart of the present invention;

[0039] Figure 2 It is a schematic diagram of the basic parameters of the voltage paralleling switching module of the present invention;

[0040] Figure 3 It is a specific parameter configuration diagram of the voltage paralleling of the voltage paralleling block of the present invention;

[0041] Figure 4 It is a specific parameter configuration diagram of the voltage switching of the voltage switching block of the present invention;

[0042] Figure 5 It is a flowchart of the voltage paralleling switching analog quantity retrieval of the present invention;

[0043] Figure 6 It is a flowchart of the voltage paralleling switching configuration parsing of the present invention;

[0044] Figure 7 It is a flowchart of the AD and SV received data processing of the present invention;

[0045] Figure 8 It is a flowchart of the paralleling data processing of the present invention;

[0046] Figure 9 It is a flowchart of the switching data processing of the present invention. Detailed implementation manners

[0047] In order to further elaborate on the technical means and effects adopted by the present invention to achieve the intended invention purpose, the following, in conjunction with the accompanying drawings and preferred embodiments, details the specific implementation manners, structures, features and their effects of the technical solutions proposed according to the present invention. The specific features, structures or characteristics in one or more embodiments may be combined in any suitable form. Unless otherwise defined, all technical and scientific terms used in the present invention have the same meaning as commonly understood by those skilled in the technical field to which the present invention belongs.

[0048] In one embodiment of the present invention, referring to Figure 1 , a method for realizing voltage paralleling switching based on FPGA is provided, including the following steps:

[0049] Step 100: Set an AD data configuration area, an SV data configuration area and a paralleling switching configuration area in the FPGA. The SV data configuration area includes an SV transmission data configuration area and an SV reception data configuration area; and configure the information of each area in the configuration register of the FPGA;

[0050] Step 200: The FPGA acquires AD data and SV reception data, and respectively performs calculation and processing on the AD data and the SV reception data by using the FPGA, and saves the processed data to a preset data buffer area in the FPGA;

[0051] Step 300: The CPU monitors the status of the telecontrol signal data in real time, performs status judgment by using the binary judgment method, and the CPU updates the result of the logical judgment to a preset status register in the FPGA in real time;

[0052] Step 400: The FPGA selects corresponding transmission data as the SV transmission data from the preset data buffer area in the FPGA according to the content of the status register and the configuration register.

[0053] The following expands on each of the above steps in detail:

[0054] Step 100: Set an AD data configuration area, an SV data configuration area and a paralleling switching configuration area in the FPGA. The SV data configuration area includes an SV transmission data configuration area and an SV reception data configuration area; configure the configuration information of each area in the configuration register of the FPGA, which specifically includes the following sub-steps:

[0055] Step 110: Configure an SV reception control block and SV transmission control block information in the SV data configuration area of the configuration register of the FPGA, which specifically includes the following sub-steps:

[0056] Step 1101: Obtain and parse the CCD (Configured Circuit Description) file, identify and extract the configuration information related to SV received data and SV transmitted data.

[0057] The CCD file is the virtual circuit configuration file of the secondary equipment IED in the intelligent substation, which is used to define the configuration file for the IED (Intelligent Electronic Device) to subscribe to and publish GOOSE (Generic Object Oriented Substation Events) and SV (Sampled Value) information. It contains the address mapping relationship between the internal address of the virtual circuit and the external device, the communication parameter information of the control block, the virtual terminal receiving port information, and the virtual terminal description information. The CCD file can be exported from the IED configuration tool or management system of the intelligent substation.

[0058] Step 1102: Obtain the network card parameters of the SV receiving and transmitting ports.

[0059] The network card parameters of the SV receiving and transmitting ports can be obtained in two ways. One way is that the CCD file itself will carry the sending or receiving physical port (network card) information during configuration, which is relatively common and can be used directly. The other way is that the receiving and transmitting ports can be configured through a separate configuration file. This method is special and needs to be parsed according to the content of the configuration file.

[0060] Step 1103: When the CPU starts, based on the extracted configuration information related to SV receiving and SV transmitting and the network card parameters of the SV receiving and transmitting ports, form the FPGA configuration information of the SV receiving control block and the FPGA configuration information of the SV transmitting control block.

[0061] Table 1 FPGA Configuration Information Table of SV Receiving and Transmitting Control Blocks

[0062]

[0063] Both the network card configuration and the data virtual terminal configuration are in bit configuration method. Each bit represents a network port or a piece of data. This method can effectively reduce the use of FPGA configuration registers.

[0064] Step 120: Configure the setting parameters, analog data, and telemetry data of the voltage paralleling switching block in the parallel switching configuration area of the FPGA configuration register, determine the mapping relationship between the setting parameters, analog data, and telemetry data during voltage paralleling and voltage switching; and store the configuration information of the voltage paralleling switching block in the FPGA configuration register.

[0065] The voltage parallel switching block configuration information includes setting parameter configuration information, analog data configuration information and remote signaling data configuration information.

[0066] Reference Figure 2 , the parameter configuration information is set to define the basic operation mode and related parameters of the voltage parallel switching block, including the parallel switching function type, signal input method, signal input type and busbar switch position acquisition. These parameters determine the behavior of the voltage parallel switching block in different scenarios.

[0067] The voltage parallel switching block setting parameters are compatible with the configuration of signal input mode, signal input type and busbar switch position acquisition when configuring, that is, voltage parallel and switching use a configuration method to meet different scenarios of voltage parallel and switching. The combination of different configurations is different, and the basis for state judgment is also different. This method can only modify the set values ​​of signal input mode, input type and busbar switch position acquisition in the basic parameters, without modifying the configuration of analog quantity and remote signaling parameters, and the judgment basis can be switched.

[0068] The telesignaling data configuration information defines the telesignaling parameters used to determine the voltage parallel and switching status. The telesignaling parameters may include hard switching, GOOSE switching or handle switching, etc., which are used to indicate the status of the section switch.

[0069] Analog data uses configuration mapping method, which can extract the mapping configuration corresponding to the sampled data according to the voltage parallel switching block setting parameters, that is, classify and sort each sampled data in the voltage parallel switching block for data filling selection when SV framing is sent. Analog data can specifically include measured voltage, metering voltage, zero-sequence voltage, etc.

[0070] Reference Figure 3 , voltage parallel module voltage parallel specific parameter configuration content, this parameter configuration can simultaneously meet the two-section bus voltage parallel and three-section bus voltage parallel functions. When the two-section bus voltage is parallel, only the first two groups of analog quantities participate in the parallel, and the judgment basis is the remote signal (segment 1 related hard opening or GOOSE opening, I bus strong use II bus and II bus strong use I bus handle opening) status in the remote signal parameter that participates in the two-section bus voltage parallel, specifically: Segment 1 related hard opening or GOOSE opening indicates the remote signal signal of the bus section switch (usually segment 1) status. When the section switch is in the closed state, it means that the two sections of the bus can run in parallel; I bus strong use II bus and II bus strong use I bus handle opening, the handle opening signal is used to indicate that in specific circumstances, such as a bus failure or maintenance, the voltage of another bus is used.

[0071] When the three-section bus voltages are paralleled, all three sets of analog quantities are involved in the paralleling. The judgment basis is the status of the telecontrol signals involved in the three-section bus voltage paralleling in the telecontrol parameters (the hard inputs or GOOSE inputs related to section 1 and section 2, and all 4 handle inputs). Specifically: The hard inputs or GOOSE inputs related to section 1 and section 2: These telecontrol signals indicate the status of the bus sectional switches (section 1 and section 2). When sectional switch 1 is in the closed state, it means that the two buses of bus I and bus II can operate in parallel. When sectional switch 2 is in the closed state, it means that the two buses of bus II and bus III can operate in parallel; All 4 handle inputs (bus I forced to use bus II, bus II forced to use bus I, bus II forced to use bus III, and bus III forced to use bus II). The handle input signal is used to indicate that in specific situations, such as when a certain section of the bus fails or is under maintenance, the voltage of other sections of the bus is used.

[0072] Refer to Figure 4 , for the specific parameter configuration content of the voltage switching module for voltage switching. This parameter configuration can simultaneously meet the functions of voltage switching for two sections of buses and dual-redundant bus voltage switching. When switching the voltage of two sections of buses, only the first two sets of analog quantities are involved in the switching. The judgment basis is the status of the telecontrol signals involved in the voltage switching of two sections of buses in the telecontrol parameters (the hard inputs of the PT disconnect switches of bus I and bus II or the GOOSE inputs of set A, and the data abnormality of set A). Specifically: The hard inputs of the PT disconnect switches of the two sections of buses are the status of the disconnect switches of the on-site hard wiring. The GOOSE inputs of set A are the status of the PT disconnect switches in the GOOSE message when the hard-wired disconnect switch status is not used according to the on-site requirements; The voltage switching for two sections of buses is for the single-set bus data. By default, set A is used, and the output voltage is switched between the voltage of bus I and bus II according to the status of the disconnect switch; If it is detected that the position of the PT disconnect switch of a certain section of the bus changes or is abnormal, the automatic voltage switching logic for two sections of buses will be triggered to perform automatic voltage switching output for use by protection devices or measurement and control devices.

[0073] When switching the voltage of dual-redundant buses, all four sets of analog quantities are involved in the switching. The judgment basis is the status of the telecontrol signals involved in the voltage switching of dual-redundant buses in the telecontrol parameters (the hard inputs of the PT disconnect switches of bus I and bus II or the GOOSE inputs of sets A and B, all 3 handle inputs, and the data abnormality of sets A and B). Specifically: The hard inputs of the PT disconnect switches of bus I and bus II or the GOOSE inputs of sets A and B: Similarly, these signals are used as the judgment basis for automatic output voltage switching, but this time it is based on the dual-redundant configuration; The input status of all 3 handles represents a certain specific switching mode or condition; If data abnormality is detected in set A or set B of the system, the redundant switching logic may need to be triggered to ensure the continuity of voltage monitoring.

[0074] The analog quantity parameters of the voltage paralleling and switching block can retrieve whether the analog quantity participating in the judgment is AD conventional data or SV received data. The retrieval basis is as Figure 5 shown, specifically including:

[0075] Initialize the analog parameters of the parallel switching module; check whether all analog parameters are repeated; if all analog parameters are repeated, the analog data check fails; if all analog parameters are not repeated, check whether the number of data in each group is the same; if the number of data in each group is not the same, the analog data check fails; if the number of data in each group is the same, check whether the data sources in each group are consistent. If they are not consistent, the analog data check fails; if the data sources in each group are consistent, detect the attribution of the data source; determine whether it is AD data. If it is AD data, the analog data check is successful; if it is not AD data, check whether it is SV data. If it is, the analog data check is successful. If not, the analog data check fails.

[0076] Taking the parallel connection of the voltages of two common busbars (AD data) and the switching of the voltages of two busbars (SV data) as an example, the configuration flow chart is as Figure 6 .

[0077] For the voltage parallel connection scenario, the FPGA configuration table of the voltage parallel connection analog data includes the serial number of the AD data, the corresponding SV transmission data mapping configuration, and the parallel module sampling data mapping configuration. These data mapping configurations allow the FPGA to accurately process and transmit AD data as needed. The FPGA configuration content of the voltage parallel connection analog data is shown in Table 2:

[0078] Table 2 FPGA Configuration Table of Voltage Parallel Connection Analog Data

[0079] AD data serial number Corresponding SV transmission data mapping configuration Parallel module sampling data mapping configuration 0 8 bytes (representing 64 bits) Classification (I, II, III busbars) / sorting 1 8 bytes Classification / sorting …… …… …… n 8 bytes Classification / sorting

[0080] According to the content of the above table, the parallel data configuration register of the FPGA can be configured for each AD data, including the 8-byte transmission data mapping and the 2-byte parallel mapping. The low byte of the 2-byte parallel mapping is used to identify the classification: Bus I (0x77), Bus II (0x88), Bus III (0x99); the high byte is used to represent the serial number of this data in this classification.

[0081] The voltage parallel connection is default applied in the AD data scenario. This method is also applicable to the application scenario of parallel connection of SV received data. When configuring the analog parameters, select the SV received data as the analog quantity.

[0082] The FPGA configuration content of the voltage switching analog data is shown in Table 3:

[0083] Table 3 FPGA Configuration Table of Voltage Switching Analog Data

[0084]

[0085] For the voltage switching scenario, the FPGA configuration table (Table 3) contains the SV control block identifier, the SV received valid data sequence number, the corresponding SV transmitted data configuration, and the switching module sampled data mapping configuration. These data mapping configurations allow the FPGA to perform voltage switching operations based on the status of the SV received data.

[0086] According to the content of the above table, the switching data configuration register of the FPGA can be configured for each SV received data, including 8-byte transmitted data mapping and 2-byte switching mapping. The low byte of the 2-byte switching mapping is used to identify the classification: Bus I (0x33), Bus II (0x44); the high byte is used to represent the sequence number of this data in this classification.

[0087] When using dual-redundancy switching, there are two SV received control blocks corresponding to the switching of the I / II bus voltages of two sets. Therefore, the CPU will first perform the switching of sets A and B, and then perform the switching of the two bus voltages. The SV control block identifier in the above table is the flag to distinguish between sets A and B: Set A (0x55), Set B (0x66).

[0088] Voltage switching is default applied in the SV received data scenario. This method is also applicable to the application scenario of switching AD data. When configuring analog parameters, select the analog quantity as AD data.

[0089] The SV transmitted data mapping configuration uses the bit-by-bit processing method, that is, each data can correspond to the position of the SV transmitted data according to the configuration. This configuration can be modified according to the FPGA resources and actual needs. The advantage of the bit-by-bit processing method is that it can perform one-to-many filling processing of data. For example, the 8-byte transmitted configuration indicates that one data can be mapped and filled in up to 64 data positions.

[0090] Step 200: Use the FPGA to perform calculation and processing on the AD data and the SV received data respectively, and save the processed data to the data buffer, referring to Figure 7 .

[0091] The FPGA uses its parallel computing ability to perform complex calculations such as interpolation calculation and synchronization processing on the AD data and the SV received data respectively, specifically including:

[0092] Step 210: Use the FPGA to collect the AD data and the SV received data, and timestamp the AD data and the SV data.

[0093] The FPGA will perform timestamp processing when collecting the AD data and the SV received data. The timestamp is the local time, which is convenient for later interpolation and synchronization processing to synchronize the AD data and the SV received data to the local time.

[0094] Step 220: Parse the SV message, and check whether it is a subscription message according to the destination MAC address, APPID, and SVID checksum in the SV reception control block configuration information. Perform in-depth parsing and alarm processing on non-storm messages.

[0095] Since the entire SV reception processing is implemented in the FPGA, when the FPGA receives a message, it first parses whether it is an SV message, and then checks whether it is a subscription message according to the destination MAC address, APPID, and SVID checksum in the SV reception control block configuration information parsed during initialization. Non-subscription messages are directly discarded. At this time, storm message detection is also required, and non-storm messages are identified based on information such as the CRC of the message for subsequent processing.

[0096] For subscribed non-storm messages, the FPGA needs to perform in-depth parsing and compare other configuration information in the control block. If there is a mismatch, a configuration error alarm will be issued; the time stamps recorded between messages can be used to monitor whether the sampling interval is abnormal for alarms related to missing points and abnormal reception; if no message is received for a long time, a disconnection alarm will be issued; alarms such as out-of-step, maintenance, and invalidity are obtained by parsing the synchronization flag and data segment quality in the message.

[0097] After the FPGA performs interpolation synchronization processing, if it detects that a frame is lost during SV reception, it will re-fit the lost frame of data based on the data of the previous and subsequent frames for supplementation. If multiple frames of messages are lost, the data corresponding to the lost frames of messages needs to be cleared and marked as invalid in terms of quality.

[0098] Step 230: Perform interpolation synchronization processing on the AD data and cache the calculated data.

[0099] The interpolation synchronization processing is the Lagrange cubic interpolation algorithm implemented by the FPGA, and the time of the corresponding sampling points in the algorithm is the time stamp marked during sampling.

[0100] Step 300: The CPU monitors the status of the telecontrol signal in real time, uses the binary judgment method for status judgment, and the CPU updates the result of the logical judgment to the status register preset in the FPGA in real time.

[0101] That is: for voltage paralleling, it is judged by the binary number formed by the handle state and the bus coupler position; for voltage switching, it is judged by the binary number formed by the I-bus PT disconnecting switch and the II-bus PT disconnecting switch.

[0102] (1) For voltage paralleling, it is judged by the binary number formed by the handle state and the bus coupler position:

[0103] The handle state, such as the handle input signal of "using II-bus when I-bus is strong" or "using I-bus when II-bus is strong";

[0104] Mother connection position: Refers to the position status of the bus connection switch (usually called the mother connection switch), which determines whether two or more busbars can be operated in parallel.

[0105] When the CPU receives these telecontrol signal data, it combines these data into a binary number. For example, if there are two handle states (each state can be open or closed, i.e., 0 or 1) and a mother connection position state (which can be 00, 01, 10, or 11), then a 4-bit binary number can be combined, and this binary number can be used to uniquely identify the current voltage parallel state.

[0106] (2) Voltage switching is judged by using the binary number formed by the combination of the isolating switch of the I-bus PT and the isolating switch of the II-bus PT:

[0107] Isolating switch of the I-bus PT and isolating switch of the II-bus PT: Refers to the isolating switch states of the potential transformers (PTs) on the I-bus and the II-bus. The isolating switch is used to isolate or connect the PT from the busbar for maintenance or switching operations.

[0108] The CPU receives the telecontrol signal data of the isolating switch and combines them into a binary number. For example, if each isolating switch has four states (00, 01, 10, or 11), then a 4-bit binary number can be combined to represent the current voltage switching state.

[0109] The advantage of the binary judgment method is that it can reduce the operation process and judgment times of each data, and increase the readability of logical judgment. This method is also applicable to more complex three-busbar voltage parallel logic and functions such as seamless selection of double-set busbar voltage cascade access.

[0110] Step 400: The FPGA selects the corresponding transmission data as the SV transmission data from the preset data buffer area of the FPGA according to the content of the status register and the configuration register.

[0111] The FPGA can know the result of the logical judgment according to the value of the status register updated in real time by the CPU, and selects the corresponding data from the processed data buffer area to fill the transmission message data according to the result of the logical judgment and the sampling mapping relationship of the initialization configuration.

[0112] The FPGA presets a parallel status register and a switching status register, each of which is 4 bytes in size.

[0113] (1) The parallel function includes the voltage parallel of two busbars and the voltage parallel of three busbars, and its data processing flow is as Figure 8 .

[0114] The 4 bytes of the FPGA parallel status register represent the output of Bus I / output of Bus II / output of Bus III / reserved byte from high to low. For example, when the voltages of two buses are in parallel, if the value of the parallel status register is 0x77880000, it means the output values are: the output of Bus I is the voltage of Bus I, and the output of Bus II is the voltage of Bus II; if the value of the parallel status register is 0x77770000, it means the output values are: the output of Bus I is the voltage of Bus I, and the output of Bus II is the voltage of Bus I; and so on. When the voltages of three buses are in parallel, if the value of the parallel status register is 0x77889900, it means the output values are: the output of Bus I is the voltage of Bus I, the output of Bus II is the voltage of Bus II, and the output of Bus III is the voltage of Bus III; if the value of the parallel status register is 0x77779900, it means the output values are: the output of Bus I is the voltage of Bus I, the output of Bus II is the voltage of Bus I, and the output of Bus III is the voltage of Bus III; and so on.

[0115] The FPGA needs to fill the corresponding bus voltage sampling data into the corresponding data area of the SV transmission message according to the logical judgment result given by the CPU.

[0116] (2) The switching function includes the switching of the voltages of two buses and the dual-redundancy switching. The dual-redundancy switching adds the processing of seamless selection of dual cascading on the basis of the switching processing of the voltages of two buses. The data processing flow of the switching function is as Figure 9 .

[0117] The high 2 bytes of the FPGA switching status register represent the switching method of Set A / Set B (a value of 0 means single-set two-bus switching); the low 2 bytes represent the switching method of Bus I / Bus II. For example, when the value of the switching status register is 0x00000033, it means single-set two-bus switching, and the output value is the voltage of Bus I; when the value of the switching status register is 0x00550044, it means that Set A is used for dual-set switching, and the output value is the voltage of Bus II; and so on. Since the judgment result of the switching has data clearing processing and data clearing and quality invalidation processing, two additional states are added to the low 2 bytes of the switching: data clearing (0x11); data clearing and quality setting to invalid (0x22).

[0118] The FPGA needs to fill the bus voltage sampling data in the selected SV cascaded data as the output voltage data into the corresponding data area of the SV transmission message according to the logical judgment result given by the CPU.

[0119] The entire framing process of the SV transmitted message is independently carried out by the FPGA, without the participation of the CPU. The FPGA frames according to the control block information configured by the initialized CPU and the filled data area. In addition to the data participating in the parallel switching, AD data and SV received data that do not participate in this function can also be added to the message data area. The frame format of the SV transmitted message adopts the message format specified in DL / T860.92.

[0120] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included in the protection scope of the present invention.

Claims

1. A method for realizing voltage parallel switching based on FPGA, characterized in that: The following steps are involved: Step 100: setting an AD data configuration area, an SV receiving data configuration area, and a parallel switching configuration area in a configuration register preset in the FPGA; and configuring information of each area in the configuration register of the FPGA; Step 200: FPGA collects AD data and SV received data, uses FPGA to calculate and process the AD data and SV received data respectively, and saves the processed data to a data buffer area preset by FPGA; Step 300: The CPU monitors the state of the remote signaling data in real time and performs state judgment, and the CPU updates the result of the logic judgment to the state register preset by the FPGA in real time; Step 400: The FPGA selects corresponding transmission data as SV transmission data from a data buffer area preset in the FPGA according to the contents of the status register and the configuration register.

2. The method for realizing voltage parallel switching based on FPGA according to claim 1, characterized in that: The parallel switching configuration area in step 100 includes: a voltage parallel analog data FPGA configuration table, including the sequence number of AD data, the corresponding SV transmission data mapping configuration and the parallel module sampling data mapping configuration; The voltage switching analog data FPGA configuration table includes the SV control block identification, the SV receiving valid data sequence number, the corresponding SV sending data configuration, and the switching module sampling data mapping configuration.

3. The method for realizing voltage parallel switching based on FPGA according to claim 1, characterized in that: The step 100 includes: determining whether the analog quantity is AD conventional data or SV received data: Initialize the analog parameters of the parallel switching module; check whether all analog parameters are repeated; if all analog parameters are repeated, the analog data check fails; if all analog parameters are not repeated, check whether the number of data in each group is the same; if the number of data in each group is different, the analog data check fails; if the number of data in each group is the same, check whether the data sources in each group are consistent, if not, the analog data check fails; if the data sources in each group are consistent, check the data source; determine whether it is AD data, if it is AD data, the analog data check is successful; if it is not AD data, check whether it is SV data, if so, the analog data check is successful, if not, the analog data check fails.

4. The method for realizing voltage parallel switching based on FPGA according to claim 1, characterized in that: In step 200, after collecting AD data and SV receiving data using FPGA, the AD data and SV data are time-stamped.

5. The method for realizing voltage parallel switching based on FPGA according to claim 4, characterized in that: In step 200, the FPGA is used to calculate and process the SV received data, which specifically includes: When receiving a message, the FPGA first analyzes whether it is an SV message. If so, it checks whether it is a subscription message based on the destination MAC address, APPID, and SVID cumulative sum in the SV receiving control block configuration information analyzed during initialization. Non-subscription messages are directly discarded; While discarding non-subscription messages, the FPGA also performs storm message detection to obtain preliminary filtered messages; Based on the initially screened message, it is compared with other configuration information in the control block. If the initially screened message does not match the information in the control block, a configuration error alarm is issued; FPGA uses the time stamp information recorded in the message to monitor whether the sampling interval is normal. If an abnormal sampling interval is detected, FPGA will trigger a corresponding alarm; If the FPGA does not receive a message within the preset time, it will determine that the communication link is interrupted and trigger a link break alarm; After interpolation synchronization, if the FPGA detects that a frame of SV message is lost, the data of the lost frame will be fitted based on the data of the previous and next frames to supplement it; if multiple frames of messages are lost, the FPGA will clear the data corresponding to the lost frame and mark its quality as invalid.

6. The method for realizing voltage parallel switching based on FPGA according to claim 4, characterized in that: The use of FPGA to calculate and process AD data specifically includes: The AD data is subjected to interpolation synchronization processing, wherein the interpolation synchronization processing is a Lagrange cubic interpolation algorithm implemented by FPGA, and the time corresponding to the sampling point in the Lagrange cubic interpolation algorithm is the time stamp at the time of sampling.

7. The method for realizing voltage parallel switching based on FPGA according to claim 1, characterized in that: In step 300, a binary judgment method is used to judge the state, which specifically includes: Voltage paralleling is judged by a binary number formed by combining the handle status and the busbar position; Voltage switching is determined by the binary number formed by the PT isolation switch combination.

8. The method for realizing voltage parallel switching based on FPGA according to claim 1, characterized in that: The voltage paralleling in step 400 includes: The FPGA receives a logic judgment result from the CPU, wherein the judgment result includes a parallel relationship between bus voltages and a bus voltage; FPGA analyzes the logical judgment results of the CPU; The FPGA selects the corresponding bus voltage sampling data according to the parsed output status and fills it into the corresponding data area of ​​the SV send message; if a bus is configured to output the voltage of another bus, the FPGA will read the sampling data of the voltage from the corresponding data buffer area.

9. The method for realizing voltage parallel switching based on FPGA according to claim 1, characterized in that: The voltage switching in step 400 includes: The FPGA receives a logic judgment result from the CPU, wherein the judgment result includes an SV control block identifier and a bus switching mode; FPGA analyzes the logical judgment results of the CPU; FPGA selects bus voltage sampling data from the data cache according to the parsed switching mode; if A set of SV cascade data is selected and I bus is selected, FPGA will select I bus voltage sampling data from A set of data cache.

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