A multi-phase clock generation circuit and calibration method thereof

Abstract

The invention discloses a multi-phase clock generating circuit and a calibration method thereof, comprising a delay chain and a delay calibration circuit, wherein the delay calibration circuit is used for feedback control and calibration of the total delay time of the delay chain, and a delay chain with a total delay of 180 degrees of phase is formed by connecting multiple stages of the same variable delay units in series, each variable delay unit is connected to the same delay control signal VCTL, so the delay time of each delay unit is the same, each variable delay unit can output a clock signal with the same phase difference in turn, thereby obtaining a multi-phase clock signal with the same phase difference, and different numbers of multi-phase clock signals can be obtained by flexibly adjusting the number of the series-connected variable delay units, and the clock signal output by the variable delay unit can be extended to more clock phases after being inverted by an inverter; the total delay time of the 180-degree phase delay chain is precisely feedback-controlled and calibrated by the delay calibration circuit, thereby ensuring the accuracy of the phase difference between the multi-phase clock signals.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and in particular to a multi-phase clock generating circuit and a calibration method thereof. Background Art

[0002] Multi-phase clock signals are used in many fields, including 4-phase orthogonal local oscillator signals used in mixers in the field of RF wireless communications, multi-phase sampling clock signals in high-speed SerDes serial communications, 4-phase orthogonal phase interpolators used in clock data recovery circuits, and so on.

[0003] There are two traditional methods for generating orthogonal signals. One is to use a multi-phase filtering method to generate orthogonal signals, and the other is to use a two-frequency division method to generate orthogonal signals. The generation of multi-phase clock signals usually requires a phase interpolator to achieve this.

[0004] Figure 1 It is a structural diagram of a multi-phase filtering method for generating an orthogonal clock signal. The orthogonal signal generated by the multi-phase filtering method has the following disadvantages: the output orthogonal clock signal amplitudes are not equal, and the subsequent stage needs to be connected to a limiting amplifier to amplify the orthogonal clock signal to the maximum. If the bandwidth of the limiting amplifier is not enough, AM PM effects will be generated, resulting in signal phase deviation; at the same time, the bandwidth of the multi-phase filter is very narrow, and multiple multi-phase filters need to be cascaded to achieve broadband characteristics. Multi-stage cascading causes the clock signal amplitude to be greatly attenuated and the signal-to-noise ratio to deteriorate; and the phase accuracy of the orthogonal signal generated by the multi-phase filter is poor.

[0005] Figure 2 It is a traditional circuit structure diagram for generating orthogonal signals based on binary frequency division. Although it can generate accurate phase quadrature signals, its input signal frequency must be twice the output signal frequency. When the output frequency reaches GHz, generating a twice-frequency signal requires greater power consumption and higher cost.

[0006] The patent with publication number CN115208363A discloses a structure based on a variable delay circuit and a phase detection and calibration circuit, which can generate 4 orthogonal clock output signals from the input differential clock signal. Figure 3 As shown, the circuit structure calibrates the variable delay circuit through the control principle of negative feedback to produce an accurate 90-degree phase delay, thereby obtaining an orthogonal clock signal output. However, the circuit structure can only produce a 4-phase orthogonal clock signal, and cannot produce a 6-phase, 8-phase or more phase clock signal output. At the same time, the structure requires an input differential clock signal for orthogonal conversion, and cannot directly perform orthogonal conversion on a single-ended input clock signal.

[0007] Based on the shortcomings of the existing multi-phase clock generation circuit technology solutions, it is necessary to design a conversion circuit that can flexibly generate more clock phases and ensure the accuracy of multiple clock phases through phase calibration technology. Summary of the invention

[0008] The object of the present invention is to overcome the deficiencies of the prior art and to provide a multi-phase clock generating circuit and a calibration method thereof.

[0009] The objective of the present invention is achieved through the following technical solutions:

[0010] In a first aspect, the present invention provides a multi-phase clock generation circuit, including a delay chain and a delay calibration circuit, wherein the delay chain is composed of a plurality of identical variable delay units connected in series, the delay chain includes an input signal and an output signal, the total delay time of the input signal and the output signal is 180 degrees in phase, the variable delay unit is connected to the same delay control signal VCTL, and is used to output clock signals with the same phase difference, so as to obtain multi-phase clock signals with the same phase difference, and the variable delay unit can obtain multi-phase clock signals of different numbers by adjusting the number of series connections, and the clock signal output by the variable delay unit is phase-inverted by an inverter, so as to obtain more clock signals with complementary phases;

[0011] The delay calibration circuit is used for feedback control to calibrate the total delay time of the delay chain. The delay calibration circuit includes a phase detection module, an RC low-pass filter, an error amplifier and a calibration control circuit. The input end of the phase detection module is connected to the input signal and the output signal, the output end of the phase detection module is connected to the input end of the RC low-pass filter, the output end of the RC low-pass filter is connected to the input end of the error amplifier, the output end of the error amplifier is connected to the calibration control circuit, and the output end of the calibration control circuit is connected to the control port of the variable delay unit.

[0012] Based on the first aspect, the phase detection module adopts an SR latch structure, the SR latch includes a first NAND gate and a second NAND gate, the first NAND gate and the second NAND gate are cross-coupled, the input end of the first NAND gate is connected to the input signal, and the input end of the second NAND gate is connected to the output signal; the output end of the first NAND gate and the output end of the second NAND gate are respectively connected to the input end of the low-pass filter.

[0013] Preferably, the low-pass filter includes a first low-pass filter and a second low-pass filter, the input end of the first low-pass filter is connected to the output end of the first NAND gate, the input end of the second low-pass filter is connected to the output end of the second NAND gate, the first low-pass filter and the second low-pass filter respectively include a series resistor R and a capacitor C connected in parallel to the ground, the output end of the first low-pass filter is connected to the positive electrode of the error amplifier, and the output end of the second low-pass filter is connected to the negative electrode of the error amplifier.

[0014] In a second aspect, the present invention provides a calibration method for a multi-phase clock generating circuit, which is applied to any of the multi-phase clock generating circuits described above, comprising:

[0015] The input signal is input to the first NAND gate of the SR latch for outputting the signal Q1, and the output signal is input to the second NAND gate of the SR latch for outputting the signal Q2; when the phase delay time is less than the phase of 180 degrees, the high level pulse time of the Q1 signal output by the phase detection module is less than the high level pulse time of the Q2 signal; when the phase delay time is greater than the phase of 180 degrees, the high level pulse time of the Q1 signal output by the phase detection module is greater than the high level pulse time of the Q2 signal; when the phase delay time is equal to the phase of 180 degrees, the high level pulse time of the Q1 signal output by the phase detection module is equal to the high level pulse time of the Q2 signal;

[0016] The Q1 signal and Q2 signal output by the phase detection module are respectively shaped and filtered by the low-pass filter circuit. The integration effect of the low-pass filter performs time-average filtering on the Q1 signal and the Q2 signal. According to the duration of the high-level pulses of the Q1 signal and the Q2 signal output by the phase detection module, analog voltage signals V1 and V2 of corresponding amplitudes are obtained, and the analog voltage signals V1 and V2 are input into the error amplifier.

[0017] The error amplifier compares the input signals V1 and V2 and outputs the error signal Error to the calibration control circuit. When the signal V1 is greater than the signal V2, the error amplifier outputs a high-level signal '1', indicating that the delay time is greater than the 180-degree phase; when the V1 signal is less than the V2 signal, the error amplifier outputs a low-level signal '0', indicating that the delay time is less than the 180-degree phase; when the V1 signal is equal to the V2 signal, the error amplifier outputs an intermediate-level signal '1 / 2', indicating that the delay time is equal to the 180-degree phase;

[0018] The calibration control circuit controls the size of the output signal VCTL according to the level of the input error signal Error. When Error is '0', it means that the delay time is less than 180 degrees of phase, the signal VCTL is reduced, and the delay time is increased; when Error is '1', it means that the delay time is greater than 180 degrees of phase, the signal VCTL is increased, and the delay time is reduced; when Error is '1 / 2', it means that the delay time is equal to 180 degrees of phase, and the size of the signal VCTL is maintained unchanged; the calibration control circuit controls all variable delay units to generate the same delay time through the output VCTL signal, which is used to ensure that the phase difference of the clock signal output by each level of variable delay unit is equal; through the negative feedback control of the delay calibration circuit, the delay time generated by the delay chain is finally equal to the 180-degree phase delay.

[0019] Based on the second aspect, according to the circuit structure of the variable delay unit, the VCTL signal includes an analog signal or a digital control signal.

[0020] The beneficial effects of the present invention are:

[0021] 1) The present invention forms a delay chain with a total delay of 180 degrees by connecting multiple stages of the same variable delay units in series. Since the delay time of each variable delay unit is the same, each variable delay unit can output a clock signal with the same phase difference in turn, thereby obtaining a multi-phase clock signal with the same phase difference.

[0022] 2) The present invention can obtain different numbers of multi-phase clock signals, such as 4-phase, 6-phase, 8-phase, etc., by flexibly adjusting the number of variable delay units connected in series.

[0023] 3) The total delay time of the 180-degree phase delay chain of the present invention is precisely controlled and calibrated by the calibration circuit, thereby ensuring the accuracy of the phase difference between the multi-phase clock signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 A structural diagram of an existing polyphase filtering method for generating orthogonal clock signals;

[0025] Figure 2 The structure diagram of a conventional circuit for generating orthogonal signals based on binary frequency division is shown;

[0026] Figure 3 It is a structural diagram of an existing circuit based on a variable delay circuit and a phase detection and calibration circuit;

[0027] Figure 4 is a structural block diagram of a multi-phase clock generating circuit according to an embodiment of the present invention;

[0028] Figure 5It is a signal timing waveform diagram of the multi-phase clock generating circuit of an embodiment of the present invention when the delay time generated by the 180-degree phase delay chain is less than the 180-degree phase;

[0029] Figure 6 It is a signal timing waveform diagram of the multi-phase clock generating circuit according to an embodiment of the present invention when the delay time generated by the 180-degree phase delay chain is greater than the 180-degree phase;

[0030] Figure 7 It is a signal timing waveform diagram of the multi-phase clock generating circuit according to an embodiment of the present invention when the delay time generated by the 180-degree phase delay chain is equal to the 180-degree phase;

[0031] Figure 8 1 is a structural diagram of a variable delay circuit according to an embodiment of the present invention, wherein (a) is a circuit diagram using an inverter and a variable capacitor; (b) is a circuit diagram in which the inverter operating voltage uses a VCTL voltage;

[0032] Fig. 9 1 is a diagram of a calibration control circuit structure according to an embodiment of the present invention, wherein (a) is a schematic diagram of an analog circuit control structure; and (b) is a schematic diagram of a digital circuit control structure. DETAILED DESCRIPTION

[0033] The technical solution of the present invention will be clearly and completely described below in conjunction with the embodiments. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0034] Exemplarily, the present invention provides a multi-phase clock generating circuit and a calibration method thereof, with the purpose of providing a conversion circuit capable of flexibly generating multi-phase clock signals and ensuring the accuracy of multiple clock phases through phase calibration technology.

[0035] For example, the structural block diagram of the multi-phase clock generating circuit provided by the present invention is as follows: Figure 4 As shown, a delay chain with a total delay of 180 degrees is formed by connecting multiple stages of the same variable delay units in series. Figure 4 The total delay time from the input signal CK0 to the output signal CK180 in is 180 degrees phase. Since each variable delay unit is connected to the same delay control signal VCTL, the delay time of each delay unit is the same, so each variable delay unit can output a clock signal with the same phase difference in turn, thereby obtaining a multi-phase clock signal with the same phase difference, such as Figure 4CK_1, CK_2, ..., CK_N, etc. shown in the figure; different numbers of multi-phase clock signals can be obtained by flexibly adjusting the number of variable delay units (N+1) connected in series, and the clock signal output by each variable delay unit can be expanded to more clock phases after being inverted by an inverter, such as 4 phases, 6 phases, 8 phases, etc.; the total delay time of the 180-degree phase delay chain is precisely feedback-controlled and calibrated by the delay calibration circuit, thereby ensuring the accuracy of the phase difference between the multi-phase clock signals.

[0036] Exemplarily, in the technical solution provided by the present invention, the 180-degree phase delay chain is composed of multiple stages of identical variable delay units connected in series, wherein a certain delay time is generated between the input signal and the output signal of the variable delay unit, and the length of the delay time is controlled by the control signal VCTL. When the VCTL signal increases, the delay time decreases, and when the VCTL signal decreases, the delay time increases; depending on the circuit structure of the variable delay unit, the VCTL signal can be an analog signal or a digital control signal; the delay control ports of all variable delay units are all connected to the same VCTL control signal to ensure that the delay time of all variable delay units is the same. The clock signal CK_N output by each variable delay unit can be phase-inverted by an inverter to obtain more phase-complementary clock signals.

[0037] Specifically, the delay calibration circuit in the technical solution provided by the present invention includes a phase detection module based on an SR latch (SR Latch), an RC low-pass filter, an error amplifier (EA), and a calibration control circuit which are sequentially connected in series. The delay calibration circuit is used for feedback control of the total delay time of the calibration delay chain. The delay calibration circuit includes a phase detection module, an RC low-pass filter, an error amplifier, and a calibration control circuit. The input end of the phase detection module is connected to the input signal and the output signal. The output end of the phase detection module is connected to the input end of the RC low-pass filter. The output end of the RC low-pass filter is connected to the input end of the error amplifier. The output end of the error amplifier is connected to the calibration control circuit. The output end of the calibration control circuit is connected to the control port of the variable delay unit. The phase detection module adopts an SR latch structure. The SR latch includes a first NAND gate and a second NAND gate. The first NAND gate and the second NAND gate are cross-coupled. The input end of the first NAND gate is connected to the input signal, and the input end of the second NAND gate is connected to the output signal. The output end of the first NAND gate and the output end of the second NAND gate are respectively connected to the input end of the low-pass filter. The low-pass filter includes a first low-pass filter and a second low-pass filter, the input end of the first low-pass filter is connected to the output end of the first NAND gate, the input end of the second low-pass filter is connected to the output end of the second NAND gate, the first low-pass filter and the second low-pass filter respectively include a series resistor R and a capacitor C connected in parallel to the ground, the output end of the first low-pass filter is connected to the positive electrode of the error amplifier, and the output end of the second low-pass filter is connected to the negative electrode of the error amplifier.

[0038] Specifically, the phase detection module adopts an SR latch structure, such as Figure 4As shown, the SR latch is composed of two cross-coupled NAND gates; one input port of the SR latch is connected to the CK0 signal, and the other input port is connected to the CK180 signal; the NAND gate output port connected to the CK0 signal outputs the Q1 signal, and the NAND gate output port connected to the CK180 signal outputs the Q2 signal. When the phase delay time of the CK0 and CK180 clocks is less than 180 degrees, the high level pulse time of the Q1 signal output by the phase detection module is less than the high level pulse time of the Q2 signal; when the phase delay time of the CK0 and CK180 clocks is greater than 180 degrees, the high level pulse time of the Q1 signal output by the phase detection module is greater than the high level pulse time of the Q2 signal; when the phase delay time of the CK0 and CK180 clocks is exactly equal to 180 degrees, the high level pulse time of the Q1 signal output by the phase detection module is equal to the high level pulse time of the Q2 signal. The Q1 signal and Q2 signal output by the phase detection module are respectively shaped and filtered by a low-pass filter to obtain average output voltages V1 and V2. The analog voltage signals V1 and V2 output by the low-pass filter are respectively connected to the positive and negative ends of the error amplifier (EA), and the error amplifier (EA) outputs an error signal Error by comparing the magnitude of the input signals V1 and V2. The Error signal output by the error amplifier (EA) is connected to the input port of the calibration control circuit, and the calibration control circuit controls the magnitude of the output signal VCTL according to the level of the input Error signal; the VCTL control signal output by the calibration control circuit is connected to the control port of all variable delay units, and controls all variable delay units to generate the same delay time, ensuring that the phase difference of the clock signal output by each level of variable delay unit is equal. Through the negative feedback control of the delay calibration module, the delay time generated by the 180-degree phase delay chain can be gradually approached to 180 degrees, and finally equal to the 180-degree phase delay, thereby ensuring that the clock signals generated by the multi-phase clock generation circuit provided by the present invention have equal and accurate phase differences. The SR latch, RC low-pass filter and error amplifier (EA) are all very common circuits, and their circuit structures will not be explained in detail.

[0039] Exemplarily, the signal timing waveform of the multi-phase clock generating circuit when the delay time generated by the 180-degree phase delay chain is less than the 180-degree phase is as follows: Figure 5 As shown in FIG. 1 , when the phase delay time of the CK0 and CK180 clocks is less than the 180-degree phase, the high-level pulse time T1 of the Q1 signal output by the phase detection module is less than the high-level pulse time T2 of the Q2 signal, so the analog voltage V1 output by the low-pass filter is less than V2, and the Error signal output by the error amplifier (EA) is '0'; the signal timing waveform diagram of the multi-phase clock generation circuit when the delay time generated by the 180-degree phase delay chain is greater than the 180-degree phase is as shown in FIG. Figure 6 As shown in the figure, when the phase delay time of the CK0 and CK180 clocks is greater than the 180-degree phase, the high-level pulse time T1 of the Q1 signal output by the phase detection module is greater than the high-level pulse time T2 of the Q2 signal, so the analog voltage V1 output by the low-pass filter is greater than V2, and the Error signal output by the error amplifier (EA) is '1'; the signal timing waveform diagram of the multi-phase clock generation circuit when the delay time generated by the 180-degree phase delay chain is equal to the 180-degree phase is as shown in the figure Figure 7 As shown in the figure, when the phase delay time of the CK0 and CK180 clocks is exactly equal to the 180-degree phase, the high-level pulse time T1 of the Q1 signal output by the phase detection module is equal to the high-level pulse time T2 of the Q2 signal, so the analog voltage V1 output by the low-pass filter is equal to V2, and the Error signal output by the error amplifier (EA) is '1 / 2'. The calibration control circuit controls the size change of the output signal VCTL according to the level of the input Error signal to realize the automatic calibration process of the delay time.

[0040] Exemplarily, the present invention provides a multi-phase clock calibration method, comprising:

[0041] The input signal is input to the first NAND gate of the SR latch for outputting the signal Q1, and the output signal is input to the second NAND gate of the SR latch for outputting the signal Q2; when the phase delay time is less than the phase of 180 degrees, the high level pulse time of the Q1 signal output by the phase detection module is less than the high level pulse time of the Q2 signal; when the phase delay time is greater than the phase of 180 degrees, the high level pulse time of the Q1 signal output by the phase detection module is greater than the high level pulse time of the Q2 signal; when the phase delay time is equal to the phase of 180 degrees, the high level pulse time of the Q1 signal output by the phase detection module is equal to the high level pulse time of the Q2 signal;

[0042] The Q1 signal and Q2 signal output by the phase detection module are respectively shaped and filtered by the low-pass filter circuit. The integration effect of the low-pass filter performs time-average filtering on the Q1 signal and the Q2 signal. According to the duration of the high-level pulses of the Q1 signal and the Q2 signal output by the phase detection module, analog voltage signals V1 and V2 of corresponding amplitudes are obtained, and the analog voltage signals V1 and V2 are input into the error amplifier.

[0043] The error amplifier compares the input signals V1 and V2 and outputs the error signal Error to the calibration control circuit. When the signal V1 is greater than the signal V2, the error amplifier outputs a high-level signal '1', indicating that the delay time is greater than the 180-degree phase; when the V1 signal is less than the V2 signal, the error amplifier outputs a low-level signal '0', indicating that the delay time is less than the 180-degree phase; when the V1 signal is equal to the V2 signal, the error amplifier outputs an intermediate-level signal '1 / 2', indicating that the delay time is equal to the 180-degree phase;

[0044] The calibration control circuit controls the size of the output signal VCTL according to the level of the input error signal Error. When Error is '0', it means that the delay time is less than 180 degrees of phase, the signal VCTL is reduced, and the delay time is increased; when Error is '1', it means that the delay time is greater than 180 degrees of phase, the signal VCTL is increased, and the delay time is reduced; when Error is '1 / 2', it means that the delay time is equal to 180 degrees of phase, and the size of the signal VCTL is maintained unchanged; the calibration control circuit controls all variable delay units to generate the same delay time through the output VCTL signal, which is used to ensure that the phase difference of the clock signal output by each level of variable delay unit is equal; through the negative feedback control of the delay calibration circuit, the delay time generated by the delay chain is finally equal to the 180-degree phase delay.

[0045] Illustratively, one embodiment of the present invention adopts Figure 4 In the circuit structure shown, the input clock signal CK0 is connected to the input end of the variable delay unit 1, and multiple stages of the same variable delay units are connected in series to form a delay chain with a total delay of 180 degrees. The last stage of variable delay unit N+1 outputs a delay signal CK180; the delay control ports of all delay units are connected to the VCTL signal. Since the delay time of each variable delay unit is the same, each variable delay unit can output a clock signal with the same phase difference in turn, thereby obtaining a multi-phase clock signal with the same phase difference, such as Figure 4 CK_1, CK_2, ..., CK_N, etc. shown in the figure; by flexibly adjusting the number of variable delay units (N+1) connected in series, different numbers of multi-phase clock signals can be obtained, and the clock signal output by each variable delay unit can be expanded to more clock phases after being inverted by an inverter, such as 4 phases, 6 phases, 8 phases, etc.

[0046] Exemplarily, the variable delay unit circuit can be implemented by a variety of circuit structures. Figure 8Two schematic diagrams of variable delay circuit structures that can be used in the technical solution of the present invention are provided, wherein (a) is a circuit diagram that uses an inverter and a variable capacitor to achieve delay control, and the control signal VCTL adjusts the delay of the delay unit circuit by controlling the size of the variable capacitor; (b) is a circuit diagram that uses the VCTL voltage as the inverter working voltage in the circuit. By adjusting the VCTL voltage, the working voltage and driving capability of the inverter can be adjusted simultaneously, and the size of the load variable capacitor can also be adjusted synchronously, thereby expanding the delay control range.

[0047] Exemplarily, the calibration control circuit provided by the present invention can be implemented in a variety of ways, and can be implemented by using a pure analog circuit structure or a digital control logic circuit; Fig. 9 Two circuit structure diagrams of implementation methods are provided. Fig. 9 (a) is a schematic diagram of the analog circuit implementation structure. The Error signal output by the error amplifier is filtered by a large capacitor C to obtain an average voltage, which is then driven by a buffer to output a VCTL signal for controlling the variable delay unit. Fig. 9 (b) is a schematic diagram of the digital circuit implementation structure. At this time, the function of the error amplifier (EA) is to act as a comparator and output the comparison result Error logic signal. The Error logic signal is input to the bidirectional counter module for addition and subtraction counting operations. Driven by the clock Clock signal, the bidirectional counter module detects the level of the Error signal at the rising edge of each Clock signal. When the Error signal is '1', the bidirectional counter is controlled to add 1 to the output counting result. When the Error signal is '0', the bidirectional counter is controlled to subtract 1 from the output counting result. The bidirectional counter outputs a multi-bit counting result signal to the digital-to-analog converter circuit module (DAC), converting the counting result from a digital logic signal to an analog control voltage VCTL signal for controlling the variable delay unit.

[0048] The above is only a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the form disclosed herein, and should not be regarded as excluding other embodiments, but can be used in various other combinations, modifications and environments, and can be modified within the scope of the concept described herein through the above teachings or the technology or knowledge of the relevant field. The changes and modifications made by those skilled in the art shall not deviate from the spirit and scope of the present invention, and shall be within the scope of protection of the claims attached to the present invention.

Claims

1. A multi-phase clock generating circuit, characterized in that: It includes a delay chain and a delay calibration circuit. The delay chain is composed of multiple stages of variable delay units connected in series. The delay chain includes an input signal and an output signal. The total delay time of the input signal and the output signal is 180 degrees in phase. The variable delay unit is connected to the same delay control signal VCTL, and is used to output clock signals with the same phase difference to obtain multi-phase clock signals with the same phase difference. The variable delay unit can obtain different numbers of multi-phase clock signals by adjusting the number of series connections. The clock signal output by the variable delay unit is phase-inverted by an inverter to obtain more phase-complementary clock signals. The delay calibration circuit is used for feedback control to calibrate the total delay time of the delay chain. The delay calibration circuit includes a phase detection module, an RC low-pass filter, an error amplifier and a calibration control circuit. The input end of the phase detection module is connected to the input signal and the output signal, the output end of the phase detection module is connected to the input end of the RC low-pass filter, the output end of the RC low-pass filter is connected to the input end of the error amplifier, the output end of the error amplifier is connected to the calibration control circuit, and the output end of the calibration control circuit is connected to the control port of the variable delay unit.

2. The multi-phase clock generating circuit according to claim 1, characterized in that: The phase detection module adopts an SR latch structure, which includes a first NAND gate and a second NAND gate. The first NAND gate and the second NAND gate are cross-coupled, the input end of the first NAND gate is connected to the input signal, and the input end of the second NAND gate is connected to the output signal; the output end of the first NAND gate and the output end of the second NAND gate are respectively connected to the input end of the low-pass filter.

3. The multi-phase clock generating circuit according to claim 2, characterized in that: The low-pass filter includes a first low-pass filter and a second low-pass filter, the input end of the first low-pass filter is connected to the output end of the first NAND gate, the input end of the second low-pass filter is connected to the output end of the second NAND gate, the first low-pass filter and the second low-pass filter respectively include a series resistor R and a capacitor C connected in parallel to the ground, the output end of the first low-pass filter is connected to the positive electrode of the error amplifier, and the output end of the second low-pass filter is connected to the negative electrode of the error amplifier.

4. A calibration method for a multi-phase clock generating circuit, applied to the multi-phase clock generating circuit according to any one of claims 1 to 3, characterized in that: include: The input signal is input to the first NAND gate of the SR latch for outputting the signal Q1, and the output signal is input to the second NAND gate of the SR latch for outputting the signal Q2; when the phase delay time is less than the phase of 180 degrees, the high level pulse time of the Q1 signal output by the phase detection module is less than the high level pulse time of the Q2 signal; when the phase delay time is greater than the phase of 180 degrees, the high level pulse time of the Q1 signal output by the phase detection module is greater than the high level pulse time of the Q2 signal; when the phase delay time is equal to the phase of 180 degrees, the high level pulse time of the Q1 signal output by the phase detection module is equal to the high level pulse time of the Q2 signal; The Q1 signal and Q2 signal output by the phase detection module are respectively shaped and filtered by the low-pass filter circuit. The integration effect of the low-pass filter performs time-average filtering on the Q1 signal and the Q2 signal. According to the duration of the high-level pulses of the Q1 signal and the Q2 signal output by the phase detection module, analog voltage signals V1 and V2 of corresponding amplitudes are obtained, and the analog voltage signals V1 and V2 are input into the error amplifier. The error amplifier compares the input signals V1 and V2 and outputs the error signal Error to the calibration control circuit. When the signal V1 is greater than the signal V2, the error amplifier outputs a high-level signal '1', indicating that the delay time is greater than the 180-degree phase; when the V1 signal is less than the V2 signal, the error amplifier outputs a low-level signal '0', indicating that the delay time is less than the 180-degree phase; when the V1 signal is equal to the V2 signal, the error amplifier outputs an intermediate-level signal '1 / 2', indicating that the delay time is equal to the 180-degree phase; The calibration control circuit controls the size of the output signal VCTL according to the level of the input error signal Error. When Error is '0', it means that the delay time is less than 180 degrees of phase, and the signal VCTL is reduced, and the delay time is increased; When Error is '1', it means that the delay time is greater than the 180-degree phase, increasing the signal VCTL and reducing the delay time; When Error is '1 / 2', it means that the delay time is equal to the 180-degree phase, and the signal VCTL is kept unchanged; the calibration control circuit controls all variable delay units to produce the same delay time through the output VCTL signal, which is used to ensure that the phase difference of the clock signal output by each level of variable delay unit is equal; through the negative feedback control of the delay calibration circuit, the delay time generated by the delay chain is finally equal to the 180-degree phase delay.

5. The calibration method of a multi-phase clock generating circuit according to claim 4, characterized in that: According to the circuit structure of the variable delay unit, the VCTL signal includes an analog signal or a digital control signal.

Images