A ramp generator, analog-to-digital converter and image sensor

Abstract

The present application discloses a ramp generator, an analog-to-digital converter and an image sensor, and relates to the field of signal processing. The ramp generator includes: a ramp counter, which is composed of a plurality of triggers, and is used to generate and output a first digital signal according to an externally input clock signal; a logic gate circuit, which is connected to the output end of the trigger, and is used to receive the first digital signal and generate a second digital signal; a plurality of current devices, each of which outputs a current signal based on the first digital signal / the second digital signal, and the output ends of the plurality of current devices are connected in parallel, and are used to superimpose the current signal; a load resistor device, which is connected to the output ends of the plurality of current devices in parallel, and is used to convert the superimposed current signal into a ramp voltage signal. Based on the above arrangement, within the same clock cycle, the parallel current signal can undergo multiple changes, thereby expanding the slope or resolution of the ramp voltage signal.

Description

Technical Field

[0001] The invention belongs to the field of signal processing, and in particular relates to a ramp generator, an analog-to-digital converter and an image sensor. Background Art

[0002] In existing image sensors, a linear ramp voltage waveform signal (Vramp, hereinafter referred to as ramp voltage signal) provided by a ramp generator is often used as a global reference signal of an analog-to-digital conversion circuit to convert an analog signal of a pixel into a digital code.

[0003] In order to meet the requirements of different working scenarios, it is often necessary to adjust the slope of the ramp voltage signal. For analog-to-digital conversion type ramp generators, the prior art often adjusts the slope of the ramp voltage signal by changing the frequency of the clock signal input to the counter.

[0004] Due to the limitation of process and structure, and the parasitic influence between devices and traces, the working frequency of the counter has a high-speed bottleneck, which limits the adjustment range of the slope of the ramp voltage signal. For example, when the delay time of the highest and lowest bits of the counter output exceeds half the clock cycle of the clock signal, it is impossible to make synchronous adjustments, resulting in bit errors in the output of the counter, affecting the normal working state of the ramp generator.

[0005] Therefore, a ramp generator is urgently needed to further expand the adjustment range of the slope of the ramp voltage signal. Summary of the invention

[0006] The present application proposes a ramp generator, an analog-to-digital converter, and an image sensor, which are used to expand the slope adjustment range of a ramp voltage signal.

[0007] To achieve the above objectives, this application proposes the following technical solutions:

[0008] In a first aspect of the present application, a ramp generator is provided, comprising:

[0009] A ramp counter, composed of a plurality of triggers, for generating and outputting a first digital signal according to an externally input clock signal; wherein output signals of different triggers are used as first digital signals of different bit numbers;

[0010] a logic gate circuit connected to the output end of the trigger, used to receive the first digital signal and perform a logic operation on the first digital signal to generate a second digital signal; wherein the second digital signal of the same bit number is delayed by 180° phase of the clock signal compared with the first digital signal;

[0011] A plurality of current devices, each of which is connected to the output end of the ramp counter or the logic gate circuit and outputs a current signal based on the first digital signal or the second digital signal, and the output ends of the plurality of current devices are connected in parallel for superimposing the current signals; wherein at least one current device is connected to the output end of the ramp counter, and another current device is connected to the output end of the logic gate circuit;

[0012] The load resistance device is connected to the output ends of the plurality of current devices connected in parallel and is used for converting the superimposed current signal into a ramp voltage signal.

[0013] Optionally, the logic gate circuit is composed of a plurality of logic units, and each logic unit is connected to a trigger in the ramp counter;

[0014] Among them, the logic unit connected to the lowest bit trigger includes an XOR logic circuit and a D latch, and the remaining logic units include an AND logic circuit, an XOR logic circuit and a D latch.

[0015] Optionally, in the logic unit connected to the lowest bit trigger, the input of the XOR logic circuit includes a clock signal and a first digital signal of the lowest bit number, and the output of the XOR logic circuit is connected to the input of the D latch.

[0016] Optionally, except for the logic unit connected to the lowest bit trigger, in the remaining logic units, the output end of the AND logic circuit is connected to the input end of the XOR logic circuit, and the output end of the XOR logic circuit is connected to the input end of the D latch; and the output signal of the AND logic circuit is used as the first logic signal, and the output signal of the XOR logic circuit is used as the second logic signal;

[0017] Among them, the first logic signal of the previous digit and the second digital signal of the previous digit are used as input signals of the AND logic circuit, and the first digital signal of the same digit and the first logic signal of the same digit are used as input signals of the XOR logic circuit.

[0018] Optionally, the ramp generator further includes a clock generating device connected to an input end of the ramp counter, for providing a clock signal, and inputting the clock signal into the ramp counter.

[0019] Optionally, when there are multiple ramp counters, the clock generating device provides multiple clock signals whose number is the same as the ramp counters; wherein each clock signal has the same clock frequency and different phases.

[0020] Optionally, the current device includes

[0021] A decoder, connected to the output end of the ramp counter or the logic gate circuit, is used to receive the first digital signal or the second digital signal and perform digital conversion on it to transform it into a digital control signal;

[0022] The current unit is connected to the output end of the decoder, and is used to receive the digital control signal, convert the digital control signal into a switch control signal, and adjust the value of the current signal based on the switch control signal.

[0023] Optionally, the total number of the current devices is an even number.

[0024] In a second aspect of the present application, an analog-to-digital converter is provided, comprising: at least one column analog-to-digital conversion unit, the column analog-to-digital conversion unit comprising: a comparator, a column counter and a ramp generator as described in the first aspect, wherein the in-phase input terminal of the comparator is connected to the output terminal of the ramp generator; the input terminal of the column counter is connected to the output terminal of the comparator.

[0025] In the third aspect of the present application, an image sensor is provided, comprising: a pixel circuit, a digital logic circuit and an analog-to-digital converter as described in the second aspect, wherein: the pixel circuit is connected to the inverting input terminal of the comparator; and the digital logic circuit is used to configure a flip point, a ramp excitation signal and a ramp initial value signal.

[0026] The beneficial effects of this application are as follows:

[0027] The present application provides a ramp generator, comprising: a ramp counter, composed of a plurality of triggers, for generating and outputting a first digital signal according to an externally input clock signal; wherein the output signals of different triggers are used as first digital signals of different bit numbers; a logic gate circuit, connected to the output end of the trigger, for receiving the first digital signal, and performing a logic operation on the first digital signal to generate a second digital signal; wherein the second digital signal of the same bit number is delayed by 180° of the phase of the clock signal compared with the first digital signal; a plurality of current devices, each of which is connected to the output end of the ramp counter or the logic gate circuit, and outputs a current signal based on the first digital signal or the second digital signal, and the output ends of the plurality of current devices are connected in parallel for superimposing the current signals; wherein at least one current device is connected to the output end of the ramp counter, and another current device is connected to the output end of the logic gate circuit; a load resistor device, connected to the output ends of the plurality of current devices connected in parallel, for converting the superimposed current signal into a ramp voltage signal.

[0028] Based on the above settings, the ramp generator provided in the present application uses a logic gate circuit to process the first digital signal to obtain a second digital signal with a phase delay of 180°, and obtains multiple current signals based on multiple current devices and the aforementioned different digital signals, and converts the current signals generated by the current devices into ramp voltage signals after parallel connection. Compared with the original ramp generator with a single clock signal, the parallel current signal can undergo multiple changes within the same clock cycle, thereby expanding the slope or resolution of the ramp voltage signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of this application. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0030] Figure 1 It is a structural schematic diagram of a ramp counter provided by the present application;

[0031] Figure 2 It is a structural schematic diagram of a logic gate circuit provided by the present application;

[0032] Figure 3 is a schematic diagram of a signal waveform provided by the present application;

[0033] Figure 4 is a schematic diagram of a signal glitch provided by the present application;

[0034] Figure 5 It is a schematic diagram of eliminating signal glitches provided by the present application;

[0035] Figure 6 is a schematic structural diagram of a ramp generator provided by the present application;

[0036] Figure 7 is a structural schematic diagram of another ramp generator provided by the present application;

[0037] Figure 8 It is a schematic diagram of a decoding and synchronous latching circuit provided by the present application;

[0038] Fig. 9 is a structural schematic diagram of another ramp generator provided by the present application;

[0039] Fig.10 is a structural schematic diagram of another ramp generator provided by the present application;

[0040] Fig.11 is a structural schematic diagram of another ramp generator provided by the present application;

[0041] Fig.12It is a structural schematic diagram of a clock generating device provided by the present application;

[0042] Fig.13 It is a structural schematic diagram of a current device provided by the present application;

[0043] Fig.14 is a structural schematic diagram of a current mirror switch provided by the present application;

[0044] Fig.15 is a schematic diagram of an original ramp voltage signal provided by the present application;

[0045] Fig.16 is a schematic diagram of an adjusted ramp voltage signal provided by the present application;

[0046] Fig.17 is a schematic diagram of another adjusted ramp voltage signal provided by the present application;

[0047] Fig.18 It is a structural schematic diagram of an analog-to-digital converter provided by the present application;

[0048] Fig.19 It is a structural schematic diagram of an image sensor circuit provided by the present application. DETAILED DESCRIPTION

[0049] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments.

[0050] In CMOS image sensors, the linear ramp voltage signal is used as a global reference signal for the analog-to-digital conversion circuit to convert the analog signal from the photodiode pixel into a digital code.

[0051] The prior art often adjusts the slope of the ramp voltage signal by changing the frequency of the clock signal input to the counter. However, due to the limitations of the process and structure, and the parasitic effects between the devices and the wiring, the operating frequency of the counter has a high-speed bottleneck, which limits the maximum value of the slope of the ramp voltage signal. The slope of the ramp voltage signal represents the absolute value of the voltage change of the ramp voltage signal per unit time.

[0052] In order to solve the above problems, the present application provides a ramp generator to further expand the adjustment range of the slope of the ramp voltage signal. The ramp generator provided by the present application includes:

[0053] The ramp counter is composed of a plurality of triggers and is used to generate and output a first digital signal according to an externally input clock signal, wherein the output signals of different triggers are used as first digital signals of different bit numbers.

[0054] The logic gate circuit is connected to the output end of the trigger, and is used to receive the first digital signal and perform a logic operation on the first digital signal to generate a second digital signal.

[0055] The second digital signal with the same bit number is delayed by 180° in phase with the clock signal compared with the first digital signal.

[0056] A plurality of current devices, each current device is connected to the output end of the ramp counter or the logic gate circuit, and outputs a current signal based on the first digital signal or the second digital signal, and the output ends of the plurality of current devices are connected in parallel for superimposing the current signals; wherein at least one current device is connected to the output end of the ramp counter, and another current device is connected to the output end of the logic gate circuit.

[0057] The load resistance device is connected to the output ends of the plurality of current devices connected in parallel and is used for converting the superimposed current signal into a ramp voltage signal.

[0058] Based on the above settings, the ramp generator provided in the present application uses a logic gate circuit to process the first digital signal to obtain a second digital signal with a phase delay of 180°, and obtains multiple current signals based on multiple current devices and the aforementioned different digital signals, and converts the current signals generated by the current devices into ramp voltage signals after parallel connection. Compared with the original ramp generator with a single clock signal, the parallel current signal can undergo multiple changes within the same clock cycle, thereby expanding the slope or resolution of the ramp voltage signal.

[0059] The ramp counter is composed of multiple D flip-flops. Each D flip-flop outputs Q inverted. , as the input trigger signal of the next D flip-flop. The number of D flip-flops is the same as the bit width of the ramp counter. If the bit width of the ramp counter is N bits, the total number of D flip-flops is N.

[0060] The internal structure of the ramp counter is as follows Figure 1 As shown, from left to right, the first D flip-flop is based on the clock signal CLK as a trigger signal and is triggered based on the rising edge of the clock signal, and outputs Q as the lowest bit Q of the first digital signal <0> , and the output Q is inverted As the input trigger signal of the second D flip-flop. After that, the output Q of the second D flip-flop is used as the first digital signal (from low to high) and the second Q <1> , As the input trigger signal of the third D flip-flop. Similarly, the output Q of each D flip-flop is the value of the corresponding bit of the first digital signal. As the input trigger signal of the next D flip-flop.

[0061] In some embodiments, the logic gate circuit is composed of a plurality of logic units, and each logic unit is connected to a trigger in the ramp counter, wherein the total number of logic units is the same as the bit width of the ramp counter.

[0062] Among them, the logic unit connected to the lowest bit trigger includes an XOR logic circuit and a D latch, and the remaining logic units include an AND logic circuit, an XOR logic circuit and a D latch.

[0063] In one implementation, in a logic unit connected to the lowest bit trigger, the input of the XOR logic circuit includes a clock signal and a first digital signal of the lowest bit number, and the output of the XOR logic circuit is connected to the input of the D latch.

[0064] Except for the logic unit connected to the lowest bit trigger, in the remaining logic units, the output end of the AND logic circuit is connected to the input end of the XOR logic circuit, and the output end of the XOR logic circuit is connected to the input end of the D latch; and the output signal of the AND logic circuit serves as the first logic signal, and the output signal of the XOR logic circuit serves as the second logic signal.

[0065] Among them, the first logic signal of the previous digit and the second digital signal of the previous digit are used as input signals of the AND logic circuit, and the first digital signal of the same digit and the first logic signal of the same digit are used as input signals of the XOR logic circuit.

[0066] Specifically, the logic gate circuit corresponding to the ramp counter with a bit width of N bits is as follows: Figure 2 As shown, the logic unit of the 0-bit position (i.e., the logic unit connected to the lowest bit trigger) is composed of an XOR logic circuit and a D latch. The input signal of the XOR logic circuit includes the clock signal CLK and the lowest bit first digital signal Q <0> (That is, the output of the lowest bit trigger, refer to Figure 1 ), the second logic signal dly output by the XOR logic circuit <0> As the input signal of the D latch. In addition, the trigger signal of the D latch in the logic gate circuit is the clock signal CLK.

[0067] Except for the 0-bit logic unit, the remaining logic units include an AND logic circuit, an XOR logic circuit, and a D latch. For the 1-bit logic unit (i.e., the logic unit connected to the second bit flip-flop according to the bit sequence from low to high), the clock signal and the first digital signal Qd output by the 0-bit logic unit <0> As the input signal of the AND logic circuit, the first logic signal hc output by the AND logic circuit <1> and the first digital signal Q of the same bit number <1> As the input signal of the XOR logic circuit, and the second logic signal dly output by the XOR logic circuit <1> As the input signal of the D latch, the second digital signal Qd of the second digit is obtained. <1> .

[0068] For a 2-bit logic unit (i.e., a logic unit connected to a third bit flip-flop according to the bit sequence from low to high), the first logic signal hc output by the 0-bit logic unit <1> and the first digital signal Qd <1> As the input signal of the AND logic circuit, the first logic signal hc output by the AND logic circuit <2> and the first digital signal Q of the same bit number <2> As the input signal of the XOR logic circuit, and the second logic signal dly output by the XOR logic circuit <2> As the input signal of the D latch, the second digital signal Qd of the second digit is obtained. <2> .

[0069] Thus, except for the logic unit connected to the lowest bit flip-flop, in the remaining logic units, the first logic signal of the last digit and the second digital signal of the last digit are used as input signals of the AND logic circuit, and the first digital signal of the same digit and the first logic signal of the same digit are used as input signals of the XOR logic circuit. Among them, for the logic unit connected to the second bit flip-flop, the first logic signal of the last digit is the clock signal CLK.

[0070] Based on the setting of the above logic gate circuit, the second digital signal with the same bit number can delay the phase of the clock signal CLK by 180° compared with the first digital signal. The corresponding signal waveform is as follows: Figure 3 shown.

[0071] like Figure 4 As shown, for the first digital signal Q of the Xth digit <x>With the first logic signal hc <x>, due to the delay between itself, it will cause the dly output by the XOR logic circuit <x>The present application can effectively eliminate the delay between the first digital signal and the first logic signal with the same bit number by setting a D latch in each logic unit, eliminate the burrs generated by the above two signals after passing through the XOR logic circuit, and effectively avoid the risk of bit errors in the second digital signal. Figure 5 As shown, Figure 5 This is a schematic diagram of the waveform after eliminating the burrs.

[0072] In one implementation, Figure 6 As shown, when the ramp generator includes only two current devices, the ramp counter only needs a clock signal CLK to be input from the outside, and the second digital signal Qd outputted through the logic gate circuit <n-1:0>Compared with the first digital signal Q directly output by the ramp counter <n-1:0>, and the phase difference is 180°. Further, the first digital signal and the second digital signal are respectively input to different current devices, and the current signals I output by the different current devices are out After being connected in parallel, they are input to the load resistance device to obtain a ramp voltage signal.

[0073] Therefore, compared with the original ramp generator with a single clock signal, the ramp generator provided in this embodiment has a current signal after parallel connection that changes twice within the same clock cycle, which can effectively increase the slope or resolution of the ramp voltage signal.

[0074] The resolution is the smallest change in the analog signal that the ADC can identify, usually expressed in bits. For example, an 8-bit ADC can identify 256 different signal levels, while a 12-bit ADC can identify 4096 signal levels.

[0075] Compared with the technical solution of using multiple clock signals to expand the slope range of the ramp voltage signal, the ramp generator provided in this embodiment only requires a single clock signal, which can effectively reduce the structural complexity of the clock generating device, and does not require multi-phase clock generating devices such as ring oscillators or phase interpolators, thereby improving the portability of the ramp generator.

[0076] At the same time, compared with the two clock signals with a phase difference of 180° provided by the multi-phase clock generating device, the phase difference of the ramp counter in this embodiment is consistent and more closely fits 180°, so that the holding time of the current signal generated based on the clock signal is the same, and the linearity of the final ramp voltage signal is more effectively reduced to eliminate the burrs of the ramp voltage signal to the greatest extent. Among them, linearity represents the deviation between the actual output ramp voltage signal and the ideal ramp voltage signal, also known as nonlinear error. The smaller the linearity, the lower the deviation, and the higher the degree of fitting straight line of the ramp voltage signal.

[0077] In addition, compared to the ramp counter in the existing ramp generator, the solution provided in the present application generates a delay of 180° compared to the clock for each bit output signal of the ramp counter through a logical method, and combines the output of the ramp counter and the output after the phase delay of 180 degrees, which is equivalent to a counting device that produces a double operating frequency of an equivalent single ramp counter.

[0078] Since the solution provided by the present application is based on the existing ramp counter, the characteristic that the low bit can be turned off is retained. For example, a 10-bit ramp counter can turn off the low bits in turn to turn it into a ramp counter with a smaller bit width, so that a low-resolution and high-slope ramp voltage signal can be obtained. If the DDR counter is applied to the ramp generator, since the DDR counter itself is based on the upper and lower edge triggers of the first bit twice, the DFF (D flip-flop) single edge trigger can be used in the future. Although the DDR counter can reach double the counting frequency, since the low bit cannot be turned off, only the high bit can be turned off, which will cause the range of the final generated ramp voltage signal to change, and cannot meet the functional requirement of adjustable bit width of the ramp counter in the ramp generator.

[0079] like Figure 6 As shown, the ramp generator provided by the present application uses a single existing counter and delays the clock output result by 180° phase shift, which can ensure double counting rate and adjust the internal bit width of the ramp counter, making the slope and resolution of the ramp voltage signal more flexible. At the same time, the advantage of the double rate counter is that the output code of the counter will directly control the current mirror array, converting the change of the ramp counter output code into the change of the current. By connecting in parallel, the two sets of digital codes can be combined, avoiding complex digital logic and simplifying the circuit scale.

[0080] It is worth noting that the present application can improve the operating frequency of the ramp counter based on the logic gate circuit. Figure 6 For example, under a single clock signal, the ramp counter can not only achieve a resolution 1 bit higher at the same clock frequency, but also achieve a counting frequency twice at the same resolution. For example, the bit width of the ramp counter is 10 bits, and the operating frequency is 1 GHz. At this time, the time from 1 to 1024 is 1024ns. For a bit width of 9 bits and an operating frequency of 1 GHz, it only takes 512ns to count, which is 1 / 2 of 10 bits. By combining the ramp counter with a logic gate circuit, 10 bits of data can be combined. That is, the present application only needs to achieve 10-bit counting in 1 / 2 of the time, which improves the operating frequency and upper limit of the ramp counter.

[0081] In some embodiments, each current device comprises:

[0082] The decoder, connected to the output end of the ramp counter or the logic gate circuit, is used to receive the first digital signal or the second digital signal, and perform digital conversion on it to transform it into a digital control signal.

[0083] The current unit is connected to the output end of the decoder, and is used to receive the digital control signal, convert the digital control signal into a switch control signal, and adjust the value of the current signal based on the switch control signal.

[0084] In one implementation, Figure 7 As shown, when the bit width of the ramp counter is N bits, the first digital signal or the second digital signal is an N-bit binary code, and the decoder converts the first Nm bits of the first digital signal or the second digital signal into a thermometer code along the bit sequence from high to low, and the last m bits remain in the binary code and are converted into a digital control signal. Wherein, m is a preset value; the thermometer code includes a row selection thermometer code and a column selection thermometer code.

[0085] Taking the ramp counter with a bit width of 10 bits and m equal to 6 as an example, the first digital signal or the second digital signal is a 10-bit binary value, and the decoder converts the upper 6-bit binary code into a 3-bit row selection (selrow) thermometer code and a 3-bit column selection (selcol) thermometer code, respectively, while the lower 4 bits remain in the binary code (sellow), thereby forming a digital control signal and outputting it from the output end of the decoder. Based on the above processing, compared with the first digital signal or the second digital signal, the digital control signal can effectively reduce the data volume of the digital signal and improve the efficiency of signal transmission.

[0086] like Figure 7 As shown, the present application provides a circuit schematic diagram based on a single clock signal ramp generator, including a clock generating device (providing a single clock signal CLK), a ramp counter, a logic gate circuit, two decoders, two current units and a load resistor device. Among them, the bit width of each ramp counter is N bits, and the switch control signal of the current unit adopts a low m bit binary code and a high Nm bit thermometer code.

[0087] To convert binary code to thermometer code, you only need to convert the high-bit binary code into row selection (selrow) and column selection (selcol) thermometer codes, and keep the low-bit binary code (sellow) for output. After decoding, different counters control two current mirror units of the same number, and (N+1) bit data can be obtained.

[0088] The existing ramp generator controls all current mirror arrays to switch in each clock cycle, thereby obtaining a change in output voltage. However, in the ramp generator with a single clock signal of the present application, the second digital signal processed by the logic gate circuit only controls the switch of 1 / 2 group of current mirror arrays (i.e., current unit 1), but keeps the unit current mirror (i.e., the adjustment amount of the current signal under each trigger) unchanged.

[0089] In each clock cycle, the current mirror array controlled by each group of ramp counters is converted into the original 1 times RAMP voltage change value through the load resistor. Similarly, after 1 / 2 clock cycle, the current mirror array controlled by the first digital signal is also converted into the 1 times RAMP voltage change value through the load resistor. The above process completes the voltage conversion at different phase moments within one clock cycle.

[0090] Compared with the traditional ramp generator, the voltage change value during the two phases changes by 1 times of the original value, and after a clock cycle, they contribute to a voltage change value of 2 times, so that the slope of the ramp voltage signal increases by 2 times. This ensures that the voltage range of RAMP remains unchanged, but the amount of data of voltage change increases, that is, the resolution increases by 1 bit. Similarly, in one cycle, the corresponding counter triggers a ramp generator with 4 phase changes to obtain an additional 2 bits of resolution, and an 8-phase ramp generator can obtain an additional 3 bits of resolution, and so on.

[0091] In some embodiments, Figure 8 As shown, the current unit includes a D latch, and the input end of the D latch is connected to an AND or NOR logic gate circuit; wherein the digital control signal is input to the D latch after passing through the AND or NOR logic gate circuit, and the digital control signal output by the D latch is used as a switch control signal.

[0092] In some embodiments, the ramp generator further includes a reference current generating circuit and a PSRR (Power Supply Rejection Ratio) compensation device, wherein the reference current generating circuit provides a bias current for the current source of the ramp generator, and the PSRR compensation device is used to reduce the power supply ripple rejection ratio of the current source.

[0093] like Fig. 9 As shown, the ramp generator corresponding to a single clock signal provided in the present application includes a clock generating device for providing a single clock signal, a ramp counter, a logic gate circuit, a current device composed of a decoding circuit (i.e., a decoder) and a current source array, a load resistor array (i.e., a load resistor device), a reference current generating circuit and a PSRR compensation device.

[0094] In some embodiments, the ramp generator further includes a clock generating device connected to an input terminal of the ramp counter for providing a clock signal and inputting the clock signal into the ramp counter.

[0095] When there are multiple ramp counters, the clock generating device provides multiple clock signals which are the same in number as the ramp counters; wherein each clock signal has the same clock frequency and different phases.

[0096] like Fig.10 As shown, the clock device provides a clock signal CLK<0°> with a phase delay of 0° and a clock signal CLK<90°> with a phase delay of 90° compared to the reference clock signal, and inputs them into two ramp counters respectively. Each ramp counter is connected to a logic gate circuit. Figure 5 It can be seen from the embodiment shown that, taking the reference clock signal as a reference, Fig.10 In the embodiment shown, four digital signals with delayed phases of 0°, 90°, 180° and 270° are respectively input into the current device, and the output current signal is connected in parallel through the load resistance device, thereby obtaining a ramp voltage signal.

[0097] Based on the above processing, within the same clock cycle, the current signal after the ramp generators are connected in parallel changes four times, which can effectively increase the slope or resolution of the ramp voltage signal.

[0098] In one implementation, Fig.11 As shown, the ramp generator only includes one logic gate circuit. Specifically, the clock generating device provides a clock signal CLK<0°> with a phase delay of 0°, a clock signal CLK<90°> with a phase delay of 90°, and a clock signal CLK<270°> with a phase delay of 270° compared to the reference clock signal, and inputs them into three ramp counters respectively. Among them, only the ramp counter receiving CLK<0°> is connected in parallel to the logic gate circuit, and the remaining ramp generators are only connected to a current device separately. It can also be achieved that four digital signals with phase delays of 0°, 90°, 180° and 270° are respectively input into the current device, and the output current signal is connected in parallel through the load resistance device, thereby obtaining a ramp voltage signal.

[0099] Similarly, the clock generating device can also provide four clock signals CLK<0°>, CLK<45°>, CLK<90°> and CLK<135°> with a phase difference of 45°, and input them into four different ramp counters respectively. Each ramp counter is connected in parallel with a logic gate circuit, so that the current signal of the ramp generator after parallel connection can change 4 times in the same clock cycle, effectively increasing the slope or resolution of the ramp voltage signal. In addition, the number of clock signals and the number of logic gate circuits can also be adjusted to obtain a ramp generator with the same technical effect but different structure.

[0100] In some embodiments, when the ramp generator includes a current device, the phase difference between two clock signals adjacent to each other in the multiple clock signals provided by the clock signal is . Wherein, a is a positive integer. It can be understood that, in the ramp generator provided in the present application, in order to ensure that the phase difference between different digital signals is consistent, the total number of the corresponding multiple current devices is an even number. And, at least one current device among the multiple current devices is connected to the output end of the ramp counter, and at least one current device is connected to the output end of the logic gate circuit.

[0101] In one implementation, the clock generation device can generate clock signals with different phases through a ring oscillator. Specifically, the reference clock signal is inserted into the ring oscillator to form clock signals with different phases. A PLL is used in the ring oscillator. Then, the clock signals with different phases are sent to different current devices.

[0102] In one implementation, the clock generation device may also provide clock signals of different phases based on a combination of a delay circuit and a plurality of phase interpolators. When the clock generation device is a four-phase clock generation circuit that provides four sets of clock signals of different phases, Fig.12 As shown, it includes a delay circuit and four phase interpolators (PI01, PI02, PI03 and PI04). Among them, the delay circuit delays the input reference clock signal by a predetermined delay time tPD and outputs a delayed clock signal. The delay time tPD is 1 / 4 cycle of the reference clock signal, and then the delay circuit sends the delayed reference clock signal to the phase interpolators PI01, PI02, PI03 and PI04 respectively.

[0103] The phase interpolators PI01, PI02, PI03 and PI04 all have the same circuit. Each phase interpolator is a circuit with two inputs and one output, and outputs a signal at a time delayed by a predetermined delay time from the middle time of the phase difference between the two input signals.

[0104] like Fig.12 As shown in , the signal obtained by delaying the reference clock signal by about 1 / 4 cycle is input to the phase interpolator PI01. The phase interpolator PI01 uses these signals to generate the clock signal q0 as one of the four-phase clock signals and outputs the generated clock signal to the outside of the four-phase clock generation circuit. The inversion signal of the reference clock signal and the signal obtained by delaying the reference clock signal by about 1 / 4 cycle are input to the phase interpolator PI02. The phase interpolator PI02 uses these signals to generate the clock signal q1 as one of the four-phase clock signals and outputs the generated clock signal to the outside of the four-phase clock generation circuit. The inversion signal of the reference clock signal and the signal obtained by delaying the reference clock signal by about 1 / 4 cycle are input to the phase interpolator PI03. The phase interpolator PI03 uses these signals to generate the clock signal q2 as one of the four-phase clock signals and outputs the generated clock signal to the outside of the four-phase clock generation circuit. The reference clock signal and the inversion signal of the signal obtained by delaying the reference clock signal by about 1 / 4 cycle are input to the phase interpolator PI04. The phase interpolator PI04 generates a clock signal q3 which is one of four-phase clock signals using these signals and outputs the generated clock signal to the outside of the four-phase clock generation circuit.

[0105] The phase interpolator generates four-phase clock signals whose phases are all shifted by 1 / 4 cycle using a reference clock signal and a signal obtained by delaying the reference clock signal by about 1 / 4 cycle, and outputs the four-phase clock signals.

[0106] In addition, you can also change Fig.12 The number or combination of phase interpolators of the phase difference clock generating circuit in the example (four-phase clock generating circuit) can generate an 8-phase clock signal with each phase shifted by 1 / 8 cycle or a 16-phase clock signal with each phase shifted by 1 / 16 cycle.

[0107] Similarly, by changing Fig.12 The number of phase interpolators, their combination and their weighting coefficient W of the phase difference clock generating circuit in the example (four-phase clock generating circuit) can generate a 3-phase clock signal with each phase shifted by 1 / 3 of a cycle or a 5-phase clock signal with each phase shifted by 1 / 5 of a cycle.

[0108] like Fig.13 As shown, a ramp generator composed of 4 current devices is taken as an example, that is, a DAC ramp (ramp generator) with a mixed structure of 4-bit binary and 4-bit thermometer code. The decoder converts the high 4-bit binary code output by the ramp counter into a 3-bit row selection thermometer control code and a 3-bit column selection thermometer control code. The 8-bit ramp generator provided in this application is equivalent to the original 10-bit ramp generator. Among them, x1...x16 respectively represent the number of current mirror tubes in the current unit, that is, current unit x1 (that is, indicating that there is 1 current mirror tube in the current unit), current unit x2 (that is, indicating that there are 2 current mirror tubes in the current unit), current unit x4, current unit x8, current unit x16 (that is, indicating that there are 16 current mirror tubes in the current unit), and the number of current unit x16 is reduced to 1 / 4.

[0109] Each decoder corresponds to a set of current mirror arrays (i.e., current units). <1> Generated clkarray, sell <1> , tiehi, tielo are connected to the clk, A, B, C ports in the first group of current units x1 respectively; clkarray, sell <2> , tiehi, tielo are connected to the clk, A, B, C ports in the first group of current unit x2 modules respectively; clkarray, sell <3> , tiehi, tielo are connected to the clk, A, B, C ports in the first group of current unit x4 modules respectively; clkarray, sell <4> , tiehi, tielo are connected to the clk, A, B, C ports in the first group of current unit x8 modules respectively; the first group of current unit x16 modules has 16 current mirror units, which connect clkarray, < 4>(sel_col<1:3>tielo),< 4>tiehi,sel_row<(1 4,2 4,3 4)〉and sel_row<(1 4,2 4,3 4)>,< 3> tielo, tiehi are connected to the clk, A, B, and C ports of Icell<16:1>. Similarly, the second, third, and fourth groups of decoders are connected to the corresponding current mirror arrays according to the above method.

[0110] like Figure 8 As shown, the row and column control codes are AND-OR-N logic inside the current unit module, and recompiled into the switch control signal of the current unit. However, since the delay path of these control signals cannot be kept completely consistent during the encoding and decoding process, the control signal needs to be passed through Dlatch (D latch) to synchronize the signals of different bits at the same clock rising edge. Finally, the time when the control signals sel and selb of different current units arrive at the current mirror switch can be kept consistent.

[0111] The structure of the current mirror switch is as follows: Fig.14 As shown in the figure, pbias represents the current tube bias voltage, pcas represents the common source and common gate tube bias voltage, sel represents the current turn-on signal, and selb represents the current turn-off signal.

[0112] If the clock signal frequency in the original ramp generator has been adjusted to the maximum value f (in Hz), the present application also provides an adjustment method for the ramp generator provided in the present application, which is used to increase the slope or resolution of the ramp voltage signal. The adjustment method includes the following steps:

[0113] Step 1: Obtain the total number b of current devices.

[0114] Step 2: Adjust the current signal to the original value at each trigger. , and keep the bit width of the ramp counter unchanged.

[0115] Based on the above processing, the adjustment amount of the current signal in the ramp generator at each trigger is adjusted to the original , so that the range of the original ramp voltage signal does not change, ensuring the applicability of the ramp generator in the present application, and can be directly applied to the usage scenario of the original ramp generator.

[0116] At the same time, although the bit width of the ramp counter remains unchanged, the total bit width of multiple ramp counters increases due to the adaptability of the number of ramp counters and the number of clock signals, thereby improving its resolution while ensuring that the range of the ramp voltage signal remains unchanged.

[0117] like Fig.15 As shown, the original ramp represents the ramp voltage signal generated by the original ramp generator, x1 represents the slope of the ramp voltage signal is 1, v represents the voltage value, and t represents the time length. Fig.16 As shown, Fig.16 Schematic diagram of a ramp voltage signal including the original ramp and the current ramp, wherein the current ramp represents the ramp voltage signal obtained based on the ramp generator provided by the present application and the above adjustment method, wherein the slope and voltage range of the current ramp are the same as those of the original ramp, but its resolution is increased by b times.

[0118] In some embodiments, the adjustment method further comprises the following steps:

[0119] Step 3: Determine whether the total number b of current devices is 2 c ; Wherein, c is an integer greater than or equal to 1.

[0120] Step 4: If yes, reduce the bit width of the ramp counter by c bits, and keep the adjustment amount of the current signal unchanged in each trigger.

[0121] Based on the above processing, by reducing the bit width of the ramp counter by c bits, the resolution of the ramp generator provided in the present application can be effectively guaranteed not to change. At the same time, the adjustment amount of the current signal under each triggering remains unchanged, which can ensure that the voltage range of the ramp voltage signal does not change, thereby ensuring the applicability of the ramp generator in the present application.

[0122] In addition, in the process of generating a ramp voltage signal, the number of triggers that cause its current signal to change within the same clock cycle is b times that of the original ramp generator. Therefore, on the basis of the unchanged resolution and voltage range of the ramp voltage signal, its slope is further increased to b times the original.

[0123] like Fig.17 As shown, this ramp is a ramp voltage signal generated based on a four-phase clock signal. Compared with the original ramp, its voltage range and resolution have not changed, but its slope has increased four times.

[0124] Based on the same inventive concept, the present application also provides an analog-to-digital converter, the analog-to-digital converter includes: at least one column analog-to-digital conversion unit, the column analog-to-digital conversion unit includes: a comparator, a column counter and a ramp generator of the present application. Among them, the in-phase input end of the comparator is connected to the output end of the ramp generator; the input end of the column counter is connected to the output end of the comparator; if the total number of current devices is b, the operating frequency of the column counter is adjusted to b times the original operating frequency. In addition, due to the increase in the slope of the ramp voltage signal, the quantization time of the ramp generator is shortened, reducing the power consumption of the analog-to-digital converter.

[0125] like Fig.18 As shown, the present application provides an analog-to-digital converter for a readout circuit. Among them, the ramp generator generates a ramp voltage signal, and the ramp voltage signal is sampled to the in-phase input terminal of each column comparator through a capacitor, and the inverting input terminal of the comparator samples the pixel signal of each column (including signal Vin1, signal Vin2, etc.), wherein the ramp voltage signal will traverse the entire quantization voltage range and be compared with the pixel signal, and the column counter starts counting at the same time. When the ramp voltage signal>pixel signal, the comparator flips, and the column counter stops working. The counting result at this time is the digital code value after the pixel signal is quantized. It is worth noting that if the slope of the ramp voltage signal generated by the ramp generator provided in the present application increases by b times, the operating frequency of the column counter needs to be increased to b times the original operating frequency.

[0126] In actual work, the operating frequency of the column counter can be adjusted by increasing the frequency of the clock signal input to the column counter.

[0127] like Fig.19 As shown, the existing CMOS image sensor circuit includes: a pixel array, a readout circuit, a functional logic unit, a control circuit and a status register. Among them, the pixel array is used to complete the photoelectric conversion and convert photons into electrons; the readout circuit is used to read the electrical signal converted by the pixel array; the functional logic unit is used to adjust the signal readout and transmission mode of the readout circuit; the status register is used to temporarily store the status of the readout circuit; the control circuit performs feedback adjustment on the pixel array by collecting the status of the readout circuit.

[0128] Based on the same inventive concept, the present application also provides an image sensor, which includes: a pixel circuit, a digital logic circuit and an analog-to-digital converter of the present application. The pixel circuit is connected to the inverting input terminal of the comparator; the digital logic circuit is used to configure the flip point, the ramp excitation signal and the ramp initial value signal.

[0129] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application. < / x> < / x> < / x>

Claims

1. A ramp generator, characterized in that: include: A ramp counter, composed of a plurality of triggers, for generating and outputting a first digital signal according to an externally input clock signal; wherein output signals of different triggers are used as first digital signals of different bit numbers; a logic gate circuit connected to the output end of the trigger, used to receive the first digital signal and perform a logic operation on the first digital signal to generate a second digital signal; wherein the second digital signal of the same bit number is delayed by 180° phase of the clock signal compared with the first digital signal; A plurality of current devices, each of which is connected to the output end of the ramp counter or the logic gate circuit and outputs a current signal based on the first digital signal or the second digital signal, and the output ends of the plurality of current devices are connected in parallel for superimposing the current signals; wherein at least one current device is connected to the output end of the ramp counter, and another current device is connected to the output end of the logic gate circuit; The load resistance device is connected to the output ends of the plurality of current devices connected in parallel and is used for converting the superimposed current signal into a ramp voltage signal.

2. The ramp generator according to claim 1, characterized in that The logic gate circuit is composed of a plurality of logic units, and each logic unit is connected to a trigger in the ramp counter; Among them, the logic unit connected to the lowest bit trigger includes an XOR logic circuit and a D latch, and the remaining logic units include an AND logic circuit, an XOR logic circuit and a D latch.

3. The ramp generator according to claim 2, characterized in that In the logic unit connected to the lowest bit trigger, the input of the XOR logic circuit includes a clock signal and a first digital signal of the lowest bit number, and the output of the XOR logic circuit is connected to the input of the D latch.

4. The ramp generator according to claim 2, characterized in that Except for the logic unit connected to the lowest bit trigger, in the remaining logic units, the output end of the AND logic circuit is connected to the input end of the XOR logic circuit, and the output end of the XOR logic circuit is connected to the input end of the D latch; and the output signal of the AND logic circuit is used as the first logic signal, and the output signal of the XOR logic circuit is used as the second logic signal; Among them, the first logic signal of the previous digit and the second digital signal of the previous digit are used as input signals of the AND logic circuit, and the first digital signal of the same digit and the first logic signal of the same digit are used as input signals of the XOR logic circuit.

5. The ramp generator according to claim 1, characterized in that: The ramp generator also includes a clock generating device connected to the input end of the ramp counter, for providing a clock signal, and inputting the clock signal into the ramp counter.

6. The ramp generator according to claim 5, characterized in that When there are multiple ramp counters, the clock generating device provides multiple clock signals which are the same in number as the ramp counters; wherein each clock signal has the same clock frequency and different phases.

7. The ramp generator according to claim 1, characterized in that The current device comprises A decoder, connected to the output end of the ramp counter or the logic gate circuit, is used to receive the first digital signal or the second digital signal and perform digital conversion on it to transform it into a digital control signal; The current unit is connected to the output end of the decoder, and is used to receive the digital control signal, convert the digital control signal into a switch control signal, and adjust the value of the current signal based on the switch control signal.

8. The ramp generator according to claim 1, characterized in that: The total number of the current devices is an even number.

9. An analog-to-digital converter, characterized in that: The analog-to-digital converter includes: at least one column analog-to-digital conversion unit, and the column analog-to-digital conversion unit includes: a comparator, a column counter and a ramp generator as described in any one of claims 1-8, wherein the non-inverting input terminal of the comparator is connected to the output terminal of the ramp generator; and the input terminal of the column counter is connected to the output terminal of the comparator.

10. An image sensor, characterized in that: The image sensor comprises: a pixel circuit, a digital logic circuit and an analog-to-digital converter as claimed in claim 9, wherein: the pixel circuit is connected to the inverting input terminal of the comparator; the digital logic circuit is used to configure the flip point, the ramp excitation signal and the ramp initial value signal.

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