Gate polysilicon open circuit test structure and generation method, device, equipment and medium

Abstract

The present application relates to a gate polysilicon disconnection test structure and a generation method, device, equipment and medium, wherein the method obtains a layout, determines at least two target areas in a standard cell area of ​​the layout; obtains the gate polysilicon in the target area, covers and connects the gate polysilicon in the target area in series by setting an auxiliary pattern, and connects the auxiliary patterns in at least two target areas in parallel; based on the gate cut-off layer in the target area and the metal interconnection line connecting the gate polysilicon, the gate polysilicon is screened to obtain the target gate polysilicon; a metal structure is generated based on the auxiliary pattern and the target gate polysilicon; the metal structure is connected to the gate polysilicon through a gate through hole, thereby solving the problems of low efficiency and poor quality in manually building a gate polysilicon test structure in the related art, realizing rapid generation of a test structure using a script through the acquired layout information, and improving the efficiency and accuracy of test structure generation.

Description

Technical Field

[0001] The present application relates to the field of chip testing technology, and in particular to a gate polysilicon open circuit test structure and a generation method, device, equipment and medium. Background Art

[0002] As the process node of integrated circuits continues to shrink to 14nm or below, the size of gate polysilicon is also shrinking. Due to the optical proximity effect during the photolithography process, there is a risk of short circuits in the gate polysilicon after actual photolithography. Therefore, it is necessary to build a test structure to test the relevant properties of the transistors in the standard cell area to quantify the above risks.

[0003] The traditional way to build a test structure is to do it manually in EDA software, which is more suitable for building a test structure for a small layout. If the layout area is too large, the manual processing method is time-consuming and cumbersome. In addition, manual drawing is more prone to human errors, resulting in structural errors, and the functions required by the test cannot be achieved.

[0004] With regard to the problem of low efficiency and poor quality of manually building test structures in related technologies, no effective solution has been proposed so far. Summary of the invention

[0005] In this embodiment, a gate polysilicon open circuit test structure and a generation method, device, equipment and medium are provided to solve the problem of low efficiency and poor quality in building a test structure in the related art.

[0006] In a first aspect, a method for generating a gate polysilicon open circuit test structure is provided in this embodiment, the method comprising:

[0007] Acquire a layout, determine a test area in a standard cell area of ​​the layout, and divide the test area into at least two target areas;

[0008] Obtaining gate polysilicon in the target area, and by setting auxiliary patterns, covering and connecting the gate polysilicon in the target area in series, and connecting the auxiliary patterns in the at least two target areas in parallel;

[0009] Based on the gate cut-off layer in the target area and the metal interconnection line connected to the gate polysilicon, screening the gate polysilicon to obtain target gate polysilicon;

[0010] Determine the position of a gate through hole at the end of the target gate polysilicon and generate the gate through hole;

[0011] A metal layer pattern is determined based on the auxiliary pattern and the target gate polysilicon, and a metal structure is generated based on the metal layer pattern; the metal structure is connected to the target gate polysilicon through the gate via, completing the generation of the gate polysilicon open circuit test structure.

[0012] In some embodiments, dividing the test area into at least two target areas comprises:

[0013] Acquire a body pole region in the test region, and divide the test region into at least two sub-regions of the same size based on the body pole region;

[0014] After shrinking the sub-areas to a first preset size, a target area is obtained.

[0015] In some embodiments, the obtaining of the gate polysilicon in the target area, by setting an auxiliary pattern, covering and connecting the gate polysilicon in the target area in series, and connecting the auxiliary patterns in the at least two target areas in parallel, comprises:

[0016] Obtaining gate polysilicon in the target area, and setting a first auxiliary pattern based on the gate polysilicon to cover and serpentinely connect the gate polysilicon in series;

[0017] Determine one end of the first auxiliary graphic as the starting end, and the other end of the first auxiliary graphic as the terminal end; set a second auxiliary graphic based on the boundary of the target area and the starting end, and use the second auxiliary graphic to connect the starting ends of the first auxiliary graphics in the at least two target areas together to form a common starting end.

[0018] In some embodiments, obtaining gate polysilicon in the target area, and setting a first auxiliary pattern based on the gate polysilicon to cover and serpentinely connect the gate polysilicon in series, include:

[0019] Acquire gate polysilicon in the target area, expand the width of the gate polysilicon to a second preset size, and generate the first auxiliary pattern A;

[0020] Adding first auxiliary graphics B at both ends of the first auxiliary graphics A in an extended manner to connect the adjacent first auxiliary graphics A end to end;

[0021] Based on the first auxiliary pattern A and the first auxiliary pattern B, a first auxiliary pattern in a serpentine shape is formed.

[0022] In some embodiments, the step of setting a second auxiliary graphic based on the boundary of the target area and the starting end, and connecting the starting ends of the first auxiliary graphics in the at least two target areas together to form a common starting end by using the second auxiliary graphic, comprises:

[0023] Acquire a vertical boundary in the target area close to the starting end of the first auxiliary figure, and use the vertical boundary as a reference to expand a second auxiliary figure A outside the target area;

[0024] generating a second auxiliary pattern B above at least two second auxiliary patterns A to connect the second auxiliary patterns A;

[0025] generating a second auxiliary graphic C between the starting end of the first auxiliary graphic and the second auxiliary graphic A to connect the starting end of the first auxiliary graphic and the second auxiliary graphic A;

[0026] Based on the second auxiliary pattern A, the second auxiliary pattern B, and the second auxiliary pattern C, a second auxiliary pattern is formed.

[0027] In some of the embodiments, the test port of the gate polysilicon open circuit test structure includes the common start end and a terminal of at least one first auxiliary pattern, and the test port is used to detect the gate polysilicon open circuit condition of the standard cell area in the test area.

[0028] In some embodiments, based on the gate cut-off layer in the target area and the metal interconnection line connected to the gate polysilicon, screening the gate polysilicon to obtain the target gate polysilicon includes:

[0029] Acquire a power line region, a gate cutoff pattern of a gate cutoff layer, and a metal interconnection line connected to gate polysilicon in the target region;

[0030] identifying the gate cut-off pattern that does not overlap with the power line region as a floating gate cut-off pattern;

[0031] A pattern that does not overlap with the power line region and does not contact the floating gate cutoff pattern and the metal interconnection line connecting the gate polysilicon is selected from the gate polysilicon as the target gate polysilicon.

[0032] In some embodiments, determining a location of a gate through hole at an end of the target gate polysilicon and generating the gate through hole comprises:

[0033] Based on the design rules, the position of at least one gate through hole is determined within the end of the target gate polysilicon pattern region by utilizing the target gate polysilicon pattern edge shrinking process.

[0034] In some embodiments, determining a metal layer pattern based on the auxiliary pattern and the target gate polysilicon, and generating a metal structure based on the metal layer pattern include:

[0035] Removing a portion of the first auxiliary pattern A having a width of a second preset size and used for covering the target gate polysilicon to form a remaining pattern;

[0036] Extending the remaining pattern to cover the gate through hole, and merging it with the first auxiliary pattern B and the second auxiliary pattern to form a metal layer pattern;

[0037] A metal structure is generated based on the metal layer pattern.

[0038] In some of the embodiments, at least two test units are connected in parallel in the gate polysilicon open circuit test structure; the test units are the gate polysilicon connected in series in the target area.

[0039] In a second aspect, the present application further provides a device for generating a gate polysilicon open circuit test structure, the device comprising:

[0040] A target area determination module, used to obtain a layout, determine a test area in a standard cell area of ​​the layout, and divide the test area into at least two target areas;

[0041] An auxiliary pattern generation module, used for obtaining the gate polysilicon in the target area, covering and connecting the gate polysilicon in the target area in series by setting an auxiliary pattern, and connecting the auxiliary patterns in the at least two target areas in parallel;

[0042] A target gate polysilicon screening module, used for screening the gate polysilicon to obtain target gate polysilicon based on the gate cut-off layer in the target area and the metal interconnection line connecting the gate polysilicon;

[0043] A gate through hole generation module, used to determine the position of the gate through hole at the end of the target gate polysilicon and generate the gate through hole;

[0044] A test structure generation module is used to determine a metal layer pattern based on the auxiliary pattern and the target gate polysilicon, and to generate a metal structure based on the metal layer pattern; the metal structure is connected to the target gate polysilicon through the gate through hole to complete the generation of the gate polysilicon open circuit test structure.

[0045] In a third aspect, the present application also provides a gate polysilicon short circuit test structure, which is generated based on the method described in the first aspect; the test structure includes: a target gate polysilicon, a metal structure and a gate via; the metal structure is connected to the target gate polysilicon in the standard cell area through the gate via.

[0046] In a fourth aspect, the present application further provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the method for generating a gate polysilicon open circuit test structure in the first aspect is implemented.

[0047] In a fifth aspect, the present application further provides a computer device, wherein the computer device comprises a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the method for generating a gate polysilicon open circuit test structure as described in the first aspect is implemented.

[0048] Compared with the related art, the gate polysilicon disconnection test structure and generation method, device, equipment and medium provided in the present embodiment, by acquiring a layout, determine a test area in a standard cell area of ​​the layout, and divide the test area into at least two target areas; acquire the gate polysilicon in the target area, and cover and connect the gate polysilicon in the target area in series by setting an auxiliary pattern, and connect the auxiliary patterns in the at least two target areas in parallel; based on the gate cut-off layer in the target area and the metal interconnection line connecting the gate polysilicon, screen the gate polysilicon to obtain the target gate polysilicon; determine the position of the gate through hole at the end of the target gate polysilicon, and generate the gate through hole; determine the metal layer pattern based on the auxiliary pattern and the target gate polysilicon, and generate the metal structure based on the metal layer pattern; the metal structure is connected to the target gate polysilicon through the gate through hole, and the generation of the gate polysilicon disconnection test structure is completed, which solves the problem of low efficiency and poor quality of manually building a gate polysilicon test structure in the related art, and realizes the rapid generation of the test structure using a script through the acquired layout information, thereby improving the efficiency and accuracy of the test structure generation.

[0049] Details of one or more embodiments of the present application are set forth in the following drawings and description to make other features, objects, and advantages of the present application more readily apparent. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0051] Figure 1 A hardware structure block diagram of a terminal of a method for generating a gate polysilicon disconnection test structure in one embodiment;

[0052] Figure 2 It is a schematic flow chart of a method for generating a gate polysilicon disconnection test structure in one embodiment;

[0053] Figure 3 A schematic diagram of a gate polysilicon disconnection test structure in one embodiment;

[0054] Figure 4 is a schematic diagram of the structure of a target area in one embodiment;

[0055] Figure 5 is a schematic diagram of a forming process of a first auxiliary pattern in one embodiment;

[0056] Figure 6 is a schematic diagram of a forming process of a first auxiliary pattern in another embodiment;

[0057] Figure 7 is a schematic diagram of a second auxiliary graphic in one embodiment;

[0058] Figure 8 is a schematic diagram of a target gate polysilicon in one embodiment;

[0059] Fig. 9 is a schematic diagram of a process for forming a gate through hole in one embodiment;

[0060] Fig.10 is a partial schematic diagram of a metal structure in one embodiment;

[0061] Fig.11 It is a schematic flow chart of a method for generating a gate polysilicon disconnection test structure in a preferred embodiment;

[0062] Fig.12 A schematic diagram of the actual effect of a gate polysilicon disconnection test structure in a preferred embodiment;

[0063] Fig.13 FIG. 4 is a structural block diagram of a device for generating a gate polysilicon disconnection test structure in an embodiment. DETAILED DESCRIPTION

[0064] In order to more clearly understand the purpose, technical solutions and advantages of the present application, the present application is described and illustrated below in conjunction with the accompanying drawings and embodiments.

[0065] Unless otherwise defined, the technical terms or scientific terms involved in this application shall have the general meaning understood by people with general skills in the technical field to which this application belongs. The words "one", "a", "the", "these" and the like in this application do not indicate a quantitative limitation, and they may be singular or plural. The terms "include", "comprise", "have" and any variants thereof involved in this application are intended to cover non-exclusive inclusions; for example, a process, method and system, product or device comprising a series of steps or modules (units) is not limited to the listed steps or modules (units), but may include unlisted steps or modules (units), or may include other steps or modules (units) inherent to these processes, methods, products or devices. The words "connect", "connected", "coupled" and the like involved in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The "multiple" involved in this application refers to two or more. "And / or" describes the association relationship of associated objects, indicating that there may be three relationships, for example, "A and / or B" may mean: A exists alone, A and B exist at the same time, and B exists alone. Generally, the character " / " indicates that the objects associated with each other are in an "or" relationship. The terms "first", "second", "third", etc. in this application are only used to distinguish similar objects and do not represent a specific ordering of the objects.

[0066] The method embodiment provided in this embodiment can be executed in a terminal, a computer or a similar computing device. For example, running on a terminal, Figure 1 1 is a hardware structure block diagram of a terminal of the method for generating a gate polysilicon disconnection test structure of this embodiment. Figure 1 As shown, the terminal may include one or more ( Figure 1 Only one is shown in the figure) a processor 102 and a memory 104 for storing data, wherein the processor 102 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA. The above terminal may also include a transmission device 106 and an input and output device 108 for communication functions. It can be understood by those skilled in the art that Figure 1 The structure shown is for illustration only and does not limit the structure of the above terminal. Figure 1 More or fewer components as shown, or with Figure 1 Different configurations shown.

[0067] The memory 104 can be used to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the method for generating the gate polysilicon disconnection test structure in the present embodiment. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, to implement the above method. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include a memory remotely arranged relative to the processor 102, and these remote memories may be connected to the terminal via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0068] The transmission device 106 is used to receive or send data via a network. The above network includes a wireless network provided by the communication provider of the terminal. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, referred to as NIC), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 106 can be a radio frequency (Radio Frequency, referred to as RF) module, which is used to communicate with the Internet wirelessly.

[0069] In this embodiment, a method for generating a gate polysilicon disconnection test structure is provided. Figure 2 is a flow chart of the method for generating the gate polysilicon disconnection test structure of this embodiment. Figure 2 As shown, the process includes the following steps:

[0070] Step S210 , obtaining a layout, determining a test area in a standard cell area of ​​the layout, and dividing the test area into at least two target areas VLDZONE_BNY.

[0071] Specifically, a test area is selected in the standard cell area of ​​the layout. In this embodiment, a rectangular test area is selected, but in some embodiments, other regular or irregular test areas may also be selected. The chip chip can be cut into n rectangles of the same size, and then the rectangle in the entire rectangular area that is full of standard cell areas is selected as the test area. In the layout design of integrated circuits, a large number of standard cells are used to form circuits. Since the layout in the standard cell area is arranged according to certain rules; the standard cell area includes gate polysilicon poly, gate cut layer polycut and other contents. All operations in this example are performed in the standard cell area. The target area VLDZONE_BNY in the test area is preferably rectangular, and may also be circular or irregular. In this embodiment, the test area is divided into at least two target areas VLDZONE_BNY, and a test structure with at least two test units in parallel can be obtained later. Among them, the local test structure corresponding to each target area VLDZONE_BNY is set in parallel form, and a test port is set on each target area VLDZONE_BNY to access voltage / current. Because when the area of ​​the test area is large, the resistance of the overall series test structure is large, which will affect the test effect. Therefore, by dividing the target area VLDZONE_BNY, a gate polysilicon open circuit test structure with multiple test ports in parallel is generated, which not only reduces the total resistance but also can perform comprehensive detection on the test area at the same time, improve test quality and test efficiency, or select the test units of the target area to be tested in parallel based on test requirements.

[0072] Among them, the pickup area refers to the body area, that is, the body area. The layout is reflected as ntap of PMOS and ptap of NMOS. The pickup area is arranged in a standard manner in the standard cell area, and has obvious graphic differences from the adjacent standard cell area on some layers. The pickup area can be identified by code statements. In this embodiment, the test area is divided into at least two target areas based on the body area of ​​the standard cell area; however, in other embodiments, the test area can be divided based on other structural graphics in the standard cell according to specific application scenario requirements to obtain at least two target areas, and even in some embodiments, manual division can be performed to obtain a target area that better meets the test requirements.

[0073] Step S220 , obtaining the gate polysilicon poly in the target area VLDZONE_BNY, and covering and connecting the gate polysilicon in the target area VLDZONE_BNY in series by setting auxiliary patterns, and connecting the auxiliary patterns in at least two target areas VLDZONE_BNY in parallel.

[0074] Specifically, the auxiliary graphics include first auxiliary graphics PO_conn_all, PO_turn and second auxiliary graphics PO_conn_pin. By setting the first auxiliary graphics, the gate polysilicon in the target area VLDZONE_BNY is covered and connected in series. Since the gate polysilicon is usually arranged in parallel in a long strip shape, the covering series connection means that the first auxiliary graphics can cover the selected gate polysilicon, and the first auxiliary graphics covering the gate polysilicon are connected in series to form a continuous graphic. The first auxiliary graphics can adopt a serpentine series structure or a Z-shaped series structure. By setting the second auxiliary graphics PO_conn_pin, the first auxiliary graphics in at least two target areas VLDZONE_BNY are connected in parallel.

[0075] Step S230 , based on the gate cut layer polycut in the target area VLDZONE_BNY and the local interconnection line Metal0poly_vldzone of the metal layer M0 connected to the gate polysilicon, the gate polysilicon is screened to obtain the target gate polysilicon POseed0 .

[0076] Specifically, in order not to affect the accuracy of the judgment of the gate polysilicon disconnection, it is necessary to find the gate polysilicon that meets the test scenario in the standard cell area. First, it is necessary to exclude the part of the gate polysilicon that contacts the gate cut-off pattern polycut (that is, the floating gate cut-off pattern) inside the standard cell. Secondly, the local interconnection line of the metal layer M0 on the gate (that is, the metal interconnection line connecting the gate polysilicon) will connect some adjacent gates. It is necessary to exclude the gate polysilicon connected to this part of the metal interconnection line Metal0poly_vldzone. After excluding the gate polysilicon connected to the floating gate cut-off pattern polycut and the metal interconnection line Metal0poly_vldzone, the target gate polysilicon POseed0 is obtained.

[0077] Step S240 , determining the position of the gate through hole POseed0_chain_gateVia at the end of the target gate polysilicon POseed0 , and generating the gate through hole POseed0_chain_gateVia.

[0078] Specifically, the gate through hole POseed0_chain_gateVia is used to connect the gate polysilicon and the metal structure of the metal layer metal1.

[0079] Step S250, determine the metal layer pattern based on the auxiliary pattern and the target gate polysilicon POseed0, and generate a metal structure on the metal layer pattern; the metal structure is located on the metal layer metal1, and the metal structure is connected to the target gate polysilicon POseed0 through the gate via POseed0_chain_gateVia to complete the generation of the gate polysilicon open circuit test structure.

[0080] Specifically, the test port can be set on the metal structure, that is, on the metal layer metal1. In subsequent tests, voltage / current is applied to the gate polysilicon open circuit test structure through the test port to test the open circuit condition of the gate polysilicon in each target area VLDZONE_BNY. The gate polysilicon open circuit test structure can have at least two test units connected in parallel at the same time; the test unit is the gate polysilicon connected in series in a target area VLDZONE_BNY.

[0081] Figure 3 Schematic diagram of the gate polysilicon disconnection test structure. Figure 3 As shown, taking two target areas VLDZONE_BNY as an example, the test structure uses metal structures and gate through holes POseed0_chain_gateVia to connect the test units in the two target areas VLDZONE_BNY in parallel, so as to detect whether the gate polysilicon (i.e., the target gate polysilicon) in each test unit is open circuit. It should be noted that Figure 3 Only the gate polysilicon in the layout is retained, and other graphic information such as the gate cut layer polycut in the layout is not shown.

[0082] In this embodiment, by extracting the gate polysilicon graphic information in the standard cell area and setting the auxiliary graphics, the metal structure and gate through hole POseed0_chain_gateVia required for the test structure are generated, and the final gate polysilicon short circuit test structure capable of testing the gate polysilicon short circuit condition is obtained. Compared with the method of manually drawing graphics to generate the test structure, a lot of time is saved, the dimensions required by the design rules are better controlled, and the efficiency and quality of the test structure design are improved.

[0083] In some of the embodiments, based on the above step S210, the test area is divided into at least two target areas VLDZONE_BNY based on the body area (pickup area) of the standard cell area, including:

[0084] Step S211, obtaining a body pole region (pickup region) in the test region, and dividing the test region into at least two sub-regions of the same size based on the body pole region (pickup region).

[0085] Specifically, a body pole region (pickup region) is selected, and two sub-regions of the same size are obtained on both sides of the body pole region (pickup region). The test area may include more than one body pole region (pickup region), and at least two sub-regions can be obtained by selecting all or part of the body pole region (pickup region). The number of sub-regions can be determined according to actual needs. For example, see Figure 4 When only two sub-areas are needed, a body pole area (pickup area) near the center of the test area is selected, and the test area is divided into two parts through the body pole area (pickup area), and two sub-areas of the same size are determined in the two divided parts. In this embodiment, a relatively uniform division is performed in the test area, that is, the test area is divided into at least two sub-areas of the same size based on the body pole area (pickup area), but in other embodiments, sub-areas of different sizes can be obtained based on the test area not being uniformly divided, and this patent does not make specific limitations.

[0086] Step S212: After shrinking the sub-areas to a first preset size, a target area VLDZONE_BNY is obtained.

[0087] Specifically, the shrinking leaves space for routing between the target area VLDZONE_BNY and the sub-area.

[0088] In this embodiment, by defining sub-areas and standardizing the position and size of the target area VLDZONE_BNY, it is helpful to improve the accuracy of the design.

[0089] In some of the embodiments, see Figure 5 , Figure 6 , Figure 7 Based on the above step S220, the gate polysilicon in the target area VLDZONE_BNY is obtained, and the gate polysilicon in the target area VLDZONE_BNY is covered and connected in series by setting an auxiliary pattern, and the auxiliary patterns in at least two target areas VLDZONE_BNY are connected in parallel, specifically including the following steps:

[0090] Step S221 , obtaining the gate polysilicon in the target area VLDZONE_BNY, and setting the first auxiliary patterns PO_conn_all and PO_turn based on the gate polysilicon to cover and serpentinely connect the gate polysilicon in series.

[0091] Specifically, a first auxiliary pattern is only for the gate polysilicon in a target area VLDZONE_BNY. The first auxiliary pattern is a continuous serpentine pattern, whose width is greater than the width of the gate polysilicon, and can cover all the gate polysilicon in the current target area VLDZONE_BNY.

[0092] Step S222, determine that one end of the first auxiliary graphic is the starting end, and the other end of the first auxiliary graphic is the terminal end (corresponding to PinS21 and PinS22 of the two first auxiliary graphics); set the second auxiliary graphic PO_conn_pin based on the boundary and starting end of the target area VLDZONE_BNY, and use the second auxiliary graphic PO_conn_pin to connect the starting ends of the first auxiliary graphics in at least two target areas VLDZONE_BNY together to form a common starting end PinS1.

[0093] Specifically, the second auxiliary pattern PO_conn_pin plays a role of connecting a plurality of first auxiliary patterns in parallel.

[0094] In this embodiment, the basic framework of the test structure is constructed step by step through the first auxiliary graphic and the second auxiliary graphic PO_conn_pin.

[0095] In some of the embodiments, see Figure 5 Based on the above step S221, the gate polysilicon in the target area VLDZONE_BNY is obtained, and a first auxiliary pattern is set based on the gate polysilicon to cover and serpentinely connect the gate polysilicon in series, specifically including the following steps:

[0096] Step S221 - 1 , obtaining gate polysilicon in the target area VLDZONE_BNY, expanding the width of the gate polysilicon to a second preset size, and generating a first auxiliary pattern A (PO_conn_all).

[0097] The second preset size is a preset width of a metal structure used to generate the metal layer metal1. The preset width of the metal layer metal1 is a constant value set after comprehensive consideration of design rules and structural electrical properties.

[0098] Step S221 - 2 , adding the first auxiliary graphics B (PO_turn) at both ends of the first auxiliary graphics A (PO_conn_all) in an extended manner, and connecting the adjacent first auxiliary graphics A (PO_conn_all) end to end.

[0099] For details, see Figure 6, the first auxiliary graphic B (PO_turn) can be completed in three steps: the first step is to select the spacing area graphics between adjacent first auxiliary graphics A (PO_conn_all), and divide the spacing area graphics into Mask1 and Mask2 by adding different masks to the spacing area graphics, and Mask1 and Mask2 are set alternately. Extend the graphics of Mask1 upward by the length of the third preset size connwidth, and take the graphics of the extended part as the upper gap auxiliary graphic PO_turn_top; extend the graphics of Mask2 downward by the length of the third preset size connwidth, and take the graphics of the extended part as the lower gap auxiliary graphic PO_turn_bot. The second step is to extend the graphics of each first auxiliary graphic A (PO_conn_all) upward and downward by the length of the third preset size connwidth at the same time, and take the graphics of the extended part as the end auxiliary graphic PO_turn_pre. The third step is to merge the upper gap auxiliary graphic PO_turn_top, the lower gap auxiliary graphic PO_turn_bot and the end auxiliary graphic PO_turn_pre, and the merged graphic is recorded as the first auxiliary graphic B (PO_turn).

[0100] Step S221 - 3 , forming a first auxiliary pattern in a serpentine shape based on the first auxiliary pattern A (PO_conn_all) and the first auxiliary pattern B (PO_turn).

[0101] In this embodiment, the gate polysilicon is quickly covered and serpentine-connected in series by constructing the first auxiliary pattern A (PO_conn_all) and the first auxiliary pattern B (PO_turn) step by step.

[0102] In some of the embodiments, see Figure 7 Based on the above step S222, a second auxiliary graphic PO_conn_pin is set based on the boundary and the starting end of the target area VLDZONE_BNY, and the starting ends of the first auxiliary graphics in at least two target areas VLDZONE_BNY are connected together by using the second auxiliary graphic PO_conn_pin to form a common starting end, which specifically includes the following steps:

[0103] Step S222 - 1 , obtaining a vertical boundary close to the beginning of the first auxiliary pattern in the target area VLDZONE_BNY, and using the vertical boundary as a reference, extending a second auxiliary pattern A (PO_pin_pre0) outside the target area VLDZONE_BNY.

[0104] For details, see Figure 4, the vertical boundary is the boundary of the target area VLDZONE_BNY, at which a rectangle with a width equal to the fourth preset size barwidth and a length equal to the height of the target area VLDZONE_BNY is extended to obtain the graphic conn_pin, and the graphic conn_pin is extended upward by the distance of the fifth preset size pinendspace, and the extended graphic is recorded as the second auxiliary graphic A (PO_pin_pre0). The purpose of extending the graphic conn_pin is to leave a distance between the second auxiliary graphic B (PO_pin_pre1) and the first auxiliary graphic B (PO_turn) to avoid violating the distance required by the design rules.

[0105] Step S222 - 2 , generating a second auxiliary pattern B (PO_pin_pre1) above at least two second auxiliary patterns A (PO_pin_pre0) to connect the second auxiliary patterns A (PO_pin_pre0).

[0106] Specifically, a rectangle with a height of the sixth preset size pinwidth is used above the second auxiliary graphic A (PO_pin_pre0) to connect the second auxiliary graphics A (PO_pin_pre0), and the rectangle is recorded as the second auxiliary graphic B (PO_pin_pre1).

[0107] Step S222 - 3 , generating a second auxiliary pattern C (PO_conn_pre) between the start end of the first auxiliary pattern and the second auxiliary pattern A (PO_pin_pre0) to connect the start end of the first auxiliary pattern and the second auxiliary pattern A (PO_pin_pre0).

[0108] Specifically, based on the first auxiliary graphic generation method of step S221-1 to step S221-3, the two ends of the first auxiliary graphic are the end auxiliary graphics PO_turn_pre in the first auxiliary graphic B (PO_turn), one end is the terminal end, and the other end is the starting end. When determining the end position, the following method can be used: since the first auxiliary graphic B (PO_turn) at the edge of the first auxiliary graphic only includes the area of ​​one PO_turn_pre, and the first auxiliary graphic B (PO_turn) in the middle includes the area sum of two PO_turn_pre and one PO_turn_top / PO_turn_bot, the first auxiliary graphic B (PO_turn) at the edge can be obtained by screening the area, that is, the starting end of the first auxiliary graphic. The second auxiliary graphic C (PO_conn_pre) is generated between the first auxiliary graphic B (PO_turn) at the edge and the second auxiliary graphic A (PO_pin_pre0).

[0109] Step S222 - 4 , forming a second auxiliary pattern PO_conn_pin based on the second auxiliary pattern A (PO_pin_pre0 ), the second auxiliary pattern B (PO_pin_pre1 ), and the second auxiliary pattern C (PO_conn_pre).

[0110] In this embodiment, by constructing the second auxiliary graphic A (PO_pin_pre0), the second auxiliary graphic B (PO_pin_pre1) and the second auxiliary graphic C (PO_conn_pre) step by step, a common starting end connecting each first auxiliary graphic is constructed quickly and standardly.

[0111] In some of the embodiments, see Figure 7 Based on the above step S222, the test port of the gate polysilicon disconnection test structure includes a common start end and a terminal of at least one first auxiliary pattern, and the test port is used to detect the gate polysilicon disconnection condition of the standard cell area in the test area.

[0112] Specifically, the test port usually includes PinS1 and PinS2, that is, the common start end is used as PinS1, and the terminal of at least one first auxiliary graphic is used as PinS2. For example, there are two target areas VLDZONE_BNY in the test area, and the terminal of the first auxiliary graphic of the first target area VLDZONE_BNY is used as the first end PinS21, and the common start end is used as PinS1. After the test structure is generated, a voltage / current is connected between the input end PinS1 and the first end PinS21, and the open circuit condition of the gate polysilicon in the first target area VLDZONE_BNY can be tested. At this time, the gate polysilicon in the second target area VLDZONE_BNY is not connected to the circuit and is not used as a test object. If the terminal of the first auxiliary graphic of the first target area VLDZONE_BNY is used as the first terminal PinS21, and the terminal of the first auxiliary graphic of the second target area VLDZONE_BNY in the test area is used as the second terminal PinS22, and voltage / current is connected between PinS1&PinS21 and PinS1&PinS22, the gate polysilicon in the first target area VLDZONE_BNY and the second target area VLDZONE_BNY can be tested in parallel at the same time.

[0113] In this embodiment, the test port is set based on the common start end and the terminal of at least one first auxiliary pattern, which simplifies the setting quantity and setting method of the port.

[0114] In some of the embodiments, see Figure 8Based on the above step S230, based on the gate cut layer polycut in the target area VLDZONE_BNY and the metal interconnection line Metal0poly_vldzone connecting the gate polysilicon, the gate polysilicon is screened to obtain the target gate polysilicon POseed0, which specifically includes the following steps:

[0115] Step S231, obtaining the power line area Stdcellpowerline, the gate cut pattern polycut of the gate cut layer, and the metal interconnection line Metal0poly_vldzone connected to the gate polysilicon in the target area VLDZONE_BNY.

[0116] In step S232, the gate cutoff pattern polycut that does not overlap with the power line region Stdcellpowerline is identified as a floating gate cutoff pattern polycut_notPW.

[0117] Step S233, selecting from the gate polysilicon a pattern that does not overlap with the power line area Stdcellpowerline and does not contact the floating gate cut pattern polycut_notPW and the metal interconnection line Metal0poly_vldzone connecting the gate polysilicon as the target gate polysilicon POseed0.

[0118] In this embodiment, the first auxiliary pattern covering the gate polysilicon is first screened, and after the required first auxiliary pattern portion is screened out, the gate polysilicon corresponding to the first auxiliary pattern is determined as the target gate polysilicon; wherein, the first auxiliary pattern used to cover the gate polysilicon can adopt the first auxiliary pattern A (PO_conn_all) in step S221-1. In other embodiments, the gate polysilicon in the target area can also be directly screened, and this patent does not make specific limitations.

[0119] Specifically, the pattern of the gate cut-off layer polycut includes a long strip gate cut-off pattern polycut at the edge of the standard cell area, and the long strip gate cut-off pattern polycut is used to separate each standard cell area; the pattern of the gate cut-off layer polycut also includes a floating gate cut-off pattern polycut free inside the standard cell area. Since the long strip gate cut-off pattern polycut and the power line area Stdcellpowerline overlap, and the power line area Stdcellpowerline is regularly arranged, according to this feature, the power line area Stdcellpowerline can be used to replace the long strip gate cut-off pattern polycut, and the part of the gate polysilicon overlapping with the power line area Stdcellpowerline is directly excluded. On the other hand, based on the power line area Stdcellpowerline, the floating gate cut-off pattern polycut_notPW can also be screened out.

[0120] In this embodiment, the pattern of the gate cut layer polycut can be quickly and accurately identified and determined based on the power line area Stdcellpowerline, thereby eliminating invalid gate polysilicon.

[0121] In some of the embodiments, see Fig. 9 Based on the above step S240, the position of the gate through hole POseed0_chain_gateVia is determined at the end of the target gate polysilicon POseed0, and the gate through hole POseed0_chain_gateVia is generated, including:

[0122] Step S241 , based on the design rules, by using the pattern edge indentation processing of the target gate polysilicon POseed0 , the position of at least one gate through hole POseed0_chain_gateVia is determined in the end pattern area of ​​the target gate polysilicon POseed0 .

[0123] Specifically, according to the through hole height and the width of the metal layer metal1 required by the design rules, the horizontal edge of the target gate polysilicon POseed0 is grown inward by a distance of gateViaSizeY+gateViaEnc×2, and the graphic POseed0_chain_M1 is obtained based on the original horizontal edge and the horizontal edge after growth. The vertical edge of the graphic POseed0_chain_M1 is shrunk inward to the width of gateViaSizeX, thereby determining the position of the two vertical edges of the gate through hole POseed0_chain_gateVia, and the horizontal edges on both sides of the graphic POseed0_chain_M1 are further shrunk inward by the distance of gateViaEnc, thereby determining the position of the two horizontal edges of the gate through hole POseed0_chain_gateVia. The horizontal direction is the X-axis direction of the layout coordinate axis, and the vertical direction is the Y-axis direction of the layout coordinate axis. After the graphic edge of the target gate polysilicon POseed0 is indented, a gate via POseed0_chain_gateVia having a size of gateViaSizeX×gateViaSizeY is obtained.

[0124] In this application, a standardized operation process is provided for the design of the gate via POseed0_chain_gateVia. Through the shrinking process, the via position that meets the design rules and matches the current test structure can be obtained. Among them, data such as gateViaSizeX, gateViaSizeY, gateViaEnc, etc. can be set based on design requirements and application scenarios while meeting the design rules.

[0125] In some embodiments, determining a metal layer pattern based on the auxiliary pattern and the target gate polysilicon POseed0, and generating a metal structure based on the metal layer pattern include:

[0126] Step S251 , removing a portion of the first auxiliary pattern A (PO_conn_all) having a width of a second preset size and used to cover the target gate polysilicon POseed0 , to form a remaining pattern PO_conn_seed0 .

[0127] Step S252 , extending the remaining pattern PO_conn_seed0 to cover the gate through hole, namely POseed0_chain_M1 , and merging it with the first auxiliary pattern B (PO_turn) and the second auxiliary pattern PO_conn_pin to form a metal layer pattern.

[0128] Step S2523, generating a metal structure on the metal layer pattern.

[0129] For details, see Fig.10 , Figure 7 and Figure 3 , remove the target gate polysilicon POseed0 from the first auxiliary graphic A (PO_conn_all) to form a remaining graphic, merge the remaining graphic PO_conn_seed0, the graphic POseed0_chain_M1 obtained in the above step S241, the first auxiliary graphic B (PO_turn) and the second auxiliary graphic PO_conn_pin into a metal layer graphic, and generate a metal structure based on the metal layer graphic, that is, the metal structure of the metal layer metal1. By passing current through PinS1&PinS21, PinS1&PinS22, it can be detected whether the gate polysilicon of the standard cells in each target area VLDZONE_BNY is broken.

[0130] In the present application, by deleting and merging various patterns, a metal layer pattern suitable for the target to be tested is obtained, thereby producing a metal structure that can achieve the test purpose.

[0131] In some of the embodiments, at least two test units are connected in parallel in the gate polysilicon open circuit test structure; the test units are gate polysilicon connected in series in the target area VLDZONE_BNY.

[0132] Specifically, the gate polysilicon connected in series is the target gate polysilicon screened out in the target area VLDZONE_BNY.

[0133] In this embodiment, the metal structure is connected to the target gate polysilicon through the gate through hole to complete the generation of the gate polysilicon open circuit test structure. Through the gate polysilicon open circuit test structure, it is possible to accurately measure whether the gate polysilicon in each test unit is open circuit.

[0134] The present embodiment is described and illustrated below through preferred embodiments.

[0135] Fig.11 FIG. 1 is a flow chart of a method for generating a gate polysilicon disconnection test structure according to the preferred embodiment of the present invention. Fig.11 As shown, the method for generating the gate polysilicon open circuit test structure includes the following steps:

[0136] Step S1. Get layout information from the original layout, including: active area, gate, polycut layer for disconnecting the gate, local interconnection line of metal layer M0 on the gate, power line area, standard cell area. All operations in this example are performed in the standard cell area. Select a rectangular area for testing in the chip layout, divide the test area into two parts through the pickup area near the center of the area, and reduce the two rectangular areas to define them as VLDZONE_BNY, such as Figure 4As shown, the purpose of shrinking is to leave space for routing.

[0137] Step S2. Select the gate polysilicon pattern in the VLDZONE_BNY area, extend the vertical edge of the gate polysilicon pattern to the left and right to the preset width of the metal layer metal1, and the extended pattern is recorded as PO_conn_all. The PO_conn_all pattern is the basis for building the final serpentine test structure.

[0138] Step S3. Select the spacing area graphics between adjacent PO_conn_all graphics, and divide the spacing area graphics into Mask1 and Mask2 by adding different masks to the spacing area graphics. Extend the Mask1 graphics upward by the length of connwidth, and record the extended part of the graphics as PO_turn_top; extend the Mask2 graphics downward by the length of connwidth, and record the extended part of the graphics as PO_turn_bot.

[0139] Step S4. Extend the PO_conn_all graph upward and downward by the length of connwidth, take the extended part of the graph and record it as PO_turn_pre, merge the graphs of PO_turn_top, PO_turn_bot, and PO_turn_pre and record it as PO_turn. At this point, a snake-shaped structure consisting of PO_conn_all and PO_turn can be built inside VLDZONE_BNY.

[0140] Step S5. Extend two rectangles with a width of barwidth and a length of VLZONE_BNY height to the left from the left border of the two VLDZONE_BNY, which are recorded as conn_pin. Since the outermost PO_turn only contains the area of ​​PO_turn_pre, and the area of ​​the middle PO_turn part is composed of two PO_turn_pre and one PO_turn_top / PO_turn_bot. According to this feature, the outermost PO_turn can be obtained by screening the area, and conn_pin and the outermost PO_turn are connected. The graphic used for connection is recorded as PO_conn_pre.

[0141] Step S6. Extend the conn_pin pattern upward by the distance of pinendspace, and record the extended pattern as PO_pin_pre0, and then use a rectangle with a height of pinwidth to connect the two PO_pin_pre0, which is recorded as PO_pin_pre1. The purpose of extending conn_pin is to leave a distance between PO_pin_pre1 and PO_turn to avoid violating the distance required by the design rules.

[0142] Step S7. Combine the graphics of PO_conn_pre, PO_pin_pre0, and PO_pin_pre1 together and record them as PO_conn_pin. A snake test structure is formed by PO_conn_pin, PO_conn_all, and PO_turn. One end PinS1 is on PO_conn_pin, and the other two ends PinS21 and PinS22 are respectively on the PO_turn at the rightmost edge of the two VLDZONEs.

[0143] Step S8. After the serpentine test structure is built, it is necessary to find the gate polysilicon that meets the test scenario in the standard cell area. Since the power lines in the standard cell area are arranged regularly, there are gate cut-off layers above and below the standard cells to separate the standard cells. These gate cut-off layers that separate the standard cell area overlap with the graphics of the power lines powerline. According to this feature, the gate cut-off graphics located at the edge inside the standard cell are distinguished. And the floating gate cut-off graphics inside the standard cell are defined as polycut_notPWR. Since there is a local interconnection of the metal layer M0 on the gate to connect adjacent gates, this situation affects the judgment of the gate polysilicon disconnection. The local interconnection area of ​​the metal layer M0 on the gate is defined as Metal0poly_vldzone. Take the part that PO_conn_all does not overlap with the power line powerline, and require that these parts do not contact polycut_notPWR and Metal0poly_vldzone. The remaining graphics are recorded as POseed0.

[0144] Step S9. According to the height of the gate via gatevia required by the design rules and the surrounding distance of the metal layer metal1, the horizontal edge of POseed0 is grown inward by the length of (gateViaSizeY+gateViaEnc×2), and the resulting graph is recorded as POseed0_chain_M1. Then the width of POseed0_chain_M1 is shrunk inward in the horizontal direction to gateViaSizeX, and the resulting graph is recorded as M1chain. Finally, the upper and lower sides of M1chain are shrunk inward by the height of gateViaEnc to obtain POseed0_chain_gateVia.

[0145] Step S10: Remove the overlapping part of PO_conn_all and POseed0 from PO_conn_all, and the obtained graph is recorded as PO_conn_seed0.

[0146] Step S11. PO_conn_seed0, POseed0_chain_M1, PO_conn_turn, and PO_conn_pin are combined and output as the metal structure of metal layer metal1, and POseed0_chain_gateVia is output as the gate via. Current is passed through PinS1&PinS21, PinS1&PinS22 to detect whether the gate polysilicon of the standard cells in the two VLDZONE_BNY is broken.

[0147] The actual effect of the gate polysilicon disconnection test structure generated based on the above preferred embodiment is as follows: Fig.12 In the layout design of integrated circuits, a large number of standard cells are used to form circuits. Since the layout in the standard cell area is arranged according to certain rules, it is a very fast way to generate test structures by using scripts after obtaining layout information. This solves the problem of low efficiency and poor quality of manually building gate polysilicon test structures in related technologies, and realizes the rapid generation of test structures using scripts through the obtained layout information, thereby improving the efficiency and accuracy of test structure generation.

[0148] It should be noted that the steps shown in the above process or the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0149] In this embodiment, a device for generating a gate polysilicon open circuit test structure is also provided, and the device is used to implement the above-mentioned embodiments and preferred implementation modes, and the descriptions that have been made will not be repeated. The terms "module", "unit", "subunit", etc. used below can implement a combination of software and / or hardware of predetermined functions. Although the devices described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.

[0150] Fig.13 is a structural block diagram of a device for generating a gate polysilicon disconnection test structure according to this embodiment. Figure 6 As shown, the device includes: a target area generation module 10, an auxiliary pattern generation module 20, a target gate polysilicon generation module 30, a gate through hole generation module 40 and a test structure generation module 50.

[0151] The target region generating module 10 is used to obtain a layout, determine a test region in a standard cell region of the layout, and divide the test region into at least two target regions.

[0152] The auxiliary pattern generation module 20 is used to obtain the gate polysilicon in the target area, cover and connect the gate polysilicon in the target area in series by setting auxiliary patterns, and connect the auxiliary patterns in the at least two target areas in parallel.

[0153] The target gate polysilicon screening module 30 is used to screen the gate polysilicon to obtain the target gate polysilicon based on the gate cut-off layer in the target area and the metal interconnection line connecting the gate polysilicon.

[0154] The gate through hole generating module 40 is used to determine the position of the gate through hole at the end of the target gate polysilicon and generate the gate through hole.

[0155] The test structure generation module 50 is used to determine the metal layer pattern based on the auxiliary pattern and the target gate polysilicon, and generate a metal structure based on the metal layer pattern; the metal structure is connected to the target gate polysilicon through the gate through hole to complete the generation of the gate polysilicon open circuit test structure.

[0156] In some embodiments, the target area generation module 10 is also used to obtain the body pole area in the test area, and divide the test area into at least two sub-areas of the same size based on the body pole area; after shrinking the sub-areas by a first preset size, the target area is obtained.

[0157] In some of the embodiments, the auxiliary graphic generation module 20 is further used to obtain the gate polysilicon in the target area, set a first auxiliary graphic based on the gate polysilicon to cover and serpentinely connect the gate polysilicon in series; determine one end of the first auxiliary graphic as the starting end, and the other end of the first auxiliary graphic as the terminal end; set a second auxiliary graphic based on the boundary of the target area and the starting end, and use the second auxiliary graphic to connect the starting ends of the first auxiliary graphics in the at least two target areas together to form a common starting end.

[0158] In some of the embodiments, the auxiliary graphic generation module 20 is further used to obtain the gate polysilicon in the target area, expand the width of the gate polysilicon to a second preset size, and generate the first auxiliary graphic A; add the first auxiliary graphic B at both ends of the first auxiliary graphic A in an extended manner to connect the adjacent first auxiliary graphics A end to end; based on the first auxiliary graphic A and the first auxiliary graphic B, a serpentine first auxiliary graphic is formed.

[0159] In some of the embodiments, the auxiliary graphic generation module 20 is also used to obtain a vertical boundary in the target area close to the starting end of the first auxiliary graphic, and use the vertical boundary as a reference to expand a second auxiliary graphic A outside the target area; generate a second auxiliary graphic B above at least two second auxiliary graphics A to connect each of the second auxiliary graphics A; generate a second auxiliary graphic C between the starting end of the first auxiliary graphic and the second auxiliary graphic A to connect the starting end of the first auxiliary graphic and the second auxiliary graphic A; and form a second auxiliary graphic based on the second auxiliary graphic A, the second auxiliary graphic B and the second auxiliary graphic C.

[0160] In some of the embodiments, in the auxiliary graphic generation module 20, the test port of the gate polysilicon open circuit test structure includes the common start end and the terminal of at least one first auxiliary graphic, and the test port is used to detect the gate polysilicon open circuit condition of the standard cell area in the test area.

[0161] In some of the embodiments, the target gate polysilicon generation module 30 is further used to obtain the power line area, the gate cut-off pattern of the gate cut-off layer and the metal interconnection line connecting the gate polysilicon in the target area; identify the gate cut-off pattern that does not overlap with the power line area as a floating gate cut-off pattern; and screen out a pattern from the gate polysilicon that does not overlap with the power line area and does not contact the floating gate cut-off pattern and the metal interconnection line connecting the gate polysilicon as the target gate polysilicon.

[0162] In some of the embodiments, the gate via generation module 40 is further used to determine the position of at least one gate via within the end of the target gate polysilicon graphic region based on design rules and utilizing the graphic edge indentation processing of the target gate polysilicon.

[0163] In some of the embodiments, the test structure generation module 50 is further used to remove the portion of the first auxiliary graphic A having a width of a second preset size used to cover the target gate polysilicon to form a remaining graphic; extend the remaining graphic to cover the gate through hole, and merge it with the first auxiliary graphic B and the second auxiliary graphic to form a metal layer graphic; and generate a metal structure based on the metal layer graphic.

[0164] In some of the embodiments, at least two test units are connected in parallel in the gate polysilicon open circuit test structure; the test units are the gate polysilicon connected in series in the target area.

[0165] It should be noted that the above modules can be functional modules or program modules, and can be implemented by software or hardware. For modules implemented by hardware, the above modules can be located in the same processor; or the above modules can be located in different processors in any combination.

[0166] In this embodiment, a computer device is further provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0167] Optionally, the computer device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0168] It should be noted that the specific examples in this embodiment can refer to the examples described in the above embodiments and optional implementation modes, and will not be repeated in this embodiment.

[0169] In addition, in combination with the method for generating a gate polysilicon disconnection test structure provided in the above embodiments, a storage medium may be provided in the present embodiment for implementation. The storage medium stores a computer program; when the computer program is executed by a processor, any method for generating a gate polysilicon disconnection test structure in the above embodiments is implemented.

[0170] It should be understood that the specific embodiments described herein are only used to explain the application, rather than to limit it. Based on the embodiments provided in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the protection scope of this application.

[0171] Obviously, the drawings are only some examples or embodiments of the present application. For ordinary technicians in the field, the present application can also be applied to other similar situations based on these drawings without creative work. In addition, it is understandable that although the work done in this development process may be complicated and lengthy, for ordinary technicians in the field, certain changes in design, manufacturing or production based on the technical content disclosed in this application are only conventional technical means and should not be regarded as insufficient content disclosed in this application.

[0172] The term "embodiment" in this application refers to a specific feature, structure or characteristic described in conjunction with the embodiment that can be included in at least one embodiment of the present application. The appearance of this phrase in various locations in the specification does not necessarily mean the same embodiment, nor does it mean that it is mutually exclusive with other embodiments and is independent or optional. It is clearly or implicitly understood by those of ordinary skill in the art that the embodiments described in this application can be combined with other embodiments without conflict.

[0173] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of patent protection. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the scope of protection of the present application. Therefore, the scope of protection of the present application shall be subject to the attached claims.

Claims

1. A method for generating a gate polysilicon disconnection test structure, characterized in that: The method comprises: Acquire a layout, determine a test area in a standard cell area of ​​the layout, and divide the test area into at least two target areas; Obtaining gate polysilicon in the target area, and by setting auxiliary patterns, covering and connecting the gate polysilicon in the target area in series, and connecting the auxiliary patterns in the at least two target areas in parallel; Based on the gate cut-off layer in the target area and the metal interconnection line connected to the gate polysilicon, screening the gate polysilicon to obtain target gate polysilicon; Determine the position of a gate through hole at the end of the target gate polysilicon and generate the gate through hole; A metal layer pattern is determined based on the auxiliary pattern and the target gate polysilicon, and a metal structure is generated based on the metal layer pattern; the metal structure is connected to the target gate polysilicon through the gate via, completing the generation of the gate polysilicon open circuit test structure.

2. The method for generating a gate polysilicon disconnection test structure according to claim 1, characterized in that: The step of dividing the test area into at least two target areas comprises: Acquire a body pole region in the test region, and divide the test region into at least two sub-regions of the same size based on the body pole region; After shrinking the sub-areas to a first preset size, a target area is obtained.

3. The method for generating a gate polysilicon disconnection test structure according to claim 1, characterized in that: The obtaining of the gate polysilicon in the target area, covering and connecting the gate polysilicon in the target area in series by setting an auxiliary pattern, and connecting the auxiliary patterns in the at least two target areas in parallel, comprises: Obtaining gate polysilicon in the target area, and setting a first auxiliary pattern based on the gate polysilicon to cover and serpentinely connect the gate polysilicon in series; Determine one end of the first auxiliary graphic as the starting end, and the other end of the first auxiliary graphic as the terminal end; set a second auxiliary graphic based on the boundary of the target area and the starting end, and use the second auxiliary graphic to connect the starting ends of the first auxiliary graphics in the at least two target areas together to form a common starting end.

4. The method for generating a gate polysilicon disconnection test structure according to claim 3, characterized in that: Obtaining gate polysilicon in the target area, and setting a first auxiliary pattern based on the gate polysilicon to cover and serpentinely connect the gate polysilicon in series, including: Acquire gate polysilicon in the target area, expand the width of the gate polysilicon to a second preset size, and generate the first auxiliary pattern A; Adding first auxiliary graphics B at both ends of the first auxiliary graphics A in an extended manner to connect the adjacent first auxiliary graphics A end to end; Based on the first auxiliary pattern A and the first auxiliary pattern B, a first auxiliary pattern in a serpentine shape is formed.

5. The method for generating a gate polysilicon disconnection test structure according to claim 3, characterized in that: The step of setting a second auxiliary graphic based on the boundary of the target area and the starting end, and connecting the starting ends of the first auxiliary graphics in the at least two target areas together to form a common starting end by using the second auxiliary graphic, comprises: Acquire a vertical boundary in the target area close to the starting end of the first auxiliary figure, and use the vertical boundary as a reference to expand a second auxiliary figure A outside the target area; generating a second auxiliary pattern B above at least two second auxiliary patterns A to connect the second auxiliary patterns A; generating a second auxiliary graphic C between the starting end of the first auxiliary graphic and the second auxiliary graphic A to connect the starting end of the first auxiliary graphic and the second auxiliary graphic A; Based on the second auxiliary pattern A, the second auxiliary pattern B, and the second auxiliary pattern C, a second auxiliary pattern is formed.

6. The method for generating a gate polysilicon disconnection test structure according to claim 3, characterized in that: The test port of the gate polysilicon disconnection test structure includes the common start end and at least one terminal of the first auxiliary pattern, and the test port is used to detect the gate polysilicon disconnection situation of the standard cell area in the test area.

7. The method for generating a gate polysilicon disconnection test structure according to claim 1, characterized in that: Based on the gate cut-off layer in the target area and the metal interconnection line connected to the gate polysilicon, the gate polysilicon is screened to obtain the target gate polysilicon, comprising: Acquire a power line region, a gate cutoff pattern of a gate cutoff layer, and a metal interconnection line connected to gate polysilicon in the target region; identifying the gate cut-off pattern that does not overlap with the power line region as a floating gate cut-off pattern; A pattern that does not overlap with the power line region and does not contact the floating gate cutoff pattern and the metal interconnection line connecting the gate polysilicon is selected from the gate polysilicon as the target gate polysilicon.

8. The method for generating a gate polysilicon disconnection test structure according to claim 1, characterized in that: Determining the position of a gate through hole at an end of the target gate polysilicon and generating the gate through hole, comprising: Based on the design rules, the position of at least one gate through hole is determined within the end of the target gate polysilicon pattern region by utilizing the target gate polysilicon pattern edge shrinking process.

9. The method for generating a gate polysilicon disconnection test structure according to claim 4, characterized in that: Determining a metal layer pattern based on the auxiliary pattern and the target gate polysilicon, and generating a metal structure based on the metal layer pattern, including: Removing a portion of the first auxiliary pattern A having a width of a second preset size and used for covering the target gate polysilicon to form a remaining pattern; Extending the remaining pattern to cover the gate through hole, and merging it with the first auxiliary pattern B and the second auxiliary pattern to form a metal layer pattern; A metal structure is generated based on the metal layer pattern.

10. The method for generating a gate polysilicon disconnection test structure according to claim 1, characterized in that: At least two test units are connected in parallel in the gate polysilicon disconnection test structure; the test units are the gate polysilicon connected in series in the target area.

11. A device for generating a gate polysilicon disconnection test structure, characterized in that: The device comprises: A target area determination module, used to obtain a layout, determine a test area in a standard cell area of ​​the layout, and divide the test area into at least two target areas; An auxiliary pattern generation module, used for obtaining the gate polysilicon in the target area, covering and connecting the gate polysilicon in the target area in series by setting an auxiliary pattern, and connecting the auxiliary patterns in the at least two target areas in parallel; A target gate polysilicon screening module, used for screening the gate polysilicon to obtain target gate polysilicon based on the gate cut-off layer in the target area and the metal interconnection line connecting the gate polysilicon; A gate through hole generation module, used to determine the position of the gate through hole at the end of the target gate polysilicon and generate the gate through hole; A test structure generation module is used to determine a metal layer pattern based on the auxiliary pattern and the target gate polysilicon, and to generate a metal structure based on the metal layer pattern; the metal structure is connected to the target gate polysilicon through the gate through hole to complete the generation of the gate polysilicon open circuit test structure.

12. A gate polysilicon disconnection test structure, characterized in that: The test structure is generated based on the method described in any one of claims 1 to 10; The test structure includes: target gate polysilicon, a metal structure and a gate through hole; the metal structure is connected to the target gate polysilicon in the standard cell area through the gate through hole.

13. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method for generating a gate polysilicon disconnect test structure according to any one of claims 1 to 10 are implemented.

14. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method for generating a gate polysilicon disconnection test structure according to any one of claims 1 to 10 are implemented.

Images