Array substrate, display panel and display device

Abstract

The application provides an array substrate, a display panel and a display device to improve color deviation of a double-gate array substrate and to easily cause crosstalk. The array substrate comprises a substrate, a plurality of data lines, the data lines comprising a first data part and a second data part arranged in sequence between adjacent gate line groups and extending along a second direction, wherein an extension line of the first data part and an extension line of the second data part do not overlap; a projection of the first data part on the substrate has an overlapping area with a side edge area of the pixel electrode in a projection of the substrate; and a projection of the second data part on the substrate has an overlapping area with a side edge area of another adjacent pixel electrode in a projection of the substrate.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more particularly to an array substrate, a display panel, and a display device. Background Technology

[0002] Dual-gate display products reduce the number of source ICs by increasing the number of gate lines and decreasing the number of data lines, thereby reducing costs.

[0003] VA display products, after undergoing ultraviolet-induced multi-domain vertical alignment (UV2A), such as Figure 1 As shown, for the dark fringes in the center of the pixel and the dark fringes on both sides (such as...) Figure 1 When viewed from the side (as seen in the black stripes), the liquid crystal molecules are viewed from the side along their long axis. Due to the birefringence of the liquid crystal, light leakage occurs in the UV2A alignment display mode. Furthermore, the different refractive indices of the different insulating layers in the display substrate cause color shift in the transmitted light from the side. In addition, existing dual-gate structure display panels are prone to crosstalk problems. Summary of the Invention

[0004] The present invention provides an array substrate, a display panel, and a display device to improve the color shift and crosstalk problems present in dual-gate array substrates.

[0005] This invention provides an array substrate, comprising:

[0006] Substrate;

[0007] Multiple gate line groups are located on one side of the substrate and extend along a first direction, wherein one of the multiple gate line groups includes two gate lines extending along the first direction;

[0008] Multiple data lines are located on the same side of the substrate as the gate line group; the multiple data lines extend along a second direction; each data line includes a first data portion and a second data portion located between adjacent gate line groups, extending along the second direction and arranged sequentially, wherein the extension lines of the first data portion and the extension lines of the second data portion do not overlap;

[0009] a plurality of pixel electrode groups, which are located at the same side of the substrate as the gate lines, and at least part of the pixel electrode groups are located in the regions where the gate line groups and the data lines cross; each of the pixel electrode groups comprises two pixel electrodes arranged along the first direction, and the two pixel electrodes of the same pixel electrode group are connected to the gate lines of different gate line groups;

[0010] wherein the first data portion has an overlapping region with the side edge region of the pixel electrode in the orthographic projection of the substrate, and the second data portion has an overlapping region with the side edge region of another pixel electrode in the orthographic projection of the substrate.

[0011] In a possible implementation, the data line further comprises a third data portion extending along the first direction and connecting the first data portion and the second data portion; an extension line of the third data portion passes through the central region of the pixel electrode in the orthographic projection of the substrate.

[0012] In a possible implementation, the array substrate further comprises a first shielding trace located in the region where the gate line groups and the data lines cross; the first shielding trace comprises a first shielding portion and a second shielding portion arranged along the second direction in sequence, wherein an extension line of the first shielding portion does not overlap with an extension line of the second shielding portion.

[0013] the first shielding portion has an overlapping region with the side edge region of one of the pixel electrodes in the orthographic projection of the substrate, and the second shielding portion has an overlapping region with the side edge region of another of the pixel electrodes in the orthographic projection of the substrate.

[0014] In a possible implementation, the display substrate further comprises a third shielding portion extending along the first direction and connecting the first shielding portion and the second shielding portion; an extension line of the third shielding portion passes through the central region of the pixel electrode in the orthographic projection of the substrate.

[0015] In a possible implementation, the array substrate comprises a first sub-pixel emitting a first light wave band, a second sub-pixel emitting a second light wave band, and a third sub-pixel emitting a third light wave band; the wavelength of the first light wave band is greater than the wavelength of the second light wave band, and the wavelength of the second light wave band is greater than the wavelength of the third light wave band.

[0016] The array substrate further includes a second shielding trace extending along the second direction, a projection of the second shielding trace on the substrate is located in the region where the pixel electrode of the first sub-pixel is located, and the second shielding trace passes through the central region of the pixel electrode of the first sub-pixel.

[0017] In a possible implementation, the array substrate further includes a transistor first electrode arranged in the same layer as the data line, the transistor first electrode includes a first portion extending along the second direction, a projection of the first portion on the substrate is located in the region where the pixel electrode is located;

[0018] The extending direction of the second shielding trace overlaps the extending direction of the first portion of the first sub-pixel, and the projection of the second shielding trace on the substrate does not overlap the projection of the first portion on the substrate.

[0019] In a possible implementation, the first portion of the second sub-pixel passes through the central region of the pixel electrode; and the first portion of the third sub-pixel does not overlap the center of the pixel electrode.

[0020] In a possible implementation, the array substrate further includes a third shielding trace located between adjacent gate groups and extending along the first direction.

[0021] The first shielding trace and the second shielding trace are electrically connected to the third shielding trace.

[0022] In a possible implementation, the first shielding trace, the second shielding trace, and the third shielding trace are located in the same layer as the gate line.

[0023] In a possible implementation, a projection of the pixel electrode on the substrate covers at least part of a projection of the gate line on the substrate.

[0024] In a possible implementation, the gate line includes a first type of gate line located on one side of the pixel electrode and a second type of gate line located on the other side of the pixel electrode; a signal loaded on the second type of gate line is delayed relative to a signal loaded on the first type of gate line.

[0025] The pixel electrode includes a first type of pixel electrode and a second type of pixel electrode, wherein the first type of pixel electrode loads the signal of the first type of gate line, and the second type of pixel electrode loads the signal of the second type of gate line; an overlapping area of a projection of the second type of pixel electrode on the substrate and a projection of the second type of gate line on the substrate is greater than an overlapping area of a projection of the first type of pixel electrode on the substrate and a projection of the first type of gate line on the substrate.

[0026] In a possible implementation, the pixel electrode covers the first data portion in the orthographic projection of the substrate, and covers the second data portion in the orthographic projection of the substrate.

[0027] In a possible implementation, the pixel electrode covers the first data portion in the orthographic projection of the substrate, and covers the second data portion in the orthographic projection of the substrate.

[0028] The display panel provided in the embodiments of the present disclosure comprises the array substrate provided in the embodiments of the present disclosure, and further comprises a counter substrate opposite to the array substrate, wherein the counter substrate is provided with a common electrode layer.

[0029] The display device provided in the embodiments of the present disclosure comprises the display panel provided in the embodiments of the present disclosure.

[0030] The display panel provided in the embodiments of the present disclosure comprises the array substrate provided in the embodiments of the present disclosure.

[0031] The display panel provided in the embodiments of the present disclosure comprises the array substrate provided in the embodiments of the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0032] Figure 1 FIG. 1 is a schematic diagram of a pixel electrode dark line position;

[0033] Figure 2A FIG. 3 is a schematic diagram of an array substrate provided in the embodiments of the present disclosure;

[0034] Figure 2B FIG. 5 is a schematic diagram of a single film layer of a gate line layer in the embodiments of the present disclosure; Figure 2A

[0035] ​Figure 2C Figure 1 is a schematic diagram of a single film layer of an active layer in the present application; Figure 2A Figure 2 is a schematic diagram of a single film layer of a data line layer in the present application;

[0036] Figure 2D Figure 3 is a schematic diagram of a single film layer of a pixel electrode layer in the present application; Figure 2A Figure 4 is a schematic diagram of a single film layer of a color filter layer in the present application;

[0037] Figure 2E Figure 5 is a schematic diagram of an array substrate provided by the present application; Figure 2A Figure 6 is a schematic diagram of a pixel electrode layer in the present application;

[0038] Figure 3A Figure 7 is a schematic diagram of the array substrate provided by the present application when the data line and the pixel electrode do not deviate;

[0039] Figure 3B Figure 8 is a schematic diagram of the array substrate provided by the present application when the data line and the pixel electrode deviate;

[0040] Figure 4A Figure 9 is a schematic diagram of the array substrate provided by the present application;

[0041] Figure 4B Figure 10 is a schematic diagram of a single film layer of a pixel electrode layer in the present application; Figure 4A

[0042] Figure 11 is a schematic diagram of the array substrate provided by the present application; Figure 5A

[0043] Figure 12 is a schematic diagram of a single film layer of a color filter layer in the present application; Figure 5B Figure 5A Figure 13 is a schematic diagram of the alignment direction of an alignment film.

[0044] Figure 6 DETAILED DESCRIPTION

[0045] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without any inventive effort fall within the protection scope of the present disclosure.

[0046] ​​Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the meanings as understood by a person of ordinary skill in the art to which the present disclosure pertains. The terms "first", "second", and similar terms are used herein to distinguish one element from another, but do not imply an order or sequence unless otherwise defined. The terms "comprises", "comprising", "includes", "including" and the like are meant to be inclusive and not exclusive, and specify the presence of stated elements or integers but not to the exclusion of others. The terms "connected", "coupled", and the like, mean to be directly or indirectly connected or coupled, and can include electrical connections, whether direct or indirect. The terms "upper", "lower", "left", "right", and the like, are used to denote relative positions, and can change when the absolute position of the described object changes.

[0047] As used herein, "about" or "approximately" means within a range that is acceptable to a person of ordinary skill in the art considering the measurement and error (i.e., limitations of the measurement system) associated with the measurement of the particular quantity. For example, "about" can mean within one or more standard deviations, or within ±30%, 20%, 10%, 5% of the stated value.

[0048] In the drawings, the thicknesses of layers, films, panels, regions, etc., are exaggerated for clarity. Exemplary embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments described herein are not to be construed as being limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an area illustrated or described as flat can typically have rough and / or nonlinear features. Moreover, sharp angles that are illustrated can be rounded. Thus, the regions illustrated in the figures are schematic and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the present claims.

[0049] In order to keep the following description of the embodiments of the present disclosure clear and concise, detailed description of known functions and known components will be omitted.

[0050] Referring to Figures 2A-2E As shown, the embodiment of the present application provides an array substrate, comprising:

[0051] a substrate 1;

[0052] a plurality of gate line groups 2 located on one side of the substrate 1 and extending along a first direction X, one gate line group 2 of the plurality of gate line groups 2 comprising: two gate lines 20 extending along the first direction X;

[0053] The plurality of data lines 3 are located on the same side of the substrate 1 as the gate line groups 2; the plurality of data lines 3 extend along the second direction Y; the data lines 3 include first data portions 31 and second data portions 32 which are arranged in sequence between adjacent gate line groups 2 and extend along the second direction Y, wherein the extension line of the first data portion 31 does not overlap the extension line of the second data portion 32;

[0054] The plurality of pixel electrode groups 4 are located on the same side of the substrate 1 as the gate lines 20, and at least part of the pixel electrode groups 4 are located in the regions formed by the intersection of the gate line groups 2 and the data lines 3; the pixel electrode groups 4 include two pixel electrodes 40 arranged along the first direction, and the two pixel electrodes 40 of the same pixel electrode group 4 correspond to the gate lines 20 of different gate line groups 2, that is, the two pixel electrodes 40 are electrically connected to different gate lines through transistors;

[0055] The first data portion 31 has an overlapping region in the orthographic projection of the substrate 1 with the side edge region of the pixel electrode 40 in the orthographic projection of the substrate 1; and the second data portion 32 has an overlapping region in the orthographic projection of the substrate 1 with the side edge region of the adjacent other pixel electrode 40 in the orthographic projection of the substrate 1.

[0056] In the embodiments of the present disclosure, the data lines 3 include first data portions 31 and second data portions 32 which are arranged in sequence between adjacent gate line groups 2 and extend along the second direction Y, wherein the extension line of the first data portion 31 does not overlap the extension line of the second data portion 32, and the first data portion 31 has an overlapping region in the orthographic projection of the substrate 1 with the side edge region of the pixel electrode 40 in the orthographic projection of the substrate 1; and the second data portion 32 has an overlapping region in the orthographic projection of the substrate 1 with the side edge region of the adjacent other pixel electrode 40 in the orthographic projection of the substrate 1. When the array substrate is applied to a display panel, the dark lines existing in the double-gate structure display panel in the UV2A mode can be shielded, and the color cast defect in the UV2A mode can be improved. Moreover, the position of the dark lines generated by the folded data line 3 and the pixel electrode 4 coincide, which can avoid the case that the dark area of the display panel as a whole is large when the two do not overlap completely, and thus the transmittance of the display panel can be improved. In addition, when the data line is offset due to manufacturing defects (for example, as shown in FIGS. 1B and 1C, wherein FIG. 1B is a schematic view of the data line not being offset, and FIG. 1C is a schematic view of the data line being offset), the data line of the present application can have the same pulling effect on the voltage loaded on the pixel electrode, so that the capacitance Cpd formed by the pixel electrode and the data line remains unchanged, and the risk of crosstalk of the display panel is reduced. Figure 3A and Figure 3B As shown in the figures, Figure 3A is a schematic view of the data line not being offset, Figure 3B is a schematic view of the data line being offset), the data line of the present application can have the same pulling effect on the voltage loaded on the pixel electrode, so that the capacitance Cpd formed by the pixel electrode and the data line remains unchanged, and the risk of crosstalk of the display panel is reduced.

[0057] In a possible implementation, referring to Figures 2A-2EAs shown in FIG. 1, the data line 3 further includes a third data portion 33 extending along the first direction X and connecting the first data portion 31 and the second data portion 32; an extension line of the third data portion 33 passes through a central region of a projection of the pixel electrode 40 on the substrate 1. In the embodiment of the present disclosure, the third data portion 33 extends along the first direction X, and the extension line passes through the central region of the projection of the pixel electrode 40 on the substrate 1, so that a new dark region of the display panel can be avoided.

[0058] Specifically, the third data portion 33 can also have other shapes, for example, a diagonal line shape, a curve shape, or a polyline shape, etc.

[0059] In a possible implementation, referring to FIG. 1, Figures 2A-2E As shown in FIG. 1, the array substrate further includes a first shielding wire 51 located in an intersection region of the gate group 2 and the data line 3, and the first shielding wire 51 includes a first shielding portion 511 and a second shielding portion 512 extending along the second direction Y and arranged in sequence, wherein an extension line of the first shielding portion 511 does not overlap with an extension line of the second shielding portion 512; a projection of the first shielding portion 511 on the substrate 1 has an overlapping region with a side edge region of one of the pixel electrodes 40 in the pixel electrode group 4 on the substrate 1; and a projection of the second shielding portion 512 on the substrate 1 has an overlapping region with a side edge region of another of the pixel electrodes 40 in the pixel electrode group 4 on the substrate 1.

[0060] In the embodiment of the present disclosure, since the double-gate structure display panel, there is no data line 3 between the two pixel electrodes 40 in the pixel electrode group 4, and the bent data line 3 cannot shield the dark lines on the side away from the data line 3 of the two pixel electrodes 40. In the embodiment of the present disclosure, by arranging the first shielding wire 51 in a bent type, the dark region on the side away from the data line 3 of the two pixel electrodes 40 in the pixel electrode group 4 can be shielded, and the pixel electrode and the shielding wire overlap in a direction perpendicular to the substrate, so that a storage capacitor can be formed.

[0061] In a possible implementation, referring to FIG. 1, Figures 2A-2E As shown in FIG. 1, the array substrate further includes a first shielding wire 51 located in an intersection region of the gate group 2 and the data line 3, and the first shielding wire 51 includes a first shielding portion 511 and a second shielding portion 512 extending along the second direction Y and arranged in sequence, wherein an extension line of the first shielding portion 511 does not overlap with an extension line of the second shielding portion 512; a projection of the first shielding portion 511 on the substrate 1 has an overlapping region with a side edge region of one of the pixel electrodes 40 in the pixel electrode group 4 on the substrate 1; and a projection of the second shielding portion 512 on the substrate 1 has an overlapping region with a side edge region of another of the pixel electrodes 40 in the pixel electrode group 4 on the substrate 1.

[0062] Specifically, the third shielding portion 513 can also have other shapes, for example, a diagonal line shape, a curve shape, or a polyline shape, etc.

[0063] In a possible implementation, referring to Figures 2A-2E As shown in the figure, the array substrate includes: a first sub-pixel P1 emitting a first light wave band, a second sub-pixel P2 emitting a second light wave band, and a third sub-pixel P3 emitting a third light wave band; the wavelength of the first light wave band is greater than the wavelength of the second light wave band, and the wavelength of the second light wave band is greater than the wavelength of the third light wave band; specifically, the first light wave band can be red light, the second light wave band can be green light, and the third light wave band can be blue light, that is, the first sub-pixel P1 can be a red sub-pixel emitting red light, the second sub-pixel P2 can be a green sub-pixel emitting green light, and the third sub-pixel P3 can be a blue sub-pixel emitting blue light; the array substrate further includes a second shielding trace 52 extending along the second direction Y, and the orthogonal projection of the second shielding trace 52 on the substrate 1 is located in the area where the pixel electrode 40 of the first sub-pixel P1 is located, and the second shielding trace 52 passes through the central area of the pixel electrode 40 of the first sub-pixel P1.

[0064] In the embodiments of the present disclosure, the first sub-pixel P1 further has a second shielding trace 52 extending along the second direction Y, and the second shielding trace 52 passes through the central area of the pixel electrode 40 of the first sub-pixel P1, which can shield the vertical dark stripes of the first sub-pixel P1 at the center.

[0065] In a possible implementation, referring to Figures 2A-2E As shown in the figure, the array substrate further includes a transistor first electrode 34 arranged in the same layer as the data line 3, and the transistor first electrode 34 includes: a first part 341 extending along the second direction Y, and the orthogonal projection of the first part 341 on the substrate 1 is located in the area where the pixel electrode 4 is located; the extension direction of the second shielding trace 52 overlaps the extension direction of the first part 341 of the first sub-pixel P1, and the orthogonal projection of the second shielding trace 52 on the substrate 1 does not overlap the orthogonal projection of the first part 341 on the substrate 1, that is, the second shielding trace 52 is located on the side of the first part 341 away from the gate line 20 connected to the first part 341, referring to Figure 2A , the transistor in the case is arranged in the area between the first sub-pixel P1 and the second sub-pixel P2.

[0066] In a possible implementation, referring to Figures 2A-2E As shown in the figure, the first part 341 of the second sub-pixel P2 passes through the central area of the pixel electrode 40; and the first part 341 of the third sub-pixel P3 does not overlap the center of the pixel electrode 4.

[0067] In the embodiments of the present disclosure, the first sub-pixel P1 is provided with the second shielding trace 52 and the first portion 341, which realizes complete shielding of the central vertical dark lines, so that the first sub-pixel P1 does not leak light (optionally, completely does not leak light) when viewed from the side of the central vertical dark lines; the first portion 341 in the second sub-pixel P2 shields half of the central vertical dark lines, so that the second sub-pixel P2 partially does not leak light when viewed from the side of the central vertical dark lines; the first portion 341 in the third sub-pixel P3 does not overlap with the center of the pixel electrode 4, that is, the first portion 341 in the third sub-pixel P3 does not shield the central vertical dark lines, so that the third sub-pixel P3 completely leaks light or the degree of light leakage is greater than that of the second sub-pixel P2 when viewed from the side of the central vertical dark lines, that is, the degrees of light leakage of the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P3 gradually increase, which can improve the large-viewing-angle color deviation phenomenon of the VA display mode and make the color difference between the side viewing angle and the normal viewing angle smaller.

[0068] In a possible implementation, referring to FIG. 1, the array substrate further includes a third shielding trace 53 located between adjacent gate groups 2 and extending along the first direction X; the first shielding trace 51 and the second shielding trace 52 are electrically connected to the third shielding trace 53. Figures 2A-2E

[0069] In a possible implementation, referring to FIG. 1, the first shielding trace 51, the second shielding trace 52 and the third shielding trace 53 are located in the same layer as the gate line 20. In this way, the first shielding trace 51, the second shielding trace 52 and the third shielding trace 53 are formed at the same time as the gate line 20 is formed, so as to simplify the manufacturing process of the array substrate. Figures 2A-2E

[0070] In a possible implementation, the first shielding trace 51 further includes a transition portion 5120 connected to an end of the second shielding portion 512, and the array substrate further includes a lap joint portion 43 arranged in the same layer as the pixel electrode 40. The transition portion 43 electrically connects the first shielding traces 51 on both sides of the gate line group 2 through a via hole, so as to form an integrated conduction structure of the first shielding traces 51 and the third shielding traces 53 in different rows.

[0071] In a possible implementation, the first shielding trace 51, the second shielding trace 52 and the third shielding trace 52 can be reused as a common signal trace to transmit a common signal, which can be the same as a signal loaded on a common electrode of the opposite substrate.

[0072] In a possible implementation, referring to FIG. 1, the first shielding trace 51, the second shielding trace 52 and the third shielding trace 53 can be reused as a common signal trace to transmit a common signal, which can be the same as a signal loaded on a common electrode of the opposite substrate. Figures 2A-2E ​​As shown, the orthogonal projection of the pixel electrode 40 on the substrate 1 covers at least part of the orthogonal projection of the gate line 20 on the substrate 1. Specifically, the orthogonal projection of the pixel electrode 40 on the substrate 1 can cover the entire orthogonal projection of the gate line 20 on the substrate 1. In the embodiment of the present disclosure, the orthogonal projection of the pixel electrode 40 on the substrate 1 covers at least part of the orthogonal projection of the gate line 20 on the substrate 1, that is, the area of the pixel electrode 40 can be increased, the display area of the display panel can be improved, the light transmittance of the display panel can be effectively increased, and the line width of the black matrix can be reduced.

[0073] In a possible implementation, referring to Figures 2A-2E As shown, the gate line 2 includes a first type of gate line 21 located on one side of the pixel electrode 40 and a second type of gate line 22 located on the other side of the pixel electrode 40; the signal loaded on the second type of gate line 22 is delayed relative to the signal loaded on the first type of gate line 21; that is, the loading process of the gate scanning signal is preferentially through the first type of gate line 21 and then through the second type of gate line 22. It should be noted that the delay here also refers to opening the corresponding gate line 20 in turn; the pixel electrode 40 includes a first type of pixel electrode and a second type of pixel electrode, wherein the first type of pixel electrode is loaded with the signal of the first type of gate line, and the second type of pixel electrode is loaded with the signal of the second type of gate line; the first type of pixel electrode 41 is electrically connected to the first type of gate line 21 through a transistor, and the gate of the transistor is electrically connected to the first type of gate line 21, that is, the first type of pixel electrode 41 is electrically connected to the first type of gate line 21 through a transistor; and the second type of pixel electrode 42 is electrically connected to the second type of gate line 22 through a transistor, and the gate of the transistor is electrically connected to the second type of gate line 22, that is, the second type of pixel electrode 42 is electrically connected to the second type of gate line 22 through a transistor; the overlapping area of the orthogonal projection of the second type of pixel electrode 41 on the substrate 1 and the orthogonal projection of the second type of gate line 22 on the substrate 1 is greater than the overlapping area of the orthogonal projection of the first type of pixel electrode 41 on the substrate 1 and the orthogonal projection of the first type of gate line 21 on the substrate 1. Referring to Figure 2E Optionally, the lower edge of the first type of pixel electrode 41 is closer to the gate line (the gate line refers to the gate electrode of the transistor electrically connected to the corresponding gate line) than the lower edge of the second type of pixel electrode 42.

[0074] In the array substrate, the scanning direction of the gate signal is first the first type of gate line 21 and then the second type of gate line 22. In this way, the opening electrode of the second type of pixel electrode 42 electrically connected with the second type of gate line 22 is the second type of gate line 22, and is only interfered by the second type of gate line 22. The first type of pixel electrode 41 electrically connected with the first type of gate line 21 is simultaneously pulled by the first type of gate line 21 and the second type of gate line 22. In the embodiment of the present disclosure, the overlapping area of the orthographic projection of the second type of pixel electrode 41 on the substrate 1 and the orthographic projection of the second type of gate line 20 on the substrate 1 is greater than the overlapping area of the orthographic projection of the first type of pixel electrode 41 on the substrate 1 and the orthographic projection of the first type of gate line 21 on the substrate 1. The coupling capacitance Cgp of the first type of pixel electrode 41 and the second type of pixel electrode 42 can be optimized to be the same, and the problem that different pixel electrodes 40 cause shaking lines due to different pulling situations of the gate line 20 can be improved.

[0075] Specifically, referring to FIG. 1, Figures 2A-2E As shown in the figure, the pixel electrode 40 can be electrically connected with the gate line 20 through a transistor T. Specifically, the transistor can include a gate electrode, an active layer 6 located on the side of the gate electrode away from the substrate, a first pole 34 of the transistor located on the side of the active layer away from the gate electrode, and a second pole 35 of the transistor connected to the data line 3.

[0076] In a possible implementation, referring to FIG. 2, Figure 4A and Figure 4B As shown in the figure, the overlapping area of the orthographic projection of the second type of pixel electrode 41 on the substrate 1 and the orthographic projection of the second type of gate line 20 on the substrate 1 can also be equal to the overlapping area of the orthographic projection of the first type of pixel electrode 41 on the substrate 1 and the orthographic projection of the first type of gate line 21 on the substrate 1.

[0077] In a possible implementation, referring to FIG. 3, Figures 2A-2E As shown in the figure, the array substrate further includes a first data part 36 connected to one end of the first pole 34 of the transistor, and the first data part 36 is in ohmic contact with the pixel electrode 40 through a via hole.

[0078] In a possible implementation, referring to FIG. 4, Figures 2A-2E As shown in the figure, the array substrate further includes a common electrode part 54 electrically connected with the third shielding part 53; the orthographic projection of the common electrode part 54 on the substrate 1 covers the orthographic projection of the first data part 36 on the substrate 1. In this way, a storage capacitor is formed by the common electrode part 54 and the first data part 36.

[0079] In a possible implementation, referring to FIG. 5, Figures 2A-2E As shown in the figure, the orthographic projection of the pixel electrode 40 on the substrate 1 covers the orthographic projection of the first data part 31 on the substrate 1 and the orthographic projection of the second data part 32 on the substrate 1.

[0080] In a possible implementation, referring to FIG. 6,Figures 2A-2E As shown, the orthographic projection of the pixel electrode 40 onto the substrate 1 also covers the orthographic projection of the first shielding portion 511 onto the substrate 1, and covers the orthographic projection of the second shielding portion 512 onto the substrate 1.

[0081] In this embodiment, the orthographic projection of the pixel electrode 40 onto the substrate 1 covers the orthographic projection of the first data section 31 onto the substrate 1, as well as the orthographic projection of the second data section 32 onto the substrate 1. It also covers the orthographic projection of the first blocking section 511 onto the substrate 1 and the orthographic projection of the second blocking section 512 onto the substrate 1. That is, since the bending shape of the data line 3 is used to block the dark texture area of ​​the pixel electrode 40, the data line 3 and the pixel electrode 40 partially overlap. Therefore, the pixel electrode 40 in this embodiment can be designed to be larger, which can improve the transmittance of the display panel.

[0082] In one possible implementation, the minimum distance between adjacent pixel electrodes 40 can be 5μm to 10μm, which is beneficial to improving the transmittance of the display panel.

[0083] In one possible implementation, see Figure 5A and Figure 5B As shown, the array substrate also includes a color filter layer located on the side of the pixel electrode 40 away from the substrate 1. The color filter layer includes a first color resist 71 corresponding to the first sub-pixel P1, a second color resist 72 corresponding to the second sub-pixel P2, and a third color resist 73 corresponding to the third sub-pixel P3.

[0084] Based on the same inventive concept, this disclosure also provides a display panel, including an array substrate as provided in this disclosure, and a counter substrate opposite to the array substrate, the counter substrate being provided with a common electrode layer.

[0085] In one possible implementation, a liquid crystal layer may be disposed between the array substrate and the opposing substrate. This liquid crystal layer has multiple liquid crystal regions in the area where the pixel electrode 40 is located, and the liquid crystal layers in different liquid crystal regions have different orientations in the initial state. Specifically, see [link to relevant documentation]. Figure 6 As shown, for example, the liquid crystal layer has four liquid crystal regions in the area where the pixel electrode 40 is located. The orthogonal projection of the four liquid crystal regions onto the substrate 1 can be located in the first region and the second region on one side of the orthogonal projection of the third blocking line 53 onto the substrate 1, and the third region and the fourth region on the other side of the orthogonal projection of the third blocking line 53, respectively. The first region and the third region can be located on one side of the orthogonal projection of the transistor first electrode 34 onto the substrate 1, and the second region and the fourth region can be located on the other side of the orthogonal projection of the transistor first electrode 34 onto the substrate 1. Specifically, the array substrate can have a first alignment film layer 81, and the opposing substrate can have a second alignment film layer 82. The orientations of the first alignment film layer 81 and the second alignment film layer 82 in different regions can be as follows: Figure 6As shown, the orientation of the first alignment film layer 81 can be perpendicular to the orientation of the second alignment film layer 82. Alternatively, the four liquid crystal regions corresponding to one pixel electrode can have different orientations, which can be achieved by irradiating the first alignment film layer and the second alignment film layer with ultraviolet light or other ways, so as to finally form four different alignment regions.

[0086] Specifically, the liquid crystal layer of different liquid crystal regions in the initial state can be understood as the deflection state of the liquid crystal layer of different liquid crystal regions without an electric field, that is, the state when no voltage is formed between the pixel electrode 40 and the common electrode.

[0087] Based on the same inventive concept, the embodiments of the present disclosure further provide a display device, which comprises the display panel provided by the embodiments of the present disclosure.

[0088] In the embodiments of the present disclosure, the display device can be any product or component with display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, etc. Other essential components of the display device are well understood by those skilled in the art and are not described here in detail, and should not be considered as a limitation on the present disclosure.

[0089] Although the preferred embodiments of the present disclosure have been described, those skilled in the art can make further changes and modifications to the embodiments once they know the basic inventive concept. Therefore, the appended claims are intended to be interpreted as including all the preferred embodiments and all the changes and modifications falling within the scope of the present disclosure.

[0090] Obviously, those skilled in the art can make various modifications and variations to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalent technologies, the present disclosure is also intended to include these modifications and variations.

Claims

1. An array substrate, characterized in that, include: Substrate; Multiple gate line groups are located on one side of the substrate and extend along a first direction, wherein one of the multiple gate line groups includes two gate lines extending along the first direction; Multiple data lines are located on the same side of the substrate as the gate line group; the multiple data lines extend along a second direction; each data line includes a first data portion and a second data portion located between adjacent gate line groups, extending along the second direction and arranged sequentially, wherein the extension lines of the first data portion and the extension lines of the second data portion do not overlap; Multiple pixel electrode groups are located on the same side of the substrate as the gate line, and at least a portion of the pixel electrode groups are located in the region formed by the intersection of the gate line group and the data line; the pixel electrode group includes two pixel electrodes arranged along the first direction, and the two pixel electrodes of the same pixel electrode group are connected to the gate line of different gate line groups; In the two pixel electrodes adjacent to the data line, the orthographic projection of the first data portion onto the substrate overlaps with the orthographic projection of the side region of one of the pixel electrodes onto the substrate; the orthographic projection of the second data portion onto the substrate overlaps with the orthographic projection of the side region of the other adjacent pixel electrode onto the substrate.

2. The array substrate as described in claim 1, characterized in that, The data line further includes: a third data section extending along the first direction and connecting the first data section and the second data section; the extension line of the third data section, in its orthographic projection on the substrate, passes through the center region of the orthographic projection of the pixel electrode on the substrate.

3. The array substrate as described in claim 2, characterized in that, The array substrate further includes: a first shielding trace located in the area where the gate line group and the data line intersect, the first shielding trace including: a first shielding portion and a second shielding portion extending along the second direction and arranged in sequence, wherein the extension line of the first shielding portion and the extension line of the second shielding portion do not overlap. The first shielding portion has an overlapping area in the orthographic projection on the substrate with the side region of one of the pixel electrodes in the pixel electrode group in the orthographic projection on the substrate; the second shielding portion has an overlapping area in the orthographic projection on the substrate with the side region of another pixel electrode in the pixel electrode group in the orthographic projection on the substrate.

4. The array substrate as described in claim 3, characterized in that, The array substrate further includes: a third shielding portion extending along the first direction and connecting the first shielding portion and the second shielding portion; the extension line of the third shielding portion, in its orthographic projection on the substrate, passes through the center region of the orthographic projection of the pixel electrode on the substrate.

5. The array substrate as described in claim 3, characterized in that, The array substrate includes: a first sub-pixel emitting a first light band, a second sub-pixel emitting a second light band, and a third sub-pixel emitting a third light band; the wavelength of the first light band is greater than the wavelength of the second light band, and the wavelength of the second light band is greater than the wavelength of the third light band. The array substrate further includes a second shielding trace extending along the second direction, wherein the orthographic projection of the second shielding trace on the substrate is located in the region where the pixel electrode of the first sub-pixel is located, and the second shielding trace passes through the central region of the pixel electrode of the first sub-pixel.

6. The array substrate as described in claim 5, characterized in that, The array substrate further includes a transistor first electrode disposed on the same layer as the data line. The transistor first electrode includes a first portion extending along the second direction, wherein the orthogonal projection of the first portion on the substrate is located in the region where the pixel electrode is located. The extension direction of the second occlusion trace overlaps with the extension direction of the first part of the first sub-pixel, and the orthographic projection of the second occlusion trace on the substrate does not overlap with the orthographic projection of the first part on the substrate.

7. The array substrate as described in claim 6, characterized in that, The first portion of the second sub-pixel passes through the central region of the pixel electrode; the first portion of the third sub-pixel does not overlap with the center of the pixel electrode.

8. The array substrate as described in claim 5, characterized in that, The array substrate further includes a third shielding trace located between adjacent gate line groups and extending along the first direction; The first and second shielding traces are both electrically connected to the third shielding trace.

9. The array substrate as described in claim 8, characterized in that, The first shielding trace, the second shielding trace, the third shielding trace, and the gate line are located on the same layer.

10. The array substrate as claimed in claim 5, characterized in that, The orthogonal projection of the pixel electrode onto the substrate at least covers the portion of the orthogonal projection of the gate line onto the substrate.

11. The array substrate as claimed in claim 8, characterized in that, The gate lines include a first type of gate line located on one side of the pixel electrode and a second type of gate line located on the other side of the pixel electrode; the signal loaded on the second type of gate line is delayed compared to the signal loaded on the first type of gate line. The pixel electrode includes: a first type of pixel electrode and a second type of pixel electrode, wherein the first type of pixel electrode loads the signal of the first type of gate line, and the second type of pixel electrode loads the signal of the second type of gate line; the overlapping area of ​​the orthographic projection of the second type of pixel electrode on the substrate and the orthographic projection of the second type of gate line on the substrate is greater than the overlapping area of ​​the orthographic projection of the first type of pixel electrode on the substrate and the orthographic projection of the first type of gate line on the substrate.

12. The array substrate as described in any one of claims 3-11, characterized in that, The orthogonal projection of the pixel electrode onto the substrate covers the orthogonal projection of the first data portion onto the substrate, and also covers the orthogonal projection of the second data portion onto the substrate.

13. The array substrate as claimed in claim 12, characterized in that, The orthogonal projection of the pixel electrode onto the substrate also covers the orthogonal projection of the first shielding portion onto the substrate, and covers the orthogonal projection of the second shielding portion onto the substrate.

14. A display panel, characterized in that, The array substrate includes the array substrate as described in any one of claims 1-13, and further includes a counter substrate opposite to the array substrate, the counter substrate being provided with a common electrode layer.

15. A display device, characterized in that, Includes the display panel as described in claim 14.

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