Chip startup method, system-on-chip, and vehicle

Abstract

The present disclosure relates to a chip startup method, a system-on-chip, and a vehicle in the technical field of vehicle chips. It is applied to the system-on-chip, and the system-on-chip includes a heterogeneous first core and a second core. The processing performance of the first core is less than that of the second core. The second core and the dynamic access memory connected to the system-on-chip form a data path, and the first core is connected to a random access memory; the second core responds to the startup of the system-on-chip, calibrates the dynamic access memory based on the data path to obtain memory calibration data; the first core stores the memory calibration data in the random access memory and performs a startup check on the dynamic access memory to perform the startup of the system-on-chip. In this way, the startup time length of the system-on-chip can be shortened, the power consumption can be reduced, and thus the startup experience of the device configured with the system-on-chip can be improved.

Description

Technical Field

[0001] The present disclosure relates to the technical field of vehicle chips, and particularly relates to a chip startup method, a system-on-chip, and a vehicle. Background Art

[0002] In a system-on-chip with multiple heterogeneous cores, there is usually a startup priority order for multiple cores when the system-on-chip starts up. For example, in a system-on-chip with two heterogeneous cores, the first core and its operating system run first, and then the second core starts to operate.

[0003] In related scenarios, as shown in Figure 1 shown, the second core manages the memory of the DDR (Double Data Rate, double data rate synchronous dynamic random access memory) (such as Figure 1 shown by the dashed line in), since the first core is the main core and shares the power supply with the system-on-chip (such as Figure 1 shown by the thick solid line in), if there is an abnormality in the initialization of the DDR, it will cause an error in the second core. Therefore, the second core reports an exception or an error to the first core, and then the first core performs a power-off restart after receiving the exception or error reported by the second core, resulting in a slow response startup speed of the system-on-chip. Summary of the Invention

[0004] To overcome the problems existing in the related art, the present disclosure provides a chip startup method, a system-on-chip, and a vehicle.

[0005] According to a first aspect of an embodiment of the present disclosure, a chip startup method is provided, which is applied to a system-on-chip. The system-on-chip includes a heterogeneous first core and a second core. The processing performance of the first core is less than that of the second core. The second core forms a data path with a dynamic access memory connected to the system-on-chip, and the first core is connected to a random access memory;

[0006] The method includes:

[0007] The second core responds to the startup of the system-on-chip and calibrates the dynamic access memory based on the data path to obtain memory calibration data;

[0008] The first core stores the memory calibration data in the random access memory and performs a startup check on the dynamic access memory to perform the startup of the system-on-chip.

[0009] Optionally, the first core stores the memory calibration data in the random access memory and performs a startup check on the dynamic access memory to perform the startup of the system-on-chip, including:

[0010] The first core stores the memory calibration data in the random access memory and performs a startup check of the dynamic access memory according to the memory calibration data;

[0011] Perform a power-on startup of the second core, and in the case where the startup check indicates an abnormality of the dynamic access memory, perform a restart of the first core after power-off to perform the startup of the system-on-chip.

[0012] Optionally, a calibration storage unit and an error check unit are connected to the random access memory, and an error check and identification unit is connected to the first core;

[0013] The performing a power-on startup of the second core, and in the case where the startup check indicates an abnormality of the dynamic access memory, performing a restart of the first core after power-off includes:

[0014] The first core stores the memory calibration data in the calibration storage unit and performs a power-on startup of the second core;

[0015] The error check unit identifies the memory calibration data and performs an anomaly repair when the memory calibration data is abnormal;

[0016] The error check and identification unit performs a restart of the first core after power-off after identifying that the error check unit has repaired the anomaly.

[0017] Optionally, the error check unit identifies the memory calibration data and performs an anomaly repair operation when the memory calibration data is abnormal, including:

[0018] The error check unit identifies the memory calibration data and, when the memory calibration data is abnormal, performs a memory repair on the dynamic access memory and sends an interrupt to the error check and identification unit;

[0019] The error check and identification unit performs a restart of the first core after power-off after identifying that the error check unit has repaired the anomaly, including:

[0020] The error check and identification unit, based on the interrupt, performs a restart of the first core after power-off after identifying that the error check unit has repaired the anomaly.

[0021] Optionally, a status detection unit is connected to the first core;

[0022] The status detection unit performs a hash detection on the status of the random access memory.

[0023] Optionally, the control regions of the second core and the first core are respectively electrically connected to the power management integrated circuit of the system-on-chip, and the power management integrated circuit independently provides operating power to loads within the control regions of the second core and the first core;

[0024] Performing power-on startup of the second core without power-off, and in the case where the startup check indicates an abnormality of the dynamic access memory, performing restart of the first core after power-off, includes:

[0025] The second core independently performs power-on startup of the second core based on the operating power provided by the power management integrated circuit;

[0026] In the case where the startup check indicates an abnormality of the dynamic access memory, independently performing restart of the first core after power-off based on the operating power provided by the power management integrated circuit.

[0027] Optionally, a controller and a physical layer of the dynamic access memory are connected to the first core;

[0028] The second core responds to the power-on startup of the system-on-chip and calibrates the dynamic access memory based on the data path to obtain memory calibration data, including:

[0029] The second core responds to the power-on startup of the system-on-chip and sends a calibration read / write request to the controller;

[0030] The controller converts the calibration read / write request into a calibration command and generates a timing signal corresponding to the calibration command;

[0031] The physical layer converts the timing signal into a protocol signal corresponding to the dynamic access memory, and sends the protocol signal to the dynamic access memory to perform calibration of the dynamic access memory to obtain the memory calibration data.

[0032] Optionally, the second core is a core of the Cortex-A hardware platform; the first core is a core of the Cortex-M hardware platform.

[0033] According to a second aspect of the embodiments of the present disclosure, a system-on-chip is provided. The system-on-chip includes a heterogeneous first core and a second core. The processing performance of the first core is less than the processing performance of the second core. The second core and the dynamic access memory connected to the system-on-chip form a data path, and the first core is connected to a random access memory;

[0034] The second core responds to the power-on startup of the system-on-chip and calibrates the dynamic access memory based on the data path to obtain memory calibration data;

[0035] The first core stores the memory calibration data in the random access memory and performs a startup check of the dynamic access memory to perform the system-on-chip startup.

[0036] Optionally, a status detection unit and an error check and identification unit are connected to the first core, and a calibration storage unit and an error check unit are connected to the random access memory;

[0037] The status detection unit is heterogeneously communicatively connected to the calibration storage unit, and the error check and identification unit is heterogeneously communicatively connected to the error check unit.

[0038] According to a third aspect of the embodiments of the present disclosure, a vehicle is provided, and the vehicle includes the system-on-chip as described in any one of the second aspects.

[0039] The technical solutions provided by the embodiments of the present disclosure may include the following beneficial effects:

[0040] By deploying the heterogeneous first core and the second core in the system-on-chip, the processing performance of the first core is less than that of the second core. The second core controls the dynamic access memory connected to the system-on-chip, and the first core is connected to the random access memory; the second core responds to the startup of the system-on-chip, calibrates the dynamic access memory, and obtains the memory calibration data; the first core stores the memory calibration data in the random access memory and performs a startup check of the dynamic access memory to perform the system-on-chip startup. Since the processing performance of the first core is less than that of the second core, during the startup process, the second core first responds to the startup signal of the system-on-chip. Based on the strong processing performance of the second core, the dynamic access memory can be calibrated to ensure the stability and accuracy of the dynamic access memory. After calibration, the first core stores these calibration data in the random access memory within its control area. Based on the strong real-time performance of the first core, it can ensure the fast read and write speed of the random access memory and the strong real-time restart of the first core, and can quickly access the memory calibration data, thereby accelerating the startup process. In this way, the startup time length of the system-on-chip can be shortened, the power consumption can be reduced, and thus the startup experience of the device configured with the system-on-chip can be improved.

[0041] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present disclosure, and are used together with the specification to explain the principles of the present disclosure.

[0043] Figure 1It is a block diagram of a system-on-chip in the prior art.

[0044] Figure 2 It is a block diagram of a system-on-chip shown according to an exemplary embodiment.

[0045] Figure 3 It is a flowchart of a chip startup method shown according to an exemplary embodiment.

[0046] Figure 4 It is a block diagram of another system-on-chip shown according to an exemplary embodiment.

[0047] Figure 5 It is a block diagram of a vehicle shown according to an exemplary embodiment.

[0048] Figure 6 It is a block diagram of a chip system shown according to an exemplary embodiment. Detailed implementation manners

[0049] Here, the exemplary embodiments will be described in detail, and the examples are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with the present disclosure. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present disclosure as detailed in the appended claims.

[0050] The implementation manners described in some embodiments of the present disclosure below do not represent all implementation manners consistent with the present disclosure. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present disclosure as detailed in the appended claims.

[0051] It should be noted that all actions of obtaining signals, information, or data in the present disclosure are carried out on the premise of complying with the corresponding data protection regulations and policies of the country where it is located and obtaining authorization from the owner of the corresponding device.

[0052] Figure 2 It is a schematic diagram of a system-on-chip shown according to an exemplary embodiment. As Figure 2 shown, the system-on-chip includes a heterogeneous first core and a second core. The processing performance of the first core is less than that of the second core. The second core and the dynamic access memory connected to the system-on-chip form a data path, and the first core is connected to a random access memory.

[0053] In the embodiments of the present disclosure, a loading and initialization module (such as Init Module) is deployed inside the second core, and the functions configured in this module can be used to perform calibration and initialization on the dynamic access memory, etc.

[0054] Among them, the dynamic access memory can be, for example, double data rate synchronous dynamic random access memory DDR, and the random access memory can be Standby RAM (STD_RAM).

[0055] Among them, the first core is connected to the random access memory. That is to say, both the first core and the random access memory can be deployed within the control area of the first core, while the second core is not deployed within the control area of the first core. The first core and the second core are heterogeneously deployed.

[0056] Among them, the connection can be to connect the first core with the random access memory, and the system-on-chip with the dynamic access memory to achieve data transmission or functional cooperation. The connection can not only achieve coupling in physical connection, but also achieve connection in logic or protocol. Specifically, the second core connecting to the dynamic access memory (DDR) establishes a direct data transmission channel and control interface between the second core and the DDR. Through this connection, the second core can read data from the DDR and also write the processed data back to the DDR. Since the DDR is usually used to store a large amount of program data and temporary data during operation, this connection method ensures that the second core can efficiently access and process this data. And the first core connecting to the random access memory (RAM) establishes a direct data exchange channel between the first core and the RAM, allowing the first core to directly read instructions and data from the RAM, or write the processing results back to the RAM. The RAM usually has a faster access speed, so connecting to the RAM may be more suitable for implementing fast-start real-time response tasks.

[0057] Figure 3 A chip startup method shown according to an exemplary embodiment, applied to Figure 2 the system-on-chip shown, the method includes:

[0058] In step S31, the second core responds to the power-on startup of the system-on-chip and calibrates the dynamic access memory based on the data path to obtain memory calibration data.

[0059] Among them, the second core refers to a low-performance processing core relative to the first core. It is usually responsible for executing some tasks that do not require high processing capabilities, such as I / O operations, memory management, etc. The system-on-chip SoC can be an integrated circuit in which multiple functional modules on a vehicle are integrated into a single chip, and usually includes a processor core, memory, I / O interfaces, etc.

[0060] Among them, the power-on startup can be generated and sent to the system-on-chip when the vehicle is powered on.

[0061] Among them, the memory calibration data is a set of data generated by the second core during the initialization or calibration of the dynamic access memory, and is used to adjust or compensate the working parameters of the dynamic access memory to ensure its correct and stable operation. For example, the memory calibration data is a set of data generated by the second core when checking the hardware status of the dynamic access memory, determining its working parameters (such as latency time, working voltage, etc.), and performing read and write tests.

[0062] In step S32, the first core stores the memory calibration data in the random access memory and performs a startup check on the dynamic access memory to perform the startup of the system-on-chip.

[0063] Among them, after storing the memory calibration data in the random access memory, the first core starts to perform a startup check on the dynamic access memory. This check process can include read and write tests to ensure that the dynamic access memory can work correctly and stably before receiving the actual workload.

[0064] Furthermore, if any problems are found in the startup check of the dynamic access memory, the first core can perform a power-off operation, and at the same time, the random access memory and the dynamic access memory can also be powered off and restarted accordingly. The second core maintains its own startup state and does not need to be powered off and restarted with the first core. Given the powerful processing performance of the first core, the first core can be restarted quickly, thereby shortening the power-on startup time length of the system-on-chip; if no problems are found in the startup check of the dynamic access memory, both the first core and the second core continue to complete the startup.

[0065] The above technical solution deploys heterogeneous first and second cores on a system-on-chip. The processing performance of the first core is less than that of the second core. The second core manages the dynamic access memory connected to the system-on-chip, and the first core is connected to a random access memory. The second core responds to the power-on startup of the system-on-chip, calibrates the dynamic access memory, and obtains memory calibration data. The first core stores the memory calibration data in the random access memory and performs a startup check on the dynamic access memory to start the system-on-chip. Since the processing performance of the first core is less than that of the second core, during startup, the second core first responds to the power-on startup signal of the system-on-chip. Based on the strong processing performance of the second core, the dynamic access memory can be calibrated to ensure the stability and accuracy of the dynamic access memory. After calibration is completed, the first core stores this calibration data in the random access memory within its management area. Based on the strong real-time performance of the first core, it can ensure the fast read and write speed of the random access memory and the strong real-time restart of the first core, and can quickly access the memory calibration data, thus accelerating the startup process. In this way, the power-on startup time length of the system-on-chip can be shortened, the power consumption can be reduced, and thus the startup experience of the device configured with this system-on-chip can be improved.

[0066] Optionally, in step S32, the first core stores the memory calibration data in the random access memory and performs a startup check on the dynamic access memory to start the system-on-chip, including:

[0067] The first core stores the memory calibration data in the random access memory and performs a startup check on the dynamic access memory according to the memory calibration data;

[0068] Among them, after the second core completes the calibration of the dynamic access memory, corresponding memory calibration data is generated. The first core reads this memory calibration data from the second core or other locations and stores it in the random access memory. Due to its high-speed access characteristics, the first core can quickly obtain and use this memory calibration data to perform a startup check.

[0069] Among them, the startup check may include a series of read and write tests, latency tests, and other performance evaluations to ensure that the DDR can stably store and read data under normal working conditions.

[0070] Perform non-power-off startup of the second core, and in the case where the startup check indicates an abnormality of the dynamic access memory, perform power-off and restart of the first core to start the system-on-chip.

[0071] Among them, the non-power-off startup can be that the second core continues to execute the startup without shutting down the power supply, which can reduce the startup time length of the second core and avoid data loss. And the restart after power-down means that the first core and other components in its control area are restarted after the power supply is turned off, so as to solve the abnormality of the dynamic access memory, and based on the strong processing performance of the first core, it can quickly complete the restart of the first core and other components in its control area.

[0072] It can be understood that when the startup check indicates that the dynamic access memory is normal, the startup operation of the first core is continued. Only when the startup check indicates that the dynamic access memory is abnormal, the first core is restarted after power-down. And when the first core is restarted after power-down, the non-power-off startup of the second core is continued.

[0073] In this way, the system-on-chip can ensure the correct configuration and working state of the dynamic access memory during startup, and at the same time can quickly complete the restart when there is an abnormality in the startup of the dynamic access memory.

[0074] Optionally, as shown in Figure 4 the calibration storage unit and the error check unit are connected to the random access memory, and the error check and identification unit is connected to the first core;

[0075] Among them, the error check and identification unit is communicatively connected to the error check unit. The error check unit can be, for example, Figure 4 the Error Correction Code Module (ECC Module) shown in the figure. The ECC Module adds additional parity bits during data storage to detect and correct errors. When data is written to the storage device, the ECC module calculates the parity bits and saves them together with the stored data.

[0076] Among them, the ECC module is composed of two modules, an encoder and a decoder. The encoding module calculates the parity bits for the data, while the decoding module is responsible for calculating the syndrome and correcting the bit in error. If the calculated syndrome is zero, it means there is no error and the data is directly output; if the syndrome is not zero, the error pattern is calculated and the data is corrected. The ECC module can detect single-bit or multiple-bit errors and can also correct these errors in some cases.

[0077] Furthermore, the error check and identification unit can receive the status reported by the error check unit and determine whether it is necessary to restart the first core after power-down based on this status.

[0078] Performing the power - on - without - power - off startup of the second core and, in the case where the startup check indicates an abnormality in the dynamic access memory, performing a restart after power - off of the first core includes:

[0079] The first core stores the memory calibration data in the calibration storage unit and performs the power - on - without - power - off startup of the second core.

[0080] Among them, since the calibration storage unit is located in the random access memory within the system - on - chip internal memory, the first core can quickly read the stored memory calibration data from the calibration storage unit.

[0081] The calibration storage unit can ensure that the stored memory calibration data can be quickly accessed. In this way, the first core performs the power - on - without - power - off startup process of the second core. Power - on - without - power - off startup means that the second core is activated while maintaining power supply, which can quickly wake up the second core from the sleep or low - power state and prepare it to execute its predetermined tasks.

[0082] The error check unit identifies the memory calibration data and performs anomaly repair when the memory calibration data is abnormal.

[0083] Among them, the error check unit is responsible for monitoring the integrity of the memory calibration data. It checks the calibration data stored in the calibration storage unit to identify whether there are any abnormalities or errors. If the error check unit finds an abnormality in the calibration data, it will initiate an anomaly repair mechanism. This mechanism may include using backup data, recalculating calibration values, or adopting other error - correction techniques to repair the errors in the data.

[0084] After the error check identification unit identifies that the error check unit has completed anomaly repair, it performs a restart after power - off of the first core.

[0085] Among them, in the case where the error check unit has completed the anomaly repair of the memory calibration data, the error check identification unit will identify this repair process. This identification process may be completed by receiving a repair - completed signal sent by the error check unit or by checking the data status after repair.

[0086] Furthermore, in the case where it is confirmed that the repair is completed and the data is normal, the error check identification unit will trigger the restart process after power - off of the first core. Restart after power - off means that the system first shuts down the power supply and then restarts the first core. This process can clear any potential error states and reload the system configuration to ensure that the system can operate normally after restart.

[0087] Through the above steps, the system-on-chip can ensure the correct configuration and working state of the dynamic access memory during the startup process. If anomalies are found in the calibration data or startup checks, corresponding measures can be taken to repair them, and in case of necessity, the system stability and reliability can be restored by powering off and restarting. This mechanism improves the error tolerance and reliability of the system-on-chip, ensuring a quick restart of the system-on-chip.

[0088] Optionally, the error checking unit identifies the memory calibration data and, when there are anomalies in the memory calibration data, performs an anomaly repair operation, including:

[0089] The error checking unit identifies the memory calibration data and, when there are anomalies in the memory calibration data, performs a memory repair on the dynamic access memory and sends an interrupt to the error checking and identification unit;

[0090] Among them, the interrupt can be an Error Correction Code (ECC) interrupt. When the ECC module detects an error, it will send an ECC interrupt signal to notify the first core that a repair action is being performed.

[0091] During the startup process of the system-on-chip, the error checking unit first identifies the memory calibration data stored in the calibration storage unit. This identification process includes checking the integrity, consistency, and other possible error metrics of the data. If the error checking unit finds anomalies in the memory calibration data, it will immediately initiate a repair operation on the dynamic access memory. This repair operation may include using the functions of the ECC module to correct the error bits in the data, or taking other measures to restore the normal working state of the memory. And at the same time, generate and send an interrupt to the error checking and identification unit.

[0092] After identifying that the error checking unit has completed the anomaly repair, the error checking and identification unit performs a power-off and restart of the first core, including:

[0093] Based on the interrupt, after identifying that the error checking unit has completed the anomaly repair, the error checking and identification unit performs a power-off and restart of the first core.

[0094] In the embodiments of the present disclosure, after receiving the interrupt sent by the error checking unit, the error checking and identification unit (such as the ECC Check Module) will start to process this interrupt. First, it will confirm the source of the interrupt, that is, confirm that the error checking unit has completed the anomaly repair of the memory calibration data. Once this information is confirmed, the error checking and identification unit will decide to take further measures to restore the system stability. For example, pause the startup of the first core and the components within its control area.

[0095] Further, in the case where the interruption disappears, for example, when the interruption stops, it is recognized that the error checking unit repairs the abnormality, and after the first core is powered off, it is restarted. In this case, the error checking and recognition unit will select to perform a power-off and restart of the first core. This means that the system will first turn off the power and then restart the first core. This restart process can clear any residual problems that may be caused by the previous error state and reload the system configuration to ensure that the system can operate normally after the restart.

[0096] In this way, when abnormal memory calibration data is detected, the repair operation is quickly started, and the stability and reliability of the system are restored by sending an interruption and performing a power-off and restart. This mechanism improves the restart speed and response speed of the system-on-chip to errors. Thereby enhancing the boot experience of the device configured with this system-on-chip.

[0097] Optionally, continue to refer to Figure 4 As shown, a state detection unit is connected to the first core;

[0098] The state detection unit performs a hash detection on the state of the random access memory.

[0099] Among them, the state detection unit can be STR State Op&Hash Check, and the state detection unit will perform a hash detection on the state of the random access memory. For example, by detecting the state of DDR Calibration in the random access memory, the data integrity in the random access memory can be ensured, and any possible data corruption or tampering can be detected in a timely manner.

[0100] First, the state detection unit will start the hash detection process. It will read a part of the data from the random access memory and calculate the hash value of these data using a pre-set hash algorithm (such as MD5, SHA-1, etc.). This hash value is a digital summary of the data content, with high uniqueness and sensitivity. Even if the data changes slightly, the hash value will be significantly different.

[0101] Next, the state detection unit will compare the calculated hash value with the pre-stored hash value (i.e., the correct hash value of the original data). This pre-stored hash value is usually generated when the RAM is initialized or data is written and stored in a safe and reliable place.

[0102] If the comparison result shows that the two hash values are the same, then the state detection unit will determine that the state of the random access memory is normal and the data has not been corrupted or tampered with. Then, it will continue to perform a hash detection on other data in the random access memory until all data has been detected.

[0103] If the comparison result shows that the two hash values are inconsistent, then the status detection unit will determine that the status of the random access memory is abnormal. For example, the random access memory is in a state of repairing a DDR anomaly. In this case, the status detection unit will immediately trigger the corresponding processing mechanism, such as recording an error log, sending an alarm signal, or performing a data recovery operation, to ensure the stability of the system and the reliability of the data.

[0104] In this way, the status detection unit can monitor the status of the random access memory in real time, detect and handle any potential data problems in a timely manner, thereby ensuring the normal operation of the system and the security of the data.

[0105] Optionally, continue to refer to Figure 2 or Figure 4 As shown, the control areas of the second core and the first core are respectively electrically connected to the power management integrated circuit of the system-on-chip, and the power management integrated circuit independently provides working power for the loads in the control areas of the second core and the first core;

[0106] Among them, Figure 2 and Figure 4 The thick solid lines in indicate that the control areas of the second core and the first core are respectively electrically connected to the power management integrated circuit of the system-on-chip, and the solid lines with arrows indicate the data flow direction.

[0107] Among them, the power management integrated circuit (PMIC) is an integrated circuit responsible for power distribution, voltage regulation, and battery management, ensuring that each component in the system obtains the correct working power. Working power refers to the power required for the normal operation of the system or component.

[0108] Performing the non-power-off startup of the second core and, in the case where the startup check indicates an anomaly in the dynamic access memory, performing a restart after powering off the first core, includes:

[0109] The second core independently performs the non-power-off startup of the second core based on the working power provided by the power management integrated circuit;

[0110] During the startup process, the second core will perform a non-power-off startup based on the working power provided by the power management integrated circuit (PMIC). This means that although the system may be running other tasks or cores, the second core can still utilize the stable power provided by the PMIC to start and be ready to execute its predetermined tasks without interrupting other parts of the system. This startup method can accelerate the overall startup speed of the system while ensuring the normal operation of other cores or system components.

[0111] In the case where the startup check indicates an abnormality in the dynamic access memory, the restart after powering down the first core is independently executed based on the operating power provided by the power management integrated circuit.

[0112] Among them, if during the startup check after the second core starts up, the system detects an abnormality in the dynamic access memory, then the restart process after powering down the first core will be triggered. This process involves first cutting off the operating power of the first core through the PMIC to completely shut it down. Then, operating power is provided again to start the first core. This way of restarting after powering down can clear any potential error states in the dynamic access memory, re-initialize the system state, and potentially solve the abnormality problem of the dynamic access memory found in the startup check.

[0113] When performing the restart after powering down, services may be temporarily interrupted or the current state may be saved to ensure that a stable operating state can be restored after the restart. This usually involves saving critical data to non-volatile memory for restoration after the restart.

[0114] In this way, while ensuring data integrity and system stability, it can effectively respond to the abnormality of the dynamic access memory and restore the normal operation of the first core through restarting after powering down. This helps to improve the reliability of the system and the user experience.

[0115] Optionally, continue to refer to Figure 4 As shown, the controller and physical layer of the dynamic access memory are attached to the first core;

[0116] Among them, as indicated by the arrow dotted line in Figure 4 , the second core is communicatively connected to the controller (such as a DDR Controller), the controller is communicatively connected to the physical layer (such as a DDR PHY), and the physical layer is communicatively connected to the dynamic access memory.

[0117] The second core responds to the startup of the system-on-chip and calibrates the dynamic access memory based on the data path to obtain memory calibration data, including:

[0118] The second core responds to the startup of the system-on-chip and sends a calibration read / write request to the controller;

[0119] Among them, the controller of the dynamic random access memory is a hardware logic component responsible for managing and controlling the operations of the dynamic random access memory. It receives instructions from the core (such as the second core), converts them into commands that the memory can understand, and performs read and write operations. The physical layer is part of the hardware interface and is responsible for converting the commands or data generated by the controller into signals that conform to the dynamic random access memory communication protocol, ensuring that the signals can be correctly transmitted between the core and the memory. The calibration read / write requests are sent by the second core to the controller during the memory initialization or startup process to perform a series of read and write operations to verify and calibrate the performance of the memory.

[0120] The controller converts the calibration read / write requests into calibration commands and generates timing signals corresponding to the calibration commands;

[0121] Among them, the timing signals are generated by the controller according to the calibration read / write requests and are a sequence of signals used to control the dynamic random access memory to perform calibration operations.

[0122] The physical layer converts the timing signals into protocol signals corresponding to the dynamic random access memory and sends the protocol signals to the dynamic random access memory to perform the calibration of the dynamic random access memory and obtain the memory calibration data.

[0123] Among them, the protocol signals are signals that the physical layer converts the timing signals into signals that conform to the dynamic random access memory communication protocol to ensure correct communication with the memory.

[0124] In one implementation, when the system-on-chip is powered on and starts up, the second core begins to execute the startup process. As part of the startup process, the second core is responsible for calibrating the dynamic random access memory. The second core sends calibration read / write requests to the dynamic random access memory controller deployed in the first core control area. These requests contain the instructions and parameters required to perform the calibration operations. After receiving the calibration read / write requests from the second core, the controller converts these requests into corresponding timing signals. The timing signals contain the precise time sequence and control information required to perform the calibration operations. The physical layer receives the timing signals from the controller and converts them into protocol signals that conform to the dynamic random access memory communication protocol. This ensures that the signal format, transmission rate, and other communication parameters match the requirements of the memory. The physical layer sends the converted protocol signals to the dynamic random access memory. After receiving these signals, the dynamic random access memory performs corresponding calibration operations, such as read / write tests, timing adjustments, etc. The dynamic random access memory performs calibration operations according to the received protocol signals to ensure that the performance of the memory reaches the preset standard. After completing the calibration operations, the dynamic random access memory generates memory calibration data. These data may include test results, adjustment parameters, etc. during the calibration process and are used for subsequent system configuration and performance optimization.

[0125] Optionally, continue to refer toFigure 4 As shown, the second core is the core of the Cortex-A hardware platform; the first core is the core of the Cortex-M hardware platform.

[0126] An embodiment of the present disclosure also provides a system-on-chip. Refer to Figure 2 or Figure 4 As shown, the system-on-chip includes a heterogeneous first core and a second core. The processing performance of the first core is less than that of the second core. The second core and the dynamic access memory connected to the system-on-chip form a data path, and the first core is connected to a random access memory;

[0127] The second core responds to the power-on startup of the system-on-chip and calibrates the dynamic access memory based on the data path to obtain memory calibration data;

[0128] The first core stores the memory calibration data in the random access memory and performs a startup check on the dynamic access memory to perform the startup of the system-on-chip.

[0129] Optionally, refer to Figure 4 As shown, the first core is connected to a status detection unit and an error check and identification unit, and the random access memory is connected to a calibration storage unit and an error check unit;

[0130] The status detection unit is heterogeneously communicatively connected to the calibration storage unit, and the error check and identification unit is heterogeneously communicatively connected to the error check unit.

[0131] According to an embodiment of the present disclosure, a vehicle is also provided. The vehicle includes the system-on-chip according to any one of the foregoing embodiments.

[0132] Figure 5 FIG. 600 is a block diagram of a vehicle 600 shown according to an exemplary embodiment. For example, the vehicle 600 can be a hybrid vehicle, or a non-hybrid vehicle, an electric vehicle, a fuel cell vehicle, or other types of vehicles. The vehicle 600 can be an autonomous vehicle, a semi-autonomous vehicle, or a non-autonomous vehicle.

[0133] Referring to Figure 5 , the vehicle 600 can include various subsystems. For example, an infotainment system 610, a perception system 620, a decision control system 630, a drive system 640, and a computing platform 650. Among them, the vehicle 600 can also include more or fewer subsystems, and each subsystem can include multiple components. In addition, each subsystem and each component of the vehicle 600 can be interconnected by wired or wireless means.

[0134] In some embodiments, the infotainment system 610 may include a communication system, an entertainment system, a navigation system, and the like.

[0135] The perception system 620 may include several sensors for sensing information about the environment around the vehicle 600. For example, the perception system 620 may include a global positioning system (the global positioning system may be a GPS system, a Beidou system, or other positioning systems), an inertial measurement unit (IMU), lidar, millimeter-wave radar, ultrasonic radar, and a camera device.

[0136] The decision control system 630 may include a computing system, a vehicle controller, a steering system, an accelerator, and a braking system.

[0137] The drive system 640 may include components that provide motive power for the vehicle 600. In one embodiment, the drive system 640 may include an engine, an energy source, a powertrain, and wheels. The engine may be one or a combination of an internal combustion engine, an electric motor, and an air compression engine. The engine is capable of converting the energy provided by the energy source into mechanical energy.

[0138] Some or all functions of the vehicle 600 are controlled by the computing platform 650. The computing platform 650 may include at least one processor 651 and a memory 652, and the processor 651 may execute instructions 653 stored in the memory 652.

[0139] The processor 651 may be any conventional processor, such as a commercially available CPU. The processor may also include, for example, a Graphic Process Unit (GPU), a Field Programmable Gate Array (FPGA), a System on Chip (SOC), an Application Specific Integrated Circuit (ASIC), or a combination thereof.

[0140] The memory 652 may be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, a magnetic disk, or an optical disk.

[0141] In addition to instruction 653, memory 652 can also store data, such as road maps, route information, data such as the position, direction, and speed of the vehicle. The data stored in memory 652 can be used by computing platform 650.

[0142] In an embodiment of the present disclosure, processor 651 can execute instruction 653 to complete all or part of the steps of the above XXXX method.

[0143] Some embodiments of the present disclosure also provide a chip system, as Figure 6 shown, the chip system includes at least one processor 1301 and at least one interface circuit 1302. Processor 1301 and interface circuit 1302 can be interconnected by a line. For example, interface circuit 1302 can be used to receive signals from other devices (such as the memory of an electronic device). Again, for example, interface circuit 1302 can be used to send signals to other devices (such as processor 1301). Exemplarily, interface circuit 1302 can read the instructions stored in the memory and send the instructions to processor 1301. When the instructions are executed by processor 1301, the chip system can execute each step in the above embodiments. Of course, the chip system can also include other discrete devices, and some embodiments of the present disclosure do not specifically limit this.

[0144] In some embodiments of the present disclosure, interface circuit 1302 can obtain data, program instructions, and / or information, etc. in the internal storage area of the chip system; it can also obtain data, program instructions, and / or information, etc. from outside the chip system.

[0145] Optionally, the chip system further includes a memory 1303, and the memory 1303 is used to store necessary computer programs and data.

[0146] Those skilled in the art can also understand that the various illustrative logical blocks and steps listed in the embodiments of the present application can be implemented by electronic hardware, computer software, or a combination of both. Whether such a function is implemented by hardware or software depends on the specific application and the design requirements of the entire system. Those skilled in the art can use various methods to implement the described function for each specific application, but such implementation should not be construed as exceeding the scope protected by the embodiments of the present application.

[0147] In addition, the word "exemplary" is used herein to mean serving as an example, instance, or illustration. Any aspect or design described herein as "exemplary" is not necessarily to be construed as advantageous over other aspects or designs. Rather, the word exemplary is intended to present concepts in a concrete fashion. Additionally, unless otherwise specified or clearly pointed to the singular form from the context, the articles "a" and "an" as used in this application and the appended claims are generally understood to mean "one or more".

[0148] Likewise, although the present disclosure has been shown and described with respect to one or more implementations, equivalent variations and modifications will occur to those skilled in the art upon reading and understanding the specification and drawings. The present disclosure includes all such modifications and variations and is limited only by the scope of the claims. Specifically with respect to the various functions performed by the components (e.g., elements, resources, etc.) described above, unless otherwise indicated, the terms used to describe such components are intended to correspond to any component (functionally equivalent) that performs the specific function of the described component, even if not structurally equivalent to the disclosed structure. Additionally, although a particular feature of the present disclosure may have been disclosed with respect to only one of several implementations, such a feature may, as may be desired and advantageous for any given or particular application, be combined with one or more other features of other implementations. Further, with respect to the use of "comprises", "comprising", "has", "having", "includes", or variants thereof in the detailed description or claims, such terms are intended to be inclusive in a manner similar to the term "including".

[0149] Other embodiments of the present disclosure will be readily apparent to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include known or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of the present disclosure are pointed out by the appended claims.

[0150] It should be understood that the present disclosure is not limited to the exact structures described above and shown in the drawings, and various modifications and changes may be made without departing from its scope. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A chip startup method, characterized in that: Applied to a system-level chip, the system-level chip includes a heterogeneous first core and a second core, the processing performance of the first core is lower than the processing performance of the second core, the second core and a dynamic access memory mounted on the system-level chip form a data path, and the first core is mounted on a random access memory; The method comprises: The second core responds to the power-on of the system-level chip, calibrates the dynamic access memory based on the data path, and obtains memory calibration data, wherein a loading and initialization module is deployed in the second core, and the function configured in the loading and initialization module is used to perform calibration and initialization on the dynamic access memory, and the memory calibration data is data generated by the second core during the initialization or calibration process of the dynamic access memory, and is used to adjust or compensate for the working parameters of the dynamic access memory; The first core stores the memory calibration data into the random access memory, performs a startup check on the dynamic access memory, and executes startup of the system-on-chip.

2. The method according to claim 1, characterized in that The first core stores the memory calibration data into the random access memory and performs a startup check of the dynamic access memory to perform the system-on-chip startup, including: The first core stores the memory calibration data in the random access memory and performs a startup check of the dynamic access memory according to the memory calibration data; The second core is started without powering off, and when the startup check indicates that the dynamic access memory is abnormal, the first core is restarted after being powered off to execute the system-on-chip startup.

3. The method according to claim 2, characterized in that A calibration storage unit and an error checking unit are mounted in the random access memory, and an error checking identification unit is mounted in the first core; The step of executing the second core to start up without powering off, and executing the first core to restart after powering off when the startup check indicates that the dynamic access memory is abnormal, comprises: The first core stores the memory calibration data into the calibration storage unit, and executes the second core to start without power failure; The error checking unit identifies the memory calibration data and performs abnormality repair when an abnormality exists in the memory calibration data; The error checking and identifying unit executes power-off and then restarting of the first core after identifying that the error checking unit repairs the abnormality.

4. The method according to claim 3, characterized in that The error checking unit identifies the memory calibration data and performs an abnormality repair operation when an abnormality exists in the memory calibration data, including: The error checking unit identifies the memory calibration data, and when the memory calibration data is abnormal, performs memory repair on the dynamic access memory, and sends an interrupt to the error checking and identifying unit; After recognizing that the error checking unit repairs the abnormality, the error checking and identifying unit executes the first core to be powered off and then restarted, including: The error checking and identifying unit, based on the interruption, executes power-off and then restart of the first core after identifying that the error checking unit repairs the abnormality.

5. The method according to claim 3, characterized in that: The first core is connected with a state detection unit; The state detection unit detects the state of the calibration storage unit by hashing.

6. The method according to claim 2, characterized in that The control areas of the second core and the first core are respectively electrically connected to the power management integrated circuit of the system-level chip, and the power management integrated circuit independently provides working power to the loads in the control areas of the second core and the first core; The step of executing the second core to start up without powering off, and executing the first core to restart after powering off when the startup check indicates that the dynamic access memory is abnormal, comprises: The second core independently performs the second core uninterrupted power-on startup based on the working power provided by the power management integrated circuit; In a case where the startup check indicates that the dynamic access memory is abnormal, the first core is independently powered off and restarted based on the working power provided by the power management integrated circuit.

7. The method according to any one of claims 1 to 6, characterized in that The first core is mounted with a controller and a physical layer of the dynamic access memory; The second core responds to the power-on of the system-level chip and calibrates the dynamic access memory based on the data path to obtain memory calibration data, including: The second core sends a calibration read / write request to the controller in response to the system-on-chip being powered on; The controller converts the calibration read / write request into a calibration command, and generates a timing signal corresponding to the calibration command; The physical layer converts the timing signal into a protocol signal corresponding to the dynamic access memory, and sends the protocol signal to the dynamic access memory to perform calibration of the dynamic access memory and obtain the memory calibration data.

8. The method according to any one of claims 1 to 6, characterized in that The second core is the core of the Cortex-A hardware platform; the first core is the core of the Cortex-M hardware platform.

9. A system-on-chip, characterized in that: The system-level chip includes a heterogeneous first core and a second core, the processing performance of the first core is lower than the processing performance of the second core, the second core and a dynamic access memory mounted on the system-level chip form a data path, and the first core is mounted on a random access memory; The second core responds to the power-on of the system-level chip, calibrates the dynamic access memory based on the data path, and obtains memory calibration data, wherein a loading and initialization module is deployed in the second core, and the function configured in the loading and initialization module is used to perform calibration and initialization on the dynamic access memory, and the memory calibration data is data generated by the second core during the initialization or calibration process of the dynamic access memory, and is used to adjust or compensate for the working parameters of the dynamic access memory; The first core stores the memory calibration data in the random access memory and performs a startup check of the dynamic access memory to perform the system-on-chip startup.

10. The system-on-chip according to claim 9, characterized in that: The first core is mounted with a state detection unit and an error checking and identifying unit, and the random access memory is mounted with a calibration storage unit and an error checking unit; The state detection unit is connected to the calibration storage unit in a heterogeneous communication manner, and the error checking and identifying unit is connected to the error checking unit in a heterogeneous communication manner.

11. A vehicle, characterized in that: The vehicle comprises the system-on-chip as claimed in claim 9 or 10.

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