A data processing device, method, computer program product, equipment and medium

Abstract

The present invention discloses a data processing device, method, computer program product, equipment and medium, and relates to the technical field of servers. The data processing device includes a target number of accelerator cards, the target number is greater than or equal to 2, and the accelerator card includes: an algorithm core, which is used to process the data to be processed and obtain the processing result; split the processing result into the target number of sub-processing results; retain one sub-processing result, and send the remaining sub-processing results to the global memory; the global memory connected to the algorithm core is used to store the sub-processing results interacted by the accelerator card with other accelerator cards; a data transmission module connected to the global memory is used to read the sub-processing results sent by the accelerator card from the global memory and transmit them to the transmission layer, or receive the sub-processing results sent by other accelerator cards transmitted by the transmission layer and store them in the global memory; the transmission layer connected to the data transmission module is used to interact with other accelerator cards in a one-to-one correspondence. The data processing efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the field of server technology, and more specifically, to a data processing device, method, computer program product, equipment and medium. Background Art

[0002] Currently, in the process of applying algorithms to operate on data, the data is usually operated from beginning to end according to the algorithm. In this way, if the amount of data is large, the operation process will take a long time, affecting the data processing efficiency and bringing a bad experience to users.

[0003] In summary, how to improve data processing efficiency is a problem that needs to be urgently solved by those skilled in the art. Summary of the invention

[0004] The object of the present invention is to provide a data processing device, which can solve the technical problem of how to improve data processing efficiency to a certain extent. The present invention also provides a data processing method, a computer program product, an electronic device and a computer readable storage medium.

[0005] In a first aspect, a data processing device is provided, including a target number of accelerator cards, the target number being greater than or equal to 2, each accelerator card including:

[0006] The algorithm kernel is used to process the data to be processed to obtain a processing result; split the processing result into the target number of sub-processing results; retain one sub-processing result and send the remaining sub-processing results to the global memory;

[0007] The global memory connected to the algorithm kernel is used to store sub-processing results of the accelerator card interacting with other accelerator cards;

[0008] A data transmission module connected to the global memory, used for reading the sub-processing results sent by the accelerator card from the global memory and transmitting them to the transmission layer, or receiving the sub-processing results sent by other accelerator cards transmitted by the transmission layer and storing them in the global memory;

[0009] The transmission layer connected to the data transmission module is used to interact with the sub-processing results of other acceleration cards in a one-to-one correspondence to process the sub-processing results.

[0010] On the other hand, when the value of the target number is 2, the transport layer includes a physical layer.

[0011] On the other hand, when the target number is greater than 2, the transmission layer includes a first number of sub-transmission layers, each of the sub-transmission layers includes a physical layer and a routing module, and the routing module is connected between the physical layer and the data transmission module;

[0012] The routing module is used to detect whether the sub-processing result transmitted by the connected physical layer is received. If so, the sub-processing result is sent to the data transmission module; if not, the sub-processing result is forwarded to the physical layer of other acceleration cards through the connected physical layer according to the routing table.

[0013] On the other hand, each physical layer of the acceleration card is connected to at most one physical layer of other acceleration cards; the first number includes a value obtained by rounding up the calculation value, and the calculation value includes a value obtained by raising the target number to a power of 2.

[0014] On the other hand, the algorithm kernel includes:

[0015] A data loading module connected to the global memory, used for interacting with the global memory for sub-processing results;

[0016] A local memory connected to the data loading module, used for storing the data to be processed, the processing results and the sub-processing results;

[0017] The computing core connected to the local memory is used to process the data to be processed to obtain a processing result; and split the processing result into the target number of molecular processing results.

[0018] On the other hand, the local memory includes a true dual-port random access memory; and the interface of the local memory is a local interface.

[0019] On the other hand, the global memory includes a high bandwidth memory or a double rate synchronous dynamic random access memory; the interface of the global memory is an advanced scalable memory mapping interface;

[0020] The data loading module has the function of converting the data protocol between the true dual-port random access memory local interface and the advanced extensible memory mapping interface.

[0021] On the other hand, the input interface of the physical layer is an advanced extensible stream interface;

[0022] The data transmission module has the function of converting the data protocol between the advanced extensible memory mapping interface and the advanced extensible stream interface.

[0023] On the other hand, it also includes:

[0024] A direct memory access engine connected to the global memory, used for receiving sub-target data assigned by the control end to the accelerator card, the sub-target data including data obtained by splitting the target data according to the target quantity;

[0025] The data loading module is also used to: read the sub-target data stored in the global memory, and write the sub-target data into the local memory as data to be processed.

[0026] On the other hand, the data loading module is also used to: read the final processing result obtained by the operation core from the local memory, and store the final processing result into the global memory; send an interrupt signal to the control end so that the control end obtains the final processing result through the direct memory access engine, and then the control end merges the final processing results obtained by all acceleration cards to obtain the processing result of the target data.

[0027] On the other hand, the algorithm core is further used to: use the combined data obtained by combining the sub-processing results retained by the algorithm core and the sub-processing results sent by other acceleration cards as the data to be processed.

[0028] On the other hand, the operation core includes a Fourier transform core, a convolution core and a transposition module; the sub-target data includes data obtained by splitting the target data in the Z direction according to the number of targets;

[0029] The operation core is used to: perform X-dimensional Fourier transform on the sub-target data through the Fourier transform core, perform transposition processing on the transformation result through the transposition module, perform Y-dimensional Fourier transform on the transposed data through the Fourier transform core to obtain the processing result, split the processing result in the X direction according to the target number to obtain the first round of sub-processing results; read the combined data obtained from the first round of sub-processing results stored for the first time from the local memory, perform Z-dimensional Fourier transform on the first combined data through the Fourier transform core, and compare the transformation result through the convolution core Convolution processing is performed, and a Z-dimensional Fourier inverse transform is performed on the convolved data through the Fourier transform core to obtain a processing result, and the processing result is split in the Z direction according to the target number to obtain a second round of sub-processing results; the merged data obtained by the second round of sub-processing results stored for the second time is read from the local memory, and the second merged data is subjected to a Y-dimensional Fourier inverse transform through the Fourier transform core, and the transformation result is transposed through the transposition module, and the transposed data is subjected to an X-dimensional Fourier inverse transform through the Fourier transform core to obtain a final processing result.

[0030] In a second aspect, a data processing method is provided, which is applied to an accelerator card of any of the above data processing devices, comprising:

[0031] Processing the data to be processed by the algorithm kernel to obtain a processing result; splitting the processing result into a target number of sub-processing results; retaining one sub-processing result and sending the remaining sub-processing results to a global memory connected to the algorithm kernel;

[0032] The sub-processing results of the interaction between the accelerator card and other accelerator cards are stored in the global memory;

[0033] Through a data transmission module connected to the global memory, the sub-processing result sent by the accelerator card is read from the global memory and transmitted to the transmission layer, or the sub-processing result sent by other accelerator cards transmitted by the transmission layer is received and stored in the global memory;

[0034] Interacting sub-processing results with other accelerator cards in a one-to-one correspondence through the transmission layer connected to the data transmission module to process the sub-processing results;

[0035] The data processing device includes the target number of acceleration cards, and the target number is greater than or equal to 2.

[0036] According to a third aspect, a computer program product is provided, comprising a computer program / instruction, which implements the steps of the data processing method described above when executed by a processor.

[0037] In a fourth aspect, an electronic device is provided, including:

[0038] Memory for storing computer programs;

[0039] A processor is used to implement the steps of the data processing method as described above when executing the computer program.

[0040] In a fifth aspect, a computer-readable storage medium is provided, wherein a computer program is stored in the computer-readable storage medium, and when the computer program is executed by a processor, the steps of the data processing method described above are implemented.

[0041] A data processing device provided by the present invention includes a target number of accelerator cards, the target number is greater than or equal to 2, and each accelerator card includes: an algorithm core, used to process data to be processed to obtain a processing result; split the processing result into a target number of sub-processing results; retain one sub-processing result, and send the remaining sub-processing results to a global memory; a global memory connected to the algorithm core, used to store sub-processing results exchanged between the accelerator card and other accelerator cards; a data transmission module connected to the global memory, used to read the sub-processing results sent by the accelerator card from the global memory and transmit them to a transmission layer, or receive the sub-processing results sent by other accelerator cards transmitted by the transmission layer and store them in the global memory; a transmission layer connected to the data transmission module, used to interact with other accelerator cards in a one-to-one correspondence to process the sub-processing results. The beneficial effects of the present invention are: a target number of accelerator cards form a data processing device, each accelerator card is provided with an algorithm kernel to process the data to be processed, and the processing result is split into a target number of sub-processing results, so that each accelerator card only retains a sub-processing result, and interacts with other accelerator cards one-to-one through global memory, data transmission module and transmission layer. The sub-processing results, in this way, each accelerator card can obtain a sub-processing result of other accelerator cards, and all the obtained sub-processing results can become new data to be processed. Finally, all accelerator cards can cooperate with each other to jointly process data. In other words, the present invention can process data in parallel with the help of a target number of accelerator cards, thereby improving data processing efficiency. A data processing method, computer program product, electronic device and computer-readable storage medium provided by the present invention also solve corresponding technical problems. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0043] Figure 1 A schematic diagram of the structure of a data processing device provided by an embodiment of the present invention;

[0044] Figure 2 This is a schematic diagram of the connection of 2 acceleration cards;

[0045] Figure 3 This is a schematic diagram of the connection of 4 accelerator cards;

[0046] Figure 4 This is a schematic diagram of 8 accelerator card connections;

[0047] Figure 5 This is a schematic diagram of the data transmission path between 4 acceleration cards;

[0048] Figure 6 Schematic diagram of data division in the X-dimensional and Y-dimensional Fourier transform and inverse transform stages when using 2 accelerator cards;

[0049] Figure 7 Schematic diagram of data division in the X-dimensional and Y-dimensional Fourier transform and inverse transform stages when there are 4 accelerator cards;

[0050] Figure 8 Schematic diagram of data division in the Z-dimensional Fourier transform and inverse transform stages when using 2 accelerator cards;

[0051] Fig. 9 Schematic diagram of data division in the Z-dimensional Fourier transform and inverse transform stages when there are 4 accelerator cards;

[0052] Fig.10 It is a schematic diagram of data interaction of Fourier transform;

[0053] Fig.11 A schematic diagram of the structure of a data processing device for Fourier transform;

[0054] Fig.12 It is a schematic diagram of the connection between global memory and local memory ports;

[0055] Fig.13 A flowchart of a data processing method provided by an embodiment of the present invention;

[0056] Fig.14 A schematic diagram of the structure of an electronic device provided by an embodiment of the present invention;

[0057] Fig.15 Another structural schematic diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0058] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0059] See also Figure 1 , Figure 1 A schematic diagram of the structure of a data processing device provided by an embodiment of the present invention.

[0060] An embodiment of the present invention provides a data processing device, comprising a target number of accelerator cards, the target number being greater than or equal to 2, and each accelerator card comprising:

[0061] The algorithm kernel is used to process the data to be processed and obtain the processing result; split the processing result into a target number of sub-processing results; retain one sub-processing result and send the remaining sub-processing results to the global memory;

[0062] The global memory connected to the algorithm kernel is used to store the sub-processing results of the accelerator card interacting with other accelerator cards;

[0063] A data transmission module connected to the global memory is used to read the sub-processing results sent by the accelerator card from the global memory and transmit them to the transport layer, or receive the sub-processing results sent by other accelerator cards transmitted by the transport layer and store them in the global memory;

[0064] The transport layer connected to the data transmission module is used to interact with the sub-processing results of other accelerator cards in a one-to-one correspondence to process the sub-processing results.

[0065] In practical applications, the type of data processed by the data processing device can be determined according to actual needs. For example, the data processing device can process images, files, server performance data, etc. In addition, the accelerator card in the present invention can be designed based on FPGA (Field Programmable Gate Array) and the like, and the value of the target quantity can be flexibly determined according to the application scenario. In the process of applying the data transposition of the present invention, taking the image processing process as an example, the target image can be first obtained, the target image can be split into a target number of sub-target images, and the sub-target images can be sent to each acceleration card, that is, each acceleration card obtains a sub-target image; the acceleration card first uses the sub-target image as the image to be processed, applies its own algorithm kernel to process the image to be processed, obtains the processing result, and splits the processing result to obtain the target number of sub-processing results; the acceleration card retains a sub-processing result, and then applies the global memory, the data transmission module and the transmission layer to interact with other acceleration cards in a one-to-one manner. The sub-processing result, that is, the acceleration card only sends a sub-processing result to one other acceleration card, and each other acceleration card obtains a different sub-processing result from the same acceleration card. In this way, each acceleration card can obtain the sub-processing results generated by the target number minus 1 other acceleration card from other acceleration cards, and the acceleration card can obtain a new round of images to be processed after merging all the sub-processing results; in this way, the target data can be processed in parallel with the help of the target number of acceleration cards until the final processing result is obtained.

[0066] In the specific application scenario, when the target quantity value is 2, such as Figure 2As shown, only two accelerator cards are exchanging data, and the two accelerator cards can quickly identify each other, so the transmission layer can be set to consist of only the physical layer. Correspondingly, when the target number is greater than 2, since each accelerator card needs to identify multiple other accelerator cards, it will be difficult for the accelerator card to determine which data needs to be transmitted to which other accelerator card. In order to avoid this situation, the transmission layer can be set to consist of a first number of sub-transmission layers, and each sub-transmission layer includes a physical layer and a routing module, and the routing module is connected between the physical layer and the data transmission module; the routing module is used to detect whether the sub-processing result transmitted by the connected physical layer is received, and if so, the sub-processing result is sent to the data transmission module to receive the sub-processing result required to be transmitted to its own accelerator card; if not, the sub-processing result is forwarded to the physical layer of other accelerator cards according to the routing table through the connected physical layer, so as to send the sub-processing result to the other accelerator cards that need to receive this sub-processing result, so as to accurately transmit the required sub-processing result to the accelerator card with the help of the routing function of the routing module.

[0067] In a specific application scenario, each physical layer of the acceleration card can be set to be connected to at most one physical layer of other acceleration cards; at this time, when determining the first number, the first number can be set to a value obtained by rounding up the calculation value, and the calculation value includes a value obtained by raising the target number to a power of 2.

[0068] For ease of understanding, assuming that the target number is 4, the operation value is 2, and the first number is 2, that is, two physical layers and two routing modules are set in each accelerator card, and the structure of the data processing device is as follows: Figure 3 Assume that the target number is 8, then the operation value is 3, and the first number is 3, that is, three physical layers and three routing modules are set in each accelerator card, and the structure of the data processing device is as follows Figure 4 As shown, it is not difficult to understand that when the target number is greater than 4 and less than 8, the operation value is greater than 2 and less than 3, and the value of the first number is 3, three physical layers and three routing modules still need to be set in each accelerator card. In this way, after each physical layer of a single accelerator card is connected to at most one physical layer of other accelerator cards, all accelerator cards can be interconnected, which reduces the difficulty of interconnection between multiple accelerator cards and facilitates faster construction of data processing devices; and the redundant physical layers and routing modules in the accelerator card can be retained for use after adding a new accelerator card, which can improve the interconnection efficiency of the accelerator card and improve the scalability of the data processing device.

[0069] In specific application scenarios, when the routing module is used to transmit data, a frame header can be added to the head of a frame of data sent by each accelerator card. The frame header indicates which accelerator card the frame of data needs to be sent to. In this way, when the data frame passes through the routing module of each accelerator card, the routing module will check the frame header. If it is data sent to its own accelerator card, it will be stored in the global memory through the data transmission module; if not, it will be forwarded from the specified port according to the definition of the routing table. Figure 3 Taking the structure shown in the figure as an example, the data transmission path between acceleration cards is as follows Figure 5 As shown, in the path through which data frames sent from accelerator card 0 to other accelerator cards pass, the data path from accelerator card 0 to accelerator card 1 is shown as the dotted line in the figure, the data path from accelerator card 0 to accelerator card 2 is shown as the solid line in the figure, the data path from accelerator card 0 to accelerator card 3 is shown as the dotted line in the figure, and the data paths of other accelerator cards are similar.

[0070] In practical applications, the algorithm kernel in the data processing device of the present invention may include: a data loading module connected to the global memory, used to exchange sub-processing results with the global memory, so as to facilitate the management of the global memory and the local memory; a local memory connected to the data loading module, used to store the processed data, processing results and sub-processing results, so as to facilitate the algorithm kernel to manage the processed data, processing results and sub-processing results; an operation core connected to the local memory, used to process the processed data, obtain the processing results, and split the processing results into a target number of sub-processing results.

[0071] In a specific application scenario, the local memory may include a true dual-port random access memory; the interface of the local memory may be a local interface. The global memory may include a high-bandwidth memory or a double-rate synchronous dynamic random access memory; the interface of the global memory may be an advanced extensible memory mapping interface; accordingly, the data loading module has the function of converting the data protocol between the local interface of the true dual-port random access memory and the advanced extensible memory mapping interface. The input interface of the physical layer may be an advanced extensible stream interface; accordingly, the data transmission module has the function of converting the data protocol between the advanced extensible memory mapping interface and the advanced extensible stream interface.

[0072] In a specific application scenario, in order to facilitate the user to operate the data processing device, the data processing device may also include: a direct memory access engine connected to the global memory, used to receive sub-target data assigned to the acceleration card by the control end, the sub-target data including data obtained by splitting the target data according to the target quantity, and the control end may be a server host, a user computer, etc.; correspondingly, the data loading module is also used to: read the sub-target data stored in the global memory, and write the sub-target data as data to be processed into the local memory.

[0073] In specific application scenarios, the data loading module can also be used to: read the final processing result of the operation core from the local memory and store the final processing result into the global memory; send an interrupt signal to the control end so that the control end can obtain the final processing result through the direct memory access engine, and then the control end can merge the final processing results of all acceleration cards to obtain the processing result of the target data.

[0074] In specific application scenarios, the algorithm kernel can also be used to: merge the sub-processing results retained by the algorithm kernel and the sub-processing results sent by other accelerator cards to obtain the merged data as the data to be processed. That is, each accelerator card can merge a portion of the sub-processing results retained by itself and the target number minus 1 portion of the sub-processing results obtained from other accelerator cards into new data to be processed, so as to combine the target number of accelerator cards to process the data in parallel.

[0075] In this way, the process of operating the data processing device through the control end can be as follows: the user inputs the target data into the control end, the target data is split at the control end to obtain the target number of sub-target data, and each sub-target data is sent to the global memory of the corresponding acceleration card through the direct memory access engine of the acceleration card; the data loading module of the acceleration card writes the sub-target data in the global memory as the data to be processed into the local memory; the computing core of the acceleration card reads the data to be processed from the local memory for processing, obtains the processing result, splits the processing result, obtains the target number of component processing results and stores them in the local memory; the data loading module of the acceleration card reads the target number minus 1 component processing result from the local memory and writes it into the global memory; the data transmission module of the acceleration card reads the sub-processing result from the global memory and transmits it to the local memory; The data transmission module of the accelerator card receives the sub-processing results sent by other accelerator cards through the transmission layer, and writes the received sub-processing results into the global memory; the data loading module of the accelerator card writes the received sub-processing results stored in the global memory into the local memory, and merges them with the sub-processing results originally retained in the local memory to generate new data to be processed; the accelerator card continues to process the data to be processed until the processing results are no longer split and the processing results are stored in the local memory; the data loading module of the accelerator card reads the processing results from the local memory and stores them back into the global memory, and informs the control end of the task completion through an interrupt signal; the control end retrieves the processing results from the global memory of each accelerator card through the direct memory access engine, and merges all the processing results into a complete processing result.

[0076] A data processing device provided by the present invention includes a target number of accelerator cards, the target number is greater than or equal to 2, and each accelerator card includes: an algorithm core, used to process data to be processed to obtain a processing result; split the processing result into a target number of sub-processing results; retain one sub-processing result, and send the remaining sub-processing results to a global memory; a global memory connected to the algorithm core, used to store sub-processing results exchanged between the accelerator card and other accelerator cards; a data transmission module connected to the global memory, used to read the sub-processing results sent by the accelerator card from the global memory and transmit them to a transmission layer, or receive the sub-processing results sent by other accelerator cards transmitted by the transmission layer and store them in the global memory; a transmission layer connected to the data transmission module, used to interact with other accelerator cards in a one-to-one correspondence to process the sub-processing results. The beneficial effects of the present invention are as follows: a target number of accelerator cards form a data processing device, each accelerator card is provided with an algorithm kernel to process the data to be processed, and the processing result is split into a target number of sub-processing results, so that each accelerator card only retains a sub-processing result, and interacts with other accelerator cards in a one-to-one manner through the global memory, the data transmission module and the transmission layer. Sub-processing results, in this way, each accelerator card can obtain a sub-processing result of other accelerator cards, and all the obtained sub-processing results are a complete set of data to be processed. Ultimately, all accelerator cards can cooperate with each other to jointly perform data processing. In other words, the present invention can process data in parallel with the help of a target number of accelerator cards, thereby improving data processing efficiency.

[0077] In order to facilitate the understanding of the application of the data processing device of the present invention, the process of PME (particle-mesh Ewald) processing of data by a data processing device composed of two accelerator cards is now described. The PME method is a method for calculating electrostatic forces in molecular dynamics. Under the PME method, the electrostatic potential energy of the simulation system is divided into three parts, namely the electrostatic potential energy in real space, the electrostatic potential energy in Fourier space, and the energy correction term. By selecting a suitable Ewald (grid) coefficient, the electrostatic potential energy in real space can be converged quickly, and then the electrostatic potential energy in real space can be processed by truncation. Since the calculation amount of the energy correction term itself is not large, the most time-consuming part of the entire PME algorithm is the calculation of the electrostatic force in Fourier space.

[0078] By analyzing the Fourier operation process in the PME algorithm, it can be seen that the three-dimensional Fourier transform, convolution calculation, and three-dimensional Fourier inverse transform in the entire PME algorithm can be divided into three stages: 1) Stage 1, which can also be called the X-dimensional and Y-dimensional Fourier transform stage. In this stage, multiple Fourier transform kernels perform Fourier transforms along the X and Y directions respectively, and complete all the Fourier transforms along the Z direction. Therefore, in this stage, the data can be divided into upper and lower parts in the Z direction, such as Figure 6As shown, each accelerator card calculates half of the data. It is not difficult to understand that when the target number is 4, the splitting process is as follows Figure 7 2) Stage 2, also known as the Z-dimensional Fourier transform and inverse transform stage, in this stage, multiple Fourier transform kernels perform Fourier transform and inverse transform along the Z direction, complete all the Fourier transform and inverse transform along the Y direction, and perform convolution operations between Fourier transform and inverse transform, so in this stage, the data can be divided into left and right parts in the X direction, as shown in Figure 8 As shown, each accelerator card calculates half of the data. It is not difficult to understand that when the target number is 4, the splitting process is as follows Fig. 9 3) Stage 3, also known as the Y-dimensional and X-dimensional inverse Fourier transform stage, in this stage, multiple Fourier transform kernels perform inverse Fourier transforms along the Y and X directions respectively, and complete all inverse Fourier transforms along the Z direction. The data division in this stage can still be based on Figure 5 conduct.

[0079] contrast Figure 6 and Figure 8 It can be seen that the two accelerator cards need to perform two data exchanges when performing three-stage calculations, one between stage 1 and stage 2, and one between stage 2 and stage 3. The two accelerator cards send half of the data in their own memory to the other accelerator card, and receive half of the data sent by the other accelerator card. The schematic diagram of data exchange is shown in the figure. Fig.10 As shown. In this way, the computing core of the acceleration card of the present invention needs to include a Fourier transform core, a convolution core and a transposition module, such as Fig.11 As shown. When performing Fourier transforms in each dimension, the Fourier transform core obtains the initial data of the transform from the local memory, and stores the transform result back to the local memory after the transform is completed. Therefore, in order to distinguish the data sent by the accelerator card and the data received, storage area 1 and storage area 2 can be set in the global memory. Storage area 1 is used to store the data to be sent out, and storage area 2 stores the data to be received. In this way, after completing the calculation of stage 1, the data loading module takes out half of the data required by the opposite accelerator card from the local memory and stores it in the storage area 1 of the global memory, and then the data transmission module takes out the data from the global memory 1 and sends it out from the physical layer. At the same time, the data transmission module also receives the data it needs from the physical layer, and stores the received data in the storage area 2 of the global memory, and then the data loading module takes out the data from the global memory 2 and stores it in the local memory. After completing the sending and receiving of all data, the Fourier transform core takes out the data from the local memory for the calculation of stage 2. The data interaction process between stage 2 and stage 3 is similar, and will not be repeated here.

[0080] The process of performing Fourier operation in PME by means of the host operating data processing device is as follows:

[0081] The host splits the target data into two sub-target data in the Z direction; and sends the sub-target data to the global memory of the two accelerator cards through the direct memory access engine;

[0082] The data loading module of the accelerator card takes out the sub-target data from the global memory and stores it in the local memory of the Fourier transform kernel and the convolution calculation kernel;

[0083] The Fourier transform core of the accelerator card performs X-dimensional Fourier transform on the sub-target data, and transposes the transform result through the transposition module. The transposed data is then stored back in the local memory. The Fourier transform core takes out the transposed data from the local memory again and performs Y-dimensional Fourier transform to obtain the first round of processing results. The processing results are split in the X direction according to the number of targets, and the first round of sub-processing results are obtained and stored in the local memory.

[0084] The data loading module of the accelerator card takes out a sub-processing result from the local memory and stores it in the global memory. The data transmission module takes out the sub-processing result from the global memory and transmits it to the physical layer. The physical layer performs data conversion and sends it to the physical layer of another accelerator card through the optical port. That is, the physical layer is responsible for converting the data stream into an optical signal. The two accelerator cards are interconnected through optical fiber. At the same time, the physical layer of the accelerator card receives a sub-processing result transmitted by the physical layer of another accelerator card through the optical port, and transmits the received sub-processing result to the data transmission module. The data transmission module stores the received sub-processing result in the global memory. The data loading module reads the received sub-processing result from the global memory and writes it to the local memory.

[0085] The Fourier transform core of the accelerator card reads the combined data obtained from the first round of sub-processing results stored for the first time from the local memory, performs a Z-dimensional Fourier transform on the first combined data, and the transform result enters the convolution core for convolution processing. The processed data is then stored back in the local memory; the Fourier transform core again takes out the convolved data from the local memory for a Z-dimensional inverse Fourier transform to obtain the second round of processing results, splits the processing results in the Z direction according to the target number, obtains the second round of sub-processing results and stores them in the local memory;

[0086] The data loading module of the accelerator card takes out a sub-processing result from the local memory and stores it in the global memory. The data transmission module takes out the sub-processing result from the global memory and transmits it to the physical layer. The physical layer performs data conversion and sends it to the physical layer of another accelerator card through the optical port. At the same time, the physical layer of the accelerator card receives a sub-processing result transmitted by the physical layer of another accelerator card through the optical port, and transmits the received sub-processing result to the data transmission module. The data transmission module stores the received sub-processing result in the global memory. The data loading module reads the received sub-processing result from the global memory and writes it to the local memory.

[0087] The Fourier transform core of the accelerator card reads the combined data obtained from the second round of processing results stored for the second time from the local memory, performs a Y-dimensional Fourier inverse transform on the second combined data, transposes the transform result through the transposition module, and stores the transposed data back to the local memory; the Fourier transform core takes out the transposed data from the local memory again, performs an X-dimensional Fourier inverse transform, obtains the final processing result and stores it in the local memory;

[0088] The data loading module of the accelerator card takes out the final processing result from the local memory and stores it back into the global memory, and tells the host computer through an interrupt signal that the computing task is complete;

[0089] The host retrieves the processing results from the global memory of each accelerator card through the direct memory access engine and merges them into a complete Fourier processing result for the host to perform further PME operations.

[0090] From this implementation process, it can be seen that the present invention restricts the specific structure of the algorithm kernel, and flexibly splits the calculation data of each time according to the specific process of Fourier operation in PME, so that the data processing device of the present invention can be used to perform calculations in parallel, and finally the corresponding operations of Fourier operation in PME are completed with the cooperation of the data processing device and the host, thereby improving the calculation efficiency of Fourier operation in PME, thereby accelerating the algorithm efficiency of PME.

[0091] It should be noted that the structure of each device in the accelerator card can be flexibly adjusted according to actual needs. For example, in order to improve the parallelism of data calculation and transmission, the port connection relationship between the global memory and the local memory is optimized. After optimization, the connection relationship between the global memory and the local memory port and each module is as follows: Fig.12 As shown, the global memory includes 3 input and output ports that can perform read and write operations simultaneously; the local memory includes 2 input and output ports that can perform read and write operations simultaneously; the first input and output port of the global memory is used for the data loading module to access the processing results; the second input and output port of the global memory is used for the data loading module to access the sub-processing results; the third input and output port of the global memory is used for the data transmission module to access the sub-processing results. The first input and output port of the local memory is used for the data loading module to read the processing results or write the sub-processing results, the second input and output port of the local memory is used for the computing core to read the data to be processed or write the processing results or write the sub-processing results, or the second input and output port of the local memory is used for the data loading module to read the sub-processing results.

[0092] From this implementation process, it can be seen that the first input and output port of the global memory is used for the data loading module to access the processing results, the second input and output port of the global memory is used for the data loading module to access the sub-processing results, and the third input and output port of the global memory is used for the data transmission module to access the sub-processing results. In this way, the data loading module and the data transmission module can process specific data through specific ports, and there is no port occupancy, which improves the data interaction efficiency of the global memory; and the first input and output port of the local memory is used for the data loading module to read the processing results or write the sub-processing results, and the second input and output port of the local memory is used for the operation core to read the data to be processed or write The processing result is written into the sub-processing result, or the second input and output port of the local memory is used for the data loading module to read the sub-processing result, that is, the data loading module does not send data and retrieve results at the same time, so it can use one port A. The Fourier transform core takes out data and the transposition module stores data back at the same time, so it can use one port B. When the data is exchanged between accelerator cards, the data loading module accesses data at the same time, so the data to be sent is taken out from port B, and the external data is written from port A to the local memory. In this way, the data loading module and the operation core can process specific data through a specific port, and there is no port occupancy, which improves the data interaction efficiency of the local memory. Ultimately, the parallelism of data calculation and transmission is improved.

[0093] See also Fig.13 , Fig.13 A flowchart of a data processing method provided by an embodiment of the present invention.

[0094] A data processing method provided by an embodiment of the present invention is applied to an accelerator card of any of the above data processing devices and may include the following steps:

[0095] Step S101: Process the data to be processed by the algorithm kernel to obtain a processing result; split the processing result into a target number of sub-processing results; retain one sub-processing result, and send the remaining sub-processing results to the global memory connected to the algorithm kernel.

[0096] Step S102: storing the sub-processing results of the interaction between the accelerator card and other accelerator cards in the global memory.

[0097] Step S103: read the sub-processing result sent by the accelerator card from the global memory and transmit it to the transport layer through the data transmission module connected to the global memory, or receive the sub-processing result sent by other accelerator cards transmitted by the transport layer and store it in the global memory.

[0098] Step S104: interacting with other accelerator cards one-to-one through a transmission layer connected to the data transmission module to process the sub-processing results; wherein the data processing device includes a target number of accelerator cards, and the target number is greater than or equal to 2.

[0099] The development of the corresponding steps in the data processing method provided by the embodiment of the present invention can refer to the description of the above-mentioned data processing device, which will not be repeated here.

[0100] The present invention also provides an electronic device and a computer-readable storage medium, both of which have the corresponding effects of a data processing method provided in an embodiment of the present invention. Fig.14 , Fig.14 A schematic diagram of the structure of an electronic device provided by an embodiment of the present invention.

[0101] An electronic device provided by an embodiment of the present invention includes a memory 201 and a processor 202. The memory 201 stores a computer program. When the processor 202 executes the computer program, the following steps are implemented:

[0102] Process the data to be processed through the algorithm kernel to obtain a processing result; split the processing result into a target number of sub-processing results; retain one sub-processing result and send the remaining sub-processing results to the global memory connected to the algorithm kernel;

[0103] The sub-processing results of the accelerator card interacting with other accelerator cards are stored in the global memory;

[0104] Through the data transmission module connected to the global memory, the sub-processing results sent by the accelerator card are read from the global memory and transmitted to the transport layer, or the sub-processing results sent by other accelerator cards transmitted by the transport layer are received and stored in the global memory;

[0105] The sub-processing results are processed by interacting with other accelerator cards in a one-to-one correspondence through a transport layer connected to the data transmission module.

[0106] See also Fig.15Another electronic device provided in an embodiment of the present invention may also include: an input port 203 connected to the processor 202, used to transmit commands input from the outside to the processor 202; a display unit 204 connected to the processor 202, used to display the processing results of the processor 202 to the outside; a communication module 205 connected to the processor 202, used to realize communication between the electronic device and the outside. The display unit 204 can be a display panel, a laser scanning display, etc.; the communication method adopted by the communication module 205 includes but is not limited to mobile high-definition link technology (Mobile High-Definition Link, MHL), Universal Serial Bus (Universal Serial Bus, USB), High-Definition Multimedia Interface (High-Definition Multimedia Interface, HDMI), wireless connection: wireless fidelity technology (WIreless Fidelity, WiFi), Bluetooth communication technology, low-power Bluetooth communication technology, and communication technology based on IEEE802.11s.

[0107] An embodiment of the present invention provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the following steps are implemented:

[0108] Process the data to be processed through the algorithm kernel to obtain a processing result; split the processing result into a target number of sub-processing results; retain one sub-processing result and send the remaining sub-processing results to the global memory connected to the algorithm kernel;

[0109] The sub-processing results of the accelerator card interacting with other accelerator cards are stored in the global memory;

[0110] Through the data transmission module connected to the global memory, the sub-processing results sent by the accelerator card are read from the global memory and transmitted to the transport layer, or the sub-processing results sent by other accelerator cards transmitted by the transport layer are received and stored in the global memory;

[0111] The sub-processing results are processed by interacting with other accelerator cards in a one-to-one correspondence through a transport layer connected to the data transmission module.

[0112] The computer-readable storage medium involved in the present invention includes random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, register, hard disk, removable disk, CD-ROM (Compact Disc Read-Only Memory), or any other form of storage medium known in the technical field.

[0113] A computer program product provided by an embodiment of the present invention includes a computer program / instruction. When the computer program / instruction is executed by a processor, the following steps are implemented:

[0114] Process the data to be processed through the algorithm kernel to obtain a processing result; split the processing result into a target number of sub-processing results; retain one sub-processing result and send the remaining sub-processing results to the global memory connected to the algorithm kernel;

[0115] The sub-processing results of the accelerator card interacting with other accelerator cards are stored in the global memory;

[0116] Through the data transmission module connected to the global memory, the sub-processing results sent by the accelerator card are read from the global memory and transmitted to the transport layer, or the sub-processing results sent by other accelerator cards transmitted by the transport layer are received and stored in the global memory;

[0117] The sub-processing results are processed by interacting with other accelerator cards in a one-to-one correspondence through a transport layer connected to the data transmission module.

[0118] For the description of the relevant parts of a data processing method, an electronic device, a computer-readable storage medium, and a computer program product provided by an embodiment of the present invention, please refer to the detailed description of the corresponding parts in a data processing device provided by an embodiment of the present invention, which will not be repeated here. In addition, the parts of the above technical solutions provided by the embodiments of the present invention that are consistent with the implementation principles of the corresponding technical solutions in the prior art are not described in detail to avoid excessive elaboration.

[0119] It should also be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0120] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A data processing device, characterized in that: The method comprises a target number of accelerator cards, the target number being greater than or equal to 2, each accelerator card comprising: The algorithm kernel is used to process the data to be processed to obtain a processing result; split the processing result into the target number of sub-processing results; retain one sub-processing result and send the remaining sub-processing results to the global memory; The global memory connected to the algorithm kernel is used to store sub-processing results of the accelerator card interacting with other accelerator cards; A data transmission module connected to the global memory, used for reading the sub-processing results sent by the accelerator card from the global memory and transmitting them to the transmission layer, or receiving the sub-processing results sent by other accelerator cards transmitted by the transmission layer and storing them in the global memory; The transmission layer connected to the data transmission module is used to send the sub-processing result sent by the data transmission module to other acceleration cards, or receive the sub-processing result sent by other acceleration cards and transmit it to the data transmission module, so as to process the sub-processing result; The data to be processed includes merged data obtained by merging the sub-processing results retained by the algorithm core and the sub-processing results sent by other acceleration cards.

2. The data processing device according to claim 1, characterized in that: When the value of the target number is 2, the transport layer includes a physical layer.

3. The data processing device according to claim 1, characterized in that: When the target number is greater than 2, the transmission layer includes a first number of sub-transmission layers, each of the sub-transmission layers includes a physical layer and a routing module, and the routing module is connected between the physical layer and the data transmission module; The routing module is used to detect whether the sub-processing result transmitted by the connected physical layer is received. If so, the sub-processing result is sent to the data transmission module; if not, the sub-processing result is forwarded to the physical layer of other acceleration cards through the connected physical layer according to the routing table.

4. The data processing device according to claim 3, characterized in that: Each physical layer of the acceleration card is connected to at most one physical layer of other acceleration cards; the first number includes a value obtained by rounding up the operation value, and the operation value includes a value obtained by exponentiating the target number with 2 as the base.

5. The data processing device according to any one of claims 2 to 4, characterized in that: The algorithm kernel includes: A data loading module connected to the global memory, used for interacting with the global memory for sub-processing results; A local memory connected to the data loading module, used for storing the data to be processed, the processing results and the sub-processing results; The computing core connected to the local memory is used to process the data to be processed to obtain a processing result; and split the processing result into the target number of molecular processing results.

6. The data processing device according to claim 5, characterized in that: The local memory includes a true dual-port random access memory; the interface of the local memory is a local interface.

7. The data processing device according to claim 6, characterized in that: The global memory includes a high bandwidth memory or a double rate synchronous dynamic random access memory; the interface of the global memory is an advanced scalable memory mapping interface; The data loading module has the function of converting the data protocol between the true dual-port random access memory local interface and the advanced extensible memory mapping interface.

8. The data processing device according to claim 7, characterized in that: The input interface of the physical layer is an advanced extensible stream interface; The data transmission module has the function of converting the data protocol between the advanced extensible memory mapping interface and the advanced extensible stream interface.

9. The data processing device according to claim 5, characterized in that: Also includes: A direct memory access engine connected to the global memory, used for receiving sub-target data assigned by the control end to the accelerator card, the sub-target data including data obtained by splitting the target data according to the target quantity; The data loading module is also used to: read the sub-target data stored in the global memory, and write the sub-target data into the local memory as data to be processed.

10. The data processing device according to claim 9, characterized in that: The data loading module is also used to: read the final processing result obtained by the operation core from the local memory, and store the final processing result into the global memory; send an interrupt signal to the control end so that the control end obtains the final processing result through the direct memory access engine, and then the control end merges the final processing results obtained by all acceleration cards to obtain the processing result of the target data.

11. The data processing device according to claim 9, characterized in that: The algorithm core is also used to: use the combined data obtained by combining the sub-processing results retained by the algorithm core and the sub-processing results sent by other acceleration cards as the data to be processed.

12. The data processing device according to claim 11, characterized in that: The operation core includes a Fourier transform core, a convolution core and a transposition module; the sub-target data includes data obtained by splitting the target data in the Z direction according to the number of targets; The operation core is used to: perform X-dimensional Fourier transform on the sub-target data through the Fourier transform core, perform transposition processing on the transformation result through the transposition module, perform Y-dimensional Fourier transform on the transposed data through the Fourier transform core to obtain a processing result, and split the processing result in the X direction according to the target number to obtain a first round of sub-processing results; Reading the combined data obtained by the first round of sub-processing results stored for the first time from the local memory, performing a Z-dimensional Fourier transform on the first combined data through the Fourier transform core, performing convolution processing on the transformation result through the convolution core, performing a Z-dimensional Fourier inverse transform on the convolved data through the Fourier transform core to obtain a processing result, splitting the processing result in the Z direction according to the target number to obtain a second round of sub-processing results; The combined data obtained by the second round of processing results stored for the second time is read from the local memory, the second combined data is subjected to the Fourier inverse transform of the Y dimension through the Fourier transform core, the transformation result is transposed through the transposition module, and the transposed data is subjected to the Fourier inverse transform of the X dimension through the Fourier transform core to obtain the final processing result.

13. A data processing method, characterized in that: An accelerator card applied to a data processing device according to any one of claims 1 to 12, comprising: Processing the data to be processed by the algorithm kernel to obtain a processing result; splitting the processing result into a target number of sub-processing results; retaining one sub-processing result and sending the remaining sub-processing results to a global memory connected to the algorithm kernel; The sub-processing results of the interaction between the accelerator card and other accelerator cards are stored in the global memory; Through a data transmission module connected to the global memory, the sub-processing result sent by the accelerator card is read from the global memory and transmitted to the transmission layer, or the sub-processing result sent by other accelerator cards transmitted by the transmission layer is received and stored in the global memory; Sending the sub-processing result sent by the data transmission module to other accelerator cards through the transmission layer connected to the data transmission module, or receiving the sub-processing result sent by other accelerator cards and transmitting it to the data transmission module, so as to process the sub-processing result; The data processing device includes the target number of acceleration cards, which is greater than or equal to 2, and the data to be processed includes merged data obtained by merging the sub-processing results retained by the algorithm kernel and the sub-processing results sent by other acceleration cards.

14. A computer program product comprising a computer program / instructions, characterized in that When the computer program / instructions are executed by a processor, the steps of the data processing method according to claim 13 are implemented.

15. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the steps of the data processing method as claimed in claim 13 when executing the computer program.

16. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the data processing method according to claim 13 are implemented.

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