A method for constructing a three-dimensional thermal resistance network model of a multi-chip module considering heat dissipation vias

Abstract

The present invention discloses a method for constructing a three-dimensional thermal resistance network model of a multi-chip module considering heat dissipation through holes, and relates to the field of microelectronics technology. The method of the present invention comprises: splitting the multi-chip module into a plurality of single-chip equivalent units containing heat dissipation through holes, and constructing a lateral thermal resistance network model corresponding to each single-chip equivalent unit; constructing a lateral thermal resistance network model of the multi-chip module according to the lateral thermal resistance network model of the single-chip equivalent unit and the coupled diffusion thermal resistance between adjacent chips in the multi-chip module; calculating the longitudinal thermal resistance of the multi-chip module and the convective heat transfer thermal resistance at the bottom of the substrate of the multi-chip module; establishing a three-dimensional thermal resistance network model of the multi-chip module according to the lateral thermal resistance network model of the multi-chip module, the longitudinal thermal resistance of the multi-chip module, and the convective heat transfer thermal resistance at the bottom of the substrate of the multi-chip module, so as to realize thermal analysis of the multi-chip module. The present invention solves the problem that heat dissipation through holes and coupled diffusion thermal resistance are not considered in the current steady-state thermal model of the multi-chip module.

Description

Technical Field

[0001] The invention belongs to the field of microelectronic technology, and in particular relates to a method for constructing a three-dimensional thermal resistance network model of a multi-chip module taking into account heat dissipation through holes. Background Art

[0002] Multi-chip modules (MCMs) integrate multiple bare chips and other components on the same substrate, which is an effective way to achieve integration, modularization and multifunctionality of electronic products. However, as MCM develops towards multifunctionality, miniaturization and high speed, more and more chips are integrated on the limited area of ​​the substrate, and the power consumption of the chip is also increasing. The heat generated by the chip cannot be transferred out in a timely and effective manner, which will inevitably lead to excessive local temperature of the chip, and then cause a series of chip failure problems, seriously affecting the service life of electronic equipment. According to the Arrhenius empirical equation, for every 10°C increase in the chip operating temperature, the reaction speed in the chip doubles and the reliability of the chip decreases by 50%. Therefore, it is necessary to analyze the thermal performance of multi-chip modules. In order to solve the thermal problem of multi-chip modules, the industry currently mainly uses microchannels, forced air cooling and adding thermal conductive vias at the bottom of the substrate for heat dissipation. However, the former two will occupy a large volume and have a high process complexity. When the volume of the module becomes smaller and smaller, the advantage of using thermal conductive vias for heat dissipation will become greater and greater.

[0003] At present, for the thermal analysis of multi-chip modules, the existing technology has adopted the following evaluation methods. First, through the thermal resistance model method, using the thermoelectric analogy method, the resistance, capacitance, voltage and current are equivalent to thermal resistance, heat capacity, temperature difference and heat flow to establish a one-dimensional thermal resistance topological network method to analyze the steady-state and transient temperature distribution characteristics of the multi-chip module; second, the thermal resistance matrix model method is adopted to calculate the self-thermal resistance and coupled thermal resistance of each chip, establish the corresponding matrix, and then solve the matrix equations according to the excitation size applied by the chip to analyze the temperature distribution of the chip; third, the numerical simulation method is adopted to discretize the actual physical model of the multi-chip module into different points and then solve the corresponding linear equations according to the finite element method, finite difference method and finite volume method to solve the complex heat transfer problem.

[0004] However, the above thermal analysis methods have some limitations. Although method 1 is simple, fast and efficient, there is heat diffusion and cross-coupling in the heat flow transmission process of multi-chip modules, which makes the traditional one-dimensional thermal resistance model have certain errors compared with the actual situation, and the error will become larger and larger as the number of chips increases. Method 2 has high accuracy when analyzing the temperature distribution of multi-chip modules, but it cannot reflect the actual heat flow transmission between multi-chip modules, and each thermal resistance value in the thermal resistance matrix needs to be determined through multiple simulations, which consumes more resources. Method 3 is time-consuming in model construction and simulation calculations. Summary of the invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a method for constructing a three-dimensional thermal resistance network model of a multi-chip module considering heat dissipation through holes. The technical problem to be solved by the present invention is achieved by the following technical solutions:

[0006] The present invention provides a method for constructing a three-dimensional thermal resistance network model of a multi-chip module taking into account heat dissipation through holes, comprising:

[0007] Step 1: split the multi-chip module into multiple single-chip equivalent units with heat dissipation through holes, and construct a lateral thermal resistance network model corresponding to each of the single-chip equivalent units;

[0008] Step 2: constructing a lateral thermal resistance network model of a multi-chip module according to the lateral thermal resistance network model of the single-chip equivalent unit and the coupled diffusion thermal resistance between adjacent chips in the multi-chip module;

[0009] Step 3: Calculate the longitudinal thermal resistance of the multi-chip module and the convection heat transfer thermal resistance of the bottom of the substrate of the multi-chip module;

[0010] Step 4: Establish a three-dimensional thermal resistance network model of the multi-chip module based on the lateral thermal resistance network model of the multi-chip module, the longitudinal thermal resistance of the multi-chip module, and the convection heat transfer thermal resistance at the bottom of the substrate of the multi-chip module, so as to realize thermal analysis of the multi-chip module using the three-dimensional thermal resistance network model of the multi-chip module.

[0011] Compared with the prior art, the present invention has the following beneficial effects:

[0012] 1. The method for constructing a three-dimensional thermal resistance network model of a multi-chip module considering heat dissipation vias of the present invention establishes equivalent thermal resistance network models at the horizontal and vertical levels respectively and then establishes a three-dimensional thermal resistance network model. The three-dimensional thermal resistance network model can be used to realize the lateral, longitudinal and thermal coupling heat transfer analysis between multi-chip modules, revealing the heat flow diffusion and thermal coupling laws of the multi-chip module.

[0013] 2. The method for constructing a three-dimensional thermal resistance network model of a multi-chip module considering heat dissipation vias of the present invention takes into account the coupled diffusion thermal resistance between adjacent chips in the multi-chip module and the thermal resistance of the heat dissipation vias when establishing the three-dimensional thermal resistance network model, thereby solving the problem that heat dissipation vias and coupled diffusion thermal resistance are not considered in the current steady-state thermal model of the multi-chip module. The chip temperature calculated using the three-dimensional thermal resistance network model has higher accuracy, and compared with finite element simulation, the calculation time is shortened and computing resources are saved.

[0014] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the following specifically cites a preferred embodiment and describes it in detail with the accompanying drawings as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a flow chart of a method for constructing a three-dimensional thermal resistance network model of a multi-chip module considering heat dissipation through holes provided by an embodiment of the present invention;

[0016] Figure 2 is a schematic structural diagram of a multi-chip module provided by an embodiment of the present invention;

[0017] Figure 3 is a schematic diagram of heat conduction of a single-chip equivalent unit provided by an embodiment of the present invention;

[0018] Figure 4 is a schematic diagram of a lateral thermal resistance network model of a single-chip equivalent unit provided by an embodiment of the present invention;

[0019] Figure 5 is a schematic diagram of a circular heat source and a circular substrate corresponding to a single-chip equivalent unit provided by an embodiment of the present invention;

[0020] Figure 6 is a schematic diagram of a coordinate system established with the lower left corner of the substrate as the coordinate origin provided by an embodiment of the present invention;

[0021] Figure 7 is a schematic diagram of heat flow coupling diffusion of multiple chips provided by an embodiment of the present invention;

[0022] Figure 8 It is a schematic diagram of a lateral thermal resistance network model of a multi-chip module provided by an embodiment of the present invention;

[0023] Fig. 9 It is a schematic diagram of a three-dimensional thermal resistance network model of a multi-chip module provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0024] In order to further illustrate the technical means and effects adopted by the present invention to achieve the predetermined purpose of the invention, the following is a detailed description of a method for constructing a three-dimensional thermal resistance network model of a multi-chip module considering heat dissipation through holes proposed in accordance with the present invention, in combination with the accompanying drawings and specific implementation methods.

[0025] The above and other technical contents, features and effects of the present invention are clearly presented in the following detailed description of the specific implementation modes in conjunction with the accompanying drawings. Through the description of the specific implementation modes, the technical means and effects adopted by the present invention to achieve the predetermined purpose can be more deeply and specifically understood. However, the attached drawings are only for reference and explanation purposes and are not used to limit the technical solutions of the present invention.

[0026] The embodiment of the present invention provides a method for constructing a three-dimensional thermal resistance network model of a multi-chip module taking into account heat dissipation through holes, see Figure 1 , Figure 1 1 is a flow chart of a method for constructing a three-dimensional thermal resistance network model of a multi-chip module taking into account heat dissipation vias provided by an embodiment of the present invention. Figure 1 As shown, the method for constructing a three-dimensional thermal resistance network model of a multi-chip module considering heat dissipation through holes in this embodiment includes:

[0027] Step 1: Split the multi-chip module into multiple single-chip equivalent units with heat dissipation vias, and construct a lateral thermal resistance network model corresponding to each single-chip equivalent unit.

[0028] In this embodiment, the multi-chip module includes a substrate and a plurality of chips arranged on the substrate. The chips serve as heat sources. Each chip is fixed to the substrate by a thermally conductive adhesive. The substrate is provided with heat dissipation holes. The heat dissipation holes include outer heat dissipation holes arranged around the chips and inner heat dissipation holes located under the chips. The heat dissipation holes are filled with copper.

[0029] For example, see Figure 2 , Figure 2 It is a structural schematic diagram of a multi-chip module provided in an embodiment of the present invention. The multi-chip module includes four chips as heat sources, and a substrate is provided with 9 external heat dissipation through holes which are respectively located around the chips, and 4 internal heat dissipation through holes which are respectively located below the chips.

[0030] In an optional embodiment, step 1 includes:

[0031] Step 1.1: Obtain the structural parameters of the multi-chip module.

[0032] In an optional embodiment, the structural parameters of the multi-chip module include substrate side length, chip side length, substrate thickness, chip thickness, thermal conductive adhesive thickness, outer heat dissipation via radius, inner heat dissipation via radius, heat dissipation via height and center point coordinates between adjacent chips.

[0033] For example, Figure 2 Taking the multi-chip module shown in the figure as an example, its structural parameters are shown in Table 1.

[0034] Table 1 Structural parameters of multi-chip modules

[0035]

[0036] Step 1.2: Split the multi-chip module into multiple single-chip equivalent units, and convert the rectangular heat source and rectangular substrate in the single-chip equivalent unit into a circular heat source and circular substrate with equal area according to the structural parameters of the multi-chip module.

[0037] In this embodiment, the substrate is divided based on the coordinates of the center points between adjacent chips, and the multi-chip module is split into multiple single-chip rectangular units as single-chip equivalent units. Each single-chip equivalent unit includes a rectangular substrate, a chip on the substrate, external heat dissipation through holes around the chip, and internal heat dissipation through holes under the chip.

[0038] For example, Figure 2 Taking the multi-chip module shown as an example, it can be divided into four single-chip equivalent units, each of which includes a rectangular substrate, a chip on the substrate, four external heat dissipation vias around the chip, and one internal heat dissipation via under the chip.

[0039] For a single chip equivalent unit, the heat conduction diagram when the substrate contains thermal vias is as follows: Figure 3 As shown, Figure 3 Schematic diagram of heat conduction of a single chip equivalent unit provided by an embodiment of the present invention. Figure 3 It can be seen that part of the heat generated by the chip as a heat source will diffuse into the external heat dissipation through-holes through lateral diffusion, and the other part will diffuse along the substrate to the bottom of the substrate or the side boundary of the substrate.

[0040] In the traditional thermal analysis model, it is assumed that the heat transfer is transmitted downward in a single direction or conducted downward at a certain heat diffusion angle in each layer, and the lateral diffusion of heat is not considered. In this embodiment, the lateral diffusion of heat is considered, and the multi-chip module is split into multiple single-chip equivalent units with heat dissipation holes. In order to facilitate the calculation of the thermal resistance of the single-chip equivalent unit, the rectangular heat source and rectangular substrate in the single-chip equivalent unit are converted into circular heat sources and circular substrates with equal areas, and the lateral thermal resistance of the single-chip equivalent unit is calculated, thereby establishing a lateral thermal resistance network model of the single-chip equivalent unit.

[0041] Step 1.3: According to the structural parameters of the single-chip equivalent unit and the multi-chip module, the lateral thermal resistance of the single-chip equivalent unit is calculated to obtain the lateral thermal resistance network model of the single-chip equivalent unit; wherein the lateral thermal resistance of the single-chip equivalent unit includes: the lateral thermal resistance of the heat flow diffusing through the substrate to the external heat dissipation vias, the lateral thermal resistance of the heat flow flowing through the external heat dissipation vias, and the lateral thermal resistance of the heat flow diffusing through the substrate.

[0042] In this embodiment, the lateral thermal resistance of heat flow through the substrate to the external heat dissipation through-hole is calculated according to the following formula:

[0043] ;

[0044] In the formula, It represents the lateral thermal resistance of the heat flow through the substrate to the external heat dissipation vias outside the chip. is the number of external heat dissipation vias in a single chip equivalent unit, is the radius of the converted circular heat source in the single-chip equivalent unit, is the diffusion radius of the heat flux in the single-chip equivalent unit from the center of the converted circular heat source to the external heat dissipation through hole on the converted circular substrate, is the radius of the external heat dissipation hole, is the thermal conductivity of the substrate, is the substrate thickness, is the integration variable.

[0045] In this embodiment, the lateral thermal resistance of the heat flow through the external heat dissipation through hole is calculated according to the following formula:

[0046] ;

[0047] In the formula, It represents the lateral thermal resistance of heat flow through the external heat dissipation through hole, is the diffusion radius of the heat flux in the single-chip equivalent unit from the center of the converted circular heat source to the edge of the converted circular substrate on the converted circular substrate, is the thermal conductivity of the external heat dissipation through hole.

[0048] In this embodiment, the lateral thermal resistance of heat flow through the substrate is calculated according to the following formula:

[0049] ;

[0050] In the formula, represents the lateral thermal resistance of heat flow through the substrate, is the side length of the equivalent unit of a single chip.

[0051] In this embodiment, , and It can be calculated according to the following formula:

[0052] ;

[0053] In the formula, and are the equivalent unit side length and chip side length respectively.

[0054] For example, Figure 3Taking the single chip equivalent unit shown in FIG. 1 as an example, the schematic diagram of the lateral thermal resistance network model and the circular heat source and circular substrate corresponding to the single chip equivalent unit is shown in FIG. Figure 4 and Figure 5 shown. Figure 4 is a schematic diagram of a lateral thermal resistance network model of a single-chip equivalent unit provided by an embodiment of the present invention, Figure 5 Schematic diagram of a circular heat source and a circular substrate corresponding to a single-chip equivalent unit provided by an embodiment of the present invention. Figure 4 middle , , and is the lateral thermal resistance of heat flow through the substrate to the external heat dissipation through-holes, all according to The calculation formula is calculated, which is expressed as . , , and is the lateral thermal resistance of heat flow through the external heat dissipation through hole, all according to The calculation formula is calculated, which is expressed as . , , and is the lateral thermal resistance of heat flow through the substrate, all according to The calculation formula is calculated, which is expressed as .

[0055] Step 2: According to the lateral thermal resistance network model of the single-chip equivalent unit and the coupled diffusion thermal resistance between adjacent chips in the multi-chip module, a lateral thermal resistance network model of the multi-chip module is constructed.

[0056] In an optional embodiment, step 2 includes:

[0057] Step 2.1: Calculate the coupled spreading thermal resistance between adjacent chips in the multi-chip module.

[0058] In a multi-chip module, cross-coupling of heat flows occurs when adjacent chips are operating, see Figure 6 and Figure 7 , Figure 6 is a schematic diagram of a coordinate system established with the lower left corner of the substrate as the coordinate origin provided by an embodiment of the present invention; Figure 7 It is a schematic diagram of heat flow coupling diffusion of multiple chips provided by an embodiment of the present invention.

[0059] set up Figure 6 The length and width of the substrate are , two chips are used as two heat sources and their size is and express, and Represent the coordinates of the center points of the two chips respectively, then, the chip Chip Coupling diffusion thermal resistance It can be expressed as:

[0060] ;

[0061] In the formula, For multi-chip modules and chips Adjacent chips Chip The coupled diffusion thermal resistance, For application on chip The thermal power on For Chip The average temperature rise of the substrate when working alone, For Chip Working chip The temperature rise produced.

[0062] in, and It can be expressed as:

[0063] ;

[0064] ;

[0065] In the formula, For Chip The area of Any coordinate point on the substrate surface On Chip Temperature rise under operation. It can be expressed as:

[0066] ;

[0067] in, , is the eigenvalue coefficient, , , and are Fourier coefficients, respectively expressed as:

[0068] ;

[0069] ;

[0070] ;

[0071] .

[0072] In the formula, , and are the eigenvalues ​​of the derivation process, respectively , , ; , and Is an extension function Function, extension function It is expressed as:

[0073] ;

[0074] when Assign values ​​to , , You can get it when , , The corresponding function value. is the substrate thickness, is the convective heat transfer coefficient at the bottom of the substrate, is the hyperbolic sine function, is a hyperbolic cosine function. In this embodiment, the substrate contains a thermal through hole, and the thermal conductivity will change. Therefore, it is necessary to solve the equivalent thermal conductivity of the two. According to the parallel flat wall equivalent method, the equivalent thermal conductivity of the substrate with through holes is It can be expressed as:

[0075] ;

[0076] ;

[0077] In the formula, , are the thermal conductivity of the substrate and the thermal conductivity of the external heat dissipation through hole, , are the projection areas of the through hole and substrate on the horizontal plane respectively.

[0078] Step 2.2: According to the structure of the multi-chip module, the lateral thermal resistance network model of the single-chip equivalent unit is connected at the intersecting temperature nodes, and the adjacent chips are connected through the coupled diffusion thermal resistance between the adjacent chips to obtain the lateral thermal resistance network model of the multi-chip module.

[0079] In this embodiment, according to the structure of the multi-chip module, the lateral thermal resistance network models of adjacent single-chip equivalent units are connected at the intersecting temperature nodes, and the coupled diffusion thermal resistance between chips is considered to establish the lateral thermal resistance network model of the multi-chip module.

[0080] For example, Figure 2Take the multi-chip module shown in the figure as an example. The lateral thermal resistance network model of the multi-chip module is as follows: Figure 8 As shown, the lateral thermal resistance of the multi-chip module includes the lateral thermal resistance of heat diffusion through the substrate to the surrounding external heat dissipation through holes, the lateral thermal resistance of heat flowing through the external heat dissipation through holes, the lateral thermal resistance of heat diffusion through the substrate and the coupled diffusion thermal resistance between chips.

[0081] Step 3: Calculate the longitudinal thermal resistance of the MCM and the convection heat transfer thermal resistance of the bottom of the MCM substrate.

[0082] In this embodiment, the longitudinal thermal resistance of the multi-chip module includes: the longitudinal thermal resistance of the heat flow through the chip, the longitudinal thermal resistance of the heat flow through the thermal conductive adhesive, the longitudinal thermal resistance of the heat flow through the external heat dissipation through holes, the longitudinal thermal resistance of the heat flow through the internal heat dissipation through holes, and the longitudinal thermal resistance of the heat flow through the substrate.

[0083] The calculation formula of longitudinal thermal resistance is as follows:

[0084] ;

[0085] In the formula, is the thermal conductivity of the material, is the longitudinal heat conduction cross-sectional area, is the longitudinal heat conduction distance.

[0086] In this embodiment, the longitudinal thermal resistance of the multi-chip module can be calculated according to the structural parameters of the multi-chip module according to the calculation formula of the longitudinal thermal resistance shown above.

[0087] In this embodiment, the convection heat transfer thermal resistance at the bottom of the substrate of the multi-chip module is calculated according to the following formula:

[0088] ;

[0089] In the formula, is the convective heat flux, is the projected area of ​​the substrate on the horizontal plane.

[0090] Step 4: According to the lateral thermal resistance network model of the multi-chip module, the longitudinal thermal resistance of the multi-chip module and the convection heat transfer thermal resistance at the bottom of the substrate of the multi-chip module, a three-dimensional thermal resistance network model of the multi-chip module is established to realize thermal analysis of the multi-chip module using the three-dimensional thermal resistance network model of the multi-chip module.

[0091] In an optional embodiment, step 4 includes:

[0092] Step 4.1: According to the structure of the multi-chip module, the transverse thermal resistance network model of the multi-chip module is connected with the longitudinal thermal resistance of the multi-chip module at the intersecting temperature nodes, and the convection heat transfer thermal resistance at the bottom of the substrate of the multi-chip module is added to obtain the three-dimensional thermal resistance network model of the multi-chip module.

[0093] Step 4.2: According to the three-dimensional thermal resistance network model of the multi-chip module, Kirchhoff's law is used to calculate the temperature of each chip in the multi-chip module to achieve thermal analysis of the multi-chip module, wherein the temperature of the chip in the multi-chip module is calculated according to the following formula:

[0094] ;

[0095] In the formula, For Chip The temperature, For Chip The power consumption, For heat flow through the chip The longitudinal thermal resistance, is the longitudinal thermal resistance of heat flow through the thermal conductive adhesive, For multi-chip modules and chips All adjacent chip-to-chip The total parallel thermal resistance of the coupled diffusion thermal resistance, is the convection heat transfer thermal resistance at the bottom of the substrate of the multi-chip module, is the lateral thermal resistance of heat flow through the external heat dissipation through-hole, is the longitudinal thermal resistance of heat flow through the external heat dissipation through-hole, is the number of heat dissipation holes in the multi-chip module, is the parallel total thermal resistance of the longitudinal thermal resistance of the heat flow through the internal heat dissipation through-holes in the multi-chip module, is the thermal resistance of heat flow through the substrate, For Chip The initial temperature, Indicates parallel connection.

[0096] It should be noted that the thermal resistance of the heat flow through the substrate It is the total thermal resistance in parallel of the longitudinal thermal resistance of the heat flow through the substrate and the lateral thermal resistance of the heat flow through the substrate, wherein the lateral thermal resistance of the heat flow through the substrate includes the lateral thermal resistance of the heat flow diffusing through the substrate to the external heat dissipation through-holes and the lateral thermal resistance of the heat flow diffusing through the substrate.

[0097] For example, Figure 2 Taking the multi-chip module shown in FIG. 1 as an example, the three-dimensional thermal resistance network model of the multi-chip module is obtained as follows: Fig. 9 As shown in the figure. R cs_21 , R cs_12is the coupling diffusion thermal resistance between chip 1 and chip 2, R cs_31 , R cs_13 is the coupling diffusion thermal resistance between chip 1 and chip 3, R cs_41 , R cs_14 is the coupling diffusion thermal resistance between chip 1 and chip 4, R cs_23 , R cs_32 is the coupling diffusion thermal resistance between chip 2 and chip 3, R cs_42 , R cs_24 is the coupling diffusion thermal resistance between chip 2 and chip 4, R cs_34 and R cs_43 is the coupling diffusion thermal resistance between chip 3 and chip 4. R L1 ~ R L9 is the lateral thermal resistance of heat flow through the external heat dissipation through-hole, R T1 ~ R T9 It is the longitudinal thermal resistance of heat flow through the external heat dissipation through-hole. R I1 ~ R I4 It represents the longitudinal thermal resistance of heat flow through the inner through hole, and its total parallel thermal resistance is . R conv is the convection heat transfer thermal resistance at the bottom of the substrate of the multi-chip module. R 1_1 、R 1_2 、R 1_4 is the lateral thermal resistance of the heat flow of chip 1 diffusing through the substrate to the external heat dissipation through-holes, R 1_3 、R 1_5 is the lateral thermal resistance of the heat flow of chip 1 through the substrate; R 2_1 、R 2_3 、R 2_4 is the lateral thermal resistance of the heat flow from chip 2 diffusing through the substrate to the external heat dissipation vias, R 2_2 、R 2_5 is the lateral thermal resistance of the heat flow of chip 2 diffusing through the substrate; R3_1 、R 3_3 、R 3_5 is the lateral thermal resistance of the heat flow of chip 3 diffusing through the substrate to the external heat dissipation through-holes, R 3_2 、R 3_4 is the lateral thermal resistance of the heat flow of chip 3 diffusing through the substrate; R 4_1 、R 4_3 、R 4_5 is the lateral thermal resistance of the heat flow of chip 4 diffusing through the substrate to the external heat dissipation through-holes, R 4_2 、R 4_4 is the lateral thermal resistance of the heat flow of chip 4 spreading through the substrate.

[0098] The method for constructing a three-dimensional thermal resistance network model of a multi-chip module considering heat dissipation vias in an embodiment of the present invention establishes equivalent thermal resistance network models at the horizontal and vertical levels respectively and then establishes a three-dimensional thermal resistance network model. The three-dimensional thermal resistance network model can realize the lateral, longitudinal and thermal coupling heat transfer analysis between the multi-chip modules, and reveals the heat flow diffusion and thermal coupling laws of the multi-chip modules. When establishing the three-dimensional thermal resistance network model, the coupled diffusion thermal resistance between adjacent chips in the multi-chip module and the thermal resistance of the heat dissipation vias are taken into account, which solves the problem that the heat dissipation vias and the coupled diffusion thermal resistance are not considered in the current steady-state thermal model of the multi-chip module. The chip temperature calculated using the three-dimensional thermal resistance network model has higher accuracy, and compared with finite element simulation, the calculation time is shortened and the calculation resources are saved.

[0099] Furthermore, in order to verify the efficiency and accuracy of the three-dimensional thermal resistance network model of a multi-chip module obtained by the method for constructing a three-dimensional thermal resistance network model of a multi-chip module considering heat dissipation vias of the present invention when calculating the temperature of each chip. Figure 7 Taking the three-dimensional thermal resistance network model of the multi-chip module shown as an example, the structural parameters of the multi-chip module are consistent with those in Table 1. The finite element simulation results are used as a reference to compare the three-dimensional thermal resistance network model with the traditional one-dimensional thermal resistance model. The comparison results are shown in Table 2, which is a comparison of the temperatures of each chip in the multi-chip module calculated by the finite element simulation model, the traditional one-dimensional thermal resistance model, and the three-dimensional thermal resistance network model constructed by the method of the present invention when the power consumption of chips 1, 2, 3, and 4 in the multi-chip module is 5W, 4W, 3W, and 2W respectively.

[0100] Table 2 Comparison of computational efficiency and accuracy of different models

[0101]

[0102] As can be seen from Table 2, the three-dimensional thermal resistance network model constructed by the method of the present invention calculates the temperature of each chip with an average error of only 0.862% compared with the finite element simulation, and the calculation time is 1.674s. Compared with the traditional thermal resistance network model, although the calculation efficiency of the three-dimensional thermal resistance network model is slightly lower, the calculation accuracy is greatly improved. The high calculation efficiency of the traditional thermal resistance network model is because it only considers the transmission of heat flow in the vertical direction, and does not analyze the lateral diffusion of heat flow in the horizontal direction, and the calculation process is relatively simple. However, in actual working conditions, as the scale of the chip becomes larger and larger, the use of the traditional thermal resistance network model to predict the chip temperature will further increase the error.

[0103] The three-dimensional thermal resistance network model of the multi-chip module obtained by the method for constructing the three-dimensional thermal resistance network model of the multi-chip module considering the heat dissipation through holes in the present invention comprehensively considers the lateral and longitudinal conduction of heat flow and the cross-coupling of heat flow between chips while ensuring accuracy, and can more completely and efficiently perform temperature characteristic analysis on high-power multi-chip modules.

[0104] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the term "include", "comprise" or any other variant is intended to cover non-exclusive inclusion, so that the article or device including a series of elements includes not only those elements, but also other elements that are not explicitly listed. In the absence of more restrictions, the elements defined by the sentence "including one..." do not exclude the existence of other identical elements in the article or device including the elements. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The orientation or position relationship indicated by "up", "down", "left", "right", etc. is based on the orientation or position relationship shown in the accompanying drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present invention.

[0105] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A method for constructing a three-dimensional thermal resistance network model of a multi-chip module considering heat dissipation through holes, characterized in that: include: Step 1: split the multi-chip module into multiple single-chip equivalent units with heat dissipation through holes, and construct a lateral thermal resistance network model corresponding to each of the single-chip equivalent units; Step 1 includes: Step 1.1: Obtaining structural parameters of the multi-chip module; Step 1.2: splitting the multi-chip module into a plurality of single-chip equivalent units, and converting the rectangular heat source and rectangular substrate in the single-chip equivalent unit into circular heat source and circular substrate with equal area according to the structural parameters of the multi-chip module; Step 1.3: Calculate the lateral thermal resistance of the single-chip equivalent unit according to the structural parameters of the single-chip equivalent unit and the multi-chip module, and obtain the lateral thermal resistance network model of the single-chip equivalent unit; wherein the lateral thermal resistance of the single-chip equivalent unit includes: the lateral thermal resistance of the heat flow diffusing from the substrate to the external heat dissipation through-hole, the lateral thermal resistance of the heat flow diffusing from the external heat dissipation through-hole, and the lateral thermal resistance of the heat flow diffusing from the substrate; Step 2: constructing a lateral thermal resistance network model of a multi-chip module according to the lateral thermal resistance network model of the single-chip equivalent unit and the coupled diffusion thermal resistance between adjacent chips in the multi-chip module; Step 2 includes: Step 2.1: Calculate the coupling diffusion thermal resistance between adjacent chips in the multi-chip module; Step 2.2: According to the structure of the multi-chip module, the lateral thermal resistance network model of the single-chip equivalent unit is connected at the intersecting temperature nodes, and the adjacent chips are connected through the coupled diffusion thermal resistance between the adjacent chips to obtain the lateral thermal resistance network model of the multi-chip module; Step 3: Calculate the longitudinal thermal resistance of the multi-chip module and the convection heat transfer thermal resistance of the bottom of the substrate of the multi-chip module; Step 4: establishing a three-dimensional thermal resistance network model of the multi-chip module according to the transverse thermal resistance network model of the multi-chip module, the longitudinal thermal resistance of the multi-chip module, and the convection heat transfer thermal resistance of the bottom of the substrate of the multi-chip module, so as to realize thermal analysis of the multi-chip module by using the three-dimensional thermal resistance network model of the multi-chip module; Step 4 includes: Step 4.1: According to the structure of the multi-chip module, the transverse thermal resistance network model of the multi-chip module and the longitudinal thermal resistance of the multi-chip module are connected at the intersecting temperature nodes, and the convection heat transfer thermal resistance of the bottom of the substrate of the multi-chip module is added to the bottom of the substrate of the multi-chip module to obtain a three-dimensional thermal resistance network model of the multi-chip module; Step 4.2: According to the three-dimensional thermal resistance network model of the multi-chip module, using Kirchhoff's law, the temperature of each chip in the multi-chip module is calculated to achieve thermal analysis of the multi-chip module, wherein the temperature of the chip in the multi-chip module is calculated according to the following formula: Where, T i is the temperature of chip i, Q i is the power consumption of chip i, R chip_i is the longitudinal thermal resistance of heat flow through chip i, R a is the longitudinal thermal resistance of heat flow through the thermal conductive adhesive, R cs_i is the total parallel thermal resistance of the coupled diffusion thermal resistances of all chips adjacent to chip i in the multi-chip module, R conv is the convection heat transfer resistance of the bottom of the MCM substrate, R Ll is the lateral thermal resistance of heat flow through the external heat dissipation through-hole, R Tl is the longitudinal thermal resistance of heat flow through the external heat dissipation through-hole, M is the number of external heat dissipation through-holes in the multi-chip module, and R I is the parallel total thermal resistance of the longitudinal thermal resistance of the heat flow through the internal heat dissipation through-holes in the multi-chip module, R b is the thermal resistance of heat flow through the substrate, T α is the initial temperature of chip i, / / indicates parallel connection.

2. The method for constructing a three-dimensional thermal resistance network model of a multi-chip module considering heat dissipation vias according to claim 1, characterized in that: The structural parameters of the multi-chip module include substrate side length, chip side length, substrate thickness, chip thickness, thermal conductive adhesive thickness, outer heat dissipation through hole radius, inner heat dissipation through hole radius, heat dissipation through hole height and center point coordinates between adjacent chips.

3. The method for constructing a three-dimensional thermal resistance network model of a multi-chip module considering heat dissipation vias according to claim 1, characterized in that: The lateral thermal resistance of the heat flow diffusing through the substrate to the external heat dissipation through-hole is calculated according to the following formula: In the formula, R b1 It represents the lateral thermal resistance of the external heat dissipation vias that diffuse heat through the substrate to the outside of the chip. N is the number of external heat dissipation vias in a single chip equivalent unit. e0 is the radius of the converted circular heat source in the single chip equivalent unit, r e1 is the diffusion radius of the heat flux in the single-chip equivalent unit from the center of the converted circular heat source on the converted circular substrate to the external heat dissipation through hole, r0 is the radius of the external heat dissipation through hole, k b is the thermal conductivity of the substrate, H is the thickness of the substrate, and r is the integral variable.

4. The method for constructing a three-dimensional thermal resistance network model of a multi-chip module considering heat dissipation vias according to claim 1, characterized in that: The lateral thermal resistance of the heat flow through the external heat dissipation through-hole is calculated according to the following formula: In the formula, R L represents the lateral thermal resistance of heat flow through the external heat dissipation through-hole, N is the number of external heat dissipation through-holes in the single chip equivalent unit, r e0 is the radius of the converted circular heat source in the single chip equivalent unit, r e1 is the diffusion radius of the heat flux in the single-chip equivalent unit from the center of the converted circular heat source to the external heat dissipation through hole on the converted circular substrate, r e2 k is the diffusion radius of the heat flux in the single-chip equivalent unit from the center of the converted circular heat source to the edge of the converted circular substrate on the converted circular substrate, via is the thermal conductivity of the external heat dissipation through hole, H is the substrate thickness, and r is the integral variable.

5. The method for constructing a three-dimensional thermal resistance network model of a multi-chip module considering heat dissipation vias according to claim 1, characterized in that: The lateral thermal resistance of the heat flow through the substrate is calculated according to the following formula: In the formula, R b2 It represents the lateral thermal resistance of heat flow through the substrate, N is the number of external heat dissipation holes in the single chip equivalent unit, r e0 is the radius of the converted circular heat source in the single chip equivalent unit, r e2 k is the diffusion radius of the heat flux in the single-chip equivalent unit from the center of the converted circular heat source to the edge of the converted circular substrate on the converted circular substrate, b is the thermal conductivity of the substrate, H is the thickness of the substrate, W is the side length of the single-chip equivalent unit, and r is the integral variable.

6. The method for constructing a three-dimensional thermal resistance network model of a multi-chip module considering heat dissipation vias according to claim 1, characterized in that: The coupling diffusion thermal resistance between adjacent chips in the multi-chip module is calculated according to the following formula: In the formula, R cs_ij is the coupling diffusion thermal resistance of chip j adjacent to chip i in the multi-chip module, P d,i is the thermal power applied to chip i, is the average temperature rise of the substrate when chip j works alone, It is the temperature rise of chip i when chip j is working.

7. The method for constructing a three-dimensional thermal resistance network model of a multi-chip module considering heat dissipation vias according to claim 1, characterized in that: The longitudinal thermal resistance of the multi-chip module includes: the longitudinal thermal resistance of heat flow through the chip, the longitudinal thermal resistance of heat flow through the thermal conductive adhesive, the longitudinal thermal resistance of heat flow through the external heat dissipation through-holes, the longitudinal thermal resistance of heat flow through the internal heat dissipation through-holes and the longitudinal thermal resistance of heat flow through the substrate.

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