Method, system and storage medium for adding vent holes in chip carrier

Abstract

The present application provides a method, system and storage medium for adding vents in a chip carrier, which includes obtaining a chip carrier design file in a format that supports layout design rule checking, generating vent layers for each layer with different sizes and / or arrays, removing vents that do not meet predetermined design rules from the generated vent layers, detecting local areas where vents are insufficiently added, and generating vent layers corresponding to the relevant local areas, and merging these layers to obtain a final vent layer. This solution not only has good flexibility and scalability, but also improves design efficiency, which is conducive to shortening the entire design and production cycle.

Description

Technical Field

[0001] The present application relates to chip packaging testing, and more particularly to a method and system for automatically adding vent holes to a chip carrier. Background Art

[0002] The statements in this section are merely intended to provide background information related to the technical solution of the present application to aid understanding, and they do not necessarily constitute prior art for the technical solution of the present application.

[0003] Chip carrier is a basic component used in the chip packaging process to protect the bare chip (die) and realize the electrical interconnection between the integrated circuit on the bare chip and the external electronic circuit, and at the same time provide protection, support, heat dissipation, assembly and other functions for the chip. The chip carrier can be regarded as a special printed circuit board, which also adopts a stacked structure formed by alternating metal layers and dielectric layers. Its circuit is realized by etching the pattern on the metal layer of the stacked structure, and the electrical interconnection between layers is realized through metallized holes.

[0004] The design cycle of the chip carrier directly affects the entire chip production and manufacturing process. In the design of the chip carrier, it is usually necessary to add degassing holes at appropriate locations of the metal layer to release the gas under the metal. If the degassing holes are not added, bubbles will be generated under the metal, which may cause the metal surface to be uneven. Generally speaking, the larger the carrier size and the more layers are stacked, the more degassing holes are required. The current solution is to set the size and array of the degassing holes through the options provided in the integrated circuit design software, and the design software adds degassing holes to each layer of the carrier in batches. However, the degassing holes added in batches are all added according to the same size and the same array, which makes it difficult to take into account the specific differences of each layer. Therefore, it is also necessary to rely on visual inspection by designers in order to manually add degassing holes to areas where the degassing holes are insufficient, which not only increases the workload but also depends on the specific experience of the designers, and is very easy to cause omissions. Therefore, after the layout design file of the chip carrier is handed over to the manufacturer, the manufacturer must also conduct relevant inspections and modifications, which undoubtedly prolongs the entire design and production cycle.

[0005] It should be noted that the above content is only used to help understand the technical solution of the present application, and is not used as a basis for evaluating the prior art of the present application. Summary of the invention

[0006] In view of the above problems, the present application provides a method, system and storage medium for efficiently adding vent holes in a chip carrier.

[0007] According to a first aspect of an embodiment of the present application, a method for adding vents in a chip carrier is provided, comprising: obtaining a chip carrier design file; generating a first vent layer corresponding to a layer to which vents need to be added in the chip carrier design file; removing vents that do not comply with predetermined design rules from the first vent layer to obtain a second vent layer; detecting local areas where vents are insufficiently added based on the second vent layer; generating a third vent layer corresponding to each local area detected; and merging the second vent layer and the third vent layer to obtain the vent layer associated with the layer.

[0008] In this embodiment, the carrier design file that supports the layout design rule checking format is automatically checked for local areas on each layer where insufficient vent holes are added, and the vent holes are regenerated for each local area, thereby avoiding visual inspection based on the personal experience of designers, reducing the error rate, and improving design efficiency. This can also reduce repeated iterations between the design team and the carrier manufacturer, which is conducive to shortening the entire design and production cycle.

[0009] In some embodiments, the chip carrier design file is in a format that supports layout design rule checking, and the obtaining of the chip carrier design file may further include converting the received chip carrier design file into a format that supports layout design rule checking. The method may further include inserting corresponding vents in the received chip carrier design file according to the position and size information of the vents in the vent layer associated with each layer.

[0010] In some embodiments, different layers may generate first vent layers in different sizes and / or arrays, so that the differences between the layers of the carrier can be taken into account and vents of different sizes and arrangements can be flexibly added to different layers.

[0011] In some embodiments, at least two adjacent layers generate the first vent layer in different sizes and / or arrays, so that the vents in the upper and lower layers are not completely aligned, thereby avoiding depressions caused by the aligned vents in the upper and lower layers during the manufacturing process.

[0012] In some embodiments, the third vent layer and the first vent layer can have different sizes and / or arrays. Each third vent layer can have different sizes and / or arrays. In these embodiments, for each local area inspected, vents are generated with sizes and / or arrays different from those of each layer of the original carrier, which is conducive to improving the efficiency of adding vents.

[0013] In some embodiments, merging the second vent layer and the third vent layer may include: retaining the vents that do not intersect each other in the second vent layer and the third vent layer; and retaining the vents with large sizes for the vents that overlap in the second vent layer and the third vent layer. This is more conducive to the subsequent processing and manufacturing process.

[0014] In some embodiments, the local area where the vents are insufficiently added may refer to an area where the metal density is greater than a preset threshold. Detecting the local area where the vents are insufficiently added based on the second vent layer may include: merging the metal layer of each level with its corresponding second vent layer to obtain a new merged layer; scanning the new merged layer based on a preset sliding window to obtain all areas where the metal density is greater than the preset threshold. Using such a sliding window to check the metal density can more quickly and accurately locate the local area where the vents are insufficiently added, which is conducive to improving the efficiency of adding vents and shortening the design time.

[0015] In some embodiments, generating a first vent layer corresponding to each level may include: for each level of the carrier hierarchy structure in the chip carrier design file to which vents need to be added, generating at least two different vent layers with at least two different sizes and arrangements, and merging the at least two different vent layers to obtain the first vent layer. In these embodiments, adding vents with different sizes and / or arrays to the same level of the carrier structure further takes into account the differences between different areas of the same level, and is more flexible and scalable.

[0016] According to the second aspect of the embodiment of the present application, a system for adding vents in a chip carrier is provided, which includes a vent adding module and an export module. The vent adding module is used to generate a first vent layer corresponding to the level in the chip carrier design file to which vents need to be added; remove vents that do not meet the predetermined design rules from the first vent layer to obtain a second vent layer; detect local areas where vents are insufficiently added based on the second vent layer; generate a third vent layer corresponding to each local area detected; and merge the second vent layer and the third vent layer to obtain the vent layer associated with the level. The export module is used to insert the corresponding vents in the received chip carrier design file according to the position and size information of the vents in the vent layers associated with each level.

[0017] In some embodiments, the system further includes a format conversion module for converting the received chip carrier design file into a format that can support layout design rule checking.

[0018] According to a third aspect of an embodiment of the present application, a computer-readable storage medium is provided, on which computer instructions are stored. When the computer instructions are executed by a processor, the method described in the first aspect of the embodiment of the present application is implemented.

[0019] Unlike the prior art, the solution of the present application does not need to rely on special carrier design software to generate exhaust holes in batches, but can flexibly generate exhaust holes at each level in different sizes and / or arrays; and by automatically checking local areas at each level where exhaust holes are insufficiently added, and generating exhaust holes with new sizes and / or arrays for each local area, visual inspection relying on the personal experience of designers is avoided, the error rate is reduced, and design efficiency is improved, thereby reducing repeated iterations between the design team and the carrier manufacturer, which is conducive to shortening the entire design and production manufacturing cycle.

[0020] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present application, and together with the specification, are used to explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0022] Figure 1 1 is a flow chart of a method for adding vent holes in a chip carrier according to an embodiment of the present application;

[0023] Figure 2 is a schematic diagram of a first vent layer according to an embodiment of the present application;

[0024] Figure 3 A schematic diagram of a process of adding exhaust holes to a local area according to an embodiment of the present application;

[0025] Figure 4 Schematic diagram of functional modules of a system for adding vent holes in a chip carrier according to an embodiment of the present application. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical solutions and advantages of this application more clear, the present application is further described in detail by specific embodiments in conjunction with the accompanying drawings. It should be understood that the described embodiments are part of the embodiments of this application, rather than all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0027] In addition, described feature, structure or characteristic can be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present application. However, those skilled in the art will appreciate that the technical scheme of the present application can be put into practice without one or more of the specific details, or other methods, components, devices, steps, etc. can be adopted. In other cases, known methods, devices, realizations or operations are not shown or described in detail to avoid blurring the various aspects of the application.

[0028] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities may be implemented in software form, or in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0029] The flowcharts shown in the accompanying drawings are only exemplary and do not necessarily include all the contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps can be decomposed, and some operations / steps can be combined or partially combined, so the actual execution order may change according to actual conditions.

[0030] The chip design and manufacturing process can be simply divided into three stages: design, manufacturing, packaging and testing. The chip design stage starts with the chip architecture design and ends with the generation of the physical layout GDS (Graphics Display System). The designed physical layout is handed over to the foundry in the form of a GDSII format file. In the chip manufacturing stage, after obtaining the GDSII format file, the foundry makes the corresponding integrated circuit (IC) on the silicon wafer to obtain a bare die, that is, a bare chip. Then, the bare chip is packaged and tested by the semiconductor packaging and testing factory to make a chip that can work normally.

[0031] Chip carrier is a basic component used in the chip packaging process to protect the bare chip and realize the electrical interconnection between the integrated circuit on the bare chip and the external electronic circuit, and at the same time provide protection, support, heat dissipation, assembly and other functions for the chip. Common chip carriers include chip packaging substrates, fan-out packages (FOP, Fanout package), etc.

[0032] In a general sense, a chip carrier can be regarded as a special printed circuit board, which also adopts a laminated structure formed by alternating metal layers and dielectric layers. Its circuit is realized by etching patterns on the metal layers of the laminated structure, and the electrical interconnection between layers is realized by metallized holes. These patterns and hole patterns etched on the metal layers of the laminated structure can be collectively referred to as layouts. The layout can be simply understood as a set of mutually nested graphics. The layout file is the starting point for processing and manufacturing. The design file of the chip carrier contains the hierarchical structure information of the carrier and the layout corresponding to each level in the carrier hierarchy. After the current chip carrier is designed, the carrier design file is usually handed over to a special carrier manufacturer for manufacturing.

[0033] With the rapid development of semiconductor integrated circuits, the integration of chips is getting higher and higher, and the number of functions is increasing, resulting in more and more carrier stacking. The design requirements of high-density multi-layer carriers in a limited space increase the complexity of chip carrier research and development, design and manufacturing. The design cycle of chip carriers directly affects the entire chip production and manufacturing process.

[0034] In the design of chip carriers, it is usually necessary to add degassing holes at appropriate locations to release the gas under the metal. If degassing holes are not added, bubbles will be generated under the metal, which may cause the metal surface to be uneven. Generally speaking, the larger the carrier size and the more layers, the more degassing holes are required. The current solution is to set the size and array of the degassing holes through the options provided in the integrated circuit design software, and the design software adds degassing holes to each layer of the carrier in batches. However, the degassing holes added in batches are all added according to the same size and the same array, which makes it difficult to take into account the specific differences of each layer. Therefore, it is also necessary to rely on visual inspection by designers in order to manually add degassing holes to areas where degassing holes are insufficient, which not only increases the workload but also depends on the specific experience of the designers, and is very easy to cause omissions. Therefore, after the layout design files of the chip carrier are handed over to the carrier manufacturer, the carrier manufacturer must also conduct relevant inspections and modifications, which undoubtedly prolongs the entire design and production cycle.

[0035] In an embodiment of the present application, a method for adding vents in a chip carrier is provided. The method can generate vents in different sizes and / or arrays for each level in the carrier hierarchy where vents need to be added, and can screen out vents that do not meet the requirements according to preset design rules, which is flexible and convenient. In addition, the method can automatically check local areas where vents are insufficiently added at each level, and generate vents in new sizes and / or arrays for each local area, avoiding visual inspection that relies on the personal experience of designers, reducing the error rate, and improving design efficiency. This can also reduce repeated iterations between the design team and the carrier manufacturer, which is conducive to shortening the entire design and production cycle.

[0036] Figure 1 A schematic flow chart of a method for adding vent holes to a chip carrier according to an embodiment of the present invention is provided. Figure 1 As shown, in step S1), the chip carrier design file is obtained. The chip carrier design file contains the design of the layout graphics of each level of the carrier structure. The chip carrier design file here adopts a format that supports layout design rule checking. Layout design rule checking (DRC) is usually aimed at checking the integrated circuit layout on the chip, and checks whether the geometric dimensions of the graphics and lines of the same process layer and different process layers meet the constraints of the design rules, such as minimum size, minimum width, minimum spacing, etc. Common DRC basic commands include inspection commands such as width (Width), spacing (SPACE), internal (INT), external (EXT), angle (ABUT), density (DENSITY); logical operation commands such as AND, OR, XOR, NOT; screening commands with conditions or variables; layer operation commands such as generating layers and merging layers, etc. The inventor found in actual work and research that using these DRC basic commands to realize the addition and inspection of the exhaust holes of the chip carrier can significantly improve the design efficiency and shorten the design time.

[0037] Considering that the chip carrier design and chip design are currently carried out using different design software, if the chip carrier design file is to be DRC checked, it is usually necessary to convert the carrier design file into a format that supports layout design rule checking, such as the current mainstream chip layout file format---GDSII. GDSII files include the plane geometry of each layer, text or labels, and other relevant information, which can be used to reconstruct all or part of the layout information.

[0038] In a file in GDSII format, all data is composed of a series of linked data blocks, which respectively define the file header, library file header, library file name, data unit, module structure header, module structure name, pixel, layer name, data type, pixel coordinate, pixel tail, module structure tail, followed by the second module structure header... and finally end with the file tail. GDSII usually has seven kinds of pixels: filled polygons (BOUNDARY), lines with a certain width (PATH), inserted modules (Reference Structure), arrays composed of inserted modules (Array), text (Text), circuit topology structure (Node), and frame structure (Box). Taking filled polygons as an example, its data structure usually includes layer number and coordinate parameters. The layer number identifies the layer to which the filled polygon (such as a quadrilateral, hexagon, etc.) belongs; the coordinate parameters identify the position coordinates of each inflection point of the filled polygon in the layer to which it belongs. For the convenience of description, the following embodiments of the present application mainly use the carrier design file in GDSII format as an example for explanation, but no limitation is imposed on this. The carrier design file can be converted into other corresponding data formats according to actual needs and different layout design rule checking platforms.

[0039] Continue to refer Figure 1 In step S2, for the layer in the chip carrier design file where the vent hole needs to be added, a first vent hole layer corresponding to the layer is generated. As mentioned above, in the design of the chip carrier, it is usually necessary to add vent holes to each metal layer. In this application, the vent hole layer refers to a planar layer containing one or more vent hole patterns. Figure 2 An example of a first vent layer according to an embodiment of the present invention is shown. Figure 2 The shape of the exhaust hole is displayed as a circle, but considering that the carrier design file being operated is in the GDSII format, the exhaust hole is represented by a filled polygon in the file, and the position and size of the exhaust hole are marked with the position coordinates of the inflection points of the corresponding filled polygon in the plane layer.

[0040] In some embodiments, different layers may generate first vent layers in different sizes and / or arrays, so that the differences between the layers of the carrier can be taken into account and vents of different sizes and arrangements can be flexibly added to different layers.

[0041] In some embodiments, at least two adjacent layers generate the first vent layer in different sizes and / or arrays, so that the vents in the upper and lower layers are not completely aligned, thereby avoiding depressions caused by the aligned vents in the upper and lower layers during the manufacturing process.

[0042] In one embodiment, for the same level of the carrier structure, vent holes of different sizes and / or arrays may be added at the same time. For example, for a level to which vent holes need to be added, at least two different vent hole layers are first generated with at least two different sizes and arrangements, and then these vent hole layers are merged to obtain a first vent hole layer corresponding to the level. The first vent hole layer generated in this way includes vent holes of at least two different sizes and / or arrays. This embodiment can also take into account the differences between different areas of the same level when adding vent holes, and is more flexible and scalable.

[0043] In this embodiment, merging at least two different vent layers includes: retaining vents that do not intersect each other in different vent layers; and retaining the vent with the largest size among overlapping vents in different vent layers. This makes subsequent processing and manufacturing more convenient.

[0044] Back to Figure 1 After obtaining the first vent layer of each level in step S2, in step S3, for each level of the first vent layer, remove the vents that do not meet the predetermined design rules to obtain a second vent layer. The predetermined design rules here refer to design rules related to vents, such as the vents do not overlap with the vents or gaps of the adjacent layers, the vents do not contact the hole plate, whether the spacing between the vents and other graphics and lines at the same level meets the minimum spacing, etc. The screening of vents that do not meet the predetermined rules can be completed by using a combination of basic DRC inspection commands, filter commands, logical operation commands, etc. The DRC inspection of graphics usually includes inner edge inspection, outer edge inspection, size inspection, coverage inspection, etc. The inner edge inspection refers to checking the inner spacing of polygons, that is, the corresponding relationship between the inner edges of polygons. The outer edge inspection refers to checking the outer spacing of polygons, that is, the relative relationship between the outer edges of polygons, mainly for checking the distance between polygons or rectangles and other graphics. The size inspection refers to the inspection of the allowed line length, graphic area, etc. The coverage inspection is used to check polygon overlap. The layer obtained by removing the vents not meeting the predetermined design rules from the first vent layer through the design rule check is recorded as the second vent layer.

[0045] In step S4, one or more local areas where vents are insufficiently added are detected based on the second vent layer. Bubbles are more likely to be generated under a continuous large area of ​​metal, so in this embodiment, metal density is used as a criterion for judging whether vents are insufficiently added. When the metal density of a certain area exceeds a set threshold, the area is determined to be an area where vents are insufficiently added. For each level to be detected in the carrier hierarchy, the metal layer of the level can be merged with its corresponding second vent layer to obtain a new merged layer, and then the merged layer is divided into multiple local areas based on a preset area size, and the metal density of each local area is detected in turn to select the local areas where vents are insufficiently added. Preferably, the new merged layer can be scanned based on a preset sliding window to obtain all areas where the metal density is greater than the set threshold, so as to more accurately locate the local areas where vents are insufficiently added.

[0046] It should be understood that the above-mentioned threshold value of metal density, preset area size, sliding window size and step size can be set according to actual needs, and the present application does not limit this. For example, assuming that the metal density is expressed in the form of a percentage, an area with a metal density of 100% or close to 100% means that there is a continuous large area of ​​metal in the area and exhaust holes need to be added. The threshold value of metal density can be set to 70%, 90%, etc. The smaller the preset area size, sliding window size and step size are, the greater the amount of calculation, and vice versa, the faster the detection speed, so it can be reasonably set or adjusted according to actual needs.

[0047] In step S5, for each vent detected at each level in the carrier structure, an insufficient local area is added, and a third vent layer corresponding to the local area is generated with a new size and / or array. Figure 3 As shown, the size and array of the vent holes in the third vent hole layer corresponding to the local area are different from the size and array used when generating the first vent hole layer in step S2. For different local areas at the same level, the corresponding third vent hole layer can be generated using the same size and / or array or using different sizes and / or arrays. For local areas at different levels, it is similar, and various sizes and / or arrays can be flexibly used to generate the corresponding third vent hole layer. Although Figure 3 It is shown that the local area does not contain any vents of the second vent layer, but it should be understood that this is only an example and not a limitation. The local area where the detected vents are insufficiently added may also cover one or several vents generated previously.

[0048] In step S6, the second vent layer and the third vent layer associated with each level in the carrier structure are merged to obtain a vent layer associated with the level. Each level may generally be associated with one or more third vent layers. Although the vents in the third vent layer are different in size from those in the second vent layer, the two may overlap or intersect. Therefore, the merging of the second vent layer and the third vent layer includes at least the following three situations:

[0049] A1) retaining the non-intersecting vents in the second vent layer and the third vent layer;

[0050] A2) For overlapping vents in the second vent layer and the third vent layer, retain the larger vents for easier processing and manufacturing.

[0051] The merging of multiple third vent layers involved in the above merging process is also similar to the above situation, and will not be repeated here. After the above merging, the vent layers associated with each level in the carrier structure are obtained. The position and size information of the vents at each level are marked by such vent layers. After appropriate adjustment and format conversion of these information, they can be imported into the original chip carrier design file, thereby obtaining a chip carrier design file with vents added. In addition, it should be understood that processes similar to the above steps S3, S4, S5, and S6 can be performed multiple times. For example, on the basis of the current vent layers at each level, it is also possible to further check the local areas where the vents are insufficiently added, for example, adjust the preset area size or the sliding window size; and use different sizes and / or arrays to generate relevant vent layers for the checked local areas until the requirements are met, which will not be repeated here.

[0052] Different from the prior art, the method of the above embodiment does not need to rely on special carrier design software to generate exhaust holes, but combines the design rule check of the graphics to flexibly generate exhaust holes in different sizes and / or arrays for each layer where exhaust holes need to be added; and can automatically check the local areas where exhaust holes are insufficient on each layer, and generate exhaust holes with new sizes and / or arrays for each local area, avoiding visual inspection relying on the personal experience of designers, reducing the error rate, and improving design efficiency, thereby reducing repeated iterations between the design team and the carrier manufacturer, which is conducive to shortening the entire design and production manufacturing cycle.

[0053] In order to better understand the method of adding vents in the chip carrier of the present application, the implementation and use scenarios of the method are illustrated below. In this example, the chip carrier design file used as the operation object uses the GDSII format, and Calibre of Mentor, USA, is used as the layout design rule checking platform. The method of the present application is implemented by using a design rule checking file (DRC file for short) written in the standard verification rule format (SVRF) language commonly used in the industry. After the DRC file is compiled, it is executed on the Calibre platform.

[0054] The DRC file includes at least the following parts: 1) environment parameter settings, 2) variable definitions; 3) hierarchy definitions and mappings; 4) operations for adding vents.

[0055] 1) Environmental parameter settings

[0056] In the environment parameter setting section, set the environment parameters related to execution, such as the format of the input layout file, the specific path and file name of the input layout file, and the name of the output check result file. An example of the environment parameter setting section is given below:

[0057] LAYOUT SYSTEM GDS-II (used to indicate that the input file format is GDS-II format)

[0058] LAYOUT PATH'myPath / Test.gds' (used to express the specific path of the input GDS-II file)

[0059] DRC RESULTS DATABASE 'DRC.db' (used to express the name of the output inspection result file)

[0060] In this way, the compiled design rule check file can read the layout file to be tested from the specified path according to its environmental parameter settings to perform relevant tests, and the results generated after execution are saved in the check result file specified by the environmental parameters.

[0061] 2. Variable definition

[0062] In this part, the parameters related to the design rules and subsequent inspection operations are defined in the form of "variable name + assignment", such as the minimum line width, minimum spacing, metal density threshold, window size for checking the insufficient area of ​​vent holes, etc. The VARIABLE command is used to define variables, and its format is variable name value, for example:

[0063] VARIABLE BU_DGH_EN_1 75

[0064] VARIABLE DGH_DN_1 0.97

[0065] BU_DGH_EN_1 refers to the minimum width of the copper wrapping around the exhaust hole, and DGH_DN_1 is used to specify the metal density threshold for checking the area where the exhaust hole is insufficiently added.

[0066] 3. Hierarchical definition and mapping

[0067] The carrier hierarchy is pre-defined in the DRC file. Subsequent operations on each layer in the DRC file are performed based on this part of pre-defined layers. For example, the layer numbers used in subsequent inspection operation commands are all layer identifiers of each layer pre-defined in this part.

[0068] In addition to the above hierarchy definition, the DRC file also includes the definition of hierarchy mapping. The mapping statement starts with the Layer map command. Through such a mapping definition, a mapping relationship is established between the carrier hierarchy in the layout file to be checked and the pre-defined hierarchy in the DRC file, so as to identify the relevant hierarchy in the input file when the DRC file is executed.

[0069] 4) Adding vents

[0070] The variables and levels defined above and the highly functional commands provided in the Calibre programming language, such as DRC check commands, logical operation commands; filtering commands with conditions or variables, layer operation commands, etc. are combined to form relevant operation statements to implement the addition of exhaust holes introduced in the above-mentioned combination of steps S2-S6.

[0071] Take the generation of the vent layer as an example. In this example, the vent is represented by a rectangle, and the statement for generating a rectangular array is the rectangles statement. If you want to generate a rectangular array in a layer named layer area_name, the statement format that can be used is: Regtangles width length widthspace lengthspace inside of layer area_name; where width and length are the width and height of the generated rectangle, respectively, and widthspace and lengthspace define the horizontal and vertical spacing between rectangles in the array, respectively. In the DRC file, the vent layer can be generated by, for example, the following statement:

[0072] DGH_RECT_150_1 = RECTANGLES 150 150 850 350 INSIDE OF LAYER outline / / Generate an exhaust hole layer DGH_RECT_150_1 containing an array of exhaust holes with a diameter of 150 for the outline layer;

[0073] DGH_RECT_150_2=SHIFT DGH_RECT_150_1BY 0 500 / / The SHIFT command is used to generate a new layer DGH_RECT_150_2 with a specific offset relative to the original layer DGH_RECT_150_1.

[0074] The distance between the two vent layers generated by the above statement is 150, but the arrays are different. If you want to merge the two layers DGH_RECT_150_1 and DGH_RECT_150_2 into a new layer L1, you can use the MERGE statement, for example:

[0075] L1=MERGE(OR DGH_RECT_150_1DGH_RECT_150_2).

[0076] The above examples are only used to assist in understanding some programming details of the method of the present invention, and the specific programming syntax is not repeated here. It should be understood that although the above embodiments are introduced with Calibre and its programming language as an application platform, this is only for the purpose of illustration and not for any limitation. Through adaptive adjustment or deformation, the method of the embodiment of the present application can also be applied to other layout design rule checking platforms.

[0077] Figure 4 FIG. 2 shows a functional module diagram of a system for adding vent holes in a chip carrier according to an embodiment of the present application. Figure 4As shown, the system 400 includes a format conversion module 401, a vent adding module 402 and an export module 403. The format conversion module 401 receives a chip carrier design file to which vents need to be added, and converts the received file into a format that can support layout design rule checking, such as a GDSII format. The vent adding module 402 obtains vent layers associated with each level in the chip carrier design file in combination with the process described in steps S2-S6 above. As described above, the vent adding module can be implemented by a design rule check (DRC) file running on Calibre, a layout verification platform for chips. The export module 403 can obtain the position and size information of the vents in the vent layers associated with each level from the results output by the execution of the DRC file, and modify the chip carrier design file received by the format conversion module 401 based on this information, and complete the insertion of all vents at one time, thereby obtaining a chip carrier design file with vents added. It should be understood that Figure 4 The conversion module 401 is an optional module. In some embodiments, the system may not include the conversion module 401, but directly processes the received chip carrier design file in a format supporting layout design rule checking.

[0078] In another embodiment of the present application, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the above-mentioned Figure 1 In the present application, a computer-readable storage medium may be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0079] It should be understood that, for the steps, processes or methods mentioned in this article, in addition to being implemented in a purely computer-readable program code, it is entirely possible to implement the same functions by logically programming the corresponding functional modules, processes or steps so that these modules are in the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers and embedded microcontrollers. Therefore, the module or device implemented in this way can be considered as a hardware component, and the submodules included therein for implementing various functions can also be regarded as the internal structure of the hardware component. Alternatively, the device for implementing various functions can be regarded as both a software module for implementing the relevant process or method steps and a structure within the hardware component.

[0080] References in this specification to "various embodiments," "some embodiments," "one embodiment," or "an embodiment," etc. refer to a particular feature, structure, or property described in conjunction with the above-described embodiment being included in at least one embodiment. Thus, the appearance of the phrases "in various embodiments," "in some embodiments," "in one embodiment," or "in an embodiment," etc., in various places throughout the specification do not necessarily refer to the same embodiment. Furthermore, particular features, structures, or properties may be combined in any suitable manner in one or more embodiments. Thus, particular features, structures, or properties shown or described in conjunction with one embodiment may be combined in whole or in part with features, structures, or properties of one or more other embodiments without restriction, as long as the combination is not illogical or inoperable.

[0081] The expressions of "including", "having" and similar meanings in this specification are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units that are not listed, or may optionally include other steps or units inherent to these processes, methods, products or devices. "One" or "an" does not exclude multiple situations. In addition, the elements in the drawings of this application are for illustrative purposes only and are not drawn to scale.

[0082] Although the present application has been described through the above-mentioned embodiments, the present application is not limited to the embodiments described herein, and also includes various changes and modifications made without departing from the scope of the present application.

Claims

1. A method for adding vent holes in a chip carrier, comprising: Obtain chip carrier design files; For the layers where vent holes need to be added in the chip carrier design file: Generate a first vent layer corresponding to the layer; Removing vents that do not meet a predetermined design rule from the first vent layer to obtain a second vent layer; Detecting local areas where vents are insufficiently added based on the second vent layer; For each detected local area, generating a third exhaust hole layer corresponding to the local area; Merge the second vent layer and the third vent layer to obtain the vent layer associated with the hierarchy; The merging of the second vent layer and the third vent layer includes: Keep the non-intersecting vents in the second vent layer and the third vent layer; For overlapping vents in the second and third vent layers, keep the larger vents.

2. The method according to claim 1, wherein: The chip carrier design file adopts a format that supports layout design rule checking, and obtaining the chip carrier design file also includes converting the received chip carrier design file into a format that supports layout design rule checking.

3. The method according to claim 2 further comprises inserting corresponding vents in the received chip carrier design file according to the position and size information of the vents in the vent layers associated with each level.

4. The method according to claim 1, wherein the first exhaust hole layers at each level have different sizes and / or arrays.

5. The method according to claim 1, wherein the first exhaust hole layers of two adjacent layers have different sizes and / or arrays.

6. The method according to claim 1, wherein the third vent layer and the first vent layer have different sizes and / or arrays.

7. The method according to claim 1, wherein each third vent hole layer has a different size and / or array.

8. The method according to any one of claims 1 to 7, wherein the local area where the vent holes are insufficiently added refers to an area where the metal density is greater than a preset threshold.

9. The method according to claim 8, wherein detecting the local area where the vents are insufficiently added based on the second vent layer comprises: Merge each metal layer with its corresponding second vent layer to obtain a new merged layer; The new merged layer is scanned based on a preset sliding window to obtain all regions where the metal density is greater than a preset threshold.

10. The method according to any one of claims 1 to 7, wherein generating a first vent layer corresponding to each layer comprises: For each level of the carrier hierarchy structure in the chip carrier design file to which vents need to be added, at least two different vent layers are generated with at least two different sizes and arrangements, respectively, and the at least two different vent layers are merged to obtain the first vent layer.

11. The method of claim 10, wherein merging the at least two different vent layers comprises: Retaining the mutually non-intersecting vents in the at least two different vent layers; For the overlapping vents in the at least two different vent layers, the vents with larger sizes are retained.

12. A system for adding vent holes in a chip carrier, comprising: A vent adding module, used for generating a first vent layer corresponding to a layer to which vents need to be added in the chip carrier design file; removing vents that do not meet a predetermined design rule from the first vent layer to obtain a second vent layer; and detecting a local area where vents are insufficiently added based on the second vent layer; For each detected local area, generating a third exhaust hole layer corresponding to the local area; and merging the second vent layer and the third vent layer to obtain a vent layer associated with the hierarchy; The merging of the second vent layer and the third vent layer includes: retaining the vents that do not intersect each other in the second vent layer and the third vent layer, and retaining the larger vents for the overlapping vents in the second vent layer and the third vent layer; The export module is used to insert corresponding vents in the received chip carrier design file according to the position and size information of the vents in the vent layers associated with each level.

13. A computer-readable storage medium having computer instructions stored thereon, wherein the computer instructions, when executed by a processor, implement the method according to any one of claims 1 to 11.

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